mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
refactor atheros system code - also add support for the reset button (sends netlink messages in the same format as broadcom-diag)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7869 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
330
target/linux/atheros-2.6/files/arch/mips/atheros/ar5315/irq.c
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330
target/linux/atheros-2.6/files/arch/mips/atheros/ar5315/irq.c
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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* Copyright (C) 2006 FON Technology, SL.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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*/
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/*
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* Platform devices for Atheros SoCs
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/reboot.h>
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#include <linux/interrupt.h>
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#include <asm/bootinfo.h>
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#include <asm/irq_cpu.h>
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#include <asm/io.h>
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#include "../ar531x.h"
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static u32 gpiointmask = 0, gpiointval = 0;
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static inline void ar5315_gpio_irq(void)
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{
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u32 pend;
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sysRegWrite(AR5315_ISR, sysRegRead(AR5315_IMR) | ~AR5315_ISR_GPIO);
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/* only do one gpio interrupt at a time */
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pend = (sysRegRead(AR5315_GPIO_DI) ^ gpiointval) & gpiointmask;
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if (!pend)
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return;
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do_IRQ(AR531X_GPIO_IRQ_BASE + 31 - clz(pend));
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}
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/*
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* Called when an interrupt is received, this function
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* determines exactly which interrupt it was, and it
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* invokes the appropriate handler.
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*
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* Implicitly, we also define interrupt priority by
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* choosing which to dispatch first.
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*/
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asmlinkage void ar5315_irq_dispatch(void)
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{
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int pending = read_c0_status() & read_c0_cause();
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if (pending & CAUSEF_IP3)
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do_IRQ(AR5315_IRQ_WLAN0_INTRS);
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else if (pending & CAUSEF_IP4)
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do_IRQ(AR5315_IRQ_ENET0_INTRS);
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else if (pending & CAUSEF_IP2) {
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unsigned int ar531x_misc_intrs = sysRegRead(AR5315_ISR) & sysRegRead(AR5315_IMR);
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if (ar531x_misc_intrs & AR5315_ISR_SPI)
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do_IRQ(AR531X_MISC_IRQ_SPI);
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else if (ar531x_misc_intrs & AR5315_ISR_TIMER)
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do_IRQ(AR531X_MISC_IRQ_TIMER);
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else if (ar531x_misc_intrs & AR5315_ISR_AHB)
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do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
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else if (ar531x_misc_intrs & AR5315_ISR_GPIO)
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ar5315_gpio_irq();
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else if (ar531x_misc_intrs & AR5315_ISR_UART0)
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do_IRQ(AR531X_MISC_IRQ_UART0);
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else if (ar531x_misc_intrs & AR5315_ISR_WD)
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do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
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else
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do_IRQ(AR531X_MISC_IRQ_NONE);
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} else if (pending & CAUSEF_IP7)
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do_IRQ(AR531X_IRQ_CPU_CLOCK);
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else
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do_IRQ(AR531X_IRQ_NONE);
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}
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static void ar5315_gpio_intr_enable(unsigned int irq)
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{
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u32 gpio, mask;
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gpio = irq - AR531X_GPIO_IRQ_BASE;
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mask = 1 << gpio;
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gpiointmask |= mask;
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/* reconfigure GPIO line as input */
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sysRegMask(AR5315_GPIO_CR, AR5315_GPIO_CR_M(gpio), AR5315_GPIO_CR_I(gpio));
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/* Enable interrupt with edge detection */
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sysRegMask(AR5315_GPIO_INT, AR5315_GPIO_INT_M | AR5315_GPIO_INT_LVL_M, gpio | AR5315_GPIO_INT_LVL(3));
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}
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static void ar5315_gpio_intr_disable(unsigned int irq)
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{
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u32 gpio, mask;
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gpio = irq - AR531X_GPIO_IRQ_BASE;
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mask = 1 << gpio;
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gpiointmask &= ~mask;
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/* Disable interrupt with edge detection */
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sysRegMask(AR5315_GPIO_INT, AR5315_GPIO_INT_M | AR5315_GPIO_INT_LVL_M, gpio | AR5315_GPIO_INT_LVL(0));
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}
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/* Turn on the specified AR531X_MISC_IRQ interrupt */
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static unsigned int ar5315_gpio_intr_startup(unsigned int irq)
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{
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ar5315_gpio_intr_enable(irq);
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return 0;
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}
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/* Turn off the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5315_gpio_intr_shutdown(unsigned int irq)
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{
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ar5315_gpio_intr_disable(irq);
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}
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static void
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ar5315_gpio_intr_ack(unsigned int irq)
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{
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ar5315_gpio_intr_disable(irq);
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}
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static void
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ar5315_gpio_intr_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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ar5315_gpio_intr_enable(irq);
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}
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static struct irq_chip ar5315_gpio_intr_controller = {
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.typename = "AR5315 GPIO",
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.startup = ar5315_gpio_intr_startup,
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.shutdown = ar5315_gpio_intr_shutdown,
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.enable = ar5315_gpio_intr_enable,
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.disable = ar5315_gpio_intr_disable,
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.ack = ar5315_gpio_intr_ack,
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.end = ar5315_gpio_intr_end,
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};
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/* Enable the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5315_misc_intr_enable(unsigned int irq)
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{
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unsigned int imr;
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imr = sysRegRead(AR5315_IMR);
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switch(irq)
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{
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case AR531X_MISC_IRQ_SPI:
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imr |= AR5315_ISR_SPI;
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break;
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case AR531X_MISC_IRQ_TIMER:
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imr |= AR5315_ISR_TIMER;
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break;
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case AR531X_MISC_IRQ_AHB_PROC:
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imr |= AR5315_ISR_AHB;
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break;
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case AR531X_MISC_IRQ_AHB_DMA:
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imr |= 0/* ?? */;
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break;
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case AR531X_MISC_IRQ_GPIO:
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imr |= AR5315_ISR_GPIO;
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break;
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case AR531X_MISC_IRQ_UART0:
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imr |= AR5315_ISR_UART0;
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break;
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case AR531X_MISC_IRQ_WATCHDOG:
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imr |= AR5315_ISR_WD;
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break;
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case AR531X_MISC_IRQ_LOCAL:
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imr |= 0/* ?? */;
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break;
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}
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sysRegWrite(AR5315_IMR, imr);
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imr=sysRegRead(AR5315_IMR); /* flush write buffer */
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}
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/* Disable the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5315_misc_intr_disable(unsigned int irq)
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{
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unsigned int imr;
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imr = sysRegRead(AR5315_IMR);
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switch(irq)
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{
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case AR531X_MISC_IRQ_SPI:
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imr &= ~AR5315_ISR_SPI;
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break;
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case AR531X_MISC_IRQ_TIMER:
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imr &= (~AR5315_ISR_TIMER);
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break;
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case AR531X_MISC_IRQ_AHB_PROC:
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imr &= (~AR5315_ISR_AHB);
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break;
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case AR531X_MISC_IRQ_AHB_DMA:
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imr &= 0/* ?? */;
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break;
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case AR531X_MISC_IRQ_GPIO:
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imr &= ~AR5315_ISR_GPIO;
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break;
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case AR531X_MISC_IRQ_UART0:
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imr &= (~AR5315_ISR_UART0);
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break;
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case AR531X_MISC_IRQ_WATCHDOG:
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imr &= (~AR5315_ISR_WD);
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break;
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case AR531X_MISC_IRQ_LOCAL:
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imr &= ~0/* ?? */;
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break;
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}
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sysRegWrite(AR5315_IMR, imr);
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sysRegRead(AR5315_IMR); /* flush write buffer */
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}
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/* Turn on the specified AR531X_MISC_IRQ interrupt */
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static unsigned int
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ar5315_misc_intr_startup(unsigned int irq)
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{
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ar5315_misc_intr_enable(irq);
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return 0;
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}
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/* Turn off the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5315_misc_intr_shutdown(unsigned int irq)
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{
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ar5315_misc_intr_disable(irq);
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}
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static void
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ar5315_misc_intr_ack(unsigned int irq)
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{
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ar5315_misc_intr_disable(irq);
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}
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static void
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ar5315_misc_intr_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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ar5315_misc_intr_enable(irq);
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}
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static struct irq_chip ar5315_misc_intr_controller = {
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.typename = "AR5315 misc",
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.startup = ar5315_misc_intr_startup,
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.shutdown = ar5315_misc_intr_shutdown,
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.enable = ar5315_misc_intr_enable,
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.disable = ar5315_misc_intr_disable,
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.ack = ar5315_misc_intr_ack,
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.end = ar5315_misc_intr_end,
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};
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static irqreturn_t ar5315_ahb_proc_handler(int cpl, void *dev_id)
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{
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sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
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sysRegRead(AR5315_AHB_ERR1);
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printk("AHB fatal error\n");
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machine_restart("AHB error"); /* Catastrophic failure */
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return IRQ_HANDLED;
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}
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static struct irqaction ar5315_ahb_proc_interrupt = {
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.handler = ar5315_ahb_proc_handler,
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.flags = SA_INTERRUPT,
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.name = "ar5315_ahb_proc_interrupt",
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};
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static struct irqaction cascade = {
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.handler = no_action,
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.flags = SA_INTERRUPT,
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.name = "cascade",
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};
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static void ar5315_gpio_intr_init(int irq_base)
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{
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int i;
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for (i = irq_base; i < irq_base + AR531X_GPIO_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &ar5315_gpio_intr_controller;
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}
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setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
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gpiointval = sysRegRead(AR5315_GPIO_DI);
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}
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void ar5315_misc_intr_init(int irq_base)
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{
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int i;
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for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &ar5315_misc_intr_controller;
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}
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setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5315_ahb_proc_interrupt);
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setup_irq(AR5315_IRQ_MISC_INTRS, &cascade);
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ar5315_gpio_intr_init(AR531X_GPIO_IRQ_BASE);
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}
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