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ifxmips pci does not cause a hang anymore, but due to lack of antenna i get no link on the atheros card, ints are flying though
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9840 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -21,6 +21,8 @@
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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//#define CONFIG_IFXMIPS_PCI_HW_SWAP 1
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static int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
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static int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
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@ -251,7 +253,7 @@ static void __init ifxmips_pci_startup (void){
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/* FPI ==> PCI IO address mapping */
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/* base: 0xbAE00000 == > 0xbAE00000 */
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/* size: 2M */
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writel(0xbae00000, PCI_CR_FCI_ADDR_MAP11hg);
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writel(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
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/* PCI ==> FPI address mapping */
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/* base: 0x0 ==> 0x0 */
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@ -262,7 +264,7 @@ static void __init ifxmips_pci_startup (void){
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writel(0, PCI_CS_BASE_ADDR1);
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#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
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/* both TX and RX endian swap are enabled */
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IFXMIPS_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
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writel(readl(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
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wmb ();
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#endif
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/*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
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@ -280,7 +282,6 @@ static void __init ifxmips_pci_startup (void){
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
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printk("\n\n\n%s:%s[%d] %d %d\n", __FILE__, __func__, __LINE__, slot, pin);
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switch (slot) {
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case 13:
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/* IDSEL = AD29 --> USB Host Controller */
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