mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
kernel: update bcma and ssb to version master-2012-04-12 from wireless-testing
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31278 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
hauke
@@ -1,6 +1,211 @@
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--- a/drivers/ssb/driver_chipcommon_pmu.c
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+++ b/drivers/ssb/driver_chipcommon_pmu.c
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@@ -13,6 +13,9 @@
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#include <linux/ssb/ssb_driver_chipcommon.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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+#ifdef CONFIG_BCM47XX
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+#include <asm/mach-bcm47xx/nvram.h>
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+#endif
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#include "ssb_private.h"
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@@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
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u32 pmuctl, tmp, pllctl;
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unsigned int i;
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- if ((bus->chip_id == 0x5354) && !crystalfreq) {
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- /* The 5354 crystal freq is 25MHz */
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- crystalfreq = 25000;
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- }
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if (crystalfreq)
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e = pmu0_plltab_find_entry(crystalfreq);
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if (!e)
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@@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
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u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
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if (bus->bustype == SSB_BUSTYPE_SSB) {
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- /* TODO: The user may override the crystal frequency. */
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+#ifdef CONFIG_BCM47XX
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+ char buf[20];
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+ if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
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+ crystalfreq = simple_strtoul(buf, NULL, 0);
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+#endif
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}
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switch (bus->chip_id) {
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@@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
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ssb_pmu1_pllinit_r0(cc, crystalfreq);
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break;
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case 0x4328:
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+ ssb_pmu0_pllinit_r0(cc, crystalfreq);
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+ break;
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case 0x5354:
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+ if (crystalfreq == 0)
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+ crystalfreq = 25000;
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ssb_pmu0_pllinit_r0(cc, crystalfreq);
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break;
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case 0x4322:
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@@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
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EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
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EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
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+
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+u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ switch (bus->chip_id) {
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+ case 0x5354:
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+ /* 5354 chip uses a non programmable PLL of frequency 240MHz */
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+ return 240000000;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "ERROR: PMU cpu clock unknown for device %04X\n",
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+ bus->chip_id);
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+ return 0;
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+ }
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+}
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+
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+u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ switch (bus->chip_id) {
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+ case 0x5354:
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+ return 120000000;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "ERROR: PMU controlclock unknown for device %04X\n",
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+ bus->chip_id);
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+ return 0;
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+ }
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+}
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
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struct ssb_bus *bus = mcore->dev->bus;
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u32 pll_type, n, m, rate = 0;
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+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
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+ return ssb_pmu_get_cpu_clock(&bus->chipco);
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+
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if (bus->extif.dev) {
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ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
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} else if (bus->chipco.dev) {
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -140,19 +140,6 @@ static void ssb_device_put(struct ssb_de
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put_device(dev->dev);
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}
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-static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
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-{
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- if (drv)
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- get_driver(&drv->drv);
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- return drv;
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-}
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-
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-static inline void ssb_driver_put(struct ssb_driver *drv)
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-{
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- if (drv)
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- put_driver(&drv->drv);
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-}
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-
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static int ssb_device_resume(struct device *dev)
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{
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struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
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@@ -250,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
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ssb_device_put(sdev);
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continue;
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}
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- sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
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- if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
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- ssb_device_put(sdev);
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+ sdrv = drv_to_ssb_drv(sdev->dev->driver);
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+ if (SSB_WARN_ON(!sdrv->remove))
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continue;
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- }
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sdrv->remove(sdev);
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ctx->device_frozen[i] = 1;
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}
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@@ -293,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
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dev_name(sdev->dev));
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result = err;
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}
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- ssb_driver_put(sdrv);
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ssb_device_put(sdev);
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}
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@@ -1094,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
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u32 plltype;
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u32 clkctl_n, clkctl_m;
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+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
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+ return ssb_pmu_get_controlclock(&bus->chipco);
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+
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if (ssb_extif_available(&bus->extif))
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ssb_extif_get_clockcontrol(&bus->extif, &plltype,
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&clkctl_n, &clkctl_m);
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
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@@ -523,7 +523,13 @@ static void sprom_extract_r45(struct ssb
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@@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ss
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{
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int i;
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u16 v;
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- s8 gain;
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u16 loc[3];
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if (out->revision == 3) /* rev 3 moved MAC */
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@@ -390,20 +389,12 @@ static void sprom_extract_r123(struct ss
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SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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/* Extract the antenna gain values. */
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- gain = r123_extract_antgain(out->revision, in,
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- SSB_SPROM1_AGAIN_BG,
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- SSB_SPROM1_AGAIN_BG_SHIFT);
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- out->antenna_gain.ghz24.a0 = gain;
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- out->antenna_gain.ghz24.a1 = gain;
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- out->antenna_gain.ghz24.a2 = gain;
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- out->antenna_gain.ghz24.a3 = gain;
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- gain = r123_extract_antgain(out->revision, in,
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- SSB_SPROM1_AGAIN_A,
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- SSB_SPROM1_AGAIN_A_SHIFT);
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- out->antenna_gain.ghz5.a0 = gain;
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- out->antenna_gain.ghz5.a1 = gain;
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- out->antenna_gain.ghz5.a2 = gain;
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- out->antenna_gain.ghz5.a3 = gain;
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+ out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
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+ SSB_SPROM1_AGAIN_BG,
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+ SSB_SPROM1_AGAIN_BG_SHIFT);
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+ out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
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+ SSB_SPROM1_AGAIN_A,
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+ SSB_SPROM1_AGAIN_A_SHIFT);
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}
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/* Revs 4 5 and 8 have partially shared layout */
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@@ -504,16 +495,14 @@ static void sprom_extract_r45(struct ssb
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}
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/* Extract the antenna gain values. */
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- SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
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+ SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
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SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
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- SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
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+ SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
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SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
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- SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
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+ SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
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SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
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- SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
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+ SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
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SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
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- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
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- sizeof(out->antenna_gain.ghz5));
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sprom_extract_r458(out, in);
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@@ -523,7 +512,13 @@ static void sprom_extract_r45(struct ssb
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static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
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{
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int i;
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@@ -15,10 +220,25 @@
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/* extract the MAC address */
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for (i = 0; i < 3; i++) {
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@@ -607,6 +613,38 @@ static void sprom_extract_r8(struct ssb_
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memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
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sizeof(out->antenna_gain.ghz5));
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@@ -596,16 +591,46 @@ static void sprom_extract_r8(struct ssb_
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SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
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/* Extract the antenna gain values. */
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- SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
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+ SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
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SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
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- SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
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+ SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
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SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
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- SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
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+ SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
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SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
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- SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
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+ SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
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SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
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- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
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- sizeof(out->antenna_gain.ghz5));
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+
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+ /* Extract cores power info info */
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+ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
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+ o = pwr_info_offset[i];
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@@ -50,10 +270,74 @@
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+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
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+ }
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+
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/* Extract FEM info */
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SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
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SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
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--- a/drivers/ssb/pcmcia.c
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+++ b/drivers/ssb/pcmcia.c
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@@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
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case SSB_PCMCIA_CIS_ANTGAIN:
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GOTO_ERROR_ON(tuple->TupleDataLen != 2,
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"antg tpl size");
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- sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
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- sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
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- sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
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- sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
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- sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
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- sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
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- sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
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- sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
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+ sprom->antenna_gain.a0 = tuple->TupleData[1];
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+ sprom->antenna_gain.a1 = tuple->TupleData[1];
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+ sprom->antenna_gain.a2 = tuple->TupleData[1];
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+ sprom->antenna_gain.a3 = tuple->TupleData[1];
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break;
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case SSB_PCMCIA_CIS_BFLAGS:
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GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
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--- a/drivers/ssb/scan.c
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+++ b/drivers/ssb/scan.c
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@@ -318,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
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bus->chip_package = 0;
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}
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}
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+ ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
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+ "package 0x%02X\n", bus->chip_id, bus->chip_rev,
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+ bus->chip_package);
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if (!bus->nr_devices)
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bus->nr_devices = chipid_to_nrcores(bus->chip_id);
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if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
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--- a/drivers/ssb/sdio.c
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+++ b/drivers/ssb/sdio.c
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@@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
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case SSB_SDIO_CIS_ANTGAIN:
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GOTO_ERROR_ON(tuple->size != 2,
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"antg tpl size");
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- sprom->antenna_gain.ghz24.a0 = tuple->data[1];
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- sprom->antenna_gain.ghz24.a1 = tuple->data[1];
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- sprom->antenna_gain.ghz24.a2 = tuple->data[1];
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- sprom->antenna_gain.ghz24.a3 = tuple->data[1];
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- sprom->antenna_gain.ghz5.a0 = tuple->data[1];
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- sprom->antenna_gain.ghz5.a1 = tuple->data[1];
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- sprom->antenna_gain.ghz5.a2 = tuple->data[1];
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- sprom->antenna_gain.ghz5.a3 = tuple->data[1];
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+ sprom->antenna_gain.a0 = tuple->data[1];
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+ sprom->antenna_gain.a1 = tuple->data[1];
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+ sprom->antenna_gain.a2 = tuple->data[1];
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+ sprom->antenna_gain.a3 = tuple->data[1];
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break;
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case SSB_SDIO_CIS_BFLAGS:
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GOTO_ERROR_ON((tuple->size != 3) &&
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--- a/drivers/ssb/ssb_private.h
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+++ b/drivers/ssb/ssb_private.h
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@@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
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}
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#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
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+/* driver_chipcommon_pmu.c */
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+extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
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+extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
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+
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#endif /* LINUX_SSB_PRIVATE_H_ */
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--- a/include/linux/ssb/ssb.h
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+++ b/include/linux/ssb/ssb.h
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@@ -16,6 +16,12 @@ struct pcmcia_device;
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@@ -63,13 +347,54 @@
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+struct ssb_sprom_core_pwr_info {
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+ u8 itssi_2g, itssi_5g;
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+ u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
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+ u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
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+ u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
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+};
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+
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struct ssb_sprom {
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u8 revision;
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u8 il0mac[6]; /* MAC address for 802.11b/g */
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@@ -82,6 +88,8 @@ struct ssb_sprom {
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@@ -26,9 +32,12 @@ struct ssb_sprom {
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u8 et0mdcport; /* MDIO for enet0 */
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u8 et1mdcport; /* MDIO for enet1 */
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u16 board_rev; /* Board revision number from SPROM. */
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+ u16 board_num; /* Board number from SPROM. */
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+ u16 board_type; /* Board type from SPROM. */
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u8 country_code; /* Country Code */
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- u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
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- u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
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+ char alpha2[2]; /* Country Code as two chars like EU or US */
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+ u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
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+ u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
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u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
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u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
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u16 pa0b0;
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@@ -47,10 +56,10 @@ struct ssb_sprom {
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u8 gpio1; /* GPIO pin 1 */
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u8 gpio2; /* GPIO pin 2 */
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u8 gpio3; /* GPIO pin 3 */
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- u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
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- u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
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- u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
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- u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
|
||||
+ u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
|
||||
+ u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
|
||||
+ u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
|
||||
+ u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
|
||||
u8 itssi_a; /* Idle TSSI Target for A-PHY */
|
||||
u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
|
||||
u8 tri2g; /* 2.4GHz TX isolation */
|
||||
@@ -61,8 +70,8 @@ struct ssb_sprom {
|
||||
u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
|
||||
u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
|
||||
u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
|
||||
- u8 rxpo2g; /* 2GHz RX power offset */
|
||||
- u8 rxpo5g; /* 5GHz RX power offset */
|
||||
+ s8 rxpo2g; /* 2GHz RX power offset */
|
||||
+ s8 rxpo5g; /* 5GHz RX power offset */
|
||||
u8 rssisav2g; /* 2GHz RSSI params */
|
||||
u8 rssismc2g;
|
||||
u8 rssismf2g;
|
||||
@@ -82,16 +91,13 @@ struct ssb_sprom {
|
||||
u16 boardflags2_hi; /* Board flags (bits 48-63) */
|
||||
/* TODO store board flags in a single u64 */
|
||||
|
||||
@@ -78,6 +403,108 @@
|
||||
/* Antenna gain values for up to 4 antennas
|
||||
* on each band. Values in dBm/4 (Q5.2). Negative gain means the
|
||||
* loss in the connectors is bigger than the gain. */
|
||||
struct {
|
||||
- struct {
|
||||
- s8 a0, a1, a2, a3;
|
||||
- } ghz24; /* 2.4GHz band */
|
||||
- struct {
|
||||
- s8 a0, a1, a2, a3;
|
||||
- } ghz5; /* 5GHz band */
|
||||
+ s8 a0, a1, a2, a3;
|
||||
} antenna_gain;
|
||||
|
||||
struct {
|
||||
@@ -103,7 +109,79 @@ struct ssb_sprom {
|
||||
} ghz5;
|
||||
} fem;
|
||||
|
||||
- /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
|
||||
+ u16 mcs2gpo[8];
|
||||
+ u16 mcs5gpo[8];
|
||||
+ u16 mcs5glpo[8];
|
||||
+ u16 mcs5ghpo[8];
|
||||
+ u8 opo;
|
||||
+
|
||||
+ u8 rxgainerr2ga[3];
|
||||
+ u8 rxgainerr5gla[3];
|
||||
+ u8 rxgainerr5gma[3];
|
||||
+ u8 rxgainerr5gha[3];
|
||||
+ u8 rxgainerr5gua[3];
|
||||
+
|
||||
+ u8 noiselvl2ga[3];
|
||||
+ u8 noiselvl5gla[3];
|
||||
+ u8 noiselvl5gma[3];
|
||||
+ u8 noiselvl5gha[3];
|
||||
+ u8 noiselvl5gua[3];
|
||||
+
|
||||
+ u8 regrev;
|
||||
+ u8 txchain;
|
||||
+ u8 rxchain;
|
||||
+ u8 antswitch;
|
||||
+ u16 cddpo;
|
||||
+ u16 stbcpo;
|
||||
+ u16 bw40po;
|
||||
+ u16 bwduppo;
|
||||
+
|
||||
+ u8 tempthresh;
|
||||
+ u8 tempoffset;
|
||||
+ u16 rawtempsense;
|
||||
+ u8 measpower;
|
||||
+ u8 tempsense_slope;
|
||||
+ u8 tempcorrx;
|
||||
+ u8 tempsense_option;
|
||||
+ u8 freqoffset_corr;
|
||||
+ u8 iqcal_swp_dis;
|
||||
+ u8 hw_iqcal_en;
|
||||
+ u8 elna2g;
|
||||
+ u8 elna5g;
|
||||
+ u8 phycal_tempdelta;
|
||||
+ u8 temps_period;
|
||||
+ u8 temps_hysteresis;
|
||||
+ u8 measpower1;
|
||||
+ u8 measpower2;
|
||||
+ u8 pcieingress_war;
|
||||
+
|
||||
+ /* power per rate from sromrev 9 */
|
||||
+ u16 cckbw202gpo;
|
||||
+ u16 cckbw20ul2gpo;
|
||||
+ u32 legofdmbw202gpo;
|
||||
+ u32 legofdmbw20ul2gpo;
|
||||
+ u32 legofdmbw205glpo;
|
||||
+ u32 legofdmbw20ul5glpo;
|
||||
+ u32 legofdmbw205gmpo;
|
||||
+ u32 legofdmbw20ul5gmpo;
|
||||
+ u32 legofdmbw205ghpo;
|
||||
+ u32 legofdmbw20ul5ghpo;
|
||||
+ u32 mcsbw202gpo;
|
||||
+ u32 mcsbw20ul2gpo;
|
||||
+ u32 mcsbw402gpo;
|
||||
+ u32 mcsbw205glpo;
|
||||
+ u32 mcsbw20ul5glpo;
|
||||
+ u32 mcsbw405glpo;
|
||||
+ u32 mcsbw205gmpo;
|
||||
+ u32 mcsbw20ul5gmpo;
|
||||
+ u32 mcsbw405gmpo;
|
||||
+ u32 mcsbw205ghpo;
|
||||
+ u32 mcsbw20ul5ghpo;
|
||||
+ u32 mcsbw405ghpo;
|
||||
+ u16 mcs32po;
|
||||
+ u16 legofdm40duppo;
|
||||
+ u8 sar2g;
|
||||
+ u8 sar5g;
|
||||
};
|
||||
|
||||
/* Information about the PCB the circuitry is soldered on. */
|
||||
--- a/include/linux/ssb/ssb_driver_gige.h
|
||||
+++ b/include/linux/ssb/ssb_driver_gige.h
|
||||
@@ -2,6 +2,7 @@
|
||||
#define LINUX_SSB_DRIVER_GIGE_H_
|
||||
|
||||
#include <linux/ssb/ssb.h>
|
||||
+#include <linux/bug.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
--- a/include/linux/ssb/ssb_regs.h
|
||||
+++ b/include/linux/ssb/ssb_regs.h
|
||||
@@ -449,6 +449,39 @@
|
||||
|
||||
Reference in New Issue
Block a user