mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
add all source code from linksys/broadcom which is free, to cvs for better maintainence inside
openwrt. this gives us the ability to better support different hardware models, without changing any external tar-balls. only et.o and wl.o is missing and is fetched from my webserver. git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@379 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
wbx
242
package/linux/kernel-source/include/sbextif.h
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242
package/linux/kernel-source/include/sbextif.h
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/*
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* Hardware-specific External Interface I/O core definitions
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* for the BCM47xx family of SiliconBackplane-based chips.
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*
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* The External Interface core supports a total of three external chip selects
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* supporting external interfaces. One of the external chip selects is
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* used for Flash, one is used for PCMCIA, and the other may be
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* programmed to support either a synchronous interface or an
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* asynchronous interface. The asynchronous interface can be used to
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* support external devices such as UARTs and the BCM2019 Bluetooth
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* baseband processor.
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* The external interface core also contains 2 on-chip 16550 UARTs, clock
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* frequency control, a watchdog interrupt timer, and a GPIO interface.
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*
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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* $Id$
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*/
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#ifndef _SBEXTIF_H
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#define _SBEXTIF_H
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/* external interface address space */
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#define EXTIF_PCMCIA_MEMBASE(x) (x)
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#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
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#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
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#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
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#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif /* PAD */
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/*
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* The multiple instances of output and output enable registers
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* are present to allow driver software for multiple cores to control
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* gpio outputs without needing to share a single register pair.
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*/
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struct gpiouser {
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uint32 out;
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uint32 outen;
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};
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#define NGPIOUSER 5
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typedef volatile struct {
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uint32 corecontrol;
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uint32 extstatus;
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uint32 PAD[2];
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/* pcmcia control registers */
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uint32 pcmcia_config;
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uint32 pcmcia_memwait;
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uint32 pcmcia_attrwait;
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uint32 pcmcia_iowait;
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/* programmable interface control registers */
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uint32 prog_config;
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uint32 prog_waitcount;
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/* flash control registers */
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uint32 flash_config;
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uint32 flash_waitcount;
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uint32 PAD[4];
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uint32 watchdog;
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/* clock control */
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uint32 clockcontrol_n;
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uint32 clockcontrol_sb;
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uint32 clockcontrol_pci;
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uint32 clockcontrol_mii;
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uint32 PAD[3];
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/* gpio */
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uint32 gpioin;
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struct gpiouser gpio[NGPIOUSER];
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uint32 PAD;
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uint32 ejtagouten;
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uint32 gpiointpolarity;
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uint32 gpiointmask;
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uint32 PAD[153];
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uint8 uartdata;
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uint8 PAD[3];
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uint8 uartimer;
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uint8 PAD[3];
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uint8 uartfcr;
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uint8 PAD[3];
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uint8 uartlcr;
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uint8 PAD[3];
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uint8 uartmcr;
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uint8 PAD[3];
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uint8 uartlsr;
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uint8 PAD[3];
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uint8 uartmsr;
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uint8 PAD[3];
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uint8 uartscratch;
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uint8 PAD[3];
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} extifregs_t;
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/* corecontrol */
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#define CC_UE (1 << 0) /* uart enable */
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/* extstatus */
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#define ES_EM (1 << 0) /* endian mode (ro) */
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#define ES_EI (1 << 1) /* external interrupt pin (ro) */
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#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
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/* gpio bit mask */
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#define GPIO_BIT0 (1 << 0)
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#define GPIO_BIT1 (1 << 1)
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#define GPIO_BIT2 (1 << 2)
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#define GPIO_BIT3 (1 << 3)
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#define GPIO_BIT4 (1 << 4)
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#define GPIO_BIT5 (1 << 5)
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#define GPIO_BIT6 (1 << 6)
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#define GPIO_BIT7 (1 << 7)
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/* pcmcia/prog/flash_config */
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#define CF_EN (1 << 0) /* enable */
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#define CF_EM_MASK 0xe /* mode */
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#define CF_EM_SHIFT 1
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#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
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#define CF_EM_SYNC 0x2 /* synchronous mode */
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#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
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#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
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#define CF_BS (1 << 5) /* byteswap */
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#define CF_CD_MASK 0xc0 /* clock divider */
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#define CF_CD_SHIFT 6
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#define CF_CD_DIV2 0x0 /* backplane/2 */
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#define CF_CD_DIV3 0x40 /* backplane/3 */
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#define CF_CD_DIV4 0x80 /* backplane/4 */
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#define CF_CE (1 << 8) /* clock enable */
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#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
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/* pcmcia_memwait */
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#define PM_W0_MASK 0x3f /* waitcount0 */
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#define PM_W1_MASK 0x1f00 /* waitcount1 */
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#define PM_W1_SHIFT 8
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#define PM_W2_MASK 0x1f0000 /* waitcount2 */
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#define PM_W2_SHIFT 16
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#define PM_W3_MASK 0x1f000000 /* waitcount3 */
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#define PM_W3_SHIFT 24
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/* pcmcia_attrwait */
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#define PA_W0_MASK 0x3f /* waitcount0 */
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#define PA_W1_MASK 0x1f00 /* waitcount1 */
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#define PA_W1_SHIFT 8
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#define PA_W2_MASK 0x1f0000 /* waitcount2 */
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#define PA_W2_SHIFT 16
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#define PA_W3_MASK 0x1f000000 /* waitcount3 */
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#define PA_W3_SHIFT 24
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/* pcmcia_iowait */
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#define PI_W0_MASK 0x3f /* waitcount0 */
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#define PI_W1_MASK 0x1f00 /* waitcount1 */
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#define PI_W1_SHIFT 8
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#define PI_W2_MASK 0x1f0000 /* waitcount2 */
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#define PI_W2_SHIFT 16
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#define PI_W3_MASK 0x1f000000 /* waitcount3 */
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#define PI_W3_SHIFT 24
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/* prog_waitcount */
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#define PW_W0_MASK 0x0000001f /* waitcount0 */
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#define PW_W1_MASK 0x00001f00 /* waitcount1 */
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#define PW_W1_SHIFT 8
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#define PW_W2_MASK 0x001f0000 /* waitcount2 */
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#define PW_W2_SHIFT 16
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#define PW_W3_MASK 0x1f000000 /* waitcount3 */
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#define PW_W3_SHIFT 24
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#define PW_W0 0x0000000c
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#define PW_W1 0x00000a00
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#define PW_W2 0x00020000
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#define PW_W3 0x01000000
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/* flash_waitcount */
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#define FW_W0_MASK 0x1f /* waitcount0 */
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#define FW_W1_MASK 0x1f00 /* waitcount1 */
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#define FW_W1_SHIFT 8
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#define FW_W2_MASK 0x1f0000 /* waitcount2 */
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#define FW_W2_SHIFT 16
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#define FW_W3_MASK 0x1f000000 /* waitcount3 */
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#define FW_W3_SHIFT 24
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/* watchdog */
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#define WATCHDOG_CLOCK 48000000 /* Hz */
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/* clockcontrol_n */
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#define CN_N1_MASK 0x3f /* n1 control */
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#define CN_N2_MASK 0x3f00 /* n2 control */
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#define CN_N2_SHIFT 8
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/* clockcontrol_sb/pci/mii */
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#define CC_M1_MASK 0x3f /* m1 control */
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#define CC_M2_MASK 0x3f00 /* m2 control */
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#define CC_M2_SHIFT 8
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#define CC_M3_MASK 0x3f0000 /* m3 control */
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#define CC_M3_SHIFT 16
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#define CC_MC_MASK 0x1f000000 /* mux control */
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#define CC_MC_SHIFT 24
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/* Clock control default values */
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#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
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#define CC_DEF_100 0x04020011
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#define CC_DEF_33 0x11030011
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#define CC_DEF_25 0x11050011
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/* Clock control values for 125Mhz */
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#define CC_125_N 0x0802
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#define CC_125_M 0x04020009
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#define CC_125_M25 0x11090009
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#define CC_125_M33 0x11090005
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/* Clock control magic field values */
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#define CC_F6_2 0x02 /* A factor of 2 in */
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#define CC_F6_3 0x03 /* 6-bit fields like */
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#define CC_F6_4 0x05 /* N1, M1 or M3 */
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#define CC_F6_5 0x09
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#define CC_F6_6 0x11
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#define CC_F6_7 0x21
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#define CC_F5_BIAS 5 /* 5-bit fields get this added */
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#define CC_MC_BYPASS 0x08
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#define CC_MC_M1 0x04
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#define CC_MC_M1M2 0x02
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#define CC_MC_M1M2M3 0x01
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#define CC_MC_M1M3 0x11
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#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
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#endif /* _SBEXTIF_H */
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