mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
bump ifxmips to .30
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17817 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
@@ -1,34 +0,0 @@
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--- a/arch/mips/kernel/traps.c
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+++ b/arch/mips/kernel/traps.c
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@@ -1464,7 +1464,16 @@ void __cpuinit per_cpu_trap_init(void)
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*/
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if (cpu_has_mips_r2) {
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cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
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+ if (!cp0_compare_irq)
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+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
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+
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cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
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+ if (!cp0_perfcount_irq)
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+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
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+
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+ if (arch_fixup_c0_irqs)
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+ arch_fixup_c0_irqs();
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+
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if (cp0_perfcount_irq == cp0_compare_irq)
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cp0_perfcount_irq = -1;
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} else {
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--- a/include/asm-mips/irq.h
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+++ b/include/asm-mips/irq.h
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@@ -156,8 +156,12 @@ extern void free_irqno(unsigned int irq)
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* IE7. Since R2 their number has to be read from the c0_intctl register.
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*/
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#define CP0_LEGACY_COMPARE_IRQ 7
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+#define CP0_LEGACY_PERFCNT_IRQ 7
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extern int cp0_compare_irq;
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extern int cp0_perfcount_irq;
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+extern void __weak arch_fixup_c0_irqs(void);
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+
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+
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#endif /* _ASM_IRQ_H */
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@@ -1,65 +0,0 @@
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--- a/arch/mips/kernel/cevt-r4k.c
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+++ b/arch/mips/kernel/cevt-r4k.c
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@@ -13,6 +13,22 @@
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#include <asm/smtc_ipi.h>
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#include <asm/time.h>
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+/*
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+ * Compare interrupt can be routed and latched outside the core,
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+ * so a single execution hazard barrier may not be enough to give
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+ * it time to clear as seen in the Cause register. 4 time the
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+ * pipeline depth seems reasonably conservative, and empirically
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+ * works better in configurations with high CPU/bus clock ratios.
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+ */
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+
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+#define compare_change_hazard() \
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+ do { \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ } while (0)
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+
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static int mips_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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@@ -28,6 +44,7 @@ static int mips_next_event(unsigned long
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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+ compare_change_hazard();
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res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
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#ifdef CONFIG_MIPS_MT_SMTC
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evpe(vpflags);
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@@ -187,7 +204,7 @@ static int c0_compare_int_usable(void)
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*/
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if (c0_compare_int_pending()) {
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write_c0_compare(read_c0_count());
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- irq_disable_hazard();
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+ compare_change_hazard();
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if (c0_compare_int_pending())
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return 0;
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}
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@@ -196,7 +213,7 @@ static int c0_compare_int_usable(void)
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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- irq_disable_hazard();
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+ compare_change_hazard();
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if ((int)(read_c0_count() - cnt) < 0)
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break;
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/* increase delta if the timer was already expired */
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@@ -205,11 +222,12 @@ static int c0_compare_int_usable(void)
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while ((int)(read_c0_count() - cnt) <= 0)
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; /* Wait for expiry */
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+ compare_change_hazard();
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if (!c0_compare_int_pending())
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return 0;
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write_c0_compare(read_c0_count());
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- irq_disable_hazard();
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+ compare_change_hazard();
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if (c0_compare_int_pending())
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return 0;
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@@ -1,72 +0,0 @@
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -78,6 +78,23 @@ config MIPS_COBALT
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select GENERIC_HARDIRQS_NO__DO_IRQ
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+config IFXMIPS
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+ bool "Infineon Twinpass, Danube, Amazon-SE"
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+ select DMA_NONCOHERENT
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+ select IRQ_CPU
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+ select CEVT_R4K
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+ select CSRC_R4K
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_HAS_CPU_MIPS32_R2
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+ select HAVE_STD_PC_SERIAL_PORT
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+ select SYS_SUPPORTS_BIG_ENDIAN
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+ select SYS_SUPPORTS_32BIT_KERNEL
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+ select SYS_SUPPORTS_MULTITHREADING
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+ select SYS_HAS_EARLY_PRINTK
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+ select HW_HAS_PCI
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+ select GENERIC_GPIO
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+ select SWAP_IO_SPACE
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+
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config MACH_DECSTATION
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bool "DECstations"
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select BOOT_ELF32
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@@ -697,6 +714,7 @@ source "arch/mips/sibyte/Kconfig"
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source "arch/mips/tx4927/Kconfig"
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source "arch/mips/tx4938/Kconfig"
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source "arch/mips/vr41xx/Kconfig"
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+source "arch/mips/ifxmips/Kconfig"
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endmenu
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -283,6 +283,13 @@ cflags-$(CONFIG_MIPS_COBALT) += -Iinclud
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load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
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#
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+# Infineon IFXMIPS
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+#
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+core-$(CONFIG_IFXMIPS) += arch/mips/ifxmips/
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+cflags-$(CONFIG_IFXMIPS) += -Iinclude/asm-mips/mach-ifxmips
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+load-$(CONFIG_IFXMIPS) += 0xffffffff80002000
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+
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+#
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# DECstation family
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#
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core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/
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--- a/include/asm-mips/bootinfo.h
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+++ b/include/asm-mips/bootinfo.h
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@@ -94,6 +94,12 @@
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#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
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#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
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+/*
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+ * Valid machtype for group IFXMIPS
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+ */
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+#define MACH_GROUP_IFXMIPS 29
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+#define MACH_INFINEON_IFXMIPS 0
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+
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#define CL_SIZE COMMAND_LINE_SIZE
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extern char *system_type;
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -48,3 +48,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-
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obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
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obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
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obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
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+obj-$(CONFIG_IFXMIPS) += pci-ifxmips.o ops-ifxmips.o
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@@ -1,149 +0,0 @@
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--- a/drivers/char/Makefile
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+++ b/drivers/char/Makefile
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@@ -114,6 +114,10 @@ obj-$(CONFIG_PS3_FLASH) += ps3flash.o
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obj-$(CONFIG_JS_RTC) += js-rtc.o
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js-rtc-y = rtc.o
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+obj-$(CONFIG_IFXMIPS_SSC) += ifxmips_ssc.o
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+obj-$(CONFIG_IFXMIPS_EEPROM) += ifxmips_eeprom.o
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+obj-$(CONFIG_IFXMIPS_MEI) += ifxmips_mei_core.o
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+
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# Files generated that shall be removed upon make clean
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clean-files := consolemap_deftbl.c defkeymap.c
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--- a/drivers/mtd/maps/Makefile
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+++ b/drivers/mtd/maps/Makefile
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@@ -67,3 +67,4 @@ obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
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obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
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obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
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obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o
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+obj-$(CONFIG_MTD_IFXMIPS) += ifxmips.o
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--- a/drivers/net/Kconfig
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+++ b/drivers/net/Kconfig
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@@ -351,6 +351,12 @@ config MACB
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source "drivers/net/arm/Kconfig"
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+config IFXMIPS_MII0
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+ tristate "Infineon IFXMips eth0 driver"
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+ depends on IFXMIPS
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+ help
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+ Support for the MII0 inside the IFXMips SOC
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+
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config AX88796
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tristate "ASIX AX88796 NE2000 clone support"
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depends on ARM || MIPS || SUPERH
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--- a/drivers/serial/Kconfig
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+++ b/drivers/serial/Kconfig
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@@ -1334,6 +1334,14 @@ config SERIAL_OF_PLATFORM
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Currently, only 8250 compatible ports are supported, but
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others can easily be added.
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+config SERIAL_IFXMIPS
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+ bool "IFXMips serial driver"
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+ depends on IFXMIPS
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+ select SERIAL_CORE
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+ select SERIAL_CORE_CONSOLE
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+ help
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+ Driver for the ifxmipss built in ASC hardware
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+
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config SERIAL_QE
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tristate "Freescale QUICC Engine serial port support"
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depends on QUICC_ENGINE
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--- a/drivers/serial/Makefile
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+++ b/drivers/serial/Makefile
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@@ -68,3 +68,4 @@ obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_s
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obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
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obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
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obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
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+obj-$(CONFIG_SERIAL_IFXMIPS) += ifxmips_asc.o
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--- a/drivers/watchdog/Makefile
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+++ b/drivers/watchdog/Makefile
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@@ -97,6 +97,7 @@ obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
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obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
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obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
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obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
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+obj-$(CONFIG_IFXMIPS_WDT) += ifxmips_wdt.o
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# PARISC Architecture
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--- a/drivers/net/Makefile
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+++ b/drivers/net/Makefile
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@@ -256,4 +256,4 @@ obj-$(CONFIG_NETXEN_NIC) += netxen/
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obj-$(CONFIG_NIU) += niu.o
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obj-$(CONFIG_VIRTIO_NET) += virtio_net.o
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obj-$(CONFIG_SFC) += sfc/
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-
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+obj-$(CONFIG_IFXMIPS_MII0) += ifxmips_mii0.o
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--- a/drivers/crypto/Kconfig
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+++ b/drivers/crypto/Kconfig
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@@ -9,6 +9,9 @@ menuconfig CRYPTO_HW
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If you say N, all options in this submenu will be skipped and disabled.
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if CRYPTO_HW
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+config CRYPTO_DEV_IFXMIPS
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+ tristate "Support for IFXMIPS Data Encryption Unit"
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+ depends on IFXMIPS
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config CRYPTO_DEV_PADLOCK
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tristate "Support for VIA PadLock ACE"
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--- a/drivers/crypto/Makefile
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+++ b/drivers/crypto/Makefile
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@@ -4,3 +4,4 @@ obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-
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obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
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obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
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obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
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+obj-$(CONFIG_CRYPTO_DEV_IFXMIPS) += ifxdeu-aes.o ifxdeu-des.o ifxdeu-dma.o ifxdeu-generic.o ifxdeu-md5.o ifxdeu-sha1.o
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--- a/drivers/usb/host/Kconfig
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+++ b/drivers/usb/host/Kconfig
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@@ -305,3 +305,10 @@ config SUPERH_ON_CHIP_R8A66597
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help
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This driver enables support for the on-chip R8A66597 in the
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SH7366 and SH7723 processors.
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+
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+config USB_DWC_HCD
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+ tristate "IFXMIPS USB Host Controller Driver"
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+ depends on USB && IFXMIPS
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+ default y
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+ help
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+ Danube USB Host Controller
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--- a/drivers/leds/Kconfig
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+++ b/drivers/leds/Kconfig
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@@ -153,6 +153,12 @@ config LEDS_CLEVO_MAIL
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To compile this driver as a module, choose M here: the
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module will be called leds-clevo-mail.
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+config LEDS_IFXMIPS
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+ tristate "LED Support for IFXMIPS LEDs"
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+ depends on LEDS_CLASS && IFXMIPS
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+ help
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+ This option enables support for the CM-X270 LEDs.
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+
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comment "LED Triggers"
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config LEDS_TRIGGERS
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--- a/drivers/leds/Makefile
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+++ b/drivers/leds/Makefile
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@@ -22,6 +22,7 @@ obj-$(CONFIG_LEDS_CM_X270)
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obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o
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obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o
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obj-$(CONFIG_LEDS_FSG) += leds-fsg.o
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+obj-$(CONFIG_LEDS_IFXMIPS) += leds-ifxmips.o
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# LED Triggers
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obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o
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--- a/drivers/watchdog/Kconfig
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+++ b/drivers/watchdog/Kconfig
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@@ -683,6 +683,12 @@ config TXX9_WDT
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help
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Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
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+config IFXMIPS_WDT
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+ bool "IFXMips watchdog"
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+ depends on IFXMIPS
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+ help
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+ Hardware driver for the IFXMIPS Watchdog Timer.
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+
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# PARISC Architecture
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# POWERPC Architecture
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@@ -1,13 +0,0 @@
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--- a/drivers/mtd/chips/cfi_cmdset_0002.c
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+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
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@@ -1041,7 +1041,9 @@ static int __xipram do_write_oneword(str
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int retry_cnt = 0;
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adr += chip->start;
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-
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+#ifdef CONFIG_IFXMIPS
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+ adr ^= 2;
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+#endif
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spin_lock(chip->mutex);
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ret = get_chip(map, chip, adr, FL_WRITING);
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if (ret) {
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@@ -1,11 +0,0 @@
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--- a/arch/mips/mm/cache.c
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+++ b/arch/mips/mm/cache.c
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@@ -50,6 +50,8 @@ void (*_dma_cache_wback)(unsigned long s
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void (*_dma_cache_inv)(unsigned long start, unsigned long size);
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EXPORT_SYMBOL(_dma_cache_wback_inv);
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+EXPORT_SYMBOL(_dma_cache_wback);
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+EXPORT_SYMBOL(_dma_cache_inv);
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#endif /* CONFIG_DMA_NONCOHERENT */
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Block a user