mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-19 23:57:08 +03:00
[ppc40x] add driver for the CF slot of the Magicbox v2/OpenRB boards
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16910 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
5850aef158
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323
target/linux/ppc40x/patches-2.6.30/100-magicbox-ide-driver.patch
Normal file
323
target/linux/ppc40x/patches-2.6.30/100-magicbox-ide-driver.patch
Normal file
@ -0,0 +1,323 @@
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--- a/drivers/ide/Kconfig
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+++ b/drivers/ide/Kconfig
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@@ -717,6 +717,11 @@ config BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
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depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX
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endchoice
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+config BLK_DEV_IDE_MAGICBOX
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+ tristate "Magicbox CF card support"
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+ depends on MAGICBOXV2 || OPENRB_LIGHT
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+ select IDE_XFER_MODE
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+
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config BLK_DEV_IDE_TX4938
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tristate "TX4938 internal IDE support"
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depends on SOC_TX4938
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--- a/drivers/ide/Makefile
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+++ b/drivers/ide/Makefile
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@@ -113,6 +113,7 @@ obj-$(CONFIG_BLK_DEV_IDE_RAPIDE) += rapi
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obj-$(CONFIG_BLK_DEV_PALMCHIP_BK3710) += palm_bk3710.o
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obj-$(CONFIG_BLK_DEV_IDE_AU1XXX) += au1xxx-ide.o
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+obj-$(CONFIG_BLK_DEV_IDE_MAGICBOX) += magicbox_ide.o
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obj-$(CONFIG_BLK_DEV_IDE_TX4938) += tx4938ide.o
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obj-$(CONFIG_BLK_DEV_IDE_TX4939) += tx4939ide.o
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--- /dev/null
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+++ b/drivers/ide/magicbox_ide.c
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@@ -0,0 +1,296 @@
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+/*
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+ * IDE driver for the MagicBox 2.0 onboard CompactFlash slot.
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+ *
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+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * Based on the original driver by Wojtek Kaniewski <wojtekka@toxygen.net>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#include <linux/types.h>
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+#include <linux/ioport.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/of_platform.h>
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+#include <linux/ide.h>
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+
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+#include <asm/dcr-native.h>
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+
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+#define DRV_DESC "IDE driver for Magicbox 2.0 onboard CF slot"
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+#define DRV_NAME "magicbox_cf"
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+
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+static inline u8 magicbox_ide_inb(unsigned long port)
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+{
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+ return (u8) (readw((void __iomem *) port) >> 8) & 0xff;
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+}
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+
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+static inline void magicbox_ide_outb(u8 value, unsigned long port)
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+{
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+ writew(value << 8, (void __iomem *) port);
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+}
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+
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+static inline void magicbox_ide_insw(unsigned long port, void *addr, u32 count)
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+{
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+ u16 *ptr;
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+
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+ for (ptr = addr; count--; ptr++)
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+ *ptr = readw((void __iomem *) port);
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+}
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+
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+static inline void magicbox_ide_insl(unsigned long port, void *addr, u32 count)
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+{
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+ u32 *ptr;
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+
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+ for (ptr = addr; count--; ptr++)
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+ *ptr = readl((void __iomem *) port);
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+}
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+
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+static inline void magicbox_ide_outsw(unsigned long port, void *addr,
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+ u32 count)
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+{
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+ u16 *ptr;
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+
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+ for (ptr = addr; count--; ptr++)
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+ writew(*ptr, (void __iomem *) port);
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+}
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+
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+static inline void magicbox_ide_outsl(unsigned long port, void *addr,
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+ u32 count)
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+{
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+ u32 *ptr;
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+
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+ for (ptr = addr; count--; ptr++)
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+ writel(*ptr, (void __iomem *) port);
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+}
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+
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+static void magicbox_ide_exec_command(ide_hwif_t *hwif, u8 cmd)
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+{
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+ magicbox_ide_outb(cmd, hwif->io_ports.command_addr);
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+}
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+
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+static u8 magicbox_ide_read_status(ide_hwif_t *hwif)
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+{
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+ return magicbox_ide_inb(hwif->io_ports.status_addr);
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+}
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+
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+static u8 magicbox_ide_read_altstatus(ide_hwif_t *hwif)
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+{
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+ return magicbox_ide_inb(hwif->io_ports.ctl_addr);
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+}
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+
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+static void magicbox_ide_write_devctl(ide_hwif_t *hwif, u8 ctl)
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+{
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+ magicbox_ide_outb(ctl, hwif->io_ports.ctl_addr);
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+}
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+
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+static void magicbox_ide_tf_load(ide_drive_t *drive, struct ide_taskfile *tf,
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+ u8 valid)
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+{
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+ struct ide_io_ports *io_ports = &drive->hwif->io_ports;
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+
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+ if (valid & IDE_VALID_FEATURE)
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+ magicbox_ide_outb(tf->feature, io_ports->feature_addr);
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+ if (valid & IDE_VALID_NSECT)
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+ magicbox_ide_outb(tf->nsect, io_ports->nsect_addr);
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+ if (valid & IDE_VALID_LBAL)
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+ magicbox_ide_outb(tf->lbal, io_ports->lbal_addr);
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+ if (valid & IDE_VALID_LBAM)
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+ magicbox_ide_outb(tf->lbam, io_ports->lbam_addr);
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+ if (valid & IDE_VALID_LBAH)
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+ magicbox_ide_outb(tf->lbah, io_ports->lbah_addr);
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+
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+ if (valid & IDE_VALID_DEVICE)
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+ magicbox_ide_outb(tf->device, io_ports->device_addr);
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+}
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+
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+static void magicbox_ide_tf_read(ide_drive_t *drive, struct ide_taskfile *tf,
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+ u8 valid)
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+{
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+ struct ide_io_ports *io_ports = &drive->hwif->io_ports;
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+
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+ if (valid & IDE_VALID_NSECT)
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+ tf->nsect = magicbox_ide_inb(io_ports->nsect_addr);
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+ if (valid & IDE_VALID_LBAL)
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+ tf->lbal = magicbox_ide_inb(io_ports->lbal_addr);
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+ if (valid & IDE_VALID_LBAM)
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+ tf->lbam = magicbox_ide_inb(io_ports->lbam_addr);
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+ if (valid & IDE_VALID_LBAH)
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+ tf->lbah = magicbox_ide_inb(io_ports->lbah_addr);
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+ if (valid & IDE_VALID_DEVICE)
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+ tf->device = magicbox_ide_inb(io_ports->device_addr);
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+}
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+
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+static void magicbox_ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
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+ void *buf, unsigned int len)
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+{
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+ unsigned long port = drive->hwif->io_ports.data_addr;
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+
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+ len++;
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+
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+ if (drive->io_32bit) {
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+ magicbox_ide_insl(port, buf, len / 4);
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+
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+ if ((len & 3) >= 2)
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+ magicbox_ide_insw(port, (u8 *)buf + (len & ~3), 1);
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+ } else {
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+ magicbox_ide_insw(port, buf, len / 2);
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+ }
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+}
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+
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+static void magicbox_ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
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+ void *buf, unsigned int len)
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+{
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+ unsigned long port = drive->hwif->io_ports.data_addr;
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+
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+ len++;
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+
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+ if (drive->io_32bit) {
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+ magicbox_ide_outsl(port, buf, len / 4);
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+
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+ if ((len & 3) >= 2)
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+ magicbox_ide_outsw(port, (u8 *)buf + (len & ~3), 1);
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+ } else {
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+ magicbox_ide_outsw(port, buf, len / 2);
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+ }
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+}
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+
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+static void magicbox_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
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+{
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+}
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+
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+static u8 magicbox_ide_cable_detect(ide_hwif_t *hwif)
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+{
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+ return ATA_CBL_PATA40;
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+}
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+
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+static const struct ide_tp_ops magicbox_ide_tp_ops = {
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+ .exec_command = magicbox_ide_exec_command,
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+ .read_status = magicbox_ide_read_status,
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+ .read_altstatus = magicbox_ide_read_altstatus,
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+ .write_devctl = magicbox_ide_write_devctl,
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+
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+ .dev_select = ide_dev_select,
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+ .tf_load = magicbox_ide_tf_load,
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+ .tf_read = magicbox_ide_tf_read,
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+
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+ .input_data = magicbox_ide_input_data,
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+ .output_data = magicbox_ide_output_data,
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+};
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+
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+static const struct ide_port_ops magicbox_ide_port_ops = {
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+ .set_pio_mode = magicbox_ide_set_pio_mode,
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+ .cable_detect = magicbox_ide_cable_detect,
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+};
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+
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+static const struct ide_port_info magicbox_ide_port_info = {
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+ .name = DRV_NAME,
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+ .chipset = ide_generic,
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+ .tp_ops = &magicbox_ide_tp_ops,
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+ .port_ops = &magicbox_ide_port_ops,
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+ .host_flags = IDE_HFLAG_SINGLE |
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+ IDE_HFLAG_NO_DMA |
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+ IDE_HFLAG_MMIO |
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+ IDE_HFLAG_UNMASK_IRQS,
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+ .pio_mask = ATA_PIO4,
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+};
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+
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+static inline void magicbox_ide_setup_hw(hw_regs_t *hw, u16 __iomem *base,
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+ u16 __iomem *ctrl, int irq)
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+{
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+ unsigned long port = (unsigned long) base;
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+ int i;
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+
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+ memset(hw, 0, sizeof(*hw));
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+ for (i = 0; i <= 7; i++)
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+ hw->io_ports_array[i] = port + i * 2;
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+
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+ /*
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+ * the IDE control register is at ATA address 6,
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+ * with CS1 active instead of CS0
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+ */
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+ hw->io_ports.ctl_addr = (unsigned long)ctrl + (6 * 2);
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+}
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+
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+static int __devinit magicbox_ide_of_probe(struct of_device *op,
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+ const struct of_device_id *match)
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+{
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+ hw_regs_t hw;
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+ hw_regs_t *hws[] = { &hw, NULL, NULL, NULL };
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+ struct ide_host *host;
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+ u16 __iomem *base;
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+ u16 __iomem *ctrl;
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+ int irq;
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+ int ret = 0;
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+
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+ irq = irq_of_parse_and_map(op->node, 0);
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+ if (irq < 0) {
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+ dev_err(&op->dev, "invalid irq\n");
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+ ret = -EINVAL;
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+ goto err_exit;
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+ }
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+
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+ base = of_iomap(op->node, 0);
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+ if (base == NULL) {
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+ ret = -ENOMEM;
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+ goto err_exit;
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+ }
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+
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+ ctrl = of_iomap(op->node, 1);
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+ if (ctrl == NULL) {
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+ ret = -ENOMEM;
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+ goto err_unmap_base;
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+ }
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+
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+ magicbox_ide_setup_hw(&hw, base, ctrl, irq);
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+
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+ hw.dev = &op->dev;
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+ hw.irq = irq;
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+ hw.chipset = ide_generic;
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+ hw.ack_intr = NULL;
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+
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+ ret = ide_host_add(&magicbox_ide_port_info, hws, &host);
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+ if (ret)
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+ goto err_unmap_ctrl;
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+
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+ dev_set_drvdata(&op->dev, host);
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+
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+ return 0;
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+
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+ err_unmap_ctrl:
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+ iounmap(ctrl);
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+ err_unmap_base:
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+ iounmap(base);
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+ err_exit:
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+ return ret;
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+}
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+
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+static struct of_device_id magicbox_ide_of_match[] = {
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+ { .compatible = "magicbox-cf", },
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+ {},
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+};
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+
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+static struct of_platform_driver magicbox_ide_of_platform_driver = {
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+ .owner = THIS_MODULE,
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+ .name = DRV_NAME,
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+ .match_table = magicbox_ide_of_match,
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+ .probe = magicbox_ide_of_probe,
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+ .driver = {
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+ .name = DRV_NAME,
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+ .owner = THIS_MODULE,
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+ },
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+};
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+
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+static int __init magicbox_ide_init(void)
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+{
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+ return of_register_platform_driver(&magicbox_ide_of_platform_driver);
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+}
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+
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+module_init(magicbox_ide_init);
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+
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+MODULE_DESCRIPTION(DRV_DESC);
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+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
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+MODULE_LICENSE("GPL v2");
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+MODULE_DEVICE_TABLE(of, magicbox_ide_of_match);
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@ -0,0 +1,12 @@
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--- a/arch/powerpc/boot/dcr.h
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+++ b/arch/powerpc/boot/dcr.h
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@@ -57,6 +57,9 @@ static const unsigned long sdram_bxcr[]
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#define EBC_BXCR_BU_WO 0x00010000
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#define EBC_BXCR_BU_RW 0x00018000
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#define EBC_BXCR_BW 0x00006000
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+#define EBC_BXCR_BW_8 0x00000000
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+#define EBC_BXCR_BW_16 0x00002000
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+#define EBC_BXCR_BW_32 0x00006000
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#define EBC_B0AP 0x10
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#define EBC_B1AP 0x11
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#define EBC_B2AP 0x12
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@ -0,0 +1,39 @@
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--- a/arch/powerpc/boot/cuboot-openrb-light.c
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+++ b/arch/powerpc/boot/cuboot-openrb-light.c
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@@ -22,8 +22,36 @@
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static bd_t bd;
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+static void fixup_cf_card(void)
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+{
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+#define DCRN_CPC0_PCI_BASE 0xf9
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+#define CF_CS0_BASE 0xff100000
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+#define CF_CS1_BASE 0xff200000
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+
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+ /* Turn on PerWE instead of PCIsomething */
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+ mtdcr(DCRN_CPC0_PCI_BASE,
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+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
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+
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+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+#undef DCRN_CPC0_PCI_BASE
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+#undef CF_CS0_BASE
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+#undef CF_CS1_BASE
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+}
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+
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static void openrb_light_fixups(void)
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{
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+ fixup_cf_card();
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ibm405ep_fixup_clocks(33333000);
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ibm4xx_sdram_fixup_memsize();
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dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
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@ -0,0 +1,17 @@
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--- a/arch/powerpc/boot/dts/openrb-light.dts
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+++ b/arch/powerpc/boot/dts/openrb-light.dts
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@@ -177,6 +177,14 @@
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*/
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clock-frequency = <0>; /* Filled in by zImage */
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+ cf_card@ff100000 {
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+ compatible = "magicbox-cf";
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+ reg = <0x00000000 0xff100000 0x00001000
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+ 0x00000000 0xff200000 0x00001000>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
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+ };
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+
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nor_flash@ff800000 {
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compatible = "cfi-flash";
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bank-width = <2>;
|
@ -0,0 +1,47 @@
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--- a/arch/powerpc/boot/cuboot-magicboxv2.c
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+++ b/arch/powerpc/boot/cuboot-magicboxv2.c
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@@ -2,6 +2,7 @@
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* Old U-boot compatibility for Magicbox v2
|
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*
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* Author: Imre Kaloz <kaloz@openwrt.org>
|
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+ * Gabor Juhos <juhosg@openwrt.org>
|
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*
|
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
@@ -22,8 +23,36 @@
|
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|
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static bd_t bd;
|
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+static void fixup_cf_card(void)
|
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+{
|
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+#define DCRN_CPC0_PCI_BASE 0xf9
|
||||
+#define CF_CS0_BASE 0xff100000
|
||||
+#define CF_CS1_BASE 0xff200000
|
||||
+
|
||||
+ /* Turn on PerWE instead of PCIsomething */
|
||||
+ mtdcr(DCRN_CPC0_PCI_BASE,
|
||||
+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
|
||||
+
|
||||
+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
|
||||
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
|
||||
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
|
||||
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
|
||||
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
|
||||
+
|
||||
+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
|
||||
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
|
||||
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
|
||||
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
|
||||
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
|
||||
+
|
||||
+#undef DCRN_CPC0_PCI_BASE
|
||||
+#undef CF_CS0_BASE
|
||||
+#undef CF_CS1_BASE
|
||||
+}
|
||||
+
|
||||
static void magicboxv2_fixups(void)
|
||||
{
|
||||
+ fixup_cf_card();
|
||||
ibm405ep_fixup_clocks(25000000);
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
|
@ -0,0 +1,25 @@
|
||||
--- a/arch/powerpc/boot/dts/magicboxv2.dts
|
||||
+++ b/arch/powerpc/boot/dts/magicboxv2.dts
|
||||
@@ -2,6 +2,7 @@
|
||||
* Device Tree Source for Magicbox v2
|
||||
*
|
||||
* Copyright 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* Based on walnut.dts
|
||||
*
|
||||
@@ -183,6 +184,14 @@
|
||||
*/
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
+ cf_card@ff100000 {
|
||||
+ compatible = "magicbox-cf";
|
||||
+ reg = <0x00000000 0xff100000 0x00001000
|
||||
+ 0x00000000 0xff200000 0x00001000>;
|
||||
+ interrupt-parent = <&UIC0>;
|
||||
+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
|
||||
+ };
|
||||
+
|
||||
nor_flash@ffc00000 {
|
||||
compatible = "cfi-flash";
|
||||
bank-width = <2>;
|
Loading…
Reference in New Issue
Block a user