uboot-xburst: update to 2012.10-rc2

package/boot/uboot-xburst/Makefile

@@ -9,13 +9,13 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=u-boot
-PKG_VERSION:=2009.11
+PKG_VERSION:=2012.10-rc2
 PKG_RELEASE:=1
 
 PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
-PKG_MD5SUM:=
+PKG_MD5SUM:=451c07271940016cec6f5ad8a155263b
 PKG_TARGETS:=bin
 
 include $(INCLUDE_DIR)/package.mk
@@ -30,20 +30,7 @@ define uboot/qi_lb60
   TITLE:=U-boot for the qi_lb60 board
 endef
 
-define uboot/avt2
+UBOOTS:=qi_lb60
-  TITLE:=U-boot for the avt2 board
-endef
-
-define uboot/sakc
-  TITLE:=U-boot for the sakc board
-endef
-
-define uboot/n516
-  TITLE:=U-boot for the N516 e-book reader
-  CONFIG:=n516_nand
-endef
-
-UBOOTS:=qi_lb60 n516 avt2 sakc
 
 define Package/uboot/template
 define Package/uboot-xburst-$(1)
@@ -51,7 +38,7 @@ define Package/uboot-xburst-$(1)
   CATEGORY:=Boot Loaders
   DEPENDS:=@TARGET_xburst
   TITLE:=$(2)
-  URL:=http://www.denx.de/wiki/U-Boot
+  URL:=http://www.denx.de/wiki/UBoot/WebHome
   VARIANT:=$(1)
 endef
 endef
@@ -66,15 +53,9 @@ endef
 ifdef BUILD_VARIANT
 $(eval $(call uboot/$(BUILD_VARIANT)))
 UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
-UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_VARIANT)-u-boot.bin)
+UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_BARIANT)-u-boot.bin)
 endif
 
-define Build/Prepare
-	$(call Build/Prepare/Default)
-	$(CP) ./files/* $(PKG_BUILD_DIR)
-	find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
-endef
-
 define Build/Configure
 	$(MAKE) -C $(PKG_BUILD_DIR) \
 		$(UBOOT_CONFIG)_config
@@ -87,8 +68,8 @@ endef
 
 define Package/uboot/install/template
 define Package/uboot-xburst-$(1)/install
-	$(INSTALL_DIR) $$(1)
+	$(CP) $(PKG_BUILD_DIR)/u-boot-xburst.bin $(BIN_DIR)/$(2)
-	$(CP) $(PKG_BUILD_DIR)/u-boot-nand.bin $(BIN_DIR)/$(2)
+	rmdir $$(1)
 endef
 endef
 

package/boot/uboot-xburst/files/board/n516/Makefile

@@ -1,40 +0,0 @@
-#
-# (C) Copyright 2006
-# Ingenic Semiconductor, <jlwei@ingenic.cn>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	= $(BOARD).o flash.o
-
-OBJS	= $(addprefix $(obj),$(COBJS))
-SOBJS	= 
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) crv $@ $(OBJS) $(SOBJS)
-
-#########################################################################
-
-$(obj).depend:	Makefile $(SOBJS:.o=.S) $(COBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(COBJS:.o=.c) > $@
-
-sinclude $(obj).depend
-
-#########################################################################

package/boot/uboot-xburst/files/board/n516/config.mk

@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2006
-# Ingenic Semiconductor, <jlwei@ingenic.cn>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Hanvon n516 e-book, MIPS32 core
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-# ROM version
-TEXT_BASE = 0x88000000
-
-# RAM version
-#TEXT_BASE = 0x80100000
-endif

package/boot/uboot-xburst/files/board/n516/flash.c

@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
-	return (0);
-}
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	printf ("flash_erase not implemented\n");
-	return 0;
-}
-
-void flash_print_info (flash_info_t * info)
-{
-	printf ("flash_print_info not implemented\n");
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	printf ("write_buff not implemented\n");
-	return (-1);
-}

package/boot/uboot-xburst/files/board/n516/n516.c

@@ -1,126 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/mipsregs.h>
-#include <asm/jz4740.h>
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
-void _machine_restart(void)
-{
-	__wdt_select_extalclk();
-	__wdt_select_clk_div64();
-	__wdt_set_data(100);
-	__wdt_set_count(0);
-	__tcu_start_wdt_clock();
-	__wdt_start();
-	while(1);
-
-}
-
-static void gpio_init(void)
-{
-
-	REG_GPIO_PXPES(0) = 0xffffffff;
-	REG_GPIO_PXPES(1) = 0xffffffff;
-	REG_GPIO_PXPES(2) = 0xffffffff;
-	REG_GPIO_PXPES(3) = 0xffffffff;
-
-	/*
-	 * Initialize NAND Flash Pins
-	 */
-	__gpio_as_nand();
-
-	/*
-	 * Initialize SDRAM pins
-	 */
-	__gpio_as_sdram_32bit();
-
-	/*
-	 * Initialize UART0 pins
-	 */
-	__gpio_as_uart0();
-
-	/*
-	 * Initialize MSC pins
-	 */
-	__gpio_as_msc();
-
-	/*
-	 * Initialize LCD pins
-	 */
-	__gpio_as_lcd_16bit();
-
-	/*
-	 * Initialize Other pins
-	 */
-	__gpio_as_output(GPIO_SD_VCC_EN_N);
-	__gpio_clear_pin(GPIO_SD_VCC_EN_N);
-
-	__gpio_as_input(GPIO_SD_CD_N);
-	__gpio_disable_pull(GPIO_SD_CD_N);
-
-	__gpio_as_output(GPIO_DISP_OFF_N);
-
-	__gpio_as_output(GPIO_LED_EN);
-	__gpio_set_pin(GPIO_LED_EN);
-
-	__gpio_as_input(127);
-}
-
-static void cpm_init(void)
-{
-	__cpm_stop_ipu();
-	__cpm_stop_cim();
-	__cpm_stop_i2c();
-	__cpm_stop_ssi();
-	__cpm_stop_uart1();
-	__cpm_stop_sadc();
-	__cpm_stop_uhc();
-	__cpm_stop_udc();
-	__cpm_stop_aic1();
-	__cpm_stop_aic2();
-	__cpm_suspend_udcphy();
-	__cpm_suspend_usbphy();
-}
-
-//----------------------------------------------------------------------
-// board early init routine
-
-void board_early_init(void)
-{
-	gpio_init();
-	cpm_init();
-}
-
-//----------------------------------------------------------------------
-// U-Boot common routines
-
-int checkboard (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	printf("Board: Hanvon n516 e-book (CPU Speed %d MHz)\n",
-	       gd->cpu_clk/1000000);
-
-	return 0; /* success */
-}

package/boot/uboot-xburst/files/board/n516/u-boot-nand.lds

@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	_gp = ALIGN(16);
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata) }
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) }
-	uboot_end = .;
-}

package/boot/uboot-xburst/files/board/n516/u-boot.lds

@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	_gp = ALIGN(16);
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata) }
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) }
-	uboot_end = .;
-}

package/boot/uboot-xburst/files/board/nanonote/Makefile

@@ -1,38 +0,0 @@
-#
-# (C) Copyright 2006
-# Ingenic Semiconductor, <jlwei@ingenic.cn>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).a
-
-OBJS	= $(BOARD).o
-SOBJS	=
-
-$(LIB):	.depend $(OBJS) $(SOBJS)
-	$(AR) crv $@ $(OBJS) $(SOBJS)
-
-#########################################################################
-
-.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################

package/boot/uboot-xburst/files/board/nanonote/config.mk

@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2006 Qi Hardware, Inc.
-# Author: Xiangfu Liu <xiangfu.z@gmail.com>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
-#
-
-ifndef TEXT_BASE
-# ROM version
-# TEXT_BASE = 0x88000000
-
-# RAM version
-TEXT_BASE = 0x80100000
-endif

package/boot/uboot-xburst/files/board/nanonote/nanonote.c

@@ -1,123 +0,0 @@
-/*
- * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 3 of the License, or (at your option) any later version.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/mipsregs.h>
-#include <asm/jz4740.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void gpio_init(void)
-{
-	/*
-	 * Initialize NAND Flash Pins
-	 */
-	__gpio_as_nand();
-
-	/*
-	 * Initialize SDRAM pins
-	 */
-	__gpio_as_sdram_32bit();
-
-	/*
-	 * Initialize LCD pins
-	 */
-	__gpio_as_lcd_8bit();
-
-	/*
-	 * Initialize MSC pins
-	 */
-	__gpio_as_msc();
-
-	/*
-	 * Initialize Other pins
-	 */
-	unsigned int i;
-	for (i = 0; i < 7; i++){
-		__gpio_as_input(GPIO_KEYIN_BASE + i);
-		__gpio_enable_pull(GPIO_KEYIN_BASE + i);
-	}
-
-	for (i = 0; i < 8; i++) {
-		__gpio_as_output(GPIO_KEYOUT_BASE + i);
-		__gpio_clear_pin(GPIO_KEYOUT_BASE + i);
-	}
-
-	/*
-	 * Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the
-	 * same gpio, init the gpio as uart0 cause a keyboard bug. so for
-	 * end user we disable the uart0
-	 */
-	if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){
-		/* if pressed [S] */
-		printf("[S] pressed, enable UART0\n");
-		gd->boot_option = 5;
-		__gpio_as_uart0();
-	} else {
-		printf("[S] not pressed, disable UART0\n");
-		__gpio_as_input(GPIO_KEYIN_8);
-		__gpio_enable_pull(GPIO_KEYIN_8);
-	}
-
-	__gpio_as_output(GPIO_AUDIO_POP);
-	__gpio_set_pin(GPIO_AUDIO_POP);
-
-	__gpio_as_output(GPIO_LCD_CS);
-	__gpio_clear_pin(GPIO_LCD_CS);
-
-	__gpio_as_output(GPIO_AMP_EN);
-	__gpio_clear_pin(GPIO_AMP_EN);
-
-	__gpio_as_output(GPIO_SDPW_EN);
-	__gpio_disable_pull(GPIO_SDPW_EN);
-	__gpio_clear_pin(GPIO_SDPW_EN);
-
-	__gpio_as_input(GPIO_SD_DETECT);
-	__gpio_disable_pull(GPIO_SD_DETECT);
-
-	__gpio_as_input(GPIO_USB_DETECT);
-	__gpio_enable_pull(GPIO_USB_DETECT);
-
-	if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) {
-		printf("[M] pressed, boot from sd card\n");
-		gd->boot_option = 1;
-	}
-}
-
-static void cpm_init(void)
-{
-	__cpm_stop_ipu();
-	__cpm_stop_cim();
-	__cpm_stop_i2c();
-	__cpm_stop_ssi();
-	__cpm_stop_uart1();
-	__cpm_stop_sadc();
-	__cpm_stop_uhc();
-	__cpm_stop_udc();
-	__cpm_stop_aic1();
-/*	__cpm_stop_aic2();*/
-}
-
-void board_early_init(void)
-{
-	gpio_init();
-	cpm_init();
-}
-
-/* U-Boot common routines */
-
-int checkboard (void)
-{
-
-	printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %d MHz)\n",
-	       gd->cpu_clk/1000000);
-
-	return 0; /* success */
-}

package/boot/uboot-xburst/files/board/nanonote/u-boot-nand.lds

@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	_gp = ALIGN(16);
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata) }
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) }
-	uboot_end = .;
-}

package/boot/uboot-xburst/files/board/nanonote/u-boot.lds

@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	_gp = ALIGN(16);
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata) }
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) }
-	uboot_end = .;
-}

package/boot/uboot-xburst/files/board/sakc/Makefile

@@ -1,38 +0,0 @@
-#
-# (C) Copyright 2006
-# Ingenic Semiconductor, <jlwei@ingenic.cn>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).a
-
-OBJS	= $(BOARD).o 
-SOBJS	= 
-
-$(LIB):	.depend $(OBJS) $(SOBJS)
-	$(AR) crv $@ $(OBJS) $(SOBJS)
-
-#########################################################################
-
-.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################

package/boot/uboot-xburst/files/board/sakc/config.mk

@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2006 Qi Hardware, Inc.
-# Author: Xiangfu Liu <xiangfu.z@gmail.com>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# SAKC Board
-#
-
-ifndef TEXT_BASE
-# ROM version
-# TEXT_BASE = 0x88000000
-
-# RAM version
-TEXT_BASE = 0x80100000
-endif

package/boot/uboot-xburst/files/board/sakc/sakc.c

@@ -1,94 +0,0 @@
-/*
- * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 3 of the License, or (at your option) any later version.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/mipsregs.h>
-#include <asm/jz4740.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void gpio_init(void)
-{
-	/*
-	 * Initialize NAND Flash Pins
-	 */
-	__gpio_as_nand();
-
-	/*
-	 * Initialize SDRAM pins
-	 */	
-	__gpio_as_sdram_16bit_4725();
-
-	/*
-	 * Initialize UART0 pins
-	 */
-	__gpio_as_uart0();
-
-	/*
-	 * Initialize LCD pins
-	 */
-	__gpio_as_lcd_18bit();
-
-	/*
-	 * Initialize MSC pins
-	 */
-	__gpio_as_msc();
-
-	/*
-	 * Initialize SSI pins
-	 */
-	__gpio_as_ssi();
-
-	/*
-	 * Initialize I2C pins
-	 */
-	__gpio_as_i2c();
-
-	/*
-	 * Initialize MSC pins
-	 */
-	__gpio_as_msc();
-
-	/*
-	 * Initialize Other pins
-	 */
-	__gpio_as_input(GPIO_SD_DETECT);
-	__gpio_disable_pull(GPIO_SD_DETECT);
-}
-/* TODO SAKC
-static void cpm_init(void)
-{
-	__cpm_stop_ipu();
-	__cpm_stop_cim();
-	__cpm_stop_i2c();
-	__cpm_stop_ssi();
-	__cpm_stop_uart1();
-	__cpm_stop_sadc();
-	__cpm_stop_uhc();
-	__cpm_stop_aic1();
-	__cpm_stop_aic2();
-}*/
-
-void board_early_init(void)
-{
-	gpio_init();
-	//cpm_init(); //TODO SAKC
-}
-
-/* U-Boot common routines */
-
-int checkboard (void)
-{
-
-	printf("Board: SAKC (Ingenic XBurst Jz4725 SoC, Speed %d MHz)\n",
-	       gd->cpu_clk/1000000);
-
-	return 0; /* success */
-}

package/boot/uboot-xburst/files/board/sakc/u-boot-nand.lds

@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	_gp = ALIGN(16);
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata) }
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) }
-	uboot_end = .;
-}

package/boot/uboot-xburst/files/board/sakc/u-boot.lds

@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	_gp = ALIGN(16);
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata) }
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) }
-	uboot_end = .;
-}

package/boot/uboot-xburst/files/cpu/mips/jz4740.c

@@ -1,559 +0,0 @@
-/*
- * Jz4740 common routines
- *
- *  Copyright (c) 2006
- *  Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-#ifdef CONFIG_JZ4740
-#include <common.h>
-#include <command.h>
-#include <asm/jz4740.h>
-
-extern void board_early_init(void);
-
-/* PLL output clock = EXTAL * NF / (NR * NO)
- *
- * NF = FD + 2, NR = RD + 2
- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
- */
-void pll_init(void)
-{
-	register unsigned int cfcr, plcr1;
-	int n2FR[33] = {
-		0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
-		7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
-		9
-	};
-	int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
-	int nf, pllout2;
-
-	cfcr = CPM_CPCCR_CLKOEN |
-		CPM_CPCCR_PCS |
-		(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
-		(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
-		(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
-		(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
-		(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
-
-	pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
-
-	/* Init USB Host clock, pllout2 must be n*48MHz */
-	REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
-
-	nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
-	plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
-		(0 << CPM_CPPCR_PLLN_BIT) |	/* RD=0, NR=2 */
-		(0 << CPM_CPPCR_PLLOD_BIT) |    /* OD=0, NO=1 */
-		(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
-		CPM_CPPCR_PLLEN;                /* enable PLL */
-
-	/* init PLL */
-	REG_CPM_CPCCR = cfcr;
-	REG_CPM_CPPCR = plcr1;
-}
-
-void pll_add_test(int new_freq)
-{
-	register unsigned int cfcr, plcr1;
-	int n2FR[33] = {
-		0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
-		7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
-		9
-	};
-	int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:M:L */
-	int nf, pllout2;
-
-	cfcr = CPM_CPCCR_CLKOEN |
-		(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
-		(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
-		(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
-		(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
-		(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
-
-	pllout2 = (cfcr & CPM_CPCCR_PCS) ? new_freq : (new_freq / 2);
-
-	/* Init UHC clock */
-	REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
-
-	/* nf = new_freq * 2 / CONFIG_SYS_EXTAL; */
-	nf = new_freq / 1000000; /* step length is 1M */
-	plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
-		(10 << CPM_CPPCR_PLLN_BIT) |	/* RD=0, NR=2 */
-		(0 << CPM_CPPCR_PLLOD_BIT) |    /* OD=0, NO=1 */
-		(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
-		CPM_CPPCR_PLLEN;                /* enable PLL */
-
-	/* init PLL */
-	REG_CPM_CPCCR = cfcr;
-	REG_CPM_CPPCR = plcr1;
-}
-
-void calc_clocks_add_test(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	unsigned int pllout;
-	unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
-
-	pllout = __cpm_get_pllout();
-
-	gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
-	gd->sys_clk = pllout / div[__cpm_get_hdiv()];
-	gd->per_clk = pllout / div[__cpm_get_pdiv()];
-	gd->mem_clk = pllout / div[__cpm_get_mdiv()];
-	gd->dev_clk = CONFIG_SYS_EXTAL;
-}
-
-void sdram_add_test(int new_freq)
-{
-	register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
-
-	unsigned int cas_latency_sdmr[2] = {
-		EMC_SDMR_CAS_2,
-		EMC_SDMR_CAS_3,
-	};
-
-	unsigned int cas_latency_dmcr[2] = {
-		1 << EMC_DMCR_TCL_BIT,	/* CAS latency is 2 */
-		2 << EMC_DMCR_TCL_BIT	/* CAS latency is 3 */
-	};
-
-	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
-
-	cpu_clk = new_freq;
-	mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
-
-	REG_EMC_RTCSR = EMC_RTCSR_CKS_DISABLE;
-	REG_EMC_RTCOR = 0;
-	REG_EMC_RTCNT = 0;
-
-	/* Basic DMCR register value. */
-	dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
-		((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
-		(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
-		(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
-		EMC_DMCR_EPIN |
-		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
-
-	/* SDRAM timimg parameters */
-	ns = 1000000000 / mem_clk;
-
-#if 0
-	tmp = SDRAM_TRAS/ns;
-	if (tmp < 4) tmp = 4;
-	if (tmp > 11) tmp = 11;
-	dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
-
-	tmp = SDRAM_RCD/ns;
-	if (tmp > 3) tmp = 3;
-	dmcr |= (tmp << EMC_DMCR_RCD_BIT);
-
-	tmp = SDRAM_TPC/ns;
-	if (tmp > 7) tmp = 7;
-	dmcr |= (tmp << EMC_DMCR_TPC_BIT);
-
-	tmp = SDRAM_TRWL/ns;
-	if (tmp > 3) tmp = 3;
-	dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
-
-	tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
-	if (tmp > 14) tmp = 14;
-	dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
-#else
-	dmcr |= 0xfffc;
-#endif
-
-	/* First, precharge phase */
-	REG_EMC_DMCR = dmcr;
-
-	/* Set refresh registers */
-	tmp = SDRAM_TREF/ns;
-	tmp = tmp/64 + 1;
-	if (tmp > 0xff) tmp = 0xff;
-
-	REG_EMC_RTCOR = tmp;
-	REG_EMC_RTCSR = EMC_RTCSR_CKS_64;	/* Divisor is 64, CKO/64 */
-
-	/* SDRAM mode values */
-	sdmode = EMC_SDMR_BT_SEQ | 
-		 EMC_SDMR_OM_NORMAL |
-		 EMC_SDMR_BL_4 | 
-		 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
-
-	/* precharge all chip-selects */
-	REG8(EMC_SDMR0|sdmode) = 0;
-
-	/* wait for precharge, > 200us */
-	tmp = (cpu_clk / 1000000) * 200;
-	while (tmp--);
-
-	/* enable refresh and set SDRAM mode */
-	REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
-
-	/* write sdram mode register for each chip-select */
-	REG8(EMC_SDMR0|sdmode) = 0;
-
-	/* everything is ok now */
-}
-
-void sdram_init(void)
-{
-	register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
-
-	unsigned int cas_latency_sdmr[2] = {
-		EMC_SDMR_CAS_2,
-		EMC_SDMR_CAS_3,
-	};
-
-	unsigned int cas_latency_dmcr[2] = {
-		1 << EMC_DMCR_TCL_BIT,	/* CAS latency is 2 */
-		2 << EMC_DMCR_TCL_BIT	/* CAS latency is 3 */
-	};
-
-	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
-
-	cpu_clk = CONFIG_SYS_CPU_SPEED;
-	mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
-
-	REG_EMC_BCR = 0;	/* Disable bus release */
-	REG_EMC_RTCSR = 0;	/* Disable clock for counting */
-
-	/* Fault DMCR value for mode register setting*/
-#define SDRAM_ROW0    11
-#define SDRAM_COL0     8
-#define SDRAM_BANK40   0
-
-	dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
-		((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
-		(SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
-		(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
-		EMC_DMCR_EPIN |
-		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
-
-	/* Basic DMCR value */
-	dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
-		((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
-		(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
-		(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
-		EMC_DMCR_EPIN |
-		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
-
-	/* SDRAM timimg */
-	ns = 1000000000 / mem_clk;
-	tmp = SDRAM_TRAS/ns;
-	if (tmp < 4) tmp = 4;
-	if (tmp > 11) tmp = 11;
-	dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
-	tmp = SDRAM_RCD/ns;
-	if (tmp > 3) tmp = 3;
-	dmcr |= (tmp << EMC_DMCR_RCD_BIT);
-	tmp = SDRAM_TPC/ns;
-	if (tmp > 7) tmp = 7;
-	dmcr |= (tmp << EMC_DMCR_TPC_BIT);
-	tmp = SDRAM_TRWL/ns;
-	if (tmp > 3) tmp = 3;
-	dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
-	tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
-	if (tmp > 14) tmp = 14;
-	dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
-
-	/* SDRAM mode value */
-	sdmode = EMC_SDMR_BT_SEQ | 
-		 EMC_SDMR_OM_NORMAL |
-		 EMC_SDMR_BL_4 | 
-		 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
-
-	/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
-	REG_EMC_DMCR = dmcr;
-	REG8(EMC_SDMR0|sdmode) = 0;
-
-	/* Wait for precharge, > 200us */
-	tmp = (cpu_clk / 1000000) * 1000;
-	while (tmp--);
-
-	/* Stage 2. Enable auto-refresh */
-	REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
-
-	tmp = SDRAM_TREF/ns;
-	tmp = tmp/64 + 1;
-	if (tmp > 0xff) tmp = 0xff;
-	REG_EMC_RTCOR = tmp;
-	REG_EMC_RTCNT = 0;
-	REG_EMC_RTCSR = EMC_RTCSR_CKS_64;	/* Divisor is 64, CKO/64 */
-
-	/* Wait for number of auto-refresh cycles */
-	tmp = (cpu_clk / 1000000) * 1000;
-	while (tmp--);
-
- 	/* Stage 3. Mode Register Set */
-	REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
-	REG8(EMC_SDMR0|sdmode) = 0;
-
-        /* Set back to basic DMCR value */
-	REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
-
-	/* everything is ok now */
-}
-
-#ifndef CONFIG_NAND_SPL
-
-static void calc_clocks(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	unsigned int pllout;
-	unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
-
-	pllout = __cpm_get_pllout();
-
-	gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
-	gd->sys_clk = pllout / div[__cpm_get_hdiv()];
-	gd->per_clk = pllout / div[__cpm_get_pdiv()];
-	gd->mem_clk = pllout / div[__cpm_get_mdiv()];
-	gd->dev_clk = CONFIG_SYS_EXTAL;
-}
-
-static void rtc_init(void)
-{
-	unsigned long rtcsta;
-
-	while ( !__rtc_write_ready()) ;
-	__rtc_enable_alarm();	/* enable alarm */
-
-	while ( !__rtc_write_ready())
-		;
-	REG_RTC_RGR   = 0x00007fff; /* type value */
-
-	while ( !__rtc_write_ready())
-		;
-	REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
-
-	while ( !__rtc_write_ready())
-		;
-	REG_RTC_HRCR  = 0x00000fe0; /* reset delay 125ms */
-#if 0
-	while ( !__rtc_write_ready())
-		;
-	rtcsta = REG_RTC_HWRSR;
-	while ( !__rtc_write_ready())
-		;
-	if (rtcsta & 0x33) {
-		if (rtcsta & 0x10) {
-			while ( !__rtc_write_ready())
-				;
-			REG_RTC_RSR = 0x0;
-		}
-		while ( !__rtc_write_ready())
-			;
-		REG_RTC_HWRSR = 0x0;
-	}
-#endif
-}
-
-/*
- * jz4740 board init routine
- */
-int jz_board_init(void)
-{
-	board_early_init();  /* init gpio, pll etc. */
-#ifndef CONFIG_NAND_U_BOOT
-	pll_init();          /* init PLL */
-	sdram_init();        /* init sdram memory */
-#endif
-	calc_clocks();       /* calc the clocks */
-	rtc_init();		/* init rtc on any reset: */
-	return 0;
-}
-
-/* U-Boot common routines */
-phys_size_t initdram(int board_type)
-{
-	u32 dmcr;
-	u32 rows, cols, dw, banks;
-	ulong size;
-
-	dmcr = REG_EMC_DMCR;
-	rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
-	cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
-	dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
-	banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
-
-	size = (1 << (rows + cols)) * dw * banks;
-
-	return size;
-}
-
-/*
- * Timer routines 
- */
-
-#define TIMER_CHAN  0
-#define TIMER_FDATA 0xffff  /* Timer full data value */
-#define TIMER_HZ    CONFIG_SYS_HZ
-
-#define READ_TIMER  REG_TCU_TCNT(TIMER_CHAN)  /* macro to read the 16 bit timer */
-
-static ulong timestamp;
-static ulong lastdec;
-
-void	reset_timer_masked	(void);
-ulong	get_timer_masked	(void);
-void	udelay_masked		(unsigned long usec);
-
-/*
- * timer without interrupts
- */
-
-int timer_init(void)
-{
-	REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
-	REG_TCU_TCNT(TIMER_CHAN) = 0;
-	REG_TCU_TDHR(TIMER_CHAN) = 0;
-	REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
-
-	REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
-	REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
-	REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
-
-	lastdec = 0;
-	timestamp = 0;
-
-	return 0;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void udelay (unsigned long usec)
-{
-	ulong tmo,tmp;
-
-	/* normalize */
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= TIMER_HZ;
-		tmo /= 1000;
-	}
-	else {
-		if (usec >= 1) {
-			tmo = usec * TIMER_HZ;
-			tmo /= (1000*1000);
-		}
-		else
-			tmo = 1;
-	}
-
-	/* check for rollover during this delay */
-	tmp = get_timer (0);
-	if ((tmp + tmo) < tmp )
-		reset_timer_masked();  /* timer would roll over */
-	else
-		tmo += tmp;
-
-	while (get_timer_masked () < tmo);
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;
-	timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;
-
-	if (lastdec <= now) {
-		/* normal mode */
-		timestamp += (now - lastdec);
-	} else {
-		/* we have an overflow ... */
-		timestamp += TIMER_FDATA + now - lastdec;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	/* normalize */
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= TIMER_HZ;
-		tmo /= 1000;
-	} else {
-		if (usec > 1) {
-			tmo = usec * TIMER_HZ;
-			tmo /= (1000*1000);
-		} else {
-			tmo = 1;
-		}
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	return TIMER_HZ;
-}
-
-#endif /* CONFIG_NAND_SPL */
-
-/* End of timer routine. */
-
-#endif

package/boot/uboot-xburst/files/cpu/mips/jz4740_nand.c

@@ -1,199 +0,0 @@
-/*
- * Platform independend driver for JZ4740.
- *
- * Copyright (c) 2007 Ingenic Semiconductor Inc.
- * Author: <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_JZ4740)
-
-#include <nand.h>
-#include <asm/jz4740.h>
-#include <asm/io.h>
-
-#define PAR_SIZE 9
-#define __nand_ecc_enable()    (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST )
-#define __nand_ecc_disable()   (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
-
-#define __nand_select_rs_ecc() (REG_EMC_NFECR |= EMC_NFECR_RS)
-
-#define __nand_rs_ecc_encoding()	(REG_EMC_NFECR |= EMC_NFECR_RS_ENCODING)
-#define __nand_rs_ecc_decoding()	(REG_EMC_NFECR |= EMC_NFECR_RS_DECODING)
-#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
-#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
-
-static void jz_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd->priv;
-	unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
-
-	if (ctrl & NAND_CTRL_CHANGE) {
-		/* Change this to use I/O accessors. */
-		if (ctrl & NAND_NCE)
-			REG_EMC_NFCSR |= EMC_NFCSR_NFCE1; 
-		else
-			REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
-	}
-
-	if (cmd == NAND_CMD_NONE)
-		return;
-
-	if (ctrl & NAND_CLE)
-		nandaddr |= 0x00008000;
-	else /* must be ALE */
-		nandaddr |= 0x00010000;
-
-	writeb(cmd, (uint8_t *)nandaddr);
-}
-
-static int jz_device_ready(struct mtd_info *mtd)
-{
-	int ready;
-	udelay(20);	/* FIXME: add 20us delay */
-	ready = (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0;
-	return ready;
-}
-
-/*
- * EMC setup
- */
-static void jz_device_setup(void)
-{
-	/* Set NFE bit */
-	REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
-	REG_EMC_SMCR1 = 0x094c4400;
-	/* REG_EMC_SMCR3 = 0x04444400; */
-}
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
-	/*
-	 * Don't use "chip" to address the NAND device,
-	 * generate the cs from the address where it is encoded.
-	 */
-}
-
-static int jzsoc_nand_calculate_rs_ecc(struct mtd_info* mtd, const u_char* dat,
-				u_char* ecc_code)
-{
-	volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
-	short i;
-
-	__nand_ecc_encode_sync()
-	__nand_ecc_disable();
-
-	for(i = 0; i < PAR_SIZE; i++)
-		ecc_code[i] = *paraddr++;
-
-	return 0;
-}
-
-static void jzsoc_nand_enable_rs_hwecc(struct mtd_info* mtd, int mode)
-{
- 	__nand_ecc_enable();
-	__nand_select_rs_ecc();
-
-	REG_EMC_NFINTS = 0x0;
-	if (NAND_ECC_READ == mode){
-		__nand_rs_ecc_decoding();
-	}
-	if (NAND_ECC_WRITE == mode){
-		__nand_rs_ecc_encoding();
-	}
-}
-
-/* Correct 1~9-bit errors in 512-bytes data */
-static void jzsoc_rs_correct(unsigned char *dat, int idx, int mask)
-{
-	int i;
-
-	idx--;
-
-	i = idx + (idx >> 3);
-	if (i >= 512)
-		return;
-
-	mask <<= (idx & 0x7);
-
-	dat[i] ^= mask & 0xff;
-	if (i < 511)
-		dat[i+1] ^= (mask >> 8) & 0xff;
-}
-
-static int jzsoc_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
-				 u_char *read_ecc, u_char *calc_ecc)
-{
-	volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
-	short k;
-	u32 stat;
-	/* Set PAR values */
-
-	for (k = 0; k < PAR_SIZE; k++) {
-		*paraddr++ = read_ecc[k];
-	}
-
-	/* Set PRDY */
-	REG_EMC_NFECR |= EMC_NFECR_PRDY;
-
-	/* Wait for completion */
-	__nand_ecc_decode_sync();
-	__nand_ecc_disable();
-
-	/* Check decoding */
-	stat = REG_EMC_NFINTS;
-	if (stat & EMC_NFINTS_ERR) {
-		if (stat & EMC_NFINTS_UNCOR) {
-			printk("Uncorrectable error occurred\n");
-			return -1;
-		}
-		else {
-			u32 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
-			switch (errcnt) {
-			case 4:
-				jzsoc_rs_correct(dat, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
-			case 3:
-				jzsoc_rs_correct(dat, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
-			case 2:
-				jzsoc_rs_correct(dat, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
-			case 1:
-				jzsoc_rs_correct(dat, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
-				return 0;
-			default:
-				break;
-	   		}
-		}
-	}
-	/* no error need to be correct */
-	return 0;
-}
-
-/*
- * Main initialization routine
- */
-int board_nand_init(struct nand_chip *nand)
-{
-	jz_device_setup();
-
-	nand->cmd_ctrl =  jz_hwcontrol;
-	nand->dev_ready = jz_device_ready;
-
-	/* FIXME: should use NAND_ECC_SOFT */
-	nand->ecc.hwctl = jzsoc_nand_enable_rs_hwecc;
-	nand->ecc.correct = jzsoc_nand_rs_correct_data;
-	nand->ecc.calculate = jzsoc_nand_calculate_rs_ecc;
-	nand->ecc.mode = NAND_ECC_HW;
-	nand->ecc.size = 512;
-	nand->ecc.bytes = 9;
-
-	/* 20 us command delay time */
-	nand->chip_delay = 20;
-
-	return 0;
-}
-#endif /* (CONFIG_SYS_CMD_NAND) */

package/boot/uboot-xburst/files/cpu/mips/jz_lcd.c

@@ -1,484 +0,0 @@
-/*
- * JzRISC lcd controller
- *
- * xiangfu liu <xiangfu.z@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Fallowing macro may be used:
- *  CONFIG_LCD                        : LCD support
- *  LCD_BPP                           : Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8
- *  CONFIG_LCD_LOGO                   : show logo
- */
-
-#include <config.h>
-#include <common.h>
-#include <lcd.h>
-
-#include <asm/io.h>               /* virt_to_phys() */
-
-#if defined(CONFIG_LCD) && !defined(CONFIG_SLCD)
-
-#if defined(CONFIG_JZ4740)
-#include <asm/jz4740.h>
-#endif
-
-#include "jz_lcd.h"
-
-
-struct jzfb_info {
-	unsigned int cfg;	/* panel mode and pin usage etc. */
-	unsigned int w;
-	unsigned int h;
-	unsigned int bpp;	/* bit per pixel */
-	unsigned int fclk;	/* frame clk */
-	unsigned int hsw;	/* hsync width, in pclk */
-	unsigned int vsw;	/* vsync width, in line count */
-	unsigned int elw;	/* end of line, in pclk */
-	unsigned int blw;	/* begin of line, in pclk */
-	unsigned int efw;	/* end of frame, in line count */
-	unsigned int bfw;	/* begin of frame, in line count */
-};
-
-static struct jzfb_info jzfb = {
-   #if defined(CONFIG_NANONOTE)
-	MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
-	320, 240, 32, 70, 1, 1, 273, 140, 1, 20
-   #endif
-
-};
-
-/************************************************************************/
-
-vidinfo_t panel_info = {
-#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01)
-	320, 240, LCD_BPP,
-#endif
-};
-
-/*----------------------------------------------------------------------*/
-
-int lcd_line_length;
-
-int lcd_color_fg;
-int lcd_color_bg;
-
-/*
- * Frame buffer memory information
- */
-void *lcd_base;			/* Start of framebuffer memory	*/
-void *lcd_console_address;	/* Start of console buffer	*/
-
-short console_col;
-short console_row;
-
-/*----------------------------------------------------------------------*/
-
-void lcd_ctrl_init (void *lcdbase);
-
-void lcd_enable (void);
-void lcd_disable (void);
-
-/*----------------------------------------------------------------------*/
-
-static int  jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
-static void jz_lcd_desc_init(vidinfo_t *vid);
-static int  jz_lcd_hw_init( vidinfo_t *vid );
-extern int flush_cache_all(void);
-
-#if LCD_BPP == LCD_COLOR8
-void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
-#endif
-#if LCD_BPP == LCD_MONOCHROME
-void lcd_initcolregs (void);
-#endif
-
-/*-----------------------------------------------------------------------*/
-
-void lcd_ctrl_init (void *lcdbase)
-{
-	__lcd_display_pin_init();
-
-	jz_lcd_init_mem(lcdbase, &panel_info);
-	jz_lcd_desc_init(&panel_info);
-	jz_lcd_hw_init(&panel_info);
-
-	__lcd_display_on() ;
-}
-
-/*----------------------------------------------------------------------*/
-#if LCD_BPP == LCD_COLOR8
-void
-lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
-{
-}
-#endif
-/*----------------------------------------------------------------------*/
-
-#if LCD_BPP == LCD_MONOCHROME
-static
-void lcd_initcolregs (void)
-{
-}
-#endif
-
-/*
- * Before enabled lcd controller, lcd registers should be configured correctly.
- */
-
-void lcd_enable (void)
-{
-	REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
-	REG_LCD_CTRL |= 1<<3;    /* LCDCTRL.ENA*/
-}
-
-void lcd_disable (void)
-{
-	REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
-	/* REG_LCD_CTRL |= (1<<3); */  /* LCDCTRL.DIS, quikly disable */
-}
-
-static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
-{
-	u_long palette_mem_size;
-	struct jz_fb_info *fbi = &vid->jz_fb;
-	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
-
-	fbi->screen = (u_long)lcdbase;
-	fbi->palette_size = 256;
-	palette_mem_size = fbi->palette_size * sizeof(u16);
-
-	debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
-	/* locate palette and descs at end of page following fb */
-	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
-
-	return 0;
-}
-
-static void jz_lcd_desc_init(vidinfo_t *vid)
-{
-	struct jz_fb_info * fbi;
-	fbi = &vid->jz_fb;
-	fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
-	fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
-	fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
-
-	#define BYTES_PER_PANEL	 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
-
-	/* populate descriptors */
-	fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
-	fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
-	fbi->dmadesc_fblow->fidr  = 0;
-	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
-
-	fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
-
-	fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); 
-	fbi->dmadesc_fbhigh->fidr = 0;
-	fbi->dmadesc_fbhigh->ldcmd =  BYTES_PER_PANEL / 4; /* length in word */
-
-	fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
-	fbi->dmadesc_palette->fidr  = 0;
-	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
-
-	if( NBITS(vid->vl_bpix) < 12)
-	{
-		/* assume any mode with <12 bpp is palette driven */
-		fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
-		fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
-		/* flips back and forth between pal and fbhigh */
-		fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
-	} else {
-		/* palette shouldn't be loaded in true-color mode */
-		fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
-		fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
-	}
-
-	flush_cache_all();
-}
-
-static int  jz_lcd_hw_init(vidinfo_t *vid)
-{
-	struct jz_fb_info *fbi = &vid->jz_fb;
-	unsigned int val = 0;
-	unsigned int pclk;
-	unsigned int stnH;
-#if defined(CONFIG_MIPS_JZ4740)
-	int pll_div;
-#endif
-
-	/* Setting Control register */
-	switch (jzfb.bpp) {
-	case 1:
-		val |= LCD_CTRL_BPP_1;
-		break;
-	case 2:
-		val |= LCD_CTRL_BPP_2;
-		break;
-	case 4:
-		val |= LCD_CTRL_BPP_4;
-		break;
-	case 8:
-		val |= LCD_CTRL_BPP_8;
-		break;
-	case 15:
-		val |= LCD_CTRL_RGB555;
-	case 16:
-		val |= LCD_CTRL_BPP_16;
-		break;
-#if defined(CONFIG_MIPS_JZ4740)
-	case 17 ... 32:
-		val |= LCD_CTRL_BPP_18_24;	/* target is 4bytes/pixel */
-		break;
-#endif
-	default:
-		printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
-		val |= LCD_CTRL_BPP_16;
-		break;
-	}
-
-	switch (jzfb.cfg & MODE_MASK) {
-	case MODE_STN_MONO_DUAL:
-	case MODE_STN_COLOR_DUAL:
-	case MODE_STN_MONO_SINGLE:
-	case MODE_STN_COLOR_SINGLE:
-		switch (jzfb.bpp) {
-		case 1:
-			/* val |= LCD_CTRL_PEDN; */
-		case 2:
-			val |= LCD_CTRL_FRC_2;
-			break;
-		case 4:
-			val |= LCD_CTRL_FRC_4;
-			break;
-		case 8:
-		default:
-			val |= LCD_CTRL_FRC_16;
-			break;
-		}
-		break;
-	}
-
-	val |= LCD_CTRL_BST_16;		/* Burst Length is 16WORD=64Byte */
-	val |= LCD_CTRL_OFUP;		/* OutFIFO underrun protect */
-
-	switch (jzfb.cfg & MODE_MASK) {
-	case MODE_STN_MONO_DUAL:
-	case MODE_STN_COLOR_DUAL:
-	case MODE_STN_MONO_SINGLE:
-	case MODE_STN_COLOR_SINGLE:
-		switch (jzfb.cfg & STN_DAT_PINMASK) {
-#define align2(n) (n)=((((n)+1)>>1)<<1)
-#define align4(n) (n)=((((n)+3)>>2)<<2)
-#define align8(n) (n)=((((n)+7)>>3)<<3)
-		case STN_DAT_PIN1:
-			/* Do not adjust the hori-param value. */
-			break;
-		case STN_DAT_PIN2:
-			align2(jzfb.hsw);
-			align2(jzfb.elw);
-			align2(jzfb.blw);
-			break;
-		case STN_DAT_PIN4:
-			align4(jzfb.hsw);
-			align4(jzfb.elw);
-			align4(jzfb.blw);
-			break;
-		case STN_DAT_PIN8:
-			align8(jzfb.hsw);
-			align8(jzfb.elw);
-			align8(jzfb.blw);
-			break;
-		}
-		break;
-	}
-
-	REG_LCD_CTRL = val;
-
-	switch (jzfb.cfg & MODE_MASK) {
-	case MODE_STN_MONO_DUAL:
-	case MODE_STN_COLOR_DUAL:
-	case MODE_STN_MONO_SINGLE:
-	case MODE_STN_COLOR_SINGLE:
-		if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
-		    ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
-			stnH = jzfb.h >> 1;
-		else
-			stnH = jzfb.h;
-
-		REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
-		REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
-
-		/* Screen setting */
-		REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
-		REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
-		REG_LCD_DAV = (0 << 16) | (stnH);
-
-		/* AC BIAs signal */
-		REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
-
-		break;
-
-	case MODE_TFT_GEN:
-	case MODE_TFT_SHARP:
-	case MODE_TFT_CASIO:
-	case MODE_TFT_SAMSUNG:
-	case MODE_8BIT_SERIAL_TFT:
-	case MODE_TFT_18BIT:
-		REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
-		REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
-#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
-		REG_LCD_DAV = (0 << 16) | ( jzfb.h );
-#else
-		REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
-#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
-		REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
-		REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
-			| (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
-		break;
-	}
-
-	switch (jzfb.cfg & MODE_MASK) {
-	case MODE_TFT_SAMSUNG:
-	{
-		unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
-		unsigned int rev_s, rev_e, inv_s, inv_e;
-
-		pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
-			(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
-
-		total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
-		tp_s = jzfb.blw + jzfb.w + 1;
-		tp_e = tp_s + 1;
-		/* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
-		ckv_s = tp_s - pclk/(1000000000/4100);
-		ckv_e = tp_s + total;
-		rev_s = tp_s - 11;	/* -11.5 clk */
-		rev_e = rev_s + total;
-		inv_s = tp_s;
-		inv_e = inv_s + total;
-		REG_LCD_CLS = (tp_s << 16) | tp_e;
-		REG_LCD_PS = (ckv_s << 16) | ckv_e;
-		REG_LCD_SPL = (rev_s << 16) | rev_e;
-		REG_LCD_REV = (inv_s << 16) | inv_e;
-		jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
-		break;
-	}
-	case MODE_TFT_SHARP:
-	{
-		unsigned int total, cls_s, cls_e, ps_s, ps_e;
-		unsigned int spl_s, spl_e, rev_s, rev_e;
-		total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
-#if !defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
-		spl_s = 1;
-		spl_e = spl_s + 1;
-		cls_s = 0;
-		cls_e = total - 60;	/* > 4us (pclk = 80ns) */
-		ps_s = cls_s;
-		ps_e = cls_e;
-		rev_s = total - 40;	/* > 3us (pclk = 80ns) */
-		rev_e = rev_s + total;
-		jzfb.cfg |= STFT_PSHI; 
-#else           /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
-		spl_s = total - 5; /* LD */
-		spl_e = total -3;
-		cls_s = 32;	/* CKV */
-		cls_e = 145;
-		ps_s  = 0;      /* OEV */
-		ps_e  = 45;
-		rev_s = 0;	/* POL */
-		rev_e = 0;
-#endif          /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
-		REG_LCD_SPL = (spl_s << 16) | spl_e;
-		REG_LCD_CLS = (cls_s << 16) | cls_e;
-		REG_LCD_PS = (ps_s << 16) | ps_e;
-		REG_LCD_REV = (rev_s << 16) | rev_e;
-		break;
-	}
-	case MODE_TFT_CASIO:
-		break;
-	}
-
-	/* Configure the LCD panel */
-	REG_LCD_CFG = jzfb.cfg;
-
-	/* Timing setting */
-	__cpm_stop_lcd();
-
-	val = jzfb.fclk; /* frame clk */
-	if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
-		pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
-			(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
-	}
-	else {
-		/* serial mode: Hsync period = 3*Width_Pixel */
-		pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
-			(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
-	}
-
-	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
-		pclk = (pclk * 3);
-
-	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
-		pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
-
-	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
-		pclk >>= 1;
-
-	pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
-	pll_div = pll_div ? 1 : 2 ;
-	val = ( __cpm_get_pllout()/pll_div ) / pclk;
-	val--;
-	if ( val > 0x1ff ) {
-		printf("CPM_LPCDR too large, set it to 0x1ff\n");
-		val = 0x1ff;
-	}
-	__cpm_set_pixdiv(val);
-
-	val = pclk * 3 ;	/* LCDClock > 2.5*Pixclock */
-	if ( val > 150000000 ) {
-		printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
-		printf("Change LCDClock to 150MHz\n");
-		val = 150000000;
-	}
-	val = ( __cpm_get_pllout()/pll_div ) / val;
-	val--;
-	if ( val > 0x1f ) {
-		printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
-		val = 0x1f;
-	}
-	__cpm_set_ldiv( val );
-	REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
-
-	__cpm_start_lcd();
-	udelay(1000);
-
-	REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
-
-	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
-		REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
-
-	return 0;
-}
-

package/boot/uboot-xburst/files/cpu/mips/jz_lcd.h

@@ -1,260 +0,0 @@
-/*
- * JzRISC lcd controller
- *
- * xiangfu liu <xiangfu.z@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __JZLCD_H__
-#define __JZLCD_H__
-
-#include <asm/io.h>
-/*
- * change u-boot macro to celinux macro
- */
-/* Chip type */
-#if defined(CONFIG_JZ4740)
-#define CONFIG_MIPS_JZ4740 		1
-#endif
-
-/* board type */
-#if defined(CONFIG_NANONOTE)
-#define CONFIG_MIPS_JZ4740_PI 		1
-#endif
-
-#define mdelay(n) 		udelay((n)*1000)
-
-/*
- * change u-boot macro to celinux macro
- */
-
-#define NR_PALETTE	256
-
-struct lcd_desc{
-	unsigned int next_desc; /* LCDDAx */
-	unsigned int databuf;   /* LCDSAx */
-	unsigned int frame_id;  /* LCDFIDx */
-	unsigned int cmd;       /* LCDCMDx */
-};
-
-#define MODE_MASK		0x0f
-#define MODE_TFT_GEN		0x00
-#define MODE_TFT_SHARP		0x01
-#define MODE_TFT_CASIO		0x02
-#define MODE_TFT_SAMSUNG	0x03
-#define MODE_CCIR656_NONINT	0x04
-#define MODE_CCIR656_INT	0x05
-#define MODE_STN_COLOR_SINGLE	0x08
-#define MODE_STN_MONO_SINGLE	0x09
-#define MODE_STN_COLOR_DUAL	0x0a
-#define MODE_STN_MONO_DUAL	0x0b
-#define MODE_8BIT_SERIAL_TFT    0x0c
-
-#define MODE_TFT_18BIT          (1<<7)
-
-#define STN_DAT_PIN1	(0x00 << 4)
-#define STN_DAT_PIN2	(0x01 << 4)
-#define STN_DAT_PIN4	(0x02 << 4)
-#define STN_DAT_PIN8	(0x03 << 4)
-#define STN_DAT_PINMASK	STN_DAT_PIN8
-
-#define STFT_PSHI	(1 << 15)
-#define STFT_CLSHI	(1 << 14)
-#define STFT_SPLHI	(1 << 13)
-#define STFT_REVHI	(1 << 12)
-
-#define SYNC_MASTER	(0 << 16)
-#define SYNC_SLAVE	(1 << 16)
-
-#define DE_P		(0 << 9)
-#define DE_N		(1 << 9)
-
-#define PCLK_P		(0 << 10)
-#define PCLK_N		(1 << 10)
-
-#define HSYNC_P		(0 << 11)
-#define HSYNC_N		(1 << 11)
-
-#define VSYNC_P		(0 << 8)
-#define VSYNC_N		(1 << 8)
-
-#define DATA_NORMAL	(0 << 17)
-#define DATA_INVERSE	(1 << 17)
-
-
-/* Jz LCDFB supported I/O controls. */
-#define FBIOSETBACKLIGHT	0x4688
-#define FBIODISPON		0x4689
-#define FBIODISPOFF		0x468a
-#define FBIORESET		0x468b
-#define FBIOPRINT_REG		0x468c
-
-/*
- * LCD panel specific definition
- */
-
-#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
-
-#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */
-#define MODE 0xcd 		/* 24bit parellel RGB */
-#endif
-#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
-#define MODE 0xc9		/* 8bit serial RGB */
-#endif
-
-#if defined(CONFIG_MIPS_JZ4740_PI) /* board pavo */
-	#define SPEN	(32*2+21)       /*LCD_SPL */
-	#define SPCK	(32*2+23)       /*LCD_CLS */
-	#define SPDA	(32*2+22)       /*LCD_D12 */
-	#define LCD_RET (32*3+27) 
-#else
-#error "cpu/misp/Jzlcd.h, please define SPI pins on your board."
-#endif
-
-	#define __spi_write_reg1(reg, val) \
-	do { \
-		unsigned char no;\
-		unsigned short value;\
-		unsigned char a=0;\
-		unsigned char b=0;\
-		a=reg;\
-		b=val;\
-		__gpio_set_pin(SPEN);\
-		__gpio_set_pin(SPCK);\
-		__gpio_clear_pin(SPDA);\
-		__gpio_clear_pin(SPEN);\
-		udelay(25);\
-		value=((a<<8)|(b&0xFF));\
-		for(no=0;no<16;no++)\
-		{\
-			__gpio_clear_pin(SPCK);\
-			if((value&0x8000)==0x8000)\
-			__gpio_set_pin(SPDA);\
-			else\
-			__gpio_clear_pin(SPDA);\
-			udelay(25);\
-			__gpio_set_pin(SPCK);\
-			value=(value<<1); \
-			udelay(25);\
-		 }\
-		__gpio_set_pin(SPEN);\
-		udelay(100);\
-	} while (0)
-
-	#define __spi_write_reg(reg, val) \
-	do {\
-		__spi_write_reg1((reg<<2|2), val);\
-		udelay(100); \
-	}while(0)
-
-	
-	#define __lcd_special_pin_init() \
-	do { \
-		__gpio_as_output(SPEN); /* use SPDA */\
-		__gpio_as_output(SPCK); /* use SPCK */\
-		__gpio_as_output(SPDA); /* use SPDA */\
-		__gpio_as_output(LCD_RET);\
-	} while (0)
-
-#if defined(CONFIG_NANONOTE)
-	#define __lcd_special_on() \
-		do { \
-		udelay(50);\
-		__spi_write_reg1(0x05, 0x16); \
-		__spi_write_reg1(0x04, 0x0b); \
-		__spi_write_reg1(0x07, 0x8d); \
-		__spi_write_reg1(0x01, 0x95); \
-		__spi_write_reg1(0x08, 0xc0); \
-		__spi_write_reg1(0x03, 0x40); \
-		__spi_write_reg1(0x06, 0x15); \
-		__spi_write_reg1(0x05, 0xd7); \
-		} while (0)	/* reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level */
-
-	#define __lcd_special_off()				\
-			  do {					\
-				  __spi_write_reg1(0x05, 0x5e);	\
-			  } while (0)
-#endif	/* CONFIG_NANONOTE */
-#endif	/* CONFIG_JZLCD_FOXCONN_PT035TN01 or CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL */
-
-#ifndef __lcd_special_pin_init
-#define __lcd_special_pin_init()
-#endif
-#ifndef __lcd_special_on
-#define __lcd_special_on()
-#endif
-#ifndef __lcd_special_off
-#define __lcd_special_off()
-#endif
-
-
-/*
- * Platform specific definition
- */
-
-#if defined(CONFIG_MIPS_JZ4740_PI)
-
-	/* 100 level: 0,1,...,100 */
-	#define __lcd_set_backlight_level(n)\
-	do { \
-	__gpio_as_output(32*3+27); \
-	__gpio_set_pin(32*3+27); \
-	} while (0)
-
-	#define __lcd_close_backlight() \
-	do { \
-	__gpio_as_output(GPIO_PWM); \
-	__gpio_clear_pin(GPIO_PWM); \
-	} while (0)
-
-	#define __lcd_display_pin_init() \
-	do { \
-		__gpio_as_output(GPIO_DISP_OFF_N); \
-		__cpm_start_tcu(); \
-		__lcd_special_pin_init(); \
-	} while (0)
-	/*	__lcd_set_backlight_level(100); \*/
-	#define __lcd_display_on() \
-	do { \
-		__gpio_set_pin(GPIO_DISP_OFF_N); \
-		__lcd_special_on(); \
-	} while (0)
-
-	#define __lcd_display_off() \
-	do { \
-		__lcd_special_off(); \
-		__gpio_clear_pin(GPIO_DISP_OFF_N); \
-	} while (0)
-
-#endif /* CONFIG_MIPS_JZ4740_PI) */
-
-/*****************************************************************************
- * LCD display pin dummy macros
- *****************************************************************************/
-#ifndef __lcd_display_pin_init
-#define __lcd_display_pin_init()
-#endif
-#ifndef __lcd_display_on
-#define __lcd_display_on()
-#endif
-#ifndef __lcd_display_off
-#define __lcd_display_off()
-#endif
-#ifndef __lcd_set_backlight_level
-#define __lcd_set_backlight_level(n)
-#endif
-

package/boot/uboot-xburst/files/cpu/mips/jz_mmc.h

@@ -1,113 +0,0 @@
-/*
- *  linux/drivers/mmc/jz_mmc.h
- *
- *  Author: Vladimir Shebordaev, Igor Oblakov
- *  Copyright:  MontaVista Software Inc.
- *
- *  $Id: jz_mmc.h,v 1.3 2007-06-15 08:04:20 jlwei Exp $
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#ifndef __MMC_JZMMC_H__
-#define __MMC_JZMMC_H__
-
-#include "mmc_protocol.h"
-
-#define MMC_DEBUG_LEVEL		0		/* Enable Debug: 0 - no debug */
-
-#define MMC_BLOCK_SIZE		512		/* MMC/SD Block Size */
-
-#define ID_TO_RCA(x) ((x)+1)
-
-#define MMC_OCR_ARG		0x00ff8000	/* Argument of OCR */
-
-enum mmc_result_t {
-	MMC_NO_RESPONSE        = -1,
-	MMC_NO_ERROR           = 0,
-	MMC_ERROR_OUT_OF_RANGE,
-	MMC_ERROR_ADDRESS,
-	MMC_ERROR_BLOCK_LEN,
-	MMC_ERROR_ERASE_SEQ,
-	MMC_ERROR_ERASE_PARAM,
-	MMC_ERROR_WP_VIOLATION,
-	MMC_ERROR_CARD_IS_LOCKED,
-	MMC_ERROR_LOCK_UNLOCK_FAILED,
-	MMC_ERROR_COM_CRC,
-	MMC_ERROR_ILLEGAL_COMMAND,
-	MMC_ERROR_CARD_ECC_FAILED,
-	MMC_ERROR_CC,
-	MMC_ERROR_GENERAL,
-	MMC_ERROR_UNDERRUN,
-	MMC_ERROR_OVERRUN,
-	MMC_ERROR_CID_CSD_OVERWRITE,
-	MMC_ERROR_STATE_MISMATCH,
-	MMC_ERROR_HEADER_MISMATCH,
-	MMC_ERROR_TIMEOUT,
-	MMC_ERROR_CRC,
-	MMC_ERROR_DRIVER_FAILURE,
-};
-
-/* the information structure of MMC/SD Card */
-typedef struct MMC_INFO
-{
-	int             id;     /* Card index */
-        int             sd;     /* MMC or SD card */
-        int             rca;    /* RCA */
-        u32             scr;    /* SCR 63:32*/
-	int             flags;  /* Ejected, inserted */
-	enum card_state state;  /* empty, ident, ready, whatever */
-
-	/* Card specific information */
-	struct mmc_cid  cid;
-	struct mmc_csd  csd;
-	u32             block_num;
-	u32             block_len;
-	u32             erase_unit;
-} mmc_info;
-
-mmc_info mmcinfo;
-
-struct mmc_request {
-	int               index;      /* Slot index - used for CS lines */
-	int               cmd;        /* Command to send */
-	u32               arg;        /* Argument to send */
-	enum mmc_rsp_t    rtype;      /* Response type expected */
-
-	/* Data transfer (these may be modified at the low level) */
-	u16               nob;        /* Number of blocks to transfer*/
-	u16               block_len;  /* Block length */
-	u8               *buffer;     /* Data buffer */
-	u32               cnt;        /* Data length, for PIO */
-
-	/* Results */
-	u8                response[18]; /* Buffer to store response - CRC is optional */
-	enum mmc_result_t result;
-};
-
-char * mmc_result_to_string(int);
-int    mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd);
-int    mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state);
-int    mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca);
-int    mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr);
-int    mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid);
-int    mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3);
-
-void   mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg, 
-		     u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer);
-u32    mmc_tran_speed(u8 ts);
-void   jz_mmc_set_clock(int sd, u32 rate);
-void   jz_mmc_hardware_init(void);
-
-static inline void mmc_simple_cmd(struct mmc_request *request, int cmd, u32 arg, enum mmc_rsp_t rtype)
-{
-	mmc_send_cmd( request, cmd, arg, 0, 0, rtype, 0);
-}
-
-int mmc_legacy_init(int verbose);
-int mmc_read(ulong src, uchar *dst, int size);
-int mmc_write(uchar *src, ulong dst, int size);
-int mmc2info(ulong addr);
-
-#endif /* __MMC_JZMMC_H__ */

package/boot/uboot-xburst/files/cpu/mips/jz_serial.c

@@ -1,141 +0,0 @@
-/*
- * Jz47xx UART support
- *
- * Hardcoded to UART 0 for now
- * Options also hardcoded to 8N1
- *
- *  Copyright (c) 2005
- *  Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-#if defined(CONFIG_JZ4740)
-
-#include <common.h>
-
-#include <asm/jz4740.h>
-
-#undef UART_BASE
-#ifndef CONFIG_SYS_UART_BASE
-#define UART_BASE  UART0_BASE
-#else
-#define UART_BASE  CONFIG_SYS_UART_BASE
-#endif
-
-/******************************************************************************
-*
-* serial_init - initialize a channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-int serial_init (void)
-{
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-	volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR);
-	volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
-	volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER);
-	volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR);
-
-	/* Disable port interrupts while changing hardware */
-	*uart_ier = 0;
-
-	/* Disable UART unit function */
-	*uart_fcr = ~UART_FCR_UUE;
-
-	/* Set both receiver and transmitter in UART mode (not SIR) */
-	*uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
-
-	/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
-	*uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
-
-	/* Set baud rate */
-	serial_setbrg();
-
-	/* Enable UART unit, enable and clear FIFO */
-	*uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
-#endif
-	return 0;
-}
-
-void serial_setbrg (void)
-{
-	volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
-	volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
-	volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
-	u32 baud_div, tmp;
-
-	baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
-
-	tmp = *uart_lcr;
-	tmp |= UART_LCR_DLAB;
-	*uart_lcr = tmp;
-
-	*uart_dlhr = (baud_div >> 8) & 0xff;
-	*uart_dllr = baud_div & 0xff;
-
-	tmp &= ~UART_LCR_DLAB;
-	*uart_lcr = tmp;
-}
-
-void serial_putc (const char c)
-{
-	volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
-	volatile u8 *uart_tdr = (volatile u8 *)(UART_BASE + OFF_TDR);
-
-	if (c == '\n') serial_putc ('\r');
-
-	/* Wait for fifo to shift out some bytes */
-	while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
-
-	*uart_tdr = (u8)c;
-}
-
-void serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int serial_getc (void)
-{
-	volatile u8 *uart_rdr = (volatile u8 *)(UART_BASE + OFF_RDR);
-
-	while (!serial_tstc());
-
-	return *uart_rdr;
-}
-
-int serial_tstc (void)
-{
-	volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
-
-	if (*uart_lsr & UART_LSR_DR) {
-		/* Data in rfifo */
-		return (1);
-	}
-	return 0;
-}
-
-#endif

package/boot/uboot-xburst/files/cpu/mips/mmc_protocol.h

@@ -1,273 +0,0 @@
-/*
-**********************************************************************
-*
-*                            uC/MMC
-*
-*             (c) Copyright 2005 - 2007, Ingenic Semiconductor, Inc
-*                      All rights reserved.
-*
-***********************************************************************
-
-----------------------------------------------------------------------
-File        : mmc_protocol.h
-Purpose     : MMC protocol definitions.
-
-----------------------------------------------------------------------
-Version-Date-----Author-Explanation
-----------------------------------------------------------------------
-1.00.00 20060831 WeiJianli     First release
-
-----------------------------------------------------------------------
-Known problems or limitations with current version
-----------------------------------------------------------------------
-(none)
----------------------------END-OF-HEADER------------------------------
-*/
-
-#ifndef __MMC_PROTOCOL__
-#define __MMC_PROTOCOL__
-
-/* Standard MMC/SD clock speeds */
-#define MMC_CLOCK_SLOW    400000      /* 400 kHz for initial setup */
-#define MMC_CLOCK_FAST  20000000      /* 20 MHz for maximum for normal operation */
-#define SD_CLOCK_FAST   24000000      /* 24 MHz for SD Cards */
- 
-/* Extra MMC commands for state control */
-/* Use negative numbers to disambiguate */
-#define MMC_CIM_RESET            -1
-
-/* Standard MMC commands (3.1)           type  argument     response */
-   /* class 1 */
-#define	MMC_GO_IDLE_STATE         0   /* bc                          */
-#define MMC_SEND_OP_COND          1   /* bcr  [31:0] OCR         R3  */
-#define MMC_ALL_SEND_CID          2   /* bcr                     R2  */
-#define MMC_SET_RELATIVE_ADDR     3   /* ac   [31:16] RCA        R1  */
-#define MMC_SET_DSR               4   /* bc   [31:16] RCA            */
-#define MMC_SELECT_CARD           7   /* ac   [31:16] RCA        R1  */
-#define MMC_SEND_CSD              9   /* ac   [31:16] RCA        R2  */
-#define MMC_SEND_CID             10   /* ac   [31:16] RCA        R2  */
-#define MMC_READ_DAT_UNTIL_STOP  11   /* adtc [31:0] dadr        R1  */
-#define MMC_STOP_TRANSMISSION    12   /* ac                      R1b */
-#define MMC_SEND_STATUS	         13   /* ac   [31:16] RCA        R1  */
-#define MMC_GO_INACTIVE_STATE    15   /* ac   [31:16] RCA            */
-
-  /* class 2 */
-#define MMC_SET_BLOCKLEN         16   /* ac   [31:0] block len   R1  */
-#define MMC_READ_SINGLE_BLOCK    17   /* adtc [31:0] data addr   R1  */
-#define MMC_READ_MULTIPLE_BLOCK  18   /* adtc [31:0] data addr   R1  */
-
-  /* class 3 */
-#define MMC_WRITE_DAT_UNTIL_STOP 20   /* adtc [31:0] data addr   R1  */
-
-  /* class 4 */
-#define MMC_SET_BLOCK_COUNT      23   /* adtc [31:0] data addr   R1  */
-#define MMC_WRITE_BLOCK          24   /* adtc [31:0] data addr   R1  */
-#define MMC_WRITE_MULTIPLE_BLOCK 25   /* adtc                    R1  */
-#define MMC_PROGRAM_CID          26   /* adtc                    R1  */
-#define MMC_PROGRAM_CSD          27   /* adtc                    R1  */
-
-  /* class 6 */
-#define MMC_SET_WRITE_PROT       28   /* ac   [31:0] data addr   R1b */
-#define MMC_CLR_WRITE_PROT       29   /* ac   [31:0] data addr   R1b */
-#define MMC_SEND_WRITE_PROT      30   /* adtc [31:0] wpdata addr R1  */
-
-  /* class 5 */
-#define MMC_ERASE_GROUP_START    35   /* ac   [31:0] data addr   R1  */
-#define MMC_ERASE_GROUP_END      36   /* ac   [31:0] data addr   R1  */
-#define MMC_ERASE                37   /* ac                      R1b */
-
-  /* class 9 */
-#define MMC_FAST_IO              39   /* ac   <Complex>          R4  */
-#define MMC_GO_IRQ_STATE         40   /* bcr                     R5  */
-
-  /* class 7 */
-#define MMC_LOCK_UNLOCK          42   /* adtc                    R1b */
-
-  /* class 8 */
-#define MMC_APP_CMD              55   /* ac   [31:16] RCA        R1  */
-#define MMC_GEN_CMD              56   /* adtc [0] RD/WR          R1b */
-
-  /* SD class */
-#define SD_SEND_OP_COND          41   /* bcr  [31:0] OCR         R3  */
-#define SET_BUS_WIDTH            6    /* ac   [1:0] bus width    R1  */
-#define SEND_SCR                 51   /* adtc [31:0] staff       R1  */
-
-/* Don't change the order of these; they are used in dispatch tables */
-enum mmc_rsp_t {
-	RESPONSE_NONE   = 0,
-	RESPONSE_R1     = 1,
-	RESPONSE_R1B    = 2,
-	RESPONSE_R2_CID = 3,
-	RESPONSE_R2_CSD  = 4,
-	RESPONSE_R3      = 5,
-	RESPONSE_R4      = 6,
-	RESPONSE_R5      = 7,
-        RESPONSE_R6      = 8,
-};
-
-
-/*
-  MMC status in R1
-  Type
-  	e : error bit
-	s : status bit
-	r : detected and set for the actual command response
-	x : detected and set during command execution. the host must poll
-            the card by sending status command in order to read these bits.
-  Clear condition
-  	a : according to the card state
-	b : always related to the previous command. Reception of
-            a valid command will clear it (with a delay of one command)
-	c : clear by read
- */
-
-#define R1_OUT_OF_RANGE		(1 << 31)	/* er, c */
-#define R1_ADDRESS_ERROR	(1 << 30)	/* erx, c */
-#define R1_BLOCK_LEN_ERROR	(1 << 29)	/* er, c */
-#define R1_ERASE_SEQ_ERROR      (1 << 28)	/* er, c */
-#define R1_ERASE_PARAM		(1 << 27)	/* ex, c */
-#define R1_WP_VIOLATION		(1 << 26)	/* erx, c */
-#define R1_CARD_IS_LOCKED	(1 << 25)	/* sx, a */
-#define R1_LOCK_UNLOCK_FAILED	(1 << 24)	/* erx, c */
-#define R1_COM_CRC_ERROR	(1 << 23)	/* er, b */
-#define R1_ILLEGAL_COMMAND	(1 << 22)	/* er, b */
-#define R1_CARD_ECC_FAILED	(1 << 21)	/* ex, c */
-#define R1_CC_ERROR		(1 << 20)	/* erx, c */
-#define R1_ERROR		(1 << 19)	/* erx, c */
-#define R1_UNDERRUN		(1 << 18)	/* ex, c */
-#define R1_OVERRUN		(1 << 17)	/* ex, c */
-#define R1_CID_CSD_OVERWRITE	(1 << 16)	/* erx, c, CID/CSD overwrite */
-#define R1_WP_ERASE_SKIP	(1 << 15)	/* sx, c */
-#define R1_CARD_ECC_DISABLED	(1 << 14)	/* sx, a */
-#define R1_ERASE_RESET		(1 << 13)	/* sr, c */
-#define R1_STATUS(x)            (x & 0xFFFFE000)
-#define R1_CURRENT_STATE(x)    	((x & 0x00001E00) >> 9)	/* sx, b (4 bits) */
-#define R1_READY_FOR_DATA	(1 << 8)	/* sx, a */
-#define R1_APP_CMD		(1 << 7)	/* sr, c */
-
-enum card_state {
-	CARD_STATE_EMPTY = -1,
-	CARD_STATE_IDLE	 = 0,
-	CARD_STATE_READY = 1,
-	CARD_STATE_IDENT = 2,
-	CARD_STATE_STBY	 = 3,
-	CARD_STATE_TRAN	 = 4,
-	CARD_STATE_DATA	 = 5,
-	CARD_STATE_RCV	 = 6,
-	CARD_STATE_PRG	 = 7,
-	CARD_STATE_DIS	 = 8,
-};
-
-/* These are unpacked versions of the actual responses */
-
- struct mmc_response_r1 {
-	u8  cmd;
-	u32 status;
-};
-
-typedef struct mmc_cid {
-	u8  mid;
-	u16 oid;
-	u8  pnm[7];   /* Product name (we null-terminate) */
-	u8  prv;
-	u32 psn;
-	u8  mdt;
-}mmc_cid_t;
-
-typedef struct mmc_csd {
-	u8  csd_structure;
-	u8  spec_vers;
-	u8  taac;
-	u8  nsac;
-	u8  tran_speed;
-	u16 ccc;
-	u8  read_bl_len;
-	u8  read_bl_partial;
-	u8  write_blk_misalign;
-	u8  read_blk_misalign;
-	u8  dsr_imp;
-	u16 c_size;
-	u8  vdd_r_curr_min;
-	u8  vdd_r_curr_max;
-	u8  vdd_w_curr_min;
-	u8  vdd_w_curr_max;
-	u8  c_size_mult;
-	union {
-		struct { /* MMC system specification version 3.1 */
-			u8  erase_grp_size;
-			u8  erase_grp_mult;
-		} v31;
-		struct { /* MMC system specification version 2.2 */
-			u8  sector_size;
-			u8  erase_grp_size;
-		} v22;
-	} erase;
-	u8  wp_grp_size;
-	u8  wp_grp_enable;
-	u8  default_ecc;
-	u8  r2w_factor;
-	u8  write_bl_len;
-	u8  write_bl_partial;
-	u8  file_format_grp;
-	u8  copy;
-	u8  perm_write_protect;
-	u8  tmp_write_protect;
-	u8  file_format;
-	u8  ecc;
-}mmc_csd_t;;
-
-struct mmc_response_r3 {
-	u32 ocr;
-};
-
-#define MMC_VDD_145_150	0x00000001	/* VDD voltage 1.45 - 1.50 */
-#define MMC_VDD_150_155	0x00000002	/* VDD voltage 1.50 - 1.55 */
-#define MMC_VDD_155_160	0x00000004	/* VDD voltage 1.55 - 1.60 */
-#define MMC_VDD_160_165	0x00000008	/* VDD voltage 1.60 - 1.65 */
-#define MMC_VDD_165_170	0x00000010	/* VDD voltage 1.65 - 1.70 */
-#define MMC_VDD_17_18	0x00000020	/* VDD voltage 1.7 - 1.8 */
-#define MMC_VDD_18_19	0x00000040	/* VDD voltage 1.8 - 1.9 */
-#define MMC_VDD_19_20	0x00000080	/* VDD voltage 1.9 - 2.0 */
-#define MMC_VDD_20_21	0x00000100	/* VDD voltage 2.0 ~ 2.1 */
-#define MMC_VDD_21_22	0x00000200	/* VDD voltage 2.1 ~ 2.2 */
-#define MMC_VDD_22_23	0x00000400	/* VDD voltage 2.2 ~ 2.3 */
-#define MMC_VDD_23_24	0x00000800	/* VDD voltage 2.3 ~ 2.4 */
-#define MMC_VDD_24_25	0x00001000	/* VDD voltage 2.4 ~ 2.5 */
-#define MMC_VDD_25_26	0x00002000	/* VDD voltage 2.5 ~ 2.6 */
-#define MMC_VDD_26_27	0x00004000	/* VDD voltage 2.6 ~ 2.7 */
-#define MMC_VDD_27_28	0x00008000	/* VDD voltage 2.7 ~ 2.8 */
-#define MMC_VDD_28_29	0x00010000	/* VDD voltage 2.8 ~ 2.9 */
-#define MMC_VDD_29_30	0x00020000	/* VDD voltage 2.9 ~ 3.0 */
-#define MMC_VDD_30_31	0x00040000	/* VDD voltage 3.0 ~ 3.1 */
-#define MMC_VDD_31_32	0x00080000	/* VDD voltage 3.1 ~ 3.2 */
-#define MMC_VDD_32_33	0x00100000	/* VDD voltage 3.2 ~ 3.3 */
-#define MMC_VDD_33_34	0x00200000	/* VDD voltage 3.3 ~ 3.4 */
-#define MMC_VDD_34_35	0x00400000	/* VDD voltage 3.4 ~ 3.5 */
-#define MMC_VDD_35_36	0x00800000	/* VDD voltage 3.5 ~ 3.6 */
-#define MMC_CARD_BUSY	0x80000000	/* Card Power up status bit */
-
-
-/* CSD field definitions */
-
-#define CSD_STRUCT_VER_1_0  0           /* Valid for system specification 1.0 - 1.2 */
-#define CSD_STRUCT_VER_1_1  1           /* Valid for system specification 1.4 - 2.2 */
-#define CSD_STRUCT_VER_1_2  2           /* Valid for system specification 3.1       */
-
-#define CSD_SPEC_VER_0      0           /* Implements system specification 1.0 - 1.2 */
-#define CSD_SPEC_VER_1      1           /* Implements system specification 1.4 */
-#define CSD_SPEC_VER_2      2           /* Implements system specification 2.0 - 2.2 */
-#define CSD_SPEC_VER_3      3           /* Implements system specification 3.1 */
-
-#if MMC_DEBUG_LEVEL
-
-#define DEBUG(n, args...)			\
-    do {    \
-	if (n <=  MMC_DEBUG_LEVEL) {	\
-		printf(args);	\
-	}    \
-    } while(0)
-#else
-#define DEBUG(n, args...)
-#endif /* MMC_DEBUG_EN */
-
-#endif  /* __MMC_PROTOCOL__ */

package/boot/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c

@@ -1,420 +0,0 @@
-/*
- * JzRISC lcd controller
- *
- * xiangfu liu <xiangfu.z@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <lcd.h>
-
-#include <asm/io.h>               /* virt_to_phys() */
-
-#include <asm/jz4740.h>
-#include "nanonote_gpm940b0.h"
-
-#define align2(n) (n)=((((n)+1)>>1)<<1)
-#define align4(n) (n)=((((n)+3)>>2)<<2)
-#define align8(n) (n)=((((n)+7)>>3)<<3)
-
-struct jzfb_info {
-	unsigned int cfg;	/* panel mode and pin usage etc. */
-	unsigned int w;
-	unsigned int h;
-	unsigned int bpp;	/* bit per pixel */
-	unsigned int fclk;	/* frame clk */
-	unsigned int hsw;	/* hsync width, in pclk */
-	unsigned int vsw;	/* vsync width, in line count */
-	unsigned int elw;	/* end of line, in pclk */
-	unsigned int blw;	/* begin of line, in pclk */
-	unsigned int efw;	/* end of frame, in line count */
-	unsigned int bfw;	/* begin of frame, in line count */
-};
-
-static struct jzfb_info jzfb = {
-	MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
-	320, 240, 32, 70, 1, 1, 273, 140, 1, 20
-};
-
-vidinfo_t panel_info = {
-	320, 240, LCD_BPP,
-};
-
-int lcd_line_length;
-
-int lcd_color_fg;
-int lcd_color_bg;
-/*
- * Frame buffer memory information
- */
-void *lcd_base;			/* Start of framebuffer memory	*/
-void *lcd_console_address;	/* Start of console buffer	*/
-
-short console_col;
-short console_row;
-
-void lcd_ctrl_init (void *lcdbase);
-void lcd_enable (void);
-void lcd_disable (void);
-
-static int  jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
-static void jz_lcd_desc_init(vidinfo_t *vid);
-static int  jz_lcd_hw_init( vidinfo_t *vid );
-extern int flush_cache_all(void);
-
-void lcd_ctrl_init (void *lcdbase)
-{
-	__lcd_display_pin_init();
-
-	jz_lcd_init_mem(lcdbase, &panel_info);
-	jz_lcd_desc_init(&panel_info);
-	jz_lcd_hw_init(&panel_info);
-
-	__lcd_display_on() ;
-}
-
-/*
- * Before enabled lcd controller, lcd registers should be configured correctly.
- */
-
-void lcd_enable (void)
-{
-	REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
-	REG_LCD_CTRL |= 1<<3;    /* LCDCTRL.ENA*/
-}
-
-void lcd_disable (void)
-{
-	REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
-	/* REG_LCD_CTRL |= (1<<3); */  /* LCDCTRL.DIS, quikly disable */
-}
-
-static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
-{
-	u_long palette_mem_size;
-	struct jz_fb_info *fbi = &vid->jz_fb;
-	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
-
-	fbi->screen = (u_long)lcdbase;
-	fbi->palette_size = 256;
-	palette_mem_size = fbi->palette_size * sizeof(u16);
-
-	debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
-	/* locate palette and descs at end of page following fb */
-	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
-
-	return 0;
-}
-
-static void jz_lcd_desc_init(vidinfo_t *vid)
-{
-	struct jz_fb_info * fbi;
-	fbi = &vid->jz_fb;
-	fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
-	fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
-	fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
-
-	#define BYTES_PER_PANEL	 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
-
-	/* populate descriptors */
-	fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
-	fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
-	fbi->dmadesc_fblow->fidr  = 0;
-	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
-
-	fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
-
-	fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
-	fbi->dmadesc_fbhigh->fidr = 0;
-	fbi->dmadesc_fbhigh->ldcmd =  BYTES_PER_PANEL / 4; /* length in word */
-
-	fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
-	fbi->dmadesc_palette->fidr  = 0;
-	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
-
-	if(NBITS(vid->vl_bpix) < 12)
-	{
-		/* assume any mode with <12 bpp is palette driven */
-		fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
-		fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
-		/* flips back and forth between pal and fbhigh */
-		fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
-	} else {
-		/* palette shouldn't be loaded in true-color mode */
-		fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
-		fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
-	}
-
-	flush_cache_all();
-}
-
-static int  jz_lcd_hw_init(vidinfo_t *vid)
-{
-	struct jz_fb_info *fbi = &vid->jz_fb;
-	unsigned int val = 0;
-	unsigned int pclk;
-	unsigned int stnH;
-	int pll_div;
-
-	/* Setting Control register */
-	switch (jzfb.bpp) {
-	case 1:
-		val |= LCD_CTRL_BPP_1;
-		break;
-	case 2:
-		val |= LCD_CTRL_BPP_2;
-		break;
-	case 4:
-		val |= LCD_CTRL_BPP_4;
-		break;
-	case 8:
-		val |= LCD_CTRL_BPP_8;
-		break;
-	case 15:
-		val |= LCD_CTRL_RGB555;
-	case 16:
-		val |= LCD_CTRL_BPP_16;
-		break;
-	case 17 ... 32:
-		val |= LCD_CTRL_BPP_18_24;	/* target is 4bytes/pixel */
-		break;
-
-	default:
-		printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
-		val |= LCD_CTRL_BPP_16;
-		break;
-	}
-
-	switch (jzfb.cfg & MODE_MASK) {
-	case MODE_STN_MONO_DUAL:
-	case MODE_STN_COLOR_DUAL:
-	case MODE_STN_MONO_SINGLE:
-	case MODE_STN_COLOR_SINGLE:
-		switch (jzfb.bpp) {
-		case 1:
-			/* val |= LCD_CTRL_PEDN; */
-		case 2:
-			val |= LCD_CTRL_FRC_2;
-			break;
-		case 4:
-			val |= LCD_CTRL_FRC_4;
-			break;
-		case 8:
-		default:
-			val |= LCD_CTRL_FRC_16;
-			break;
-		}
-		break;
-	}
-
-	val |= LCD_CTRL_BST_16;		/* Burst Length is 16WORD=64Byte */
-	val |= LCD_CTRL_OFUP;		/* OutFIFO underrun protect */
-
-	switch (jzfb.cfg & MODE_MASK) {
-	case MODE_STN_MONO_DUAL:
-	case MODE_STN_COLOR_DUAL:
-	case MODE_STN_MONO_SINGLE:
-	case MODE_STN_COLOR_SINGLE:
-		switch (jzfb.cfg & STN_DAT_PINMASK) {
-		case STN_DAT_PIN1:
-			/* Do not adjust the hori-param value. */
-			break;
-		case STN_DAT_PIN2:
-			align2(jzfb.hsw);
-			align2(jzfb.elw);
-			align2(jzfb.blw);
-			break;
-		case STN_DAT_PIN4:
-			align4(jzfb.hsw);
-			align4(jzfb.elw);
-			align4(jzfb.blw);
-			break;
-		case STN_DAT_PIN8:
-			align8(jzfb.hsw);
-			align8(jzfb.elw);
-			align8(jzfb.blw);
-			break;
-		}
-		break;
-	}
-
-	REG_LCD_CTRL = val;
-
-	switch (jzfb.cfg & MODE_MASK) {
-	case MODE_STN_MONO_DUAL:
-	case MODE_STN_COLOR_DUAL:
-	case MODE_STN_MONO_SINGLE:
-	case MODE_STN_COLOR_SINGLE:
-		if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
-		    ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
-			stnH = jzfb.h >> 1;
-		else
-			stnH = jzfb.h;
-
-		REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
-		REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
-
-		/* Screen setting */
-		REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
-		REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
-		REG_LCD_DAV = (0 << 16) | (stnH);
-
-		/* AC BIAs signal */
-		REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
-
-		break;
-
-	case MODE_TFT_GEN:
-	case MODE_TFT_SHARP:
-	case MODE_TFT_CASIO:
-	case MODE_TFT_SAMSUNG:
-	case MODE_8BIT_SERIAL_TFT:
-	case MODE_TFT_18BIT:
-		REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
-		REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
-		REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
-		REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
-		REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
-			| (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
-		break;
-	}
-
-	switch (jzfb.cfg & MODE_MASK) {
-	case MODE_TFT_SAMSUNG:
-	{
-		unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
-		unsigned int rev_s, rev_e, inv_s, inv_e;
-
-		pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
-			(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
-
-		total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
-		tp_s = jzfb.blw + jzfb.w + 1;
-		tp_e = tp_s + 1;
-		/* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
-		ckv_s = tp_s - pclk/(1000000000/4100);
-		ckv_e = tp_s + total;
-		rev_s = tp_s - 11;	/* -11.5 clk */
-		rev_e = rev_s + total;
-		inv_s = tp_s;
-		inv_e = inv_s + total;
-		REG_LCD_CLS = (tp_s << 16) | tp_e;
-		REG_LCD_PS = (ckv_s << 16) | ckv_e;
-		REG_LCD_SPL = (rev_s << 16) | rev_e;
-		REG_LCD_REV = (inv_s << 16) | inv_e;
-		jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
-		break;
-	}
-	case MODE_TFT_SHARP:
-	{
-		unsigned int total, cls_s, cls_e, ps_s, ps_e;
-		unsigned int spl_s, spl_e, rev_s, rev_e;
-		total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
-		spl_s = 1;
-		spl_e = spl_s + 1;
-		cls_s = 0;
-		cls_e = total - 60;	/* > 4us (pclk = 80ns) */
-		ps_s = cls_s;
-		ps_e = cls_e;
-		rev_s = total - 40;	/* > 3us (pclk = 80ns) */
-		rev_e = rev_s + total;
-		jzfb.cfg |= STFT_PSHI; 
-		REG_LCD_SPL = (spl_s << 16) | spl_e;
-		REG_LCD_CLS = (cls_s << 16) | cls_e;
-		REG_LCD_PS = (ps_s << 16) | ps_e;
-		REG_LCD_REV = (rev_s << 16) | rev_e;
-		break;
-	}
-	case MODE_TFT_CASIO:
-		break;
-	}
-
-	/* Configure the LCD panel */
-	REG_LCD_CFG = jzfb.cfg;
-
-	/* Timing setting */
-	__cpm_stop_lcd();
-
-	val = jzfb.fclk; /* frame clk */
-	if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
-		pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
-			(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
-	} else {
-		/* serial mode: Hsync period = 3*Width_Pixel */
-		pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
-			(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
-	}
-
-	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
-		pclk = (pclk * 3);
-
-	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
-		pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
-
-	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
-		pclk >>= 1;
-
-	pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
-	pll_div = pll_div ? 1 : 2 ;
-	val = ( __cpm_get_pllout()/pll_div ) / pclk;
-	val--;
-	if ( val > 0x1ff ) {
-		printf("CPM_LPCDR too large, set it to 0x1ff\n");
-		val = 0x1ff;
-	}
-	__cpm_set_pixdiv(val);
-
-	val = pclk * 3 ;	/* LCDClock > 2.5*Pixclock */
-	if ( val > 150000000 ) {
-		printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
-		printf("Change LCDClock to 150MHz\n");
-		val = 150000000;
-	}
-	val = ( __cpm_get_pllout()/pll_div ) / val;
-	val--;
-	if ( val > 0x1f ) {
-		printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
-		val = 0x1f;
-	}
-	__cpm_set_ldiv( val );
-	REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
-
-	__cpm_start_lcd();
-	udelay(1000);
-
-	REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
-
-	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
-	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
-		REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
-
-	return 0;
-}
-
-void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
-{
-}
-
-void lcd_initcolregs (void)
-{
-}

package/boot/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h

@@ -1,234 +0,0 @@
-/*
- * JzRISC lcd controller
- *
- * xiangfu liu <xiangfu.z@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __QI_LB60_GPM940B0_H__
-#define __QI_LB60_GPM940B0_H__
-
-#include <asm/io.h>
-
-#define mdelay(n)	udelay((n)*1000)
-
-#define NR_PALETTE	256
-
-struct lcd_desc{
-	unsigned int next_desc; /* LCDDAx */
-	unsigned int databuf;   /* LCDSAx */
-	unsigned int frame_id;  /* LCDFIDx */ 
-	unsigned int cmd;       /* LCDCMDx */
-};
-
-#define MODE_MASK		0x0f
-#define MODE_TFT_GEN		0x00
-#define MODE_TFT_SHARP		0x01
-#define MODE_TFT_CASIO		0x02
-#define MODE_TFT_SAMSUNG	0x03
-#define MODE_CCIR656_NONINT	0x04
-#define MODE_CCIR656_INT	0x05
-#define MODE_STN_COLOR_SINGLE	0x08
-#define MODE_STN_MONO_SINGLE	0x09
-#define MODE_STN_COLOR_DUAL	0x0a
-#define MODE_STN_MONO_DUAL	0x0b
-#define MODE_8BIT_SERIAL_TFT    0x0c
-
-#define MODE_TFT_18BIT          (1<<7)
-
-#define STN_DAT_PIN1	(0x00 << 4)
-#define STN_DAT_PIN2	(0x01 << 4)
-#define STN_DAT_PIN4	(0x02 << 4)
-#define STN_DAT_PIN8	(0x03 << 4)
-#define STN_DAT_PINMASK	STN_DAT_PIN8
-
-#define STFT_PSHI	(1 << 15)
-#define STFT_CLSHI	(1 << 14)
-#define STFT_SPLHI	(1 << 13)
-#define STFT_REVHI	(1 << 12)
-
-#define SYNC_MASTER	(0 << 16)
-#define SYNC_SLAVE	(1 << 16)
-
-#define DE_P		(0 << 9)
-#define DE_N		(1 << 9)
-
-#define PCLK_P		(0 << 10)
-#define PCLK_N		(1 << 10)
-
-#define HSYNC_P		(0 << 11)
-#define HSYNC_N		(1 << 11)
-
-#define VSYNC_P		(0 << 8)
-#define VSYNC_N		(1 << 8)
-
-#define DATA_NORMAL	(0 << 17)
-#define DATA_INVERSE	(1 << 17)
-
-
-/* Jz LCDFB supported I/O controls. */
-#define FBIOSETBACKLIGHT	0x4688
-#define FBIODISPON		0x4689
-#define FBIODISPOFF		0x468a
-#define FBIORESET		0x468b
-#define FBIOPRINT_REG		0x468c
-
-/*
- * LCD panel specific definition
- */
-#define MODE	0xc9		/* 8bit serial RGB */
-#define SPEN	(32*2+21)       /*LCD_SPL */
-#define SPCK	(32*2+23)       /*LCD_CLS */
-#define SPDA	(32*2+22)       /*LCD_D12 */
-#define LCD_RET (32*3+27) 
-
-#define __spi_write_reg1(reg, val) \
-do { \
-	unsigned char no;\
-	unsigned short value;\
-	unsigned char a=0;\
-	unsigned char b=0;\
-	a=reg;\
-	b=val;\
-	__gpio_set_pin(SPEN);\
-	__gpio_set_pin(SPCK);\
-	__gpio_clear_pin(SPDA);\
-	__gpio_clear_pin(SPEN);\
-	udelay(25);\
-	value=((a<<8)|(b&0xFF));\
-	for(no=0;no<16;no++)\
-	{\
-		__gpio_clear_pin(SPCK);\
-		if((value&0x8000)==0x8000)\
-		__gpio_set_pin(SPDA);\
-		else\
-		__gpio_clear_pin(SPDA);\
-		udelay(25);\
-		__gpio_set_pin(SPCK);\
-		value=(value<<1); \
-		udelay(25);\
-	 }\
-	__gpio_set_pin(SPEN);\
-	udelay(100);\
-} while (0)
-
-#define __spi_write_reg(reg, val) \
-do {\
-	__spi_write_reg1((reg<<2|2), val);\
-	udelay(100); \
-}while(0)
-
-#define __lcd_special_pin_init() \
-do { \
-	__gpio_as_output(SPEN); /* use SPDA */\
-	__gpio_as_output(SPCK); /* use SPCK */\
-	__gpio_as_output(SPDA); /* use SPDA */\
-	__gpio_as_output(LCD_RET);\
-} while (0)
-
-#define __lcd_special_on() \
-do { \
-	__spi_write_reg1(0x05, 0x1e); \
-	udelay(50);\
-	__spi_write_reg1(0x05, 0x5d); \
-	__spi_write_reg1(0x0B, 0x81); \
-	__spi_write_reg1(0x01, 0x95); \
-	__spi_write_reg1(0x00, 0x07); \
-	__spi_write_reg1(0x06, 0x15); \
-	__spi_write_reg1(0x07, 0x8d); \
-	__spi_write_reg1(0x04, 0x0f); \
-	__spi_write_reg1(0x0d, 0x3d); \
-	__spi_write_reg1(0x10, 0x42); \
-	__spi_write_reg1(0x11, 0x3a); \
-	__spi_write_reg1(0x05, 0x5f); \
-} while (0)
-
-#define __lcd_special_off() \
-do {					\
-	__spi_write_reg1(0x05, 0x5e);	\
-} while (0)
-
-#define __lcd_display_pin_init() \
-do { \
-	__lcd_special_pin_init();\
-	__gpio_as_pwm();\
-	__lcd_set_backlight_level(8);\
-} while (0)
-
-#define __lcd_display_on() \
-do { \
-	__lcd_set_backlight_level(8); \
-	__lcd_special_on();\
-} while (0)
-
-#define __lcd_display_off() \
-do { \
-	__lcd_set_backlight_level(0); \
-	__lcd_special_off();\
-} while (0)
-
-#define __lcd_set_backlight_level(n)\
-do { \
-	__gpio_as_output(LCD_RET); \
-	__gpio_set_pin(LCD_RET); \
-} while (0)
-
-#if defined(CONFIG_SAKC)
-#define __lcd_close_backlight() \
-do { \
-	__gpio_as_output(GPIO_PWM); \
-	__gpio_clear_pin(GPIO_PWM); \
-} while (0)
-#endif
-
-#if defined(CONFIG_SAKC)
-#define __lcd_display_pin_init() \
-do { \
-	__cpm_start_tcu(); \
-	__lcd_special_pin_init(); \
-} while (0)
-
-#define __lcd_display_on() \
-do { \
-	__lcd_special_on(); \
-} while (0)
-
-#define __lcd_display_off() \
-do { \
-	__lcd_special_off(); \
-} while (0)
-#else
-#define __lcd_display_pin_init() \
-do { \
-	__cpm_start_tcu(); \
-	__lcd_special_pin_init(); \
-} while (0)
-
-#define __lcd_display_on() \
-do { \
-	__gpio_set_pin(GPIO_DISP_OFF_N); \
-	__lcd_special_on(); \
-} while (0)
-
-#define __lcd_display_off() \
-do { \
-	__lcd_special_off(); \
-	__gpio_clear_pin(GPIO_DISP_OFF_N); \
-} while (0)
-#endif
-
-#endif /* __QI_LB60_GPM940B0_H__ */

package/boot/uboot-xburst/files/cpu/mips/usb_boot.S

@@ -1,880 +0,0 @@
-/*
- *  for jz4740 usb boot
- *
- *  Copyright (c) 2009	Xiangfu Liu <xiangfu.z@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-    .set noreorder
-    .globl usb_boot
-    .text
-
-//----------------------------------------------------------------------
-// Both NAND and USB boot load data to D-Cache first, then transfer
-// data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
-// So init caches first and then dispatch to a proper boot routine.
-//----------------------------------------------------------------------
-
-.macro load_addr reg addr
-	li \reg, 0x80000000
-	addiu \reg, \reg, \addr
-	la $2, usbboot_begin
-	subu \reg, \reg, $2
-.endm
-
-usb_boot:
-	//--------------------------------------------------------------
-	// Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
-	//--------------------------------------------------------------
-	la	$9, 0xB0000000		// CPCCR: Clock Control Register
-	la	$8, 0x42041110		// I:S:M:P=1:2:2:2
-	sw	$8, 0($9)
-
-	la	$9, 0xB0000010		// CPPCR: PLL Control Register
-	la	$8, 0x06000120		// M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
-	sw	$8, 0($9)
-
-	mtc0	$0, $26			// CP0_ERRCTL, restore WST reset state
-	nop
-
-	mtc0	$0, $16			// CP0_CONFIG
-	nop
-
-	// Relocate code to beginning of the ram
-
-	la $2, usbboot_begin
-	la $3, usbboot_end
-	li $4, 0x80000000
-
-1:
-	lw $5, 0($2)
-	sw $5, 0($4)
-	addiu $2, $2, 4
-	bne $2, $3, 1b
-	addiu $4, $4, 4
-
-	li $2, 0x80000000
-	ori $3, $2, 0
-	addiu $3, $3, usbboot_end
-	la $4, usbboot_begin
-	subu $3, $3, $4
-
-
-2:
-	cache	0x0, 0($2)		// Index_Invalidate_I
-	cache	0x1, 0($2)		// Index_Writeback_Inv_D
-	addiu	$2, $2, 32
-	subu $4, $3, $2
-	bgtz	$4, 2b
-	nop
-
-	load_addr $3, usb_boot_return
-
-	jr $3
-
-usbboot_begin:
-
-init_caches:
-	li	$2, 3			// cacheable for kseg0 access
-	mtc0	$2, $16			// CP0_CONFIG
-	nop
-
-	li	$2, 0x20000000		// enable idx-store-data cache insn
-	mtc0	$2, $26			// CP0_ERRCTL
-
-	ori	$2, $28, 0		// start address
-	ori	$3, $2, 0x3fe0		// end address, total 16KB
-	mtc0	$0, $28, 0		// CP0_TAGLO
-	mtc0	$0, $28, 1		// CP0_DATALO
-cache_clear_a_line:
-	cache	0x8, 0($2)		// Index_Store_Tag_I
-	cache	0x9, 0($2)		// Index_Store_Tag_D
-	bne	$2, $3, cache_clear_a_line
-	addiu	$2, $2, 32		// increment CACHE_LINE_SIZE
-
-	ori	$2, $28, 0		// start address
-	ori	$3, $2, 0x3fe0		// end address, total 16KB
-	la	$4, 0x1ffff000		// physical address and 4KB page mask
-cache_alloc_a_line:
-	and	$5, $2, $4
-	ori	$5, $5, 1		// V bit of the physical tag
-	mtc0	$5, $28, 0		// CP0_TAGLO
-	cache	0x8, 0($2)		// Index_Store_Tag_I
-	cache	0x9, 0($2)		// Index_Store_Tag_D
-	bne	$2, $3, cache_alloc_a_line
-	addiu	$2, $2, 32		// increment CACHE_LINE_SIZE
-
-	nop
-	nop
-	nop
-	//--------------------------------------------------------------
-	// Transfer data from dcache to icache, then jump to icache.
-	//
-	// Input parameters:
-	//
-	// $19: data length in bytes
-	// $20: jump target address
-	//--------------------------------------------------------------
-xfer_d2i:
-
-	ori	$8, $20, 0
-	addu	$9, $8, $19		// total 16KB
-
-1:
-	cache	0x0, 0($8)		// Index_Invalidate_I
-	cache	0x1, 0($8)		// Index_Writeback_Inv_D
-	bne	$8, $9, 1b
-	addiu	$8, $8, 32
-
-	// flush write-buffer
-	sync
-
-	// Invalidate BTB
-	mfc0	$8, $16, 7		// CP0_CONFIG
-	nop
-	ori	$8, 2
-	mtc0	$8, $16, 7
-	nop
-
-	// Overwrite config to disable ram initalisation
-	li $2, 0xff
-	sb $2, 20($20)
-
-	jalr	$20
-	nop
-
-icache_return:
-	//--------------------------------------------------------------
-	// User code can return to here after executing itself in 
-	// icache, by jumping to $31.
-	//--------------------------------------------------------------
-	b	usb_boot_return
-	nop
-
-
-usb_boot_return:
-	//--------------------------------------------------------------
-	// Enable the USB PHY
-	//--------------------------------------------------------------
-	la	$9, 0xB0000024		// CPM_SCR
-	lw	$8, 0($9)
-	ori	$8, 0x40		// USBPHY_ENABLE
-	sw	$8, 0($9)
-
-	//--------------------------------------------------------------
-	// Initialize USB registers
-	//--------------------------------------------------------------
-	la	$27, 0xb3040000		// USB registers base address
-
-	sb	$0, 0x0b($27)		// INTRUSBE: disable common USB interrupts
-	sh	$0, 0x06($27)		// INTRINE: disable EPIN interrutps
-	sh	$0, 0x08($27)		// INTROUTE: disable EPOUT interrutps
-
-	li	$9, 0x61
-	sb	$9, 0x01($27)		// POWER: HSENAB | SUSPENDM | SOFTCONN
-
-	//--------------------------------------------------------------
-	// Initialize USB states
-	//--------------------------------------------------------------
-	li	$22, 0			// set EP0 to IDLE state
-	li	$23, 1			// no data stage
-
-	//--------------------------------------------------------------
-	// Main loop of polling the usb commands
-	//--------------------------------------------------------------
-usb_command_loop:
-	lbu	$9, 0x0a($27)		// read INTRUSB
-	andi	$9, 0x04		// check USB_INTR_RESET
-	beqz	$9, check_intr_ep0in
-	nop
-
-	//--------------------------------------------------------------
- 	// 1. Handle USB reset interrupt
-	//--------------------------------------------------------------
-handle_reset_intr:
-	lbu	$9, 0x01($27)		// read POWER
-	andi	$9, 0x10		// test HS_MODE
-	bnez	$9, _usb_set_maxpktsize
-	li	$9, 512			// max packet size of HS mode
-	li	$9, 64			// max packet size of FS mode
-
-_usb_set_maxpktsize:
-	li	$8, 1
-	sb	$8, 0x0e($27)		// set INDEX 1
-
-	sh	$9, 0x10($27)		// INMAXP
-	sb	$0, 0x13($27)		// INCSRH
-	sh	$9, 0x14($27)		// OUTMAXP
-	sb	$0, 0x17($27)		// OUTCSRH
-
-_usb_flush_fifo:
-	li	$8, 0x48		// INCSR_CDT && INCSR_FF
-	sb	$8, 0x12($27)		// INCSR
-	li	$8, 0x90		// OUTCSR_CDT && OUTCSR_FF
-	sb	$8, 0x16($27)		// OUTCSR
-
-	li	$22, 0			// set EP0 to IDLE state
-	li	$23, 1			// no data stage
-
-	//--------------------------------------------------------------
-	// 2. Check and handle EP0 interrupt
-	//--------------------------------------------------------------
-check_intr_ep0in:
-	lhu	$10, 0x02($27)		// read INTRIN
-	andi	$9, $10, 0x1		// check EP0 interrupt
-	beqz	$9, check_intr_ep1in
-	nop
-
-handle_ep0_intr:
-	sb	$0, 0x0e($27)		// set INDEX 0
-	lbu	$11, 0x12($27)		// read CSR0
-
-	andi	$9, $11, 0x04		// check SENTSTALL
-	beqz	$9, _ep0_setupend
-	nop
-
-_ep0_sentstall:
-	andi	$9, $11, 0xdb
-	sb	$9, 0x12($27)		// clear SENDSTALL and SENTSTALL
-	li	$22, 0			// set EP0 to IDLE state
-
-_ep0_setupend:
-	andi	$9, $11, 0x10		// check SETUPEND
-	beqz	$9, ep0_idle_state
-	nop
-
-	ori	$9, $11, 0x80
-	sb	$9, 0x12($27)		// set SVDSETUPEND
-	li	$22, 0			// set EP0 to IDLE state
-
-ep0_idle_state:
-	bnez	$22, ep0_tx_state
-	nop
-
-	//--------------------------------------------------------------
-	// 2.1 Handle EP0 IDLE state interrupt
-	//--------------------------------------------------------------
-	andi	$9, $11, 0x01		// check OUTPKTRDY
-	beqz	$9, check_intr_ep1in
-	nop
-
-	//--------------------------------------------------------------
-	// Read 8-bytes setup packet from the FIFO
-	//--------------------------------------------------------------
-	lw	$25, 0x20($27)		// first word of setup packet
-	lw	$26, 0x20($27)		// second word of setup packet
-
-	andi	$9, $25, 0x60		// bRequestType & USB_TYPE_MASK
-	beqz	$9, _ep0_std_req
-	nop
-
-	//--------------------------------------------------------------
-	// 2.1.1 Vendor-specific setup request
-	//--------------------------------------------------------------
-_ep0_vend_req:
-	li	$22, 0			// set EP0 to IDLE state
-	li	$23, 1			// NoData = 1
-
-	andi	$9, $25, 0xff00		// check bRequest
-	srl	$9, $9, 8
-	beqz	$9, __ep0_get_cpu_info
-	sub	$8, $9, 0x1
-	beqz	$8, __ep0_set_data_address
-	sub	$8, $9, 0x2
-	beqz	$8, __ep0_set_data_length
-	sub	$8, $9, 0x3
-	beqz	$8, __ep0_flush_caches
-	sub	$8, $9, 0x4
-	beqz	$8, __ep0_prog_start1
-	sub	$8, $9, 0x5
-	beqz	$8, __ep0_prog_start2
-	nop
-	b	_ep0_idle_state_fini	// invalid request
-	nop
-
-__ep0_get_cpu_info:
-	load_addr $20, cpu_info_data	// data pointer to transfer
-	li	$21, 8			// bytes left to transfer
-	li	$22, 1			// set EP0 to TX state
-	li	$23, 0			// NoData = 0
-
-	b	_ep0_idle_state_fini
-	nop
-
-__ep0_set_data_address:
-	li	$9, 0xffff0000
-	and	$9, $25, $9
-	andi	$8, $26, 0xffff
-	or	$20, $9, $8		// data address of next transfer
-
-	b	_ep0_idle_state_fini
-	nop
-
-__ep0_set_data_length:
-	li	$9, 0xffff0000
-	and	$9, $25, $9
-	andi	$8, $26, 0xffff
-	or	$21, $9, $8		// data length of next transfer
-
-	li	$9, 0x48		// SVDOUTPKTRDY and DATAEND
-	sb	$9, 0x12($27)		// CSR0
-
-	// We must write packet to FIFO before EP1-IN interrupt here.
-	b	handle_epin1_intr
-	nop
-
-__ep0_flush_caches:
-	// Flush dcache and invalidate icache.
-	li	$8, 0x80000000
-	addi	$9, $8, 0x3fe0		// total 16KB
-
-1:
-	cache	0x0, 0($8)		// Index_Invalidate_I
-	cache	0x1, 0($8)		// Index_Writeback_Inv_D
-	bne	$8, $9, 1b
-	addiu	$8, $8, 32
-
-	// flush write-buffer
-	sync
-
-	// Invalidate BTB
-	mfc0	$8, $16, 7		// CP0_CONFIG
-	nop
-	ori	$8, 2
-	mtc0	$8, $16, 7
-	nop
-
-	b	_ep0_idle_state_fini
-	nop
-
-__ep0_prog_start1:
-	li	$9, 0x48		// SVDOUTPKTRDY and DATAEND
-	sb	$9, 0x12($27)		// CSR0
-
-	li	$9, 0xffff0000
-	and	$9, $25, $9
-	andi	$8, $26, 0xffff
-	or	$20, $9, $8		// target address
-
-	b	xfer_d2i
-	li	$19, 0x2000		// 16KB data length
-
-__ep0_prog_start2:
-	li	$9, 0x48		// SVDOUTPKTRDY and DATAEND
-	sb	$9, 0x12($27)		// CSR0
-
-	li	$9, 0xffff0000
-	and	$9, $25, $9
-	andi	$8, $26, 0xffff
-	or	$20, $9, $8		// target address
-
-	jalr	$20			// jump, and place the return address in $31
-	nop
-
-__ep0_prog_start2_return:
-	// User code can return to here after executing itself, by jumping to $31.
-	b	usb_boot_return
-	nop
-
-	//--------------------------------------------------------------
-	// 2.1.2 Standard setup request
-	//--------------------------------------------------------------
-_ep0_std_req:
-	andi	$12, $25, 0xff00	// check bRequest
-	srl	$12, $12, 8
-	sub	$9, $12, 0x05		// check USB_REQ_SET_ADDRESS
-	bnez	$9, __ep0_req_set_config
-	nop
-
-	//--------------------------------------------------------------
-	// Handle USB_REQ_SET_ADDRESS
-	//--------------------------------------------------------------
-__ep0_req_set_addr:
-	srl	$9, $25, 16		// get wValue
-	sb	$9, 0x0($27)		// set FADDR
-	li	$23, 1			// NoData = 1
-	b	_ep0_idle_state_fini
-	nop
-
-__ep0_req_set_config:
-	sub	$9, $12, 0x09		// check USB_REQ_SET_CONFIGURATION
-	bnez	$9, __ep0_req_get_desc
-	nop
-
-	//--------------------------------------------------------------
-	// Handle USB_REQ_SET_CONFIGURATION
-	//--------------------------------------------------------------
-	li	$23, 1			// NoData = 1
-	b	_ep0_idle_state_fini
-	nop
-
-__ep0_req_get_desc:
-	sub	$9, $12, 0x06		// check USB_REQ_GET_DESCRIPTOR
-	bnez	$9, _ep0_idle_state_fini
-	li	$23, 1			// NoData = 1
-
-	//--------------------------------------------------------------
-	// Handle USB_REQ_GET_DESCRIPTOR
-	//--------------------------------------------------------------
-	li	$23, 0			// NoData = 0
-
-	srl	$9, $25, 24		// wValue >> 8
-	sub	$8, $9, 0x01		// check USB_DT_DEVICE
-	beqz	$8, ___ep0_get_dev_desc
-	srl	$21, $26, 16		// get wLength
-	sub	$8, $9, 0x02		// check USB_DT_CONFIG
-	beqz	$8, ___ep0_get_conf_desc
-	sub	$8, $9, 0x03		// check USB_DT_STRING
-	beqz	$8, ___ep0_get_string_desc
-	sub	$8, $9, 0x06		// check USB_DT_DEVICE_QUALIFIER
-	beqz	$8, ___ep0_get_dev_qualifier
-	nop
-	b	_ep0_idle_state_fini
-	nop
-
-___ep0_get_dev_desc:
-	load_addr	$20, device_desc	// data pointer
-	li	$22, 1			// set EP0 to TX state
-	sub	$8, $21, 18
-	blez	$8, _ep0_idle_state_fini // wLength <= 18
-	nop
-	li	$21, 18			// max length of device_desc
-	b	_ep0_idle_state_fini
-	nop
-
-___ep0_get_dev_qualifier:
-	load_addr	$20, dev_qualifier	// data pointer
-	li	$22, 1			// set EP0 to TX state
-	sub	$8, $21, 10
-	blez	$8, _ep0_idle_state_fini // wLength <= 10
-	nop
-	li	$21, 10			// max length of dev_qualifier
-	b	_ep0_idle_state_fini
-	nop
-
-___ep0_get_conf_desc:
-	load_addr	$20, config_desc_fs	// data pointer of FS mode
-	lbu	$8, 0x01($27)		// read POWER
-	andi	$8, 0x10		// test HS_MODE
-	beqz	$8, ___ep0_get_conf_desc2
-	nop
-	load_addr $20, config_desc_hs	// data pointer of HS mode
-
-___ep0_get_conf_desc2:
-	li	$22, 1			// set EP0 to TX state
-	sub	$8, $21, 32
-	blez	$8, _ep0_idle_state_fini // wLength <= 32
-	nop
-	li	$21, 32			// max length of config_desc
-	b	_ep0_idle_state_fini
-	nop
-
-___ep0_get_string_desc:
-	li	$22, 1			// set EP0 to TX state
-
-	srl	$9, $25, 16		// wValue & 0xff
-	andi	$9, 0xff
-
-	sub	$8, $9, 1
-	beqz	$8, ___ep0_get_string_manufacture
-	sub	$8, $9, 2
-	beqz	$8, ___ep0_get_string_product
-	nop
-
-___ep0_get_string_lang_ids:
-	load_addr	$20, string_lang_ids	// data pointer
-	b	_ep0_idle_state_fini
-	li	$21, 4			// data length
-
-___ep0_get_string_manufacture:
-	load_addr	$20, string_manufacture	// data pointer
-	b	_ep0_idle_state_fini
-	li	$21, 16			// data length
-
-___ep0_get_string_product:
-	load_addr	$20, string_product	// data pointer
-	b	_ep0_idle_state_fini
-	li	$21, 46			// data length
-
-_ep0_idle_state_fini:
-	li	$9, 0x40		// SVDOUTPKTRDY
-	beqz	$23, _ep0_idle_state_fini2
-	nop
-	ori	$9, $9, 0x08		// DATAEND
-_ep0_idle_state_fini2:
-	sb	$9, 0x12($27)		// CSR0
-	beqz	$22, check_intr_ep1in
-	nop
-
-	//--------------------------------------------------------------
-	// 2.2 Handle EP0 TX state interrupt
-	//--------------------------------------------------------------
-ep0_tx_state:
-	sub	$9, $22, 1
-	bnez	$9, check_intr_ep1in
-	nop
-
-	sub	$9, $21, 64		// max packetsize
-	blez	$9, _ep0_tx_state2	// data count <= 64
-	ori	$19, $21, 0
-	li	$19, 64
-
-_ep0_tx_state2:
-	beqz	$19, _ep0_tx_state3	// send ZLP
-	ori	$18, $19, 0		// record bytes to be transferred
-	sub	$21, $21, $19		// decrement data count
-
-_ep0_fifo_write_loop:
-	lbu	$9, 0($20)		// read data
-	sb	$9, 0x20($27)		// load FIFO
-	sub	$19, $19, 1		// decrement counter
-	bnez	$19, _ep0_fifo_write_loop
-	addi	$20, $20, 1		// increment data pointer
-
-	sub	$9, $18, 64		// max packetsize
-	beqz	$9, _ep0_tx_state4
-	nop
-
-_ep0_tx_state3:
-	// transferred bytes < max packetsize
-	li	$9, 0x0a		// set INPKTRDY and DATAEND
-	sb	$9, 0x12($27)		// CSR0
-	li	$22, 0			// set EP0 to IDLE state
-	b	check_intr_ep1in
-	nop
-
-_ep0_tx_state4:
-	// transferred bytes == max packetsize
-	li	$9, 0x02		// set INPKTRDY
-	sb	$9, 0x12($27)		// CSR0
-	b	check_intr_ep1in
-	nop
-
-	//--------------------------------------------------------------
-	// 3. Check and handle EP1 BULK-IN interrupt
-	//--------------------------------------------------------------
-check_intr_ep1in:
-	andi	$9, $10, 0x2		// check EP1 IN interrupt
-	beqz	$9, check_intr_ep1out
-	nop
-
-handle_epin1_intr:
-	li	$9, 1
-	sb	$9, 0x0e($27)		// set INDEX 1
-	lbu	$9, 0x12($27)		// read INCSR
-
-	andi	$8, $9, 0x2		// check INCSR_FFNOTEMPT
-	bnez	$8, _epin1_tx_state4
-	nop
-
-_epin1_write_fifo:
-	lhu	$9, 0x10($27)		// get INMAXP
-	sub	$8, $21, $9
-	blez	$8, _epin1_tx_state1	// bytes left <= INMAXP
-	ori	$19, $21, 0
-	ori	$19, $9, 0
-
-_epin1_tx_state1:
-	beqz	$19, _epin1_tx_state4	// No data
-	nop
-
-	sub	$21, $21, $19		// decrement data count
-
-	srl	$5, $19, 2		// # of word
-	andi	$6, $19, 0x3		// # of byte
-	beqz	$5, _epin1_tx_state2
-	nop
-
-_epin1_fifo_write_word:
-	lw	$9, 0($20)		// read data from source address
-	sw	$9, 0x24($27)		// write FIFO
-	sub	$5, $5, 1		// decrement counter
-	bnez	$5, _epin1_fifo_write_word
-	addiu	$20, $20, 4		// increment dest address
-
-_epin1_tx_state2:
-	beqz	$6, _epin1_tx_state3
-	nop
-
-_epin1_fifo_write_byte:
-	lbu	$9, 0($20)		// read data from source address
-	sb	$9, 0x24($27)		// write FIFO
-	sub	$6, $6, 1		// decrement counter
-	bnez	$6, _epin1_fifo_write_byte
-	addiu	$20, $20, 1		// increment dest address
-
-_epin1_tx_state3:
-	li	$9, 0x1
-	sb	$9, 0x12($27)		// INCSR, set INPKTRDY
-
-_epin1_tx_state4:
-	// nop
-
-	//--------------------------------------------------------------
-	// 4. Check and handle EP1 BULK-OUT interrupt
-	//--------------------------------------------------------------
-check_intr_ep1out:
-	lhu	$9, 0x04($27)		// read INTROUT
-	andi	$9, 0x2
-	beqz	$9, check_status_next
-	nop
-
-handle_epout1_intr:
-	li	$9, 1
-	sb	$9, 0x0e($27)		// set INDEX 1
-
-	lbu	$9, 0x16($27)		// read OUTCSR
-	andi	$9, 0x1			// check OUTPKTRDY
-	beqz	$9, check_status_next
-	nop
-
-_epout1_read_fifo:
-	lhu	$19, 0x18($27)		// read OUTCOUNT
-	srl	$5, $19, 2		// # of word
-	andi	$6, $19, 0x3		// # of byte
-	beqz	$5, _epout1_rx_state1
-	nop
-
-_epout1_fifo_read_word:
-	lw	$9, 0x24($27)		// read FIFO
-	sw	$9, 0($20)		// store to dest address
-	sub	$5, $5, 1		// decrement counter
-	bnez	$5, _epout1_fifo_read_word
-	addiu	$20, $20, 4		// increment dest address
-
-_epout1_rx_state1:
-	beqz	$6, _epout1_rx_state2
-	nop
-
-_epout1_fifo_read_byte:
-	lbu	$9, 0x24($27)		// read FIFO
-	sb	$9, 0($20)		// store to dest address
-	sub	$6, $6, 1		// decrement counter
-	bnez	$6, _epout1_fifo_read_byte
-	addiu	$20, $20, 1		// increment dest address
-
-_epout1_rx_state2:
-	sb	$0, 0x16($27)		// clear OUTPKTRDY
-
-check_status_next:
-	b	usb_command_loop
-	nop
-
-//--------------------------------------------------------------
-// Device/Configuration/Interface/Endpoint/String Descriptors
-//--------------------------------------------------------------
-
-	.align	2
-device_desc:
-	.byte	0x12		// bLength
-	.byte	0x01		// bDescriptorType
-	.byte	0x00		// bcdUSB
-	.byte	0x02		// bcdUSB
-	.byte	0x00		// bDeviceClass
-	.byte	0x00		// bDeviceSubClass
-	.byte	0x00		// bDeviceProtocol
-	.byte	0x40		// bMaxPacketSize0
-	.byte	0x1a		// idVendor
-	.byte	0x60		// idVendor
-	.byte	0x40		// idProduct
-	.byte	0x47		// idProduct
-	.byte	0x00		// bcdDevice
-	.byte	0x01		// bcdDevice
-	.byte	0x01		// iManufacturer
-	.byte	0x02		// iProduct
-	.byte	0x00		// iSerialNumber
-	.byte	0x01		// bNumConfigurations
-
-	.align	2
-dev_qualifier:
-	.byte	0x0a		// bLength
-	.byte	0x06		// bDescriptorType
-	.byte	0x00		// bcdUSB
-	.byte	0x02		// bcdUSB
-	.byte	0x00		// bDeviceClass
-	.byte	0x00		// bDeviceSubClass
-	.byte	0x00		// bDeviceProtocol
-	.byte	0x40		// bMaxPacketSize0
-	.byte	0x01		// bNumConfigurations
-	.byte	0x00		// bRESERVED
-
-	.align	2
-config_desc_hs:
-	.byte	0x09		// bLength
-	.byte	0x02		// bDescriptorType
-	.byte	0x20		// wTotalLength
-	.byte	0x00		// wTotalLength
-	.byte	0x01		// bNumInterfaces
-	.byte	0x01		// bConfigurationValue
-	.byte	0x00		// iConfiguration
-	.byte	0xc0		// bmAttributes
-	.byte	0x01		// MaxPower
-intf_desc_hs:
-	.byte	0x09		// bLength
-	.byte	0x04		// bDescriptorType
-	.byte	0x00		// bInterfaceNumber
-	.byte	0x00		// bAlternateSetting
-	.byte	0x02		// bNumEndpoints
-	.byte	0xff		// bInterfaceClass
-	.byte	0x00		// bInterfaceSubClass
-	.byte	0x50		// bInterfaceProtocol
-	.byte	0x00		// iInterface
-ep1_desc_hs:
-	.byte	0x07		// bLength
-	.byte	0x05		// bDescriptorType
-	.byte	0x01		// bEndpointAddress
-	.byte	0x02		// bmAttributes
-	.byte	0x00		// wMaxPacketSize
-	.byte	0x02		// wMaxPacketSize
-	.byte	0x00		// bInterval
-ep2_desc_hs:
-	.byte	0x07		// bLength
-	.byte	0x05		// bDescriptorType
-	.byte	0x81		// bEndpointAddress
-	.byte	0x02		// bmAttributes
-	.byte	0x00		// wMaxPacketSize
-	.byte	0x02		// wMaxPacketSize
-	.byte	0x00		// bInterval
-
-	.align	2
-config_desc_fs:
-	.byte	0x09		// bLength
-	.byte	0x02		// bDescriptorType
-	.byte	0x20		// wTotalLength
-	.byte	0x00		// wTotalLength
-	.byte	0x01		// bNumInterfaces
-	.byte	0x01		// bConfigurationValue
-	.byte	0x00		// iConfiguration
-	.byte	0xc0		// bmAttributes
-	.byte	0x01		// MaxPower
-intf_desc_fs:
-	.byte	0x09		// bLength
-	.byte	0x04		// bDescriptorType
-	.byte	0x00		// bInterfaceNumber
-	.byte	0x00		// bAlternateSetting
-	.byte	0x02		// bNumEndpoints
-	.byte	0xff		// bInterfaceClass
-	.byte	0x00		// bInterfaceSubClass
-	.byte	0x50		// bInterfaceProtocol
-	.byte	0x00		// iInterface
-ep1_desc_fs:
-	.byte	0x07		// bLength
-	.byte	0x05		// bDescriptorType
-	.byte	0x01		// bEndpointAddress
-	.byte	0x02		// bmAttributes
-	.byte	0x40		// wMaxPacketSize
-	.byte	0x00		// wMaxPacketSize
-	.byte	0x00		// bInterval
-ep2_desc_fs:
-	.byte	0x07		// bLength
-	.byte	0x05		// bDescriptorType
-	.byte	0x81		// bEndpointAddress
-	.byte	0x02		// bmAttributes
-	.byte	0x40		// wMaxPacketSize
-	.byte	0x00		// wMaxPacketSize
-	.byte	0x00		// bInterval
-
-	.align	2
-string_lang_ids:
-	.byte	0x04
-	.byte	0x03
-	.byte	0x09
-	.byte	0x04
-
-	.align	2
-string_manufacture:
-	.byte	0x10
-	.byte	0x03
-	.byte	0x49
-	.byte	0x00
-	.byte	0x6e
-	.byte	0x00
-	.byte	0x67
-	.byte	0x00
-	.byte	0x65
-	.byte	0x00
-	.byte	0x6e
-	.byte	0x00
-	.byte	0x69
-	.byte	0x00
-	.byte	0x63
-	.byte	0x00
-
-	.align	2
-string_product:
-	.byte	0x2e
-	.byte	0x03
-	.byte	0x4a
-	.byte	0x00
-	.byte	0x5a
-	.byte	0x00
-	.byte	0x34
-	.byte	0x00
-	.byte	0x37
-	.byte	0x00
-	.byte	0x34
-	.byte	0x00
-	.byte	0x30
-	.byte	0x00
-	.byte	0x20
-	.byte	0x00
-	.byte	0x55
-	.byte	0x00
-	.byte	0x53
-	.byte	0x00
-	.byte	0x42
-	.byte	0x00
-	.byte	0x20
-	.byte	0x00
-	.byte	0x42
-	.byte	0x00
-	.byte	0x6f
-	.byte	0x00
-	.byte	0x6f
-	.byte	0x00
-	.byte	0x74
-	.byte	0x00
-	.byte	0x20
-	.byte	0x00
-	.byte	0x44
-	.byte	0x00
-	.byte	0x65
-	.byte	0x00
-	.byte	0x76
-	.byte	0x00
-	.byte	0x69
-	.byte	0x00
-	.byte	0x63
-	.byte	0x00
-	.byte	0x65
-	.byte	0x00
-
-	.align	2
-cpu_info_data:
-	.byte	0x4a
-	.byte	0x5a
-	.byte	0x34
-	.byte	0x37
-	.byte	0x34
-	.byte	0x30
-	.byte	0x56
-	.byte	0x31
-usbboot_end:
-
-    .set reorder

package/boot/uboot-xburst/files/include/configs/avt2.h

@@ -1,26 +0,0 @@
-#ifndef __CONFIG_AVT2_H
-#define __CONFIG_AVT2_H
-
-#include <configs/nanonote.h>
-
-#define CONFIG_AVT2 1
-
-#define CONFIG_BOOTARGS		"mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait avt2=1"
-#define CONFIG_BOOTARGSFROMSD	"mem=64M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait avt2=1"
-#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
-
-/* SDRAM paramters */
-#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
-#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
-#define SDRAM_ROW		13	/* Row address: 11 to 13 */
-#define SDRAM_COL		10	/* Column address: 8 to 12 */
-#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
-
-/* SDRAM Timings, unit: ns */
-#define SDRAM_TRAS		45	/* RAS# Active Time */
-#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
-#define SDRAM_TPC		20	/* RAS# Precharge Time */
-#define SDRAM_TRWL		7	/* Write Latency Time */
-#define SDRAM_TREF	        15625	/* Refresh period: 8192 cycles/64ms */
-
-#endif	/* __CONFIG_AVT_H */

package/boot/uboot-xburst/files/include/configs/n516.h

@@ -1,311 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file contains the configuration parameters for the pavo board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-//#define DEBUG
-//#define DEBUG_SHELL
-
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core */
-#define CONFIG_JzRISC		1  /* JzRISC core */
-#define CONFIG_JZSOC		1  /* Jz SoC */
-#define CONFIG_JZ4740		1  /* Jz4740 SoC */
-#define CONFIG_PAVO		1  /* PAVO validation board */
-
-#define CONFIG_BOARD_NAME	"n516"
-#define CONFIG_BOARD_HWREV	"1.0"
-#define CONFIG_FIRMWARE_EPOCH	"0"
-#define CONFIG_UPDATE_TMPBUF	0x80600000
-#define CONFIG_UPDATE_CHUNKSIZE	0x800000
-#define CONFIG_UPDATE_FILENAME	"update.oifw"
-#define CONFIG_UPDATE_FILEEXT	".oifw"
-#define CONFIG_UBI_PARTITION	"UBI"
-
-#define CONFIG_SKIP_LOWLEVEL_INIT	1
-#undef  CONFIG_SKIP_RELOCATE_UBOOT
-
-#if 0
-#define CONFIG_LCD                 /* LCD support */
-#define CONFIG_JZLCD_METRONOME_800x600
-#define LCD_BPP			LCD_COLOR8
-
-#define WFM_DATA_SIZE  ( 1 << 14 )
-#define CONFIG_METRONOME_WF_LEN (64 * (1 << 10))
-#define CONFIG_METRONOME_WF_NAND_OFFSET (0x100000)
-#define BMP_LOGO_HEIGHT 0
-#define CONFIG_UBI_WF_VOLUME "waveforms"
-#define CONFIG_UBI_BOOTSPLASH_VOLUME "bootsplash"
-#define CONFIG_METRONOME_BOOTSPLASH_LEN 480000
-#endif
-
-#if 0
-#define CONFIG_JZSOC_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED	100000
-#define CONFIG_SYS_I2C_SLAVE	0
-#define CONFIG_LPC_I2C_ADDR	0x54
-#endif
-
-#define JZ4740_NORBOOT_CFG	JZ4740_NORBOOT_16BIT	/* NOR Boot config code */
-#define JZ4740_NANDBOOT_CFG	JZ4740_NANDBOOT_B8R3	/* NAND Boot config code */
-
-#define CONFIG_SYS_CPU_SPEED		336000000	/* CPU clock: 336 MHz */
-#define CONFIG_SYS_EXTAL		12000000	/* EXTAL freq: 12 MHz */
-#define	CONFIG_SYS_HZ			(CONFIG_SYS_EXTAL/256) /* incrementer freq */
-
-#define CONFIG_SYS_UART_BASE  		UART0_BASE	/* Base of the UART channel */
-
-#define CONFIG_BAUDRATE		57600
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-
-#define CONFIG_MMC      	1
-#define CONFIG_GENERIC_MMC	1
-#define CONFIG_JZ_MMC		1
-#define CONFIG_FAT		1
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 ">"
-#define CONFIG_CMDLINE_EDITING
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_BDI		/* bdinfo			*/
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_ECHO		/* echo arguments		*/
-#undef CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
-#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
-#undef CONFIG_CMD_IMI		/* iminfo			*/
-#undef CONFIG_CMD_ITEST	/* Integer (and string) test	*/
-#undef CONFIG_CMD_LOADB	/* loadb			*/
-#undef CONFIG_CMD_LOADS	/* loads			*/
-#undef CONFIG_CMD_NFS		/* NFS support			*/
-#undef CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
-#undef CONFIG_CMD_SOURCE	/* "source" command support	*/
-#undef CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
-#undef CONFIG_CMD_NET
-
-//#define CONFIG_CMD_ASKENV
-//#define CONFIG_CMD_DHCP
-//#define CONFIG_CMD_PING
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-/*#define CONFIG_CMD_UBI*/
-/*#define CONFIG_CMD_MTDPARTS*/
-//#define CONFIG_CMD_JFFS2
-//#define CONFIG_JFFS2_NAND
-//#define CONFIG_JFFS2_CMDLINE
-#define CONFIG_CMD_UPDATE
-
-#define CONFIG_DOS_PARTITION
-
-/*#define CONFIG_MTD_PARTITIONS*/
-#define CONFIG_RBTREE
-
-#define CONFIG_BOOTP_MASK	( CONFIG_BOOTP_DEFAUL )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#if 0
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTDELAY	0
-#define CONFIG_BOOTFILE	        uImage	/* file to load */
-#define CONFIG_BOOTARGS		"mem=64M console=ttyS0,57600n8 ip=off rootfstype=ubifs root=ubi:rootfs ubi.mtd=UBI rw panic=5 " MTDPARTS_DEFAULT
-#define CONFIG_BOOTCOMMAND	"check_and_update; setenv bootargs $bootargs $batt_level_param; ubi read 0x80600000 bootsplash && show_image 0x80600000; ubi read 0x80600000 kernel; bootm 0x80600000; ubi read 0x80600000 errorsplash && show_image 0x80600000; while test 0 = 0; do check_and_update; done"
-#define CONFIG_SYS_AUTOLOAD	"n"		/* No autoload */
-#define CONFIG_IPADDR		192.168.111.1
-#define CONFIG_SERVERIP		192.168.111.2
-#define MTDIDS_DEFAULT		"nand0=jz4740-nand"
-#define MTDPARTS_DEFAULT	"mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)"
-#define CONFIG_EXTRA_ENV_SETTINGS "mtdids=nand0=jz4740-nand\0mtdparts=mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)\0" \
-				"stdout=serial\0stderr=lcd\0"
-#endif
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
-#define CONFIG_BOOTDELAY	0
-#define CONFIG_BOOTFILE		"uImage"	/* file to load */
-#define CONFIG_BOOTARGS		"mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
-#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
-
-
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/*
- * Serial download configuration
- *
- */
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP				/* undef to save memory      */
-#define	CONFIG_SYS_PROMPT		"n516 # "	/* Monitor Command Prompt    */
-#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16		/* max number of command args*/
-
-#define CONFIG_SYS_MALLOC_LEN		1024*1024*2
-#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
-
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
-
-#define	CONFIG_SYS_LOAD_ADDR		0x80600000     /* default load address	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x80100000
-#define CONFIG_SYS_MEMTEST_END		0x80800000
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * NAND FLASH configuration
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define NAND_MAX_CHIPS          1
-#define CONFIG_SYS_NAND_BASE           0xB8000000
-#define CONFIG_SYS_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
-
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 8k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- */
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x80100000	/* Load NUB to this addr	*/
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)	/* Offset to RAM U-Boot image	*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)	/* Size of RAM U-Boot image	*/
-
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)	/* NAND chip block size		*/
-#define CONFIG_SYS_NAND_BADBLOCK_PAGE	63		/* NAND bad block was marked at this page in a block, starting from 0 */
-#define CONFIG_SYS_NAND_ECC_POS		6
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-//#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_SIZE			(128 * 1024)
-//#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE)	/* environment starts here  */
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
-//#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * NOR FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-
-#define PHYS_FLASH_1		0xa8000000 /* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE   /* in pavo/config.mk TEXT_BASE=0x88000000*/ 
-#define	CONFIG_SYS_SYS_MONITOR_BASE	TEXT_BASE   /* in pavo/config.mk TEXT_BASE=0x88000000*/ 
-#define	CONFIG_SYS_MONITOR_LEN		(256*1024)  /* Reserve 256 kB for Monitor */
-
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define	CONFIG_ENV_IS_NOWHERE	1
-#define CONFIG_ENV_ADDR		0xa8040000
-#define CONFIG_ENV_SIZE		0x20000
-#endif
-
-/*-----------------------------------------------------------------------
- * SDRAM Info.
- */
-#define CONFIG_NR_DRAM_BANKS	1
-
-// SDRAM paramters
-#define SDRAM_BW16		0	/* Data bus width: 0-32bit, 1-16bit */
-#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
-#define SDRAM_ROW		13	/* Row address: 11 to 13 */
-#define SDRAM_COL		9	/* Column address: 8 to 12 */
-#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
-
-// SDRAM Timings, unit: ns
-#define SDRAM_TRAS		45	/* RAS# Active Time */
-#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
-#define SDRAM_TPC		20	/* RAS# Precharge Time */
-#define SDRAM_TRWL		7	/* Write Latency Time */
-#define SDRAM_TREF	        15625	/* Refresh period: 4096 refresh cycles/64ms */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*-----------------------------------------------------------------------
- * GPIO definition
- */
-#define GPIO_SD_VCC_EN_N	113 /* GPD17 */
-#define GPIO_SD_CD_N           103 /* GPD7 */
-#define GPIO_SD_WP             111 /* GPD15 */
-#define GPIO_USB_DETE          115 /* GPD6 */
-//#define GPIO_DC_DETE_N               103 /* GPD7 */
-#define GPIO_CHARG_STAT_N      112 /* GPD15 */
-#define GPIO_DISP_OFF_N                97 /* GPD1 */
-#define GPIO_UDC_HOTPLUG       100 /* GPD4 */
-#define GPIO_LED_EN            124 /* GPD28 */
-
-#define GPIO_RST_L          50   /* GPB18 LCD_SPL */
-#define GPIO_LCDRDY         49   /* GPB17 LCD_CLS */
-#define GPIO_STBY           86   /* GPC22 LCD_PS */
-#define GPIO_ERR            87   /* GPC23 LCD_REV */
-
-#endif	/* __CONFIG_H */

package/boot/uboot-xburst/files/include/configs/nanonote.h

@@ -1,191 +0,0 @@
-/*
- * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 3 of the License, or (at your option) any later version.
- */
-
-/*
- * This file contains the configuration parameters for the NanoNote.
- */
-#ifndef __CONFIG_NANONOTE_H
-#define __CONFIG_NANONOTE_H
-
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core */
-#define CONFIG_JzRISC		1  /* JzRISC core */
-#define CONFIG_JZSOC		1  /* Jz SoC */
-#define CONFIG_JZ4740		1  /* Jz4740 SoC */
-#define CONFIG_NANONOTE		1
-
-#define CONFIG_LCD		1  /* LCD support */
-#define LCD_BPP			LCD_COLOR32	/*5:18,24,32 bits per pixel */
-#define CONFIG_SYS_WHITE_ON_BLACK	1
-
-#define CONFIG_SYS_CPU_SPEED	336000000	/* CPU clock: 336 MHz */
-#define CONFIG_SYS_EXTAL		12000000	/* EXTAL freq: 12 MHz */
-#define CONFIG_SYS_HZ		(CONFIG_SYS_EXTAL / 256) /* incrementer freq */
-#define CONFIG_SYS_MIPS_TIMER_FREQ	CONFIG_SYS_CPU_SPEED
-
-#define CONFIG_SYS_UART_BASE	UART0_BASE	/* Base of the UART channel */
-#define CONFIG_BAUDRATE		57600
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_MMC      	1
-#define CONFIG_FAT      	1
-#define CONFIG_DOS_PARTITION	1
-#define CONFIG_SKIP_LOWLEVEL_INIT	1
-#define CONFIG_BOARD_EARLY_INIT_F	1
-#define CONFIG_SYS_NO_FLASH	1
-#define CONFIG_ENV_OVERWRITE	1
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
-#define CONFIG_BOOTDELAY	0
-#define CONFIG_BOOTFILE		"uImage"	/* file to load */
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BOOTD	/* bootd			*/
-#define CONFIG_CMD_CONSOLE	/* coninfo			*/
-#define CONFIG_CMD_ECHO		/* echo arguments		*/
-
-#define CONFIG_CMD_LOADB	/* loadb			*/
-#define CONFIG_CMD_LOADS	/* loads			*/
-#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
-#define CONFIG_CMD_MISC		/* Misc functions like sleep etc*/
-#define CONFIG_CMD_RUN		/* run command in env variable	*/
-#define CONFIG_CMD_SAVEENV	/* saveenv			*/
-#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
-#define CONFIG_CMD_SOURCE	/* "source" command support	*/
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-
-/*
- * Serial download configuration
- */
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define	CONFIG_SYS_PROMPT		"QI# "	/* Monitor Command Prompt */
-#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16	/* max number of command args*/
-
-#define CONFIG_SYS_MALLOC_LEN		896 * 1024
-#define CONFIG_SYS_BOOTPARAMS_LEN	128 * 1024
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
-#define CONFIG_SYS_LOAD_ADDR		0x80600000     /* default load address */
-#define CONFIG_SYS_MEMTEST_START	0x80100000
-#define CONFIG_SYS_MEMTEST_END		0x80800000
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars */
-
-/*
- * NAND FLASH configuration
- */
-/* NAND Boot config code */
-#define JZ4740_NANDBOOT_CFG	JZ4740_NANDBOOT_B8R3
-
-#define NANONOTE_NAND_SIZE	2 /* if board nand flash is 1GB, set to 1
-				   * if board nand flash is 2GB, set to 2
-				   * for change the PAGE_SIZE and BLOCK_SIZE
-				   * will delete when there is no 1GB flash
-				   */
-
-#define CONFIG_SYS_NAND_PAGE_SIZE	(2048 * NANONOTE_NAND_SIZE)
-/* nand chip block size	*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * NANONOTE_NAND_SIZE << 10)
-/* nand bad block was marked at this page in a block, start from 0 */
-#define CONFIG_SYS_NAND_BADBLOCK_PAGE	127
-/* ECC offset position in oob area, default value is 6 if it isn't defined */
-#define CONFIG_SYS_NAND_ECC_POS	(6 * NANONOTE_NAND_SIZE)
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define NAND_MAX_CHIPS          1
-#define CONFIG_SYS_NAND_BASE           0xB8000000
-#define CONFIG_SYS_NAND_SELECT_DEVICE  1 /* nand driver supports mutipl.*/
-#define CONFIG_SYS_ONENAND_BASE	CONFIG_SYS_NAND_BASE
-
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 8k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- */
-#define CONFIG_SYS_NAND_U_BOOT_DST		0x80100000	/* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST 
-/* Start NUB from this addr*/
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)	/* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)	/* Size of RAM U-Boot image */
-
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	(CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE)
-/* environment starts here  */
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-
-/* in board/nanonote/config.mk TEXT_BAS = 0x88000000 */
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
-
-/*
- * SDRAM Info.
- */
-#define CONFIG_NR_DRAM_BANKS	1
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE	16384
-#define CONFIG_SYS_ICACHE_SIZE	16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
- * GPIO definition
- */
-#define GPIO_LCD_CS	(2 * 32 + 21)
-#define GPIO_DISP_OFF_N (3 * 32 + 21)
-#define GPIO_PWM	(3 * 32 + 27)
-
-#define GPIO_AMP_EN	(3 * 32 + 4)
-
-#define GPIO_SDPW_EN	(3 * 32 + 2)
-#define	GPIO_SD_DETECT	(3 * 32 + 0)
-
-#define	GPIO_USB_DETECT	(3 * 32 + 27)
-#define	GPIO_BUZZ_PWM	(3 * 32 + 28)
-
-#define	GPIO_AUDIO_POP	(1 * 32 + 29)
-#define GPIO_COB_TEST	(1 * 32 + 30)
-
-#define	GPIO_KEYOUT_BASE	(2 * 32 + 10)
-#define	GPIO_KEYIN_BASE	(3 * 32 + 18)
-#define	GPIO_KEYIN_8	(3 * 32 + 26)
-
-#define GPIO_SD_CD_N	GPIO_SD_DETECT		/* SD Card insert detect */
-#define GPIO_SD_VCC_EN_N	GPIO_SDPW_EN	/* SD Card Power Enable */
-
-#endif	/* __CONFIG_NANONOTE_H */

package/boot/uboot-xburst/files/include/configs/qi_lb60.h

@@ -1,27 +0,0 @@
-#ifndef __CONFIG_QI_LB60_H
-#define __CONFIG_QI_LB60_H
-
-#include <configs/nanonote.h>
-
-#define CONFIG_QI_LB60 1
-
-#define CONFIG_BOOTARGS		"mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
-#define CONFIG_BOOTARGSFROMSD	"mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootwait"
-#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
-#define CONFIG_BOOTCOMMANDFROMSD	"mmc init; fatload mmc 0 0x80600000 uImage; bootm"
-
-/* SDRAM paramters */
-#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
-#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
-#define SDRAM_ROW		13	/* Row address: 11 to 13 */
-#define SDRAM_COL		9	/* Column address: 8 to 12 */
-#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
-
-/* SDRAM Timings, unit: ns */
-#define SDRAM_TRAS		45	/* RAS# Active Time */
-#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
-#define SDRAM_TPC		20	/* RAS# Precharge Time */
-#define SDRAM_TRWL		7	/* Write Latency Time */
-#define SDRAM_TREF	        15625	/* Refresh period: 8192 cycles/64ms */
-
-#endif

package/boot/uboot-xburst/files/include/configs/sakc.h

@@ -1,200 +0,0 @@
-/*
- * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 3 of the License, or (at your option) any later version.
- */
-
-/*
- * This file contains the configuration parameters for SAKC.
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define DEBUG
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core */
-#define CONFIG_JzRISC		1  /* JzRISC core */
-#define CONFIG_JZSOC		1  /* Jz SoC */
-#define CONFIG_JZ4725		1  /* Jz4725 SoC */
-#define CONFIG_JZ4740		1  /* Jz4740 SoC */
-#define CONFIG_SAKC			1  /* SAKC board */
-
-#define MMC_BUS_WIDTH_1BIT	1  /* 1 for MMC  1Bit Bus Width */
-
-//#define CONFIG_LCD		1  /* LCD support */
-//#define LCD_BPP			LCD_COLOR32	/*5:18,24,32 bits per pixel */
-//#define CONFIG_SYS_WHITE_ON_BLACK	1
-
-#define CONFIG_SYS_CPU_SPEED	336000000	/* CPU clock: 336 MHz */
-#define CONFIG_SYS_EXTAL		12000000	/* EXTAL freq: 12 MHz */
-#define CONFIG_SYS_HZ		(CONFIG_SYS_EXTAL / 256) /* incrementer freq */
-#define CONFIG_SYS_MIPS_TIMER_FREQ	CONFIG_SYS_CPU_SPEED
-
-#define CONFIG_SYS_UART_BASE	UART0_BASE	/* Base of the UART channel */
-#define CONFIG_BAUDRATE		57600
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_MMC      	1
-#define CONFIG_FAT      	1  
-#define CONFIG_DOS_PARTITION	1
-#define CONFIG_SKIP_LOWLEVEL_INIT	1
-#define CONFIG_BOARD_EARLY_INIT_F	1
-#define CONFIG_SYS_NO_FLASH	1
-#define CONFIG_ENV_OVERWRITE	1
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTFILE		"uImage"	/* file to load */
-#define CONFIG_BOOTARGS		"mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
-#define CONFIG_EXTRA_ENV_SETTINGS	1
-#define CONFIG_BOOTARGSFROMSD	"mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
-#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BDI		/* bdinfo			*/
-#define CONFIG_CMD_BOOTD	/* bootd			*/
-#define CONFIG_CMD_CONSOLE	/* coninfo			*/
-#define CONFIG_CMD_ECHO		/* echo arguments		*/
-#define CONFIG_CMD_IMI		/* iminfo			*/
-#define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
-
-#define CONFIG_CMD_LOADB	/* loadb			*/
-#define CONFIG_CMD_LOADS	/* loads			*/
-#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
-#define CONFIG_CMD_MISC		/* Misc functions like sleep etc*/
-#define CONFIG_CMD_RUN		/* run command in env variable	*/
-#define CONFIG_CMD_SAVEENV	/* saveenv			*/
-#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
-#define CONFIG_CMD_SOURCE	/* "source" command support	*/
-#define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-
-/*
- * Serial download configuration
- */
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define	CONFIG_SYS_PROMPT		"SAKC# "	/* Monitor Command Prompt */
-#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16	/* max number of command args*/
-
-#define CONFIG_SYS_MALLOC_LEN		128 * 1024
-#define CONFIG_SYS_BOOTPARAMS_LEN	128 * 1024
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
-#define CONFIG_SYS_LOAD_ADDR		0x80600000     /* default load address */
-#define CONFIG_SYS_MEMTEST_START	0x80100000
-#define CONFIG_SYS_MEMTEST_END		0x80800000
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars */
-
-/*
- * NAND FLASH configuration
- */
-/* NAND Boot config code */
-#define JZ4740_NANDBOOT_CFG	JZ4740_NANDBOOT_B8R3 
-
-#define SAKC_NAND_SIZE	1 /* if board nand flash is 1GB, set to 1
-				   * if board nand flash is 2GB, set to 2
-				   * for change the PAGE_SIZE and BLOCK_SIZE
-				   * will delete when there is no 1GB flash
-				   */
-
-#define CONFIG_SYS_NAND_PAGE_SIZE	(2048 * SAKC_NAND_SIZE)
-/* nand chip block size	*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * SAKC_NAND_SIZE << 10)	
-/* nand bad block was marked at this page in a block, start from 0 */
-#define CONFIG_SYS_NAND_BADBLOCK_PAGE	127 
-/* ECC offset position in oob area, default value is 6 if it isn't defined */
-#define CONFIG_SYS_NAND_ECC_POS	(6 * SAKC_NAND_SIZE)
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define NAND_MAX_CHIPS          1
-#define CONFIG_SYS_NAND_BASE           0xB8000000
-#define CONFIG_SYS_NAND_SELECT_DEVICE  1 /* nand driver supports mutipl.*/
-#define CONFIG_SYS_ONENAND_BASE	CONFIG_SYS_NAND_BASE
-
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 8k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- */
-#define CONFIG_SYS_NAND_U_BOOT_DST		0x80100000	/* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST 
-/* Start NUB from this addr*/
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)	/* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)	/* Size of RAM U-Boot image */
-
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	(CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE)
-/* environment starts here  */
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-
-/* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
-
-/*
- * SDRAM Info.
- */
-#define CONFIG_NR_DRAM_BANKS	1
-
-/* SDRAM paramters */
-#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
-#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
-#define SDRAM_ROW		13	/* Row address: 11 to 13 */
-#define SDRAM_COL		9	/* Column address: 8 to 12 */
-#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
-
-/* SDRAM Timings, unit: ns */
-#define SDRAM_TRAS		45	/* RAS# Active Time */
-#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
-#define SDRAM_TPC		20	/* RAS# Precharge Time */
-#define SDRAM_TRWL		7	/* Write Latency Time */
-#define SDRAM_TREF	        15625	/* Refresh period: 8192 cycles/64ms */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE	16384
-#define CONFIG_SYS_ICACHE_SIZE	16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
- * GPIO definition
- */  
-#define	GPIO_SD_DETECT		(2 * 32 + 27)
-#define GPIO_SD_CD_N		GPIO_SD_DETECT	/* SD Card insert detect */
-#define GPIO_SD_VCC_EN_N	GPIO_SDPW_EN	/* SD Card Power Enable */
-
-#endif	/* __CONFIG_H */

package/boot/uboot-xburst/files/nand_spl/board/n516/Makefile

@@ -1,104 +0,0 @@
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
-
-SOBJS	= start.o usb_boot.o
-COBJS	= nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
-
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
-
-nandobj	:= $(OBJTREE)/nand_spl/
-
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-all:	$(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
-	dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
-	cat $< $(nandobj)junk1 > $(nandobj)junk2
-	dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
-	cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
-	dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
-	cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
-	dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
-	rm -f $(nandobj)junk*
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS)
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)start.S:
-	@rm -f $(obj)start.S
-	ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
-
-$(obj)usb_boot.S:
-	@rm -f $(obj)usb_boot.S
-	ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
-
-$(obj)cpu.c:
-	@rm -f $(obj)cpu.c
-	ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
-
-$(obj)jz4740.c:
-	@rm -f $(obj)jz4740.c
-	ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
-
-$(obj)jz_serial.c:
-	@rm -f $(obj)jz_serial.c
-	ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
-
-# from nand_spl directory
-$(obj)nand_boot_jz4740.c:
-	@rm -f $(obj)nand_boot_jz4740.c
-	ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

package/boot/uboot-xburst/files/nand_spl/board/n516/config.mk

@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#
-# Ingenic JZ4740 Reference Platform
-#
-
-#
-# TEXT_BASE for SPL:
-#
-# On JZ4730 platforms the SPL is located at 0x80000000...0x80001000,
-# in the first 4kBytes of memory space in cache. So we set
-# TEXT_BASE to starting address in internal cache here.
-#
-TEXT_BASE = 0x80000000

package/boot/uboot-xburst/files/nand_spl/board/n516/u-boot.lds

@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2005
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	_gp = ALIGN(16);
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata) }
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) }
-	uboot_end = .;
-}

package/boot/uboot-xburst/files/nand_spl/board/nanonote/Makefile

@@ -1,104 +0,0 @@
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
-
-SOBJS	= start.o usb_boot.o
-COBJS	= nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
-
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
-
-nandobj	:= $(OBJTREE)/nand_spl/
-
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-all:	$(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
-	dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
-	cat $< $(nandobj)junk1 > $(nandobj)junk2
-	dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
-	cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
-	dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
-	cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
-	dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
-	rm -f $(nandobj)junk*
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS)
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)start.S:
-	@rm -f $(obj)start.S
-	ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
-
-$(obj)usb_boot.S:
-	@rm -f $(obj)usb_boot.S
-	ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
-
-$(obj)cpu.c:
-	@rm -f $(obj)cpu.c
-	ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
-
-$(obj)jz4740.c:
-	@rm -f $(obj)jz4740.c
-	ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
-
-$(obj)jz_serial.c:
-	@rm -f $(obj)jz_serial.c
-	ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
-
-# from nand_spl directory
-$(obj)nand_boot_jz4740.c:
-	@rm -f $(obj)nand_boot_jz4740.c
-	ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

package/boot/uboot-xburst/files/nand_spl/board/nanonote/config.mk

@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#
-# Ingenic JZ4740 Reference Platform
-#
-
-#
-# TEXT_BASE for SPL:
-#
-# On JZ4730 platforms the SPL is located at 0x80000000...0x80001000,
-# in the first 4kBytes of memory space in cache. So we set
-# TEXT_BASE to starting address in internal cache here.
-#
-TEXT_BASE = 0x80000000

package/boot/uboot-xburst/files/nand_spl/board/nanonote/u-boot.lds

@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2005
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	_gp = ALIGN(16);
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata) }
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) }
-	uboot_end = .;
-}

package/boot/uboot-xburst/files/nand_spl/board/sakc/Makefile

@@ -1,104 +0,0 @@
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
-
-SOBJS	= start.o usb_boot.o
-COBJS	= nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
-
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
-
-nandobj	:= $(OBJTREE)/nand_spl/
-
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-all:	$(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
-	dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
-	cat $< $(nandobj)junk1 > $(nandobj)junk2
-	dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
-	cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
-	dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
-	cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
-	dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
-	rm -f $(nandobj)junk*
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS)
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)start.S:
-	@rm -f $(obj)start.S
-	ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
-
-$(obj)usb_boot.S:
-	@rm -f $(obj)usb_boot.S
-	ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
-
-$(obj)cpu.c:
-	@rm -f $(obj)cpu.c
-	ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
-
-$(obj)jz4740.c:
-	@rm -f $(obj)jz4740.c
-	ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
-
-$(obj)jz_serial.c:
-	@rm -f $(obj)jz_serial.c
-	ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
-
-# from nand_spl directory
-$(obj)nand_boot_jz4740.c:
-	@rm -f $(obj)nand_boot_jz4740.c
-	ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

package/boot/uboot-xburst/files/nand_spl/board/sakc/config.mk

@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#
-# Ingenic JZ4740 Reference Platform
-#
-
-#
-# TEXT_BASE for SPL:
-#
-# On JZ4730 platforms the SPL is located at 0x80000000...0x80001000,
-# in the first 4kBytes of memory space in cache. So we set
-# TEXT_BASE to starting address in internal cache here.
-#
-TEXT_BASE = 0x80000000

package/boot/uboot-xburst/files/nand_spl/board/sakc/u-boot.lds

@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2005
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = ALIGN(4);
-	.sdata  : { *(.sdata) }
-
-	_gp = ALIGN(16);
-
-	__got_start = .;
-	.got  : { *(.got) }
-	__got_end = .;
-
-	.sdata  : { *(.sdata) }
-
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss  : { *(.sbss) }
-	.bss  : { *(.bss) }
-	uboot_end = .;
-}

package/boot/uboot-xburst/files/nand_spl/nand_boot_jz4740.c

@@ -1,429 +0,0 @@
-/*
- * Copyright (C) 2007 Ingenic Semiconductor Inc.
- * Author: Peter <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <nand.h>
-
-#include <asm/io.h>
-#include <asm/jz4740.h>
-
-#define KEY_U_OUT       (32 * 2 + 16)
-#define KEY_U_IN        (32 * 3 + 19)
-
-/*
- * NAND flash definitions
- */
-
-#define NAND_DATAPORT	0xb8000000
-#define NAND_ADDRPORT	0xb8010000
-#define NAND_COMMPORT	0xb8008000
-
-#define ECC_BLOCK	512
-#define ECC_POS		6
-#define PAR_SIZE	9
-
-#define __nand_enable()		(REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1)
-#define __nand_disable()	(REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
-#define __nand_ecc_rs_encoding() \
-	(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
-#define __nand_ecc_rs_decoding() \
-	(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING)
-#define __nand_ecc_disable()	(REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
-#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
-#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
-
-static inline void __nand_dev_ready(void)
-{
-	unsigned int timeout = 10000;
-	while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
-	while (!(REG_GPIO_PXPIN(2) & 0x40000000));
-}
-
-#define __nand_cmd(n)		(REG8(NAND_COMMPORT) = (n))
-#define __nand_addr(n)		(REG8(NAND_ADDRPORT) = (n))
-#define __nand_data8()		REG8(NAND_DATAPORT)
-#define __nand_data16()		REG16(NAND_DATAPORT)
-
-#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3)
-	#define NAND_BUS_WIDTH 8
-	#define NAND_ROW_CYCLE 3
-#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
-	#define NAND_BUS_WIDTH 8
-	#define NAND_ROW_CYCLE 2
-#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3)
-	#define NAND_BUS_WIDTH 16
-	#define NAND_ROW_CYCLE 3
-#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
-	#define NAND_BUS_WIDTH 16
-	#define NAND_ROW_CYCLE 2
-#endif
-
-/*
- * NAND flash parameters
- */
-static int page_size = 2048;
-static int oob_size = 64;
-static int ecc_count = 4;
-static int page_per_block = 64;
-static int bad_block_pos = 0;
-static int block_size = 131072;
-
-static unsigned char oob_buf[128] = {0};
-
-/*
- * External routines
- */
-extern void flush_cache_all(void);
-extern int serial_init(void);
-extern void serial_puts(const char *s);
-extern void sdram_init(void);
-extern void pll_init(void);
-extern void usb_boot();
-
-/*
- * NAND flash routines
- */
-#if NAND_BUS_WIDTH == 16
-static inline void nand_read_buf16(void *buf, int count)
-{
-	int i;
-	u16 *p = (u16 *)buf;
-
-	for (i = 0; i < count; i += 2)
-		*p++ = __nand_data16();
-}
-#define nand_read_buf nand_read_buf16
-
-#elif NAND_BUS_WIDTH == 8
-static inline void nand_read_buf8(void *buf, int count)
-{
-	int i;
-	u8 *p = (u8 *)buf;
-
-	for (i = 0; i < count; i++)
-		*p++ = __nand_data8();
-}
-#define nand_read_buf nand_read_buf8
-
-#endif
-
-/* Correct 1~9-bit errors in 512-bytes data */
-static void rs_correct(unsigned char *dat, int idx, int mask)
-{
-	int i;
-
-	idx--;
-
-	i = idx + (idx >> 3);
-	if (i >= 512)
-		return;
-
-	mask <<= (idx & 0x7);
-
-	dat[i] ^= mask & 0xff;
-	if (i < 511)
-		dat[i+1] ^= (mask >> 8) & 0xff;
-}
-
-static int nand_read_oob(int page_addr, uchar *buf, int size)
-{
-	int col_addr;
-	if (page_size != 512)
-		col_addr = page_size;
-	else {
-		col_addr = 0;
-		__nand_dev_ready();
-	}
-
-	if (page_size != 512)
-		/* Send READ0 command */
-		__nand_cmd(NAND_CMD_READ0);
-	else
-		/* Send READOOB command */
-		__nand_cmd(NAND_CMD_READOOB);
-
-	/* Send column address */
-	__nand_addr(col_addr & 0xff);
-	if (page_size != 512)
-		__nand_addr((col_addr >> 8) & 0xff);
-
-	/* Send page address */
-	__nand_addr(page_addr & 0xff);
-	__nand_addr((page_addr >> 8) & 0xff);
-	#ifdef NAND_ROW_CYCLE == 3
-		__nand_addr((page_addr >> 16) & 0xff);
-	#endif
-
-	/* Send READSTART command for 2048 or 4096 ps NAND */
-	if (page_size != 512)
-		__nand_cmd(NAND_CMD_READSTART);
-
-	/* Wait for device ready */
-	__nand_dev_ready();
-
-	/* Read oob data */
-	nand_read_buf(buf, size);
-	if (page_size == 512)
-		__nand_dev_ready();
-	return 0;
-}
-
-static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
-{
-	uchar *databuf = dst, *tmpbuf;
-	int i, j;
-
-	/*
-	 * Read oob data
-	 */
-	nand_read_oob(page_addr, oobbuf, oob_size);
-
-	/*
-	 * Read page data
-	 */
-
-	/* Send READ0 command */
-	__nand_cmd(NAND_CMD_READ0);
-
-	/* Send column address */
-	__nand_addr(0);
-	if (page_size != 512)
-		__nand_addr(0);
-
-	/* Send page address */
-	__nand_addr(page_addr & 0xff);
-	__nand_addr((page_addr >> 8) & 0xff);
-	#if NAND_ROW_CYCLE == 3
-		__nand_addr((page_addr >> 16) & 0xff);
-	#endif
-
-	/* Send READSTART command for 2048 or 4096 ps NAND */
-	if (page_size != 512)
-		__nand_cmd(NAND_CMD_READSTART);
-
-	/* Wait for device ready */
-	__nand_dev_ready();
-
-	/* Read page data */
-	tmpbuf = databuf;
-
-	for (i = 0; i < ecc_count; i++) {
-		volatile unsigned char *paraddr = (volatile unsigned char *)EMC_NFPAR0;
-		unsigned int stat;
-
-		/* Enable RS decoding */
-		REG_EMC_NFINTS = 0x0;
-		__nand_ecc_rs_decoding();
-
-		/* Read data */
-		nand_read_buf((void *)tmpbuf, ECC_BLOCK);
-
-		/* Set PAR values */
-		for (j = 0; j < PAR_SIZE; j++) {
-#if defined(CONFIG_SYS_NAND_ECC_POS)
-			*paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*PAR_SIZE + j];
-#else
-			*paraddr++ = oobbuf[ECC_POS + i*PAR_SIZE + j];
-#endif
-		}
-
-		/* Set PRDY */
-		REG_EMC_NFECR |= EMC_NFECR_PRDY;
-
-		/* Wait for completion */
-		__nand_ecc_decode_sync();
-
-		/* Disable decoding */
-		__nand_ecc_disable();
-
-		/* Check result of decoding */
-		stat = REG_EMC_NFINTS;
-		if (stat & EMC_NFINTS_ERR) {
-			/* Error occurred */
-			/* serial_puts("\n Error occurred\n"); */
-			if (stat & EMC_NFINTS_UNCOR) {
-				/* Uncorrectable error occurred */
-				/* serial_puts("\nUncorrectable error occurred\n"); */
-			}
-			else {
-				unsigned int errcnt, index, mask;
-
-				errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
-				switch (errcnt) {
-				case 4:
-					index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
-					mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
-					rs_correct(tmpbuf, index, mask);
-					/* FALL-THROUGH */
-				case 3:
-					index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
-					mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
-					rs_correct(tmpbuf, index, mask);
-					/* FALL-THROUGH */
-				case 2:
-					index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
-					mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
-					rs_correct(tmpbuf, index, mask);
-					/* FALL-THROUGH */
-				case 1:
-					index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
-					mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
-					rs_correct(tmpbuf, index, mask);
-					break;
-				default:
-					break;
-				}
-			}
-		}
-
-		tmpbuf += ECC_BLOCK;
-	}
-
-	return 0;
-}
-
-#ifndef CONFIG_SYS_NAND_BADBLOCK_PAGE
-#define CONFIG_SYS_NAND_BADBLOCK_PAGE 0 /* NAND bad block was marked at this page in a block, starting from 0 */
-#endif
-
-static void nand_load(int offs, int uboot_size, uchar *dst)
-{
-	int page;
-	int pagecopy_count;
-
-	__nand_enable();
-
-	page = offs / page_size;
-	pagecopy_count = 0;
-	while (pagecopy_count < (uboot_size / page_size)) {
-		if (page % page_per_block == 0) {
-			nand_read_oob(page + CONFIG_SYS_NAND_BADBLOCK_PAGE, oob_buf, oob_size);
-			if (oob_buf[bad_block_pos] != 0xff) {
-				page += page_per_block;
-				/* Skip bad block */
-				continue;
-			}
-		}
-		/* Load this page to dst, do the ECC */
-		nand_read_page(page, dst, oob_buf);
-
-		dst += page_size;
-		page++;
-		pagecopy_count++;
-	}
-
-	__nand_disable();
-}
-
-static void jz_nand_init(void) {
-
- 	/* Optimize the timing of nand */
-	REG_EMC_SMCR1 = 0x094c4400;
-}
-
-static void gpio_init(void)
-{
-	/*
-	 * Initialize SDRAM pins
-	 */
-#if defined(CONFIG_JZ4720)
-	__gpio_as_sdram_16bit_4720();
-#elif defined(CONFIG_JZ4725)
-	__gpio_as_sdram_16bit_4725();
-#else
-	__gpio_as_sdram_32bit();
-#endif
-
-	/*
-	 * Initialize UART0 pins
-	 */
-	__gpio_as_uart0();
-}
-
-static int is_usb_boot()
-{
- 	int keyU = 0;
-
- 	__gpio_as_input(KEY_U_IN);
- 	__gpio_enable_pull(KEY_U_IN);
-
- 	__gpio_as_output(KEY_U_OUT);
- 	__gpio_clear_pin(KEY_U_OUT);
-
- 	keyU = __gpio_get_pin(KEY_U_IN);
-
- 	if (keyU)
- 		serial_puts("[U] not pressed\n");
- 	else
- 		serial_puts("[U] pressed\n");
-
-	return !keyU;
-}
-
-void nand_boot(void)
-{
-	void (*uboot)(void);
-
-	/*
-	 * Init hardware
-	 */
-	jz_nand_init();
-	gpio_init();
-	serial_init();
-
-	serial_puts("\n\nNAND Secondary Program Loader\n\n");
-
-	pll_init();
-	sdram_init();
-
-#if defined(CONFIG_NANONOTE)
-	if(is_usb_boot()) {
-		serial_puts("enter USB BOOT mode\n");
-		usb_boot();
-	}
-#endif
-
-	page_size = CONFIG_SYS_NAND_PAGE_SIZE;
-	block_size = CONFIG_SYS_NAND_BLOCK_SIZE;
-	page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
-	bad_block_pos = (page_size == 512) ? 5 : 0;
-	oob_size = page_size / 32;
-	ecc_count = page_size / ECC_BLOCK;
-
-	/*
-	 * Load U-Boot image from NAND into RAM
-	 */
-	nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
-		  (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
-
-	uboot = (void (*)(void))CONFIG_SYS_NAND_U_BOOT_START;
-
-	serial_puts("Starting U-Boot ...\n");
-
-	/*
-	 * Flush caches
-	 */
-	flush_cache_all();
-
-	/*
-	 * Jump to U-Boot image
-	 */
-	(*uboot)();
-}

package/boot/uboot-xburst/patches/0001-qi_lb60-add-nand-spl-support.patch

@@ -0,0 +1,894 @@
+From 0329cf7965956a5a7044827e0ce88ae8d5150e54 Mon Sep 17 00:00:00 2001
+From: Xiangfu <xiangfu@openmobilefree.net>
+Date: Fri, 12 Oct 2012 09:46:58 +0800
+Subject: [PATCH 1/6] qi_lb60: add nand spl support
+
+  The JZ4740 CPU can load 8KB from two different addresses:
+   1. the normal area up to 8KB starting from NAND flash address 0x00000000
+   2. the backup area up to 8KB starting from NAND flash address 0x00002000
+
+Signed-off-by: Xiangfu <xiangfu@openmobilefree.net>
+---
+ Makefile                          |   12 +++
+ arch/mips/cpu/xburst/Makefile     |    7 +-
+ arch/mips/cpu/xburst/cpu.c        |    4 +
+ arch/mips/cpu/xburst/jz4740.c     |   82 +++++++----------
+ arch/mips/cpu/xburst/spl/Makefile |   47 ++++++++++
+ arch/mips/cpu/xburst/spl/start.S  |   63 +++++++++++++
+ board/qi/qi_lb60/Makefile         |    4 +
+ board/qi/qi_lb60/qi_lb60-spl.c    |   30 +++++++
+ board/qi/qi_lb60/qi_lb60.c        |    8 +-
+ board/qi/qi_lb60/u-boot-spl.lds   |   61 +++++++++++++
+ drivers/mtd/nand/jz4740_nand.c    |   39 ++++++++-
+ include/configs/qi_lb60.h         |  175 ++++++++++++++++++-------------------
+ 12 files changed, 386 insertions(+), 146 deletions(-)
+ create mode 100644 arch/mips/cpu/xburst/spl/Makefile
+ create mode 100644 arch/mips/cpu/xburst/spl/start.S
+ create mode 100644 board/qi/qi_lb60/qi_lb60-spl.c
+ create mode 100644 board/qi/qi_lb60/u-boot-spl.lds
+
+diff --git a/Makefile b/Makefile
+index 34d9075..a22778e 100644
+--- a/Makefile
++++ b/Makefile
+@@ -393,6 +393,10 @@ ALL-y += $(obj)u-boot-nodtb-tegra.bin
+ endif
+ endif
+ 
++ifeq ($(CPU),xburst)
++ALL-y += $(obj)u-boot-xburst.bin
++endif
++
+ all:		$(ALL-y) $(SUBDIR_EXAMPLES)
+ 
+ $(obj)u-boot.dtb:	$(obj)u-boot
+@@ -506,6 +510,14 @@ $(obj)u-boot-nodtb-tegra.bin:	$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ endif
+ endif
+ 
++ifeq ($(CPU),xburst)
++$(obj)u-boot-xburst.bin:	$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
++	        dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin conv=sync bs=8192 count=1
++		dd if=$(obj)spl/u-boot-spl.bin of=$(obj)spl/u-boot-pad.bin conv=sync,notrunc oflag=append bs=8192 count=1
++	        tr '\0' '\377' < /dev/zero | dd of=$(obj)spl/u-boot-pad.bin conv=sync,notrunc oflag=append bs=16384 count=1
++	        cat $(obj)spl/u-boot-pad.bin u-boot.bin > $@
++endif
++
+ ifeq ($(CONFIG_SANDBOX),y)
+ GEN_UBOOT = \
+ 		cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
+diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
+index b1f2ae4..ec35e55 100644
+--- a/arch/mips/cpu/xburst/Makefile
++++ b/arch/mips/cpu/xburst/Makefile
+@@ -24,9 +24,12 @@ include $(TOPDIR)/config.mk
+ 
+ LIB	= $(obj)lib$(CPU).o
+ 
++COBJS-y	= cpu.o jz_serial.o
++
++ifneq ($(CONFIG_SPL_BUILD),y)
+ START	= start.o
+-SOBJS-y	=
+-COBJS-y	= cpu.o timer.o jz_serial.o
++COBJS-y += timer.o
++endif
+ 
+ COBJS-$(CONFIG_JZ4740) += jz4740.o
+ 
+diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
+index ddcbfaa..1432838 100644
+--- a/arch/mips/cpu/xburst/cpu.c
++++ b/arch/mips/cpu/xburst/cpu.c
+@@ -42,6 +42,8 @@
+ 		:			\
+ 		: "i" (op), "R" (*(unsigned char *)(addr)))
+ 
++#ifndef CONFIG_SPL_BUILD
++
+ void __attribute__((weak)) _machine_restart(void)
+ {
+ 	struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
+@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
+ 		cache_op(Hit_Invalidate_D, addr);
+ }
+ 
++#endif
++
+ void flush_icache_all(void)
+ {
+ 	u32 addr, t = 0;
+diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c
+index c0b9817..8816aa3 100644
+--- a/arch/mips/cpu/xburst/jz4740.c
++++ b/arch/mips/cpu/xburst/jz4740.c
+@@ -32,31 +32,19 @@ int disable_interrupts(void)
+ 	return 0;
+ }
+ 
+-/*
+- * PLL output clock = EXTAL * NF / (NR * NO)
+- * NF = FD + 2, NR = RD + 2
+- * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
+- */
+ void pll_init(void)
+ {
+ 	struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
+ 
+-	register unsigned int cfcr, plcr1;
+-	int n2FR[33] = {
+-		0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
+-		7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
+-		9
+-	};
+-	int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
+-	int nf, pllout2;
++	register unsigned int cfcr, plcr;
++	unsigned int nf, pllout2;
+ 
+ 	cfcr =	CPM_CPCCR_CLKOEN |
+-		CPM_CPCCR_PCS |
+-		(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
+-		(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
+-		(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
+-		(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
+-		(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
++		(0 << CPM_CPCCR_CDIV_BIT) |
++		(2 << CPM_CPCCR_HDIV_BIT) |
++		(2 << CPM_CPCCR_PDIV_BIT) |
++		(2 << CPM_CPCCR_MDIV_BIT) |
++		(2 << CPM_CPCCR_LDIV_BIT);
+ 
+ 	pllout2 = (cfcr & CPM_CPCCR_PCS) ?
+ 		CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
+@@ -65,15 +53,18 @@ void pll_init(void)
+ 	writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
+ 
+ 	nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
+-	plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
++	plcr = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
+ 		(0 << CPM_CPPCR_PLLN_BIT) |	/* RD=0, NR=2 */
+ 		(0 << CPM_CPPCR_PLLOD_BIT) |	/* OD=0, NO=1 */
+-		(0x20 << CPM_CPPCR_PLLST_BIT) |	/* PLL stable time */
++		(0x32 << CPM_CPPCR_PLLST_BIT) |	/* PLL stable time */
+ 		CPM_CPPCR_PLLEN;		/* enable PLL */
+ 
+ 	/* init PLL */
+ 	writel(cfcr, &cpm->cpccr);
+-	writel(plcr1, &cpm->cppcr);
++	writel(plcr, &cpm->cppcr);
++
++	while (!(readl(&cpm->cppcr) & CPM_CPPCR_PLLS))
++		;
+ }
+ 
+ void sdram_init(void)
+@@ -92,26 +83,12 @@ void sdram_init(void)
+ 		2 << EMC_DMCR_TCL_BIT	/* CAS latency is 3 */
+ 	};
+ 
+-	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+-
+ 	cpu_clk = CONFIG_SYS_CPU_SPEED;
+-	mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
++	mem_clk = 84000000;
+ 
+ 	writel(0, &emc->bcr);	/* Disable bus release */
+ 	writew(0, &emc->rtcsr);	/* Disable clock for counting */
+ 
+-	/* Fault DMCR value for mode register setting*/
+-#define SDRAM_ROW0	11
+-#define SDRAM_COL0	8
+-#define SDRAM_BANK40	0
+-
+-	dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
+-		((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
+-		(SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
+-		(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
+-		EMC_DMCR_EPIN |
+-		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
+-
+ 	/* Basic DMCR value */
+ 	dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
+ 		((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
+@@ -128,31 +105,31 @@ void sdram_init(void)
+ 	if (tmp > 11)
+ 		tmp = 11;
+ 	dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
+-	tmp = SDRAM_RCD / ns;
+ 
++	tmp = SDRAM_RCD / ns;
+ 	if (tmp > 3)
+ 		tmp = 3;
+ 	dmcr |= tmp << EMC_DMCR_RCD_BIT;
+-	tmp = SDRAM_TPC / ns;
+ 
++	tmp = SDRAM_TPC / ns;
+ 	if (tmp > 7)
+ 		tmp = 7;
+ 	dmcr |= tmp << EMC_DMCR_TPC_BIT;
+-	tmp = SDRAM_TRWL / ns;
+ 
++	tmp = SDRAM_TRWL / ns;
+ 	if (tmp > 3)
+ 		tmp = 3;
+ 	dmcr |= tmp << EMC_DMCR_TRWL_BIT;
+-	tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
+ 
++	tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
+ 	if (tmp > 14)
+ 		tmp = 14;
+ 	dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
+ 
+ 	/* SDRAM mode value */
+-	sdmode = EMC_SDMR_BT_SEQ |
+-		 EMC_SDMR_OM_NORMAL |
+-		 EMC_SDMR_BL_4 |
++	sdmode = EMC_SDMR_BT_SEQ	|
++		 EMC_SDMR_OM_NORMAL	|
++		 EMC_SDMR_BL_4		|
+ 		 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
+ 
+ 	/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
+@@ -172,8 +149,8 @@ void sdram_init(void)
+ 	if (tmp > 0xff)
+ 		tmp = 0xff;
+ 	writew(tmp, &emc->rtcor);
++
+ 	writew(0, &emc->rtcnt);
+-	/* Divisor is 64, CKO/64 */
+ 	writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
+ 
+ 	/* Wait for number of auto-refresh cycles */
+@@ -182,13 +159,17 @@ void sdram_init(void)
+ 		;
+ 
+ 	/* Stage 3. Mode Register Set */
++	dmcr0 = (11 << EMC_DMCR_RA_BIT)	|
++		(8 << EMC_DMCR_CA_BIT)	|
++		(0 << EMC_DMCR_BA_BIT)	|
++		EMC_DMCR_EPIN		|
++		(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
++		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
+ 	writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
+ 	writeb(0, JZ4740_EMC_SDMR0 | sdmode);
+ 
+ 	/* Set back to basic DMCR value */
+ 	writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
+-
+-	/* everything is ok now */
+ }
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+@@ -232,9 +213,10 @@ void rtc_init(void)
+ phys_size_t initdram(int board_type)
+ {
+ 	struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
+-	u32 dmcr;
+-	u32 rows, cols, dw, banks;
+-	ulong size;
++
++	unsigned int dmcr;
++	unsigned int rows, cols, dw, banks;
++	unsigned long size;
+ 
+ 	dmcr = readl(&emc->dmcr);
+ 	rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
+diff --git a/arch/mips/cpu/xburst/spl/Makefile b/arch/mips/cpu/xburst/spl/Makefile
+new file mode 100644
+index 0000000..f45e8c8
+--- /dev/null
++++ b/arch/mips/cpu/xburst/spl/Makefile
+@@ -0,0 +1,47 @@
++#
++# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(CPU).o
++
++START	= start.o
++SOBJS-y	=
++COBJS-y	=
++
++SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
++OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
++START	:= $(addprefix $(obj),$(START))
++
++all:	$(obj).depend $(START) $(LIB)
++
++$(LIB):	$(OBJS)
++	$(call cmd_link_o_target, $(OBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/arch/mips/cpu/xburst/spl/start.S b/arch/mips/cpu/xburst/spl/start.S
+new file mode 100644
+index 0000000..e31c4c8
+--- /dev/null
++++ b/arch/mips/cpu/xburst/spl/start.S
+@@ -0,0 +1,63 @@
++/*
++ * Copyright (c) 2010 Xiangfu Liu <xiangfu@openmobilefree.net>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 3 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++#include <asm/regdef.h>
++#include <asm/mipsregs.h>
++#include <asm/addrspace.h>
++#include <asm/cacheops.h>
++
++#include <asm/jz4740.h>
++
++	.set noreorder
++
++	.globl _start
++	.text
++_start:
++	.word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
++reset:
++	/*
++	 * STATUS register
++	 * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
++	 */
++	li	t0, 0x0040FC04
++	mtc0	t0, CP0_STATUS
++	/*
++	 * CAUSE register
++	 * IV=1, use the specical interrupt vector (0x200)
++	 */
++	li	t1, 0x00800000
++	mtc0	t1, CP0_CAUSE
++
++	bal     1f
++	 nop
++	.word   _GLOBAL_OFFSET_TABLE_
++1:
++	move    gp, ra
++	lw      t1, 0(ra)
++	move	gp, t1
++
++	la	sp, 0x80004000
++	la	t9, nand_spl_boot
++	j	t9
++	nop
+diff --git a/board/qi/qi_lb60/Makefile b/board/qi/qi_lb60/Makefile
+index 5dae11b..e399246 100644
+--- a/board/qi/qi_lb60/Makefile
++++ b/board/qi/qi_lb60/Makefile
+@@ -22,7 +22,11 @@ include $(TOPDIR)/config.mk
+ 
+ LIB	= $(obj)lib$(BOARD).o
+ 
++ifeq ($(CONFIG_SPL_BUILD),y)
++COBJS	:= $(BOARD)-spl.o
++else
+ COBJS	:= $(BOARD).o
++endif
+ 
+ SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+ OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+diff --git a/board/qi/qi_lb60/qi_lb60-spl.c b/board/qi/qi_lb60/qi_lb60-spl.c
+new file mode 100644
+index 0000000..3fe3fa3
+--- /dev/null
++++ b/board/qi/qi_lb60/qi_lb60-spl.c
+@@ -0,0 +1,30 @@
++/*
++ * Authors: Xiangfu Liu <xiangfu@openmobilefree.cc>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 3 of the License, or (at your option) any later version.
++ */
++
++#include <common.h>
++#include <nand.h>
++#include <asm/io.h>
++#include <asm/jz4740.h>
++
++void nand_spl_boot(void)
++{
++	__gpio_as_sdram_16bit_4720();
++	__gpio_as_uart0();
++	__gpio_jtag_to_uart0();
++
++	serial_init();
++
++	pll_init();
++	sdram_init();
++
++	nand_init();
++
++	puts("\nQi LB60 SPL: Starting U-Boot ...\n");
++	nand_boot();
++}
+diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c
+index d975209..3bd4e2f 100644
+--- a/board/qi/qi_lb60/qi_lb60.c
++++ b/board/qi/qi_lb60/qi_lb60.c
+@@ -1,5 +1,5 @@
+ /*
+- * Authors: Xiangfu Liu <xiangfu@sharism.cc>
++ * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License
+@@ -97,8 +97,10 @@ int board_early_init_f(void)
+ /* U-Boot common routines */
+ int checkboard(void)
+ {
+-	printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n",
+-	       gd->cpu_clk / 1000000);
++	printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC)\n");
++	printf(" CPU: %ld\n", gd->cpu_clk);
++	printf(" MEM: %ld\n", gd->mem_clk);
++	printf(" DEV: %ld\n", gd->dev_clk);
+ 
+ 	return 0;
+ }
+diff --git a/board/qi/qi_lb60/u-boot-spl.lds b/board/qi/qi_lb60/u-boot-spl.lds
+new file mode 100644
+index 0000000..930537f
+--- /dev/null
++++ b/board/qi/qi_lb60/u-boot-spl.lds
+@@ -0,0 +1,61 @@
++/*
++ * (C) Copyright 2012 Xiangfu Liu <xiangfu@openmobilefree.net>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
++
++OUTPUT_ARCH(mips)
++ENTRY(_start)
++SECTIONS
++{
++	. = 0x80000000;
++	. = ALIGN(4);
++	.text :
++	{
++	  *(.text)
++	}
++
++	. = ALIGN(4);
++	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
++
++	. = ALIGN(4);
++	.data  : { *(.data) }
++
++	. = ALIGN(4);
++	.sdata  : { *(.sdata) }
++
++	_gp = ALIGN(16);
++
++	__got_start = .;
++	.got  : { *(.got) }
++	__got_end = .;
++
++	. = .;
++	__u_boot_cmd_start = .;
++	.u_boot_cmd : { *(.u_boot_cmd) }
++	__u_boot_cmd_end = .;
++
++	uboot_end_data = .;
++	num_got_entries = (__got_end - __got_start) >> 2;
++
++	. = ALIGN(4);
++	.sbss  : { *(.sbss) }
++	.bss  : { *(.bss) }
++	uboot_end = .;
++}
++ASSERT(uboot_end <= 0x80002000, "NAND bootstrap too big");
+diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
+index 3ec34f3..24a4921 100644
+--- a/drivers/mtd/nand/jz4740_nand.c
++++ b/drivers/mtd/nand/jz4740_nand.c
+@@ -15,6 +15,9 @@
+ #include <asm/io.h>
+ #include <asm/jz4740.h>
+ 
++#ifdef CONFIG_SPL_BUILD
++#define printf(s) puts(s)
++#endif
+ #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
+ #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
+ #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
+@@ -176,7 +179,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
+ 		for (k = 0; k < 9; k++)
+ 			writeb(read_ecc[k], &emc->nfpar[k]);
+ 	}
+-	/* Set PRDY */
++
+ 	writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
+ 
+ 	/* Wait for completion */
+@@ -184,7 +187,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
+ 		status = readl(&emc->nfints);
+ 	} while (!(status & EMC_NFINTS_DECF));
+ 
+-	/* disable ecc */
++	/* Disable ECC */
+ 	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
+ 
+ 	/* Check decoding */
+@@ -192,7 +195,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
+ 		return 0;
+ 
+ 	if (status & EMC_NFINTS_UNCOR) {
+-		printf("uncorrectable ecc\n");
++		printf("JZ4740 uncorrectable ECC\n");
+ 		return -1;
+ 	}
+ 
+@@ -230,6 +233,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
+ 	return errcnt;
+ }
+ 
++#ifdef CONFIG_SPL_BUILD
++static void jz_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
++{
++	int i;
++	struct nand_chip *this = mtd->priv;
++
++#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) || \
++	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
++	for (i = 0; i < len; i += 2)
++		buf[i] = readw(this->IO_ADDR_R);
++#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) || \
++	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
++	for (i = 0; i < len; i++)
++		buf[i] = readb(this->IO_ADDR_R);
++#else
++	#error JZ4740_NANDBOOT_CFG not defined or wrong
++#endif
++}
++
++static uint8_t jz_nand_read_byte(struct mtd_info *mtd)
++{
++	struct nand_chip *this = mtd->priv;
++	return readb(this->IO_ADDR_R);
++}
++#endif
++
+ /*
+  * Main initialization routine
+  */
+@@ -254,6 +283,10 @@ int board_nand_init(struct nand_chip *nand)
+ 	nand->ecc.size		= CONFIG_SYS_NAND_ECCSIZE;
+ 	nand->ecc.bytes		= CONFIG_SYS_NAND_ECCBYTES;
+ 	nand->ecc.layout	= &qi_lb60_ecclayout_2gb;
++#ifdef CONFIG_SPL_BUILD
++	nand->read_byte		= jz_nand_read_byte;
++	nand->read_buf		= jz_nand_read_buf;
++#endif
+ 	nand->chip_delay	= 50;
+ 	nand->options		= NAND_USE_FLASH_BBT;
+ 
+diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
+index 4bb5bbc..7bff444 100644
+--- a/include/configs/qi_lb60.h
++++ b/include/configs/qi_lb60.h
+@@ -1,5 +1,5 @@
+ /*
+- * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
++ * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License
+@@ -14,7 +14,6 @@
+ #define CONFIG_SYS_LITTLE_ENDIAN
+ #define CONFIG_JZSOC		/* Jz SoC */
+ #define CONFIG_JZ4740		/* Jz4740 SoC */
+-#define CONFIG_NAND_JZ4740
+ 
+ #define CONFIG_SYS_CPU_SPEED	336000000	/* CPU clock: 336 MHz */
+ #define CONFIG_SYS_EXTAL	12000000	/* EXTAL freq: 12 MHz */
+@@ -24,24 +23,43 @@
+ #define CONFIG_SYS_UART_BASE	JZ4740_UART0_BASE /* Base of the UART channel */
+ #define CONFIG_BAUDRATE		57600
+ 
++#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
++#define CONFIG_BOOTDELAY	0
++#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
++#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x280000;bootm"
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
++#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
++#define CONFIG_SYS_LOAD_ADDR		0x80600000
++#define CONFIG_SYS_MEMTEST_START	0x80100000
++#define CONFIG_SYS_MEMTEST_END		0x80A00000
++#define CONFIG_SYS_TEXT_BASE		0x80100000
++#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
++
++#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
++#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
++
++#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
++
++#define CONFIG_SYS_LONGHELP
++#define CONFIG_SYS_MAXARGS	16
++#define CONFIG_SYS_PROMPT	"NanoNote# "
++
+ #define CONFIG_SKIP_LOWLEVEL_INIT
+ #define CONFIG_BOARD_EARLY_INIT_F
+ #define CONFIG_SYS_NO_FLASH
+ #define CONFIG_SYS_FLASH_BASE	0 /* init flash_base as 0 */
+-#define CONFIG_ENV_OVERWRITE
+-
+-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
+-#define CONFIG_BOOTDELAY	0
+-#define CONFIG_BOOTARGS		"mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
+-#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
+ 
+ /*
+- * Command line configuration.
++ * Command line configuration
+  */
+ #define CONFIG_CMD_BOOTD	/* bootd			*/
+ #define CONFIG_CMD_CONSOLE	/* coninfo			*/
+ #define CONFIG_CMD_ECHO		/* echo arguments		*/
+-
+ #define CONFIG_CMD_LOADB	/* loadb			*/
+ #define CONFIG_CMD_LOADS	/* loads			*/
+ #define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
+@@ -58,45 +76,16 @@
+ #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+ 
+ /*
+- * Miscellaneous configurable options
+- */
+-#define CONFIG_SYS_MAXARGS 16
+-#define CONFIG_SYS_LONGHELP
+-#define CONFIG_SYS_PROMPT "NanoNote# "
+-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+-
+-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+-#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+-
+-#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
+-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+-#define CONFIG_SYS_LOAD_ADDR		0x80600000
+-#define CONFIG_SYS_MEMTEST_START	0x80100000
+-#define CONFIG_SYS_MEMTEST_END		0x80800000
+-
+-/*
+- * Environment
++ * NAND driver configuration
+  */
+-#define CONFIG_ENV_IS_IN_NAND		/* use NAND for environment vars */
+-
+-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+-/*
+- * if board nand flash is 1GB, set to 1
+- * if board nand flash is 2GB, set to 2
+- * for change the PAGE_SIZE and BLOCK_SIZE
+- * will delete when there is no 1GB flash
+- */
+-#define NANONOTE_NAND_SIZE	2
+-
+-#define CONFIG_SYS_NAND_PAGE_SIZE	(2048 * NANONOTE_NAND_SIZE)
+-#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * NANONOTE_NAND_SIZE << 10)
+-/* nand bad block was marked at this page in a block, start from 0 */
++#define CONFIG_NAND_JZ4740
++#define CONFIG_SYS_NAND_PAGE_SIZE	4096
++#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 << 10)
++/* NAND bad block was marked at this page in a block, start from 0 */
+ #define CONFIG_SYS_NAND_BADBLOCK_PAGE	127
+ #define CONFIG_SYS_NAND_PAGE_COUNT	128
+ #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+-/* ECC offset position in oob area, default value is 6 if it isn't defined */
+-#define CONFIG_SYS_NAND_ECC_POS		(6 * NANONOTE_NAND_SIZE)
++#define CONFIG_SYS_NAND_ECC_POS		12
+ #define CONFIG_SYS_NAND_ECCSIZE		512
+ #define CONFIG_SYS_NAND_ECCBYTES	9
+ #define CONFIG_SYS_NAND_ECCPOS		\
+@@ -115,10 +104,9 @@
+ #define CONFIG_SYS_ONENAND_BASE		CONFIG_SYS_NAND_BASE
+ #define CONFIG_SYS_MAX_NAND_DEVICE	1
+ #define CONFIG_SYS_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl.*/
+-#define CONFIG_NAND_SPL_TEXT_BASE	0x80000000
+ 
+ /*
+- * IPL (Initial Program Loader, integrated inside CPU)
++ * IPL (Initial Program Loader, integrated inside Ingenic Xburst JZ4740 CPU)
+  * Will load first 8k from NAND (SPL) into cache and execute it from there.
+  *
+  * SPL (Secondary Program Loader)
+@@ -130,77 +118,88 @@
+  * NUB (NAND U-Boot)
+  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+- *
+  */
++
++/*
++ * NAND SPL configuration
++ */
++#define CONFIG_SPL
++#define CONFIG_SPL_LIBGENERIC_SUPPORT
++#define CONFIG_SPL_LIBCOMMON_SUPPORT
++#define CONFIG_SPL_NAND_LOAD
++#define CONFIG_SPL_NAND_SIMPLE
++#define CONFIG_SPL_NAND_SUPPORT
++#define CONFIG_SPL_TEXT_BASE	0x80000000
++#define CONFIG_SPL_START_S_PATH	"arch/mips/cpu/xburst/spl"
++
++#define CONFIG_SYS_NAND_5_ADDR_CYCLE
++#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
++#define JZ4740_NANDBOOT_CFG		JZ4740_NANDBOOT_B8R3
++
+ #define CONFIG_SYS_NAND_U_BOOT_DST	0x80100000 /* Load NUB to this addr */
+ #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+-/* Start NUB from this addr*/
++					/* Start NUB from this addr */
++#define CONFIG_SYS_NAND_U_BOOT_OFFS (32  << 10) /* Offset of NUB */
++#define CONFIG_SYS_NAND_U_BOOT_SIZE (256 << 10) /* Size of NUB */
+ 
+ /*
+- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
++ * Environment configuration
+  */
+-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
+-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
+-
++#define CONFIG_ENV_OVERWRITE
++#define CONFIG_ENV_IS_IN_NAND
+ #define CONFIG_ENV_SIZE		(4 << 10)
+ #define CONFIG_ENV_OFFSET	\
+ 	(CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
+ #define CONFIG_ENV_OFFSET_REDUND \
+ 	(CONFIG_ENV_OFFSET  + CONFIG_SYS_NAND_BLOCK_SIZE)
+ 
+-#define CONFIG_SYS_TEXT_BASE	0x80100000
+-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+-
+ /*
+- * SDRAM Info.
++ * CPU cache configuration
+  */
+-#define CONFIG_NR_DRAM_BANKS	1
++#define CONFIG_SYS_DCACHE_SIZE		16384
++#define CONFIG_SYS_ICACHE_SIZE		16384
++#define CONFIG_SYS_CACHELINE_SIZE	32
+ 
+ /*
+- * Cache Configuration
++ * SDRAM configuration
+  */
+-#define CONFIG_SYS_DCACHE_SIZE	16384
+-#define CONFIG_SYS_ICACHE_SIZE	16384
+-#define CONFIG_SYS_CACHELINE_SIZE	32
++#define CONFIG_NR_DRAM_BANKS	1
++
++#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
++#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
++#define SDRAM_ROW		13	/* Row address: 11 to 13 */
++#define SDRAM_COL		9	/* Column address: 8 to 12 */
++#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
++#define SDRAM_TRAS		45	/* RAS# Active Time */
++#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
++#define SDRAM_TPC		20	/* RAS# Precharge Time */
++#define SDRAM_TRWL		7	/* Write Latency Time */
++#define SDRAM_TREF		15625	/* Refresh period: 8192 cycles/64ms */
+ 
+ /*
+- * GPIO definition
++ * GPIO configuration
+  */
+-#define GPIO_LCD_CS	(2 * 32 + 21)
+-#define GPIO_AMP_EN	(3 * 32 + 4)
++#define GPIO_LCD_CS		(2 * 32 + 21)
++#define GPIO_AMP_EN		(3 * 32 + 4)
+ 
+-#define GPIO_SDPW_EN	(3 * 32 + 2)
+-#define GPIO_SD_DETECT	(3 * 32 + 0)
++#define GPIO_SDPW_EN		(3 * 32 + 2)
++#define GPIO_SD_DETECT		(3 * 32 + 0)
+ 
+-#define GPIO_BUZZ_PWM	(3 * 32 + 27)
+-#define GPIO_USB_DETECT	(3 * 32 + 28)
++#define GPIO_BUZZ_PWM		(3 * 32 + 27)
++#define GPIO_USB_DETECT		(3 * 32 + 28)
+ 
+-#define GPIO_AUDIO_POP	(1 * 32 + 29)
+-#define GPIO_COB_TEST	(1 * 32 + 30)
++#define GPIO_AUDIO_POP		(1 * 32 + 29)
++#define GPIO_COB_TEST		(1 * 32 + 30)
+ 
+ #define GPIO_KEYOUT_BASE	(2 * 32 + 10)
+-#define GPIO_KEYIN_BASE	(3 * 32 + 18)
+-#define GPIO_KEYIN_8	(3 * 32 + 26)
++#define GPIO_KEYIN_BASE		(3 * 32 + 18)
++#define GPIO_KEYIN_8		(3 * 32 + 26)
+ 
+-#define GPIO_SD_CD_N	GPIO_SD_DETECT		/* SD Card insert detect */
++#define GPIO_SD_CD_N		GPIO_SD_DETECT	/* SD Card insert detect */
+ #define GPIO_SD_VCC_EN_N	GPIO_SDPW_EN	/* SD Card Power Enable */
+ 
+ #define SPEN	GPIO_LCD_CS	/* LCDCS :Serial command enable      */
+ #define SPDA	(2 * 32 + 22)	/* LCDSCL:Serial command clock input */
+ #define SPCK	(2 * 32 + 23)	/* LCDSDA:Serial command data input  */
+ 
+-/* SDRAM paramters */
+-#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
+-#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
+-#define SDRAM_ROW		13	/* Row address: 11 to 13 */
+-#define SDRAM_COL		9	/* Column address: 8 to 12 */
+-#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
+-
+-/* SDRAM Timings, unit: ns */
+-#define SDRAM_TRAS		45	/* RAS# Active Time */
+-#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
+-#define SDRAM_TPC		20	/* RAS# Precharge Time */
+-#define SDRAM_TRWL		7	/* Write Latency Time */
+-#define SDRAM_TREF		15625	/* Refresh period: 8192 cycles/64ms */
+-
+ #endif
+-- 
+1.7.9.5
+

package/boot/uboot-xburst/patches/0002-qi_lb60-add-software-usbboot-support.patch

@@ -0,0 +1,916 @@
+From fa51192b912d296b8eec10f7d44c6c17eb1dd368 Mon Sep 17 00:00:00 2001
+From: Xiangfu <xiangfu@openmobilefree.net>
+Date: Fri, 12 Oct 2012 09:47:39 +0800
+Subject: [PATCH 2/6] qi_lb60: add software usbboot support
+
+  JZ4740 CPU have a internal ROM have such kind of code, that make
+  JZ4740 can boot from USB
+
+  usbboot.S can downloads user program from the USB port to internal
+  SRAM and branches to the internal SRAM to execute the program
+
+Signed-off-by: Xiangfu <xiangfu@openmobilefree.net>
+---
+ board/qi/qi_lb60/Makefile      |    1 +
+ board/qi/qi_lb60/qi_lb60-spl.c |   20 +
+ board/qi/qi_lb60/usbboot.S     |  838 ++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 859 insertions(+)
+ create mode 100644 board/qi/qi_lb60/usbboot.S
+
+diff --git a/board/qi/qi_lb60/Makefile b/board/qi/qi_lb60/Makefile
+index e399246..6dd8c6f 100644
+--- a/board/qi/qi_lb60/Makefile
++++ b/board/qi/qi_lb60/Makefile
+@@ -23,6 +23,7 @@ include $(TOPDIR)/config.mk
+ LIB	= $(obj)lib$(BOARD).o
+ 
+ ifeq ($(CONFIG_SPL_BUILD),y)
++SOBJS	:= usbboot.o
+ COBJS	:= $(BOARD)-spl.o
+ else
+ COBJS	:= $(BOARD).o
+diff --git a/board/qi/qi_lb60/qi_lb60-spl.c b/board/qi/qi_lb60/qi_lb60-spl.c
+index 3fe3fa3..aea459c 100644
+--- a/board/qi/qi_lb60/qi_lb60-spl.c
++++ b/board/qi/qi_lb60/qi_lb60-spl.c
+@@ -12,6 +12,24 @@
+ #include <asm/io.h>
+ #include <asm/jz4740.h>
+ 
++#define KEY_U_OUT       (32 * 2 + 16)
++#define KEY_U_IN        (32 * 3 + 19)
++
++extern void usb_boot(void);
++
++static void check_usb_boot(void)
++{
++	__gpio_as_input(KEY_U_IN);
++	__gpio_enable_pull(KEY_U_IN);
++	__gpio_as_output(KEY_U_OUT);
++	__gpio_clear_pin(KEY_U_OUT);
++
++	if (!__gpio_get_pin(KEY_U_IN)) {
++		puts("[U] pressed, goto USBBOOT mode\n");
++		usb_boot();
++	}
++}
++
+ void nand_spl_boot(void)
+ {
+ 	__gpio_as_sdram_16bit_4720();
+@@ -23,6 +41,8 @@ void nand_spl_boot(void)
+ 	pll_init();
+ 	sdram_init();
+ 
++	check_usb_boot();
++
+ 	nand_init();
+ 
+ 	puts("\nQi LB60 SPL: Starting U-Boot ...\n");
+diff --git a/board/qi/qi_lb60/usbboot.S b/board/qi/qi_lb60/usbboot.S
+new file mode 100644
+index 0000000..c872266
+--- /dev/null
++++ b/board/qi/qi_lb60/usbboot.S
+@@ -0,0 +1,838 @@
++/*
++ *  for jz4740 usb boot
++ *
++ *  Copyright (c) 2009 Author: <jlwei@ingenic.cn>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++    .set noreorder
++    .globl usb_boot
++    .text
++
++/*
++ * Both NAND and USB boot load data to D-Cache first, then transfer
++ * data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
++ * So init caches first and then dispatch to a proper boot routine.
++ */
++
++.macro load_addr reg addr
++	li \reg, 0x80000000
++	addiu \reg, \reg, \addr
++	la $2, usbboot_begin
++	subu \reg, \reg, $2
++.endm
++
++usb_boot:
++	/* Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz. */
++	la	$9, 0xB0000000		/* CPCCR: Clock Control Register */
++	la	$8, 0x42041110		/* I:S:M:P=1:2:2:2 */
++	sw	$8, 0($9)
++
++	la	$9, 0xB0000010		/* CPPCR: PLL Control Register */
++	la	$8, 0x06000120		/* M=12 N=0 D=0 CLK=12*(M+2)/(N+2) */
++	sw	$8, 0($9)
++
++	mtc0	$0, $26		/* CP0_ERRCTL, restore WST reset state */
++	nop
++
++	mtc0	$0, $16			/* CP0_CONFIG */
++	nop
++
++	/* Relocate code to beginning of the ram */
++
++	la $2, usbboot_begin
++	la $3, usbboot_end
++	li $4, 0x80000000
++
++1:
++	lw $5, 0($2)
++	sw $5, 0($4)
++	addiu $2, $2, 4
++	bne $2, $3, 1b
++	addiu $4, $4, 4
++
++	li $2, 0x80000000
++	ori $3, $2, 0
++	addiu $3, $3, usbboot_end
++	la $4, usbboot_begin
++	subu $3, $3, $4
++
++
++2:
++	cache	0x0, 0($2)		/* Index_Invalidate_I */
++	cache	0x1, 0($2)		/* Index_Writeback_Inv_D */
++	addiu	$2, $2, 32
++	subu $4, $3, $2
++	bgtz	$4, 2b
++	nop
++
++	load_addr $3, usb_boot_return
++
++	jr $3
++
++usbboot_begin:
++
++init_caches:
++	li	$2, 3			/* cacheable for kseg0 access */
++	mtc0	$2, $16			/* CP0_CONFIG */
++	nop
++
++	li	$2, 0x20000000		/* enable idx-store-data cache insn */
++	mtc0	$2, $26			/* CP0_ERRCTL */
++
++	ori	$2, $28, 0		/* start address */
++	ori	$3, $2, 0x3fe0		/* end address, total 16KB */
++	mtc0	$0, $28, 0		/* CP0_TAGLO */
++	mtc0	$0, $28, 1		/* CP0_DATALO */
++cache_clear_a_line:
++	cache	0x8, 0($2)		/* Index_Store_Tag_I */
++	cache	0x9, 0($2)		/* Index_Store_Tag_D */
++	bne	$2, $3, cache_clear_a_line
++	addiu	$2, $2, 32		/* increment CACHE_LINE_SIZE */
++
++	ori	$2, $28, 0		/* start address */
++	ori	$3, $2, 0x3fe0		/* end address, total 16KB */
++	la	$4, 0x1ffff000		/* physical address and 4KB page mask */
++cache_alloc_a_line:
++	and	$5, $2, $4
++	ori	$5, $5, 1		/* V bit of the physical tag */
++	mtc0	$5, $28, 0		/* CP0_TAGLO */
++	cache	0x8, 0($2)		/* Index_Store_Tag_I */
++	cache	0x9, 0($2)		/* Index_Store_Tag_D */
++	bne	$2, $3, cache_alloc_a_line
++	addiu	$2, $2, 32		/* increment CACHE_LINE_SIZE */
++
++	nop
++	nop
++	nop
++	/*
++	 * Transfer data from dcache to icache, then jump to icache.
++	 * Input parameters:
++	 * $19: data length in bytes
++	 * $20: jump target address
++	 */
++xfer_d2i:
++
++	ori	$8, $20, 0
++	addu	$9, $8, $19		/* total 16KB */
++
++1:
++	cache	0x0, 0($8)		/* Index_Invalidate_I */
++	cache	0x1, 0($8)		/* Index_Writeback_Inv_D */
++	bne	$8, $9, 1b
++	addiu	$8, $8, 32
++
++	/* flush write-buffer */
++	sync
++
++	/* Invalidate BTB */
++	mfc0	$8, $16, 7		/* CP0_CONFIG */
++	nop
++	ori	$8, 2
++	mtc0	$8, $16, 7
++	nop
++
++	/* Overwrite config to disable ram initalisation */
++	li $2, 0xff
++	sb $2, 20($20)
++
++	jalr	$20
++	nop
++
++icache_return:
++	/* User code can return to here after executing itself in
++	  icache, by jumping to $31. */
++	b	usb_boot_return
++	nop
++
++
++usb_boot_return:
++	/* Enable the USB PHY */
++	la	$9, 0xB0000024		/* CPM_SCR */
++	lw	$8, 0($9)
++	ori	$8, 0x40		/* USBPHY_ENABLE */
++	sw	$8, 0($9)
++
++	/* Initialize USB registers */
++	la	$27, 0xb3040000	/* USB registers base address */
++
++	sb	$0, 0x0b($27)	/* INTRUSBE: disable common USB interrupts */
++	sh	$0, 0x06($27)	/* INTRINE: disable EPIN interrutps */
++	sh	$0, 0x08($27)	/* INTROUTE: disable EPOUT interrutps */
++
++	li	$9, 0x61
++	sb	$9, 0x01($27)	/* POWER: HSENAB | SUSPENDM | SOFTCONN */
++
++	/* Initialize USB states */
++	li	$22, 0			/* set EP0 to IDLE state */
++	li	$23, 1			/* no data stage */
++
++	/* Main loop of polling the usb commands */
++usb_command_loop:
++	lbu	$9, 0x0a($27)		/* read INTRUSB */
++	andi	$9, 0x04		/* check USB_INTR_RESET */
++	beqz	$9, check_intr_ep0in
++	nop
++
++ 	/* 1. Handle USB reset interrupt */
++handle_reset_intr:
++	lbu	$9, 0x01($27)		/* read POWER */
++	andi	$9, 0x10		/* test HS_MODE */
++	bnez	$9, _usb_set_maxpktsize
++	li	$9, 512			/* max packet size of HS mode */
++	li	$9, 64			/* max packet size of FS mode */
++
++_usb_set_maxpktsize:
++	li	$8, 1
++	sb	$8, 0x0e($27)		/* set INDEX 1 */
++
++	sh	$9, 0x10($27)		/* INMAXP */
++	sb	$0, 0x13($27)		/* INCSRH */
++	sh	$9, 0x14($27)		/* OUTMAXP */
++	sb	$0, 0x17($27)		/* OUTCSRH */
++
++_usb_flush_fifo:
++	li	$8, 0x48		/* INCSR_CDT && INCSR_FF */
++	sb	$8, 0x12($27)		/* INCSR */
++	li	$8, 0x90		/* OUTCSR_CDT && OUTCSR_FF */
++	sb	$8, 0x16($27)		/* OUTCSR */
++
++	li	$22, 0			/* set EP0 to IDLE state */
++	li	$23, 1			/* no data stage */
++
++	/* 2. Check and handle EP0 interrupt */
++check_intr_ep0in:
++	lhu	$10, 0x02($27)		/* read INTRIN */
++	andi	$9, $10, 0x1		/* check EP0 interrupt */
++	beqz	$9, check_intr_ep1in
++	nop
++
++handle_ep0_intr:
++	sb	$0, 0x0e($27)		/* set INDEX 0 */
++	lbu	$11, 0x12($27)		/* read CSR0 */
++
++	andi	$9, $11, 0x04		/* check SENTSTALL */
++	beqz	$9, _ep0_setupend
++	nop
++
++_ep0_sentstall:
++	andi	$9, $11, 0xdb
++	sb	$9, 0x12($27)		/* clear SENDSTALL and SENTSTALL */
++	li	$22, 0			/* set EP0 to IDLE state */
++
++_ep0_setupend:
++	andi	$9, $11, 0x10		/* check SETUPEND */
++	beqz	$9, ep0_idle_state
++	nop
++
++	ori	$9, $11, 0x80
++	sb	$9, 0x12($27)		/* set SVDSETUPEND */
++	li	$22, 0			/* set EP0 to IDLE state */
++
++ep0_idle_state:
++	bnez	$22, ep0_tx_state
++	nop
++
++	/* 2.1 Handle EP0 IDLE state interrupt */
++	andi	$9, $11, 0x01		/* check OUTPKTRDY */
++	beqz	$9, check_intr_ep1in
++	nop
++
++	/* Read 8-bytes setup packet from the FIFO */
++	lw	$25, 0x20($27)		/* first word of setup packet */
++	lw	$26, 0x20($27)		/* second word of setup packet */
++
++	andi	$9, $25, 0x60		/* bRequestType & USB_TYPE_MASK */
++	beqz	$9, _ep0_std_req
++	nop
++
++	/* 2.1.1 Vendor-specific setup request */
++_ep0_vend_req:
++	li	$22, 0			/* set EP0 to IDLE state */
++	li	$23, 1			/* NoData = 1 */
++
++	andi	$9, $25, 0xff00		/* check bRequest */
++	srl	$9, $9, 8
++	beqz	$9, __ep0_get_cpu_info
++	sub	$8, $9, 0x1
++	beqz	$8, __ep0_set_data_address
++	sub	$8, $9, 0x2
++	beqz	$8, __ep0_set_data_length
++	sub	$8, $9, 0x3
++	beqz	$8, __ep0_flush_caches
++	sub	$8, $9, 0x4
++	beqz	$8, __ep0_prog_start1
++	sub	$8, $9, 0x5
++	beqz	$8, __ep0_prog_start2
++	nop
++	b	_ep0_idle_state_fini	/* invalid request */
++	nop
++
++__ep0_get_cpu_info:
++	load_addr $20, cpu_info_data	/* data pointer to transfer */
++	li	$21, 8			/* bytes left to transfer */
++	li	$22, 1			/* set EP0 to TX state */
++	li	$23, 0			/* NoData = 0 */
++
++	b	_ep0_idle_state_fini
++	nop
++
++__ep0_set_data_address:
++	li	$9, 0xffff0000
++	and	$9, $25, $9
++	andi	$8, $26, 0xffff
++	or	$20, $9, $8		/* data address of next transfer */
++
++	b	_ep0_idle_state_fini
++	nop
++
++__ep0_set_data_length:
++	li	$9, 0xffff0000
++	and	$9, $25, $9
++	andi	$8, $26, 0xffff
++	or	$21, $9, $8		/* data length of next transfer */
++
++	li	$9, 0x48		/* SVDOUTPKTRDY and DATAEND */
++	sb	$9, 0x12($27)		/* CSR0 */
++
++	/* We must write packet to FIFO before EP1-IN interrupt here. */
++	b	handle_epin1_intr
++	nop
++
++__ep0_flush_caches:
++	/* Flush dcache and invalidate icache. */
++	li	$8, 0x80000000
++	addi	$9, $8, 0x3fe0		/* total 16KB */
++
++1:
++	cache	0x0, 0($8)		/* Index_Invalidate_I */
++	cache	0x1, 0($8)		/* Index_Writeback_Inv_D */
++	bne	$8, $9, 1b
++	addiu	$8, $8, 32
++
++	/* flush write-buffer */
++	sync
++
++	/* Invalidate BTB */
++	mfc0	$8, $16, 7		/* CP0_CONFIG */
++	nop
++	ori	$8, 2
++	mtc0	$8, $16, 7
++	nop
++
++	b	_ep0_idle_state_fini
++	nop
++
++__ep0_prog_start1:
++	li	$9, 0x48		/* SVDOUTPKTRDY and DATAEND */
++	sb	$9, 0x12($27)		/* CSR0 */
++
++	li	$9, 0xffff0000
++	and	$9, $25, $9
++	andi	$8, $26, 0xffff
++	or	$20, $9, $8		/* target address */
++
++	b	xfer_d2i
++	li	$19, 0x2000		/* 16KB data length */
++
++__ep0_prog_start2:
++	li	$9, 0x48		/* SVDOUTPKTRDY and DATAEND */
++	sb	$9, 0x12($27)		/* CSR0 */
++
++	li	$9, 0xffff0000
++	and	$9, $25, $9
++	andi	$8, $26, 0xffff
++	or	$20, $9, $8		/* target address */
++
++	jalr	$20		/* jump, and place the return address in $31 */
++	nop
++
++__ep0_prog_start2_return:
++/* User code can return to here after executing itself, by jumping to $31 */
++	b	usb_boot_return
++	nop
++
++	/* 2.1.2 Standard setup request */
++_ep0_std_req:
++	andi	$12, $25, 0xff00	/* check bRequest */
++	srl	$12, $12, 8
++	sub	$9, $12, 0x05		/* check USB_REQ_SET_ADDRESS */
++	bnez	$9, __ep0_req_set_config
++	nop
++
++	/* Handle USB_REQ_SET_ADDRESS */
++__ep0_req_set_addr:
++	srl	$9, $25, 16		/* get wValue */
++	sb	$9, 0x0($27)		/* set FADDR */
++	li	$23, 1			/* NoData = 1 */
++	b	_ep0_idle_state_fini
++	nop
++
++__ep0_req_set_config:
++	sub	$9, $12, 0x09		/* check USB_REQ_SET_CONFIGURATION */
++	bnez	$9, __ep0_req_get_desc
++	nop
++
++	/* Handle USB_REQ_SET_CONFIGURATION */
++	li	$23, 1			/* NoData = 1 */
++	b	_ep0_idle_state_fini
++	nop
++
++__ep0_req_get_desc:
++	sub	$9, $12, 0x06		/* check USB_REQ_GET_DESCRIPTOR */
++	bnez	$9, _ep0_idle_state_fini
++	li	$23, 1			/* NoData = 1 */
++
++	/* Handle USB_REQ_GET_DESCRIPTOR */
++	li	$23, 0			/* NoData = 0 */
++
++	srl	$9, $25, 24		/* wValue >> 8 */
++	sub	$8, $9, 0x01		/* check USB_DT_DEVICE */
++	beqz	$8, ___ep0_get_dev_desc
++	srl	$21, $26, 16		/* get wLength */
++	sub	$8, $9, 0x02		/* check USB_DT_CONFIG */
++	beqz	$8, ___ep0_get_conf_desc
++	sub	$8, $9, 0x03		/* check USB_DT_STRING */
++	beqz	$8, ___ep0_get_string_desc
++	sub	$8, $9, 0x06		/* check USB_DT_DEVICE_QUALIFIER */
++	beqz	$8, ___ep0_get_dev_qualifier
++	nop
++	b	_ep0_idle_state_fini
++	nop
++
++___ep0_get_dev_desc:
++	load_addr	$20, device_desc	/* data pointer */
++	li	$22, 1			/* set EP0 to TX state */
++	sub	$8, $21, 18
++	blez	$8, _ep0_idle_state_fini /* wLength <= 18 */
++	nop
++	li	$21, 18			/* max length of device_desc */
++	b	_ep0_idle_state_fini
++	nop
++
++___ep0_get_dev_qualifier:
++	load_addr	$20, dev_qualifier	/* data pointer */
++	li	$22, 1			/* set EP0 to TX state */
++	sub	$8, $21, 10
++	blez	$8, _ep0_idle_state_fini /* wLength <= 10 */
++	nop
++	li	$21, 10			/* max length of dev_qualifier */
++	b	_ep0_idle_state_fini
++	nop
++
++___ep0_get_conf_desc:
++	load_addr	$20, config_desc_fs	/* data pointer of FS mode */
++	lbu	$8, 0x01($27)		/* read POWER */
++	andi	$8, 0x10		/* test HS_MODE */
++	beqz	$8, ___ep0_get_conf_desc2
++	nop
++	load_addr $20, config_desc_hs	/* data pointer of HS mode */
++
++___ep0_get_conf_desc2:
++	li	$22, 1			/* set EP0 to TX state */
++	sub	$8, $21, 32
++	blez	$8, _ep0_idle_state_fini /* wLength <= 32 */
++	nop
++	li	$21, 32			/* max length of config_desc */
++	b	_ep0_idle_state_fini
++	nop
++
++___ep0_get_string_desc:
++	li	$22, 1			/* set EP0 to TX state */
++
++	srl	$9, $25, 16		/* wValue & 0xff */
++	andi	$9, 0xff
++
++	sub	$8, $9, 1
++	beqz	$8, ___ep0_get_string_manufacture
++	sub	$8, $9, 2
++	beqz	$8, ___ep0_get_string_product
++	nop
++
++___ep0_get_string_lang_ids:
++	load_addr	$20, string_lang_ids	/* data pointer */
++	b	_ep0_idle_state_fini
++	li	$21, 4			/* data length */
++
++___ep0_get_string_manufacture:
++	load_addr	$20, string_manufacture	/* data pointer */
++	b	_ep0_idle_state_fini
++	li	$21, 16			/* data length */
++
++___ep0_get_string_product:
++	load_addr	$20, string_product	/* data pointer */
++	b	_ep0_idle_state_fini
++	li	$21, 46			/* data length */
++
++_ep0_idle_state_fini:
++	li	$9, 0x40		/* SVDOUTPKTRDY */
++	beqz	$23, _ep0_idle_state_fini2
++	nop
++	ori	$9, $9, 0x08		/* DATAEND */
++_ep0_idle_state_fini2:
++	sb	$9, 0x12($27)		/* CSR0 */
++	beqz	$22, check_intr_ep1in
++	nop
++
++	/* 2.2 Handle EP0 TX state interrupt */
++ep0_tx_state:
++	sub	$9, $22, 1
++	bnez	$9, check_intr_ep1in
++	nop
++
++	sub	$9, $21, 64		/* max packetsize */
++	blez	$9, _ep0_tx_state2	/* data count <= 64 */
++	ori	$19, $21, 0
++	li	$19, 64
++
++_ep0_tx_state2:
++	beqz	$19, _ep0_tx_state3	/* send ZLP */
++	ori	$18, $19, 0		/* record bytes to be transferred */
++	sub	$21, $21, $19		/* decrement data count */
++
++_ep0_fifo_write_loop:
++	lbu	$9, 0($20)		/* read data */
++	sb	$9, 0x20($27)		/* load FIFO */
++	sub	$19, $19, 1		/* decrement counter */
++	bnez	$19, _ep0_fifo_write_loop
++	addi	$20, $20, 1		/* increment data pointer */
++
++	sub	$9, $18, 64		/* max packetsize */
++	beqz	$9, _ep0_tx_state4
++	nop
++
++_ep0_tx_state3:
++	/* transferred bytes < max packetsize */
++	li	$9, 0x0a		/* set INPKTRDY and DATAEND */
++	sb	$9, 0x12($27)		/* CSR0 */
++	li	$22, 0			/* set EP0 to IDLE state */
++	b	check_intr_ep1in
++	nop
++
++_ep0_tx_state4:
++	/* transferred bytes == max packetsize */
++	li	$9, 0x02		/* set INPKTRDY */
++	sb	$9, 0x12($27)		/* CSR0 */
++	b	check_intr_ep1in
++	nop
++
++	/* 3. Check and handle EP1 BULK-IN interrupt */
++check_intr_ep1in:
++	andi	$9, $10, 0x2		/* check EP1 IN interrupt */
++	beqz	$9, check_intr_ep1out
++	nop
++
++handle_epin1_intr:
++	li	$9, 1
++	sb	$9, 0x0e($27)		/* set INDEX 1 */
++	lbu	$9, 0x12($27)		/* read INCSR */
++
++	andi	$8, $9, 0x2		/* check INCSR_FFNOTEMPT */
++	bnez	$8, _epin1_tx_state4
++	nop
++
++_epin1_write_fifo:
++	lhu	$9, 0x10($27)		/* get INMAXP */
++	sub	$8, $21, $9
++	blez	$8, _epin1_tx_state1	/* bytes left <= INMAXP */
++	ori	$19, $21, 0
++	ori	$19, $9, 0
++
++_epin1_tx_state1:
++	beqz	$19, _epin1_tx_state4	/* No data */
++	nop
++
++	sub	$21, $21, $19		/* decrement data count */
++
++	srl	$5, $19, 2		/* # of word */
++	andi	$6, $19, 0x3		/* # of byte */
++	beqz	$5, _epin1_tx_state2
++	nop
++
++_epin1_fifo_write_word:
++	lw	$9, 0($20)		/* read data from source address */
++	sw	$9, 0x24($27)		/* write FIFO */
++	sub	$5, $5, 1		/* decrement counter */
++	bnez	$5, _epin1_fifo_write_word
++	addiu	$20, $20, 4		/* increment dest address */
++
++_epin1_tx_state2:
++	beqz	$6, _epin1_tx_state3
++	nop
++
++_epin1_fifo_write_byte:
++	lbu	$9, 0($20)		/* read data from source address */
++	sb	$9, 0x24($27)		/* write FIFO */
++	sub	$6, $6, 1		/* decrement counter */
++	bnez	$6, _epin1_fifo_write_byte
++	addiu	$20, $20, 1		/* increment dest address */
++
++_epin1_tx_state3:
++	li	$9, 0x1
++	sb	$9, 0x12($27)		/* INCSR, set INPKTRDY */
++
++_epin1_tx_state4:
++	/* 4. Check and handle EP1 BULK-OUT interrupt */
++check_intr_ep1out:
++	lhu	$9, 0x04($27)		/* read INTROUT */
++	andi	$9, 0x2
++	beqz	$9, check_status_next
++	nop
++
++handle_epout1_intr:
++	li	$9, 1
++	sb	$9, 0x0e($27)		/* set INDEX 1 */
++
++	lbu	$9, 0x16($27)		/* read OUTCSR */
++	andi	$9, 0x1			/* check OUTPKTRDY */
++	beqz	$9, check_status_next
++	nop
++
++_epout1_read_fifo:
++	lhu	$19, 0x18($27)		/* read OUTCOUNT */
++	srl	$5, $19, 2		/* # of word */
++	andi	$6, $19, 0x3		/* # of byte */
++	beqz	$5, _epout1_rx_state1
++	nop
++
++_epout1_fifo_read_word:
++	lw	$9, 0x24($27)		/* read FIFO */
++	sw	$9, 0($20)		/* store to dest address */
++	sub	$5, $5, 1		/* decrement counter */
++	bnez	$5, _epout1_fifo_read_word
++	addiu	$20, $20, 4		/* increment dest address */
++
++_epout1_rx_state1:
++	beqz	$6, _epout1_rx_state2
++	nop
++
++_epout1_fifo_read_byte:
++	lbu	$9, 0x24($27)		/* read FIFO */
++	sb	$9, 0($20)		/* store to dest address */
++	sub	$6, $6, 1		/* decrement counter */
++	bnez	$6, _epout1_fifo_read_byte
++	addiu	$20, $20, 1		/* increment dest address */
++
++_epout1_rx_state2:
++	sb	$0, 0x16($27)		/* clear OUTPKTRDY */
++
++check_status_next:
++	b	usb_command_loop
++	nop
++
++/* Device/Configuration/Interface/Endpoint/String Descriptors */
++
++	.align	2
++device_desc:
++	.byte	0x12		/* bLength */
++	.byte	0x01		/* bDescriptorType */
++	.byte	0x00		/* bcdUSB */
++	.byte	0x02		/* bcdUSB */
++	.byte	0x00		/* bDeviceClass */
++	.byte	0x00		/* bDeviceSubClass */
++	.byte	0x00		/* bDeviceProtocol */
++	.byte	0x40		/* bMaxPacketSize0 */
++	.byte	0x1a		/* idVendor */
++	.byte	0x60		/* idVendor */
++	.byte	0x40		/* idProduct */
++	.byte	0x47		/* idProduct */
++	.byte	0x00		/* bcdDevice */
++	.byte	0x01		/* bcdDevice */
++	.byte	0x01		/* iManufacturer */
++	.byte	0x02		/* iProduct */
++	.byte	0x00		/* iSerialNumber */
++	.byte	0x01		/* bNumConfigurations */
++
++	.align	2
++dev_qualifier:
++	.byte	0x0a		/* bLength */
++	.byte	0x06		/* bDescriptorType */
++	.byte	0x00		/* bcdUSB */
++	.byte	0x02		/* bcdUSB */
++	.byte	0x00		/* bDeviceClass */
++	.byte	0x00		/* bDeviceSubClass */
++	.byte	0x00		/* bDeviceProtocol */
++	.byte	0x40		/* bMaxPacketSize0 */
++	.byte	0x01		/* bNumConfigurations */
++	.byte	0x00		/* bRESERVED */
++
++	.align	2
++config_desc_hs:
++	.byte	0x09		/* bLength */
++	.byte	0x02		/* bDescriptorType */
++	.byte	0x20		/* wTotalLength */
++	.byte	0x00		/* wTotalLength */
++	.byte	0x01		/* bNumInterfaces */
++	.byte	0x01		/* bConfigurationValue */
++	.byte	0x00		/* iConfiguration */
++	.byte	0xc0		/* bmAttributes */
++	.byte	0x01		/* MaxPower */
++intf_desc_hs:
++	.byte	0x09		/* bLength */
++	.byte	0x04		/* bDescriptorType */
++	.byte	0x00		/* bInterfaceNumber */
++	.byte	0x00		/* bAlternateSetting */
++	.byte	0x02		/* bNumEndpoints */
++	.byte	0xff		/* bInterfaceClass */
++	.byte	0x00		/* bInterfaceSubClass */
++	.byte	0x50		/* bInterfaceProtocol */
++	.byte	0x00		/* iInterface */
++ep1_desc_hs:
++	.byte	0x07		/* bLength */
++	.byte	0x05		/* bDescriptorType */
++	.byte	0x01		/* bEndpointAddress */
++	.byte	0x02		/* bmAttributes */
++	.byte	0x00		/* wMaxPacketSize */
++	.byte	0x02		/* wMaxPacketSize */
++	.byte	0x00		/* bInterval */
++ep2_desc_hs:
++	.byte	0x07		/* bLength */
++	.byte	0x05		/* bDescriptorType */
++	.byte	0x81		/* bEndpointAddress */
++	.byte	0x02		/* bmAttributes */
++	.byte	0x00		/* wMaxPacketSize */
++	.byte	0x02		/* wMaxPacketSize */
++	.byte	0x00		/* bInterval */
++
++	.align	2
++config_desc_fs:
++	.byte	0x09		/* bLength */
++	.byte	0x02		/* bDescriptorType */
++	.byte	0x20		/* wTotalLength */
++	.byte	0x00		/* wTotalLength */
++	.byte	0x01		/* bNumInterfaces */
++	.byte	0x01		/* bConfigurationValue */
++	.byte	0x00		/* iConfiguration */
++	.byte	0xc0		/* bmAttributes */
++	.byte	0x01		/* MaxPower */
++intf_desc_fs:
++	.byte	0x09		/* bLength */
++	.byte	0x04		/* bDescriptorType */
++	.byte	0x00		/* bInterfaceNumber */
++	.byte	0x00		/* bAlternateSetting */
++	.byte	0x02		/* bNumEndpoints */
++	.byte	0xff		/* bInterfaceClass */
++	.byte	0x00		/* bInterfaceSubClass */
++	.byte	0x50		/* bInterfaceProtocol */
++	.byte	0x00		/* iInterface */
++ep1_desc_fs:
++	.byte	0x07		/* bLength */
++	.byte	0x05		/* bDescriptorType */
++	.byte	0x01		/* bEndpointAddress */
++	.byte	0x02		/* bmAttributes */
++	.byte	0x40		/* wMaxPacketSize */
++	.byte	0x00		/* wMaxPacketSize */
++	.byte	0x00		/* bInterval */
++ep2_desc_fs:
++	.byte	0x07		/* bLength */
++	.byte	0x05		/* bDescriptorType */
++	.byte	0x81		/* bEndpointAddress */
++	.byte	0x02		/* bmAttributes */
++	.byte	0x40		/* wMaxPacketSize */
++	.byte	0x00		/* wMaxPacketSize */
++	.byte	0x00		/* bInterval */
++
++	.align	2
++string_lang_ids:
++	.byte	0x04
++	.byte	0x03
++	.byte	0x09
++	.byte	0x04
++
++	.align	2
++string_manufacture:
++	.byte	0x10
++	.byte	0x03
++	.byte	0x49
++	.byte	0x00
++	.byte	0x6e
++	.byte	0x00
++	.byte	0x67
++	.byte	0x00
++	.byte	0x65
++	.byte	0x00
++	.byte	0x6e
++	.byte	0x00
++	.byte	0x69
++	.byte	0x00
++	.byte	0x63
++	.byte	0x00
++
++	.align	2
++string_product:
++	.byte	0x2e
++	.byte	0x03
++	.byte	0x4a
++	.byte	0x00
++	.byte	0x5a
++	.byte	0x00
++	.byte	0x34
++	.byte	0x00
++	.byte	0x37
++	.byte	0x00
++	.byte	0x34
++	.byte	0x00
++	.byte	0x30
++	.byte	0x00
++	.byte	0x20
++	.byte	0x00
++	.byte	0x55
++	.byte	0x00
++	.byte	0x53
++	.byte	0x00
++	.byte	0x42
++	.byte	0x00
++	.byte	0x20
++	.byte	0x00
++	.byte	0x42
++	.byte	0x00
++	.byte	0x6f
++	.byte	0x00
++	.byte	0x6f
++	.byte	0x00
++	.byte	0x74
++	.byte	0x00
++	.byte	0x20
++	.byte	0x00
++	.byte	0x44
++	.byte	0x00
++	.byte	0x65
++	.byte	0x00
++	.byte	0x76
++	.byte	0x00
++	.byte	0x69
++	.byte	0x00
++	.byte	0x63
++	.byte	0x00
++	.byte	0x65
++	.byte	0x00
++
++	.align	2
++cpu_info_data:
++	.byte	0x4a
++	.byte	0x5a
++	.byte	0x34
++	.byte	0x37
++	.byte	0x34
++	.byte	0x30
++	.byte	0x56
++	.byte	0x31
++usbboot_end:
++
++    .set reorder
+-- 
+1.7.9.5
+

package/boot/uboot-xburst/patches/0004-add-more-boot-options-F1-F2-F3-F4-M-S.patch

@@ -0,0 +1,200 @@
+From c52b6168979d03fc31205444c3278c537787472a Mon Sep 17 00:00:00 2001
+From: Xiangfu <xiangfu@openmobilefree.net>
+Date: Wed, 10 Oct 2012 18:39:55 +0800
+Subject: [PATCH 4/6] add more boot options(F1/F2/F3/F4/M/S)
+
+---
+ arch/mips/include/asm/global_data.h |    3 +++
+ arch/mips/lib/bootm.c               |   17 ++++++++++++++++-
+ board/qi/qi_lb60/qi_lb60.c          |   26 +++++++++++++++++++++++---
+ common/main.c                       |   21 +++++++++++++++++++--
+ include/configs/qi_lb60.h           |   32 ++++++++++++++++++++++++++++++++
+ 5 files changed, 93 insertions(+), 6 deletions(-)
+
+diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
+index 6e2cdc7..cd03d7e 100644
+--- a/arch/mips/include/asm/global_data.h
++++ b/arch/mips/include/asm/global_data.h
+@@ -59,6 +59,9 @@ typedef	struct	global_data {
+ 	unsigned long	env_valid;	/* Checksum of Environment valid? */
+ 	void		**jt;		/* jump table */
+ 	char		env_buf[32];	/* buffer for getenv() before reloc. */
++#if defined(CONFIG_NANONOTE)
++        unsigned long   boot_option;
++#endif
+ } gd_t;
+ 
+ #include <asm-generic/global_data_flags.h>
+diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
+index 608c1a7..e00416b 100644
+--- a/arch/mips/lib/bootm.c
++++ b/arch/mips/lib/bootm.c
+@@ -47,10 +47,25 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
+ 			bootm_headers_t *images)
+ {
+ 	void (*theKernel) (int, char **, char **, int *);
+-	char *commandline = getenv("bootargs");
++	char *commandline;
+ 	char env_buf[12];
+ 	char *cp;
+ 
++#if defined(CONFIG_NANONOTE)
++        if (gd->boot_option & BOOT_FROM_MEMCARD)
++                commandline = getenv ("bootargsfromsd");
++        else if (gd->boot_option & BOOT_WITH_F1)
++                commandline = getenv ("bootargsf1");
++        else if (gd->boot_option & BOOT_WITH_F2)
++                commandline = getenv ("bootargsf2");
++        else if (gd->boot_option & BOOT_WITH_F3)
++                commandline = getenv ("bootargsf3");
++        else if (gd->boot_option & BOOT_WITH_F4)
++                commandline = getenv ("bootargsf4");
++        else
++#endif
++                commandline = getenv ("bootargs");
++
+ 	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+ 		return 1;
+ 
+diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c
+index a2ba648..d622219 100644
+--- a/board/qi/qi_lb60/qi_lb60.c
++++ b/board/qi/qi_lb60/qi_lb60.c
+@@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
+ 
+ static void gpio_init(void)
+ {
+-	unsigned int i;
++	unsigned int i, j;
+ 
+ 	/* Initialize NAND Flash Pins */
+ 	__gpio_as_nand();
+@@ -42,14 +42,34 @@ static void gpio_init(void)
+ 
+ 	if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){
+ 		printf("[S] pressed, enable UART0\n");
++		gd->boot_option |= BOOT_WITH_ENABLE_UART;
+ 		__gpio_as_uart0();
+ 	} else {
+ 		__gpio_as_input(GPIO_KEYIN_8);
+ 		__gpio_enable_pull(GPIO_KEYIN_8);
+ 	}
+ 
+-	/* enable the TP4, TP5 as UART0 */
+-	__gpio_jtag_to_uart0();
++	if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) {
++		printf("[M] pressed, boot from memory card\n");
++		gd->boot_option |= BOOT_FROM_MEMCARD;
++		__gpio_jtag_to_uart0();
++	}
++
++	for (j = 0; j < 4; j++) {
++		for (i = 0; i < 4; i++)
++			__gpio_set_pin(GPIO_KEYOUT_BASE + i);
++
++		__gpio_clear_pin(GPIO_KEYOUT_BASE + j);
++
++		if (__gpio_get_pin(GPIO_KEYIN_BASE) == 0) {
++			printf("[F%d] pressed", (j + 1));
++			gd->boot_option |= (1 << (j + 2));
++			/* BOOT_WITH_F1	(1 << 2) */
++			/* BOOT_WITH_F2	(1 << 3) */
++			/* BOOT_WITH_F3	(1 << 4) */
++			/* BOOT_WITH_F4	(1 << 5) */
++		}
++	}
+ 
+ 	__gpio_as_output(GPIO_AUDIO_POP);
+ 	__gpio_set_pin(GPIO_AUDIO_POP);
+diff --git a/common/main.c b/common/main.c
+index 9507cec..dbfb7ca 100644
+--- a/common/main.c
++++ b/common/main.c
+@@ -355,7 +355,11 @@ void main_loop (void)
+ #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
+ 	s = getenv ("bootdelay");
+ 	bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
+-
++#if defined(CONFIG_NANONOTE)
++	DECLARE_GLOBAL_DATA_PTR;
++	if (gd->boot_option & BOOT_WITH_ENABLE_UART)
++		bootdelay = 3;
++# endif
+ 	debug ("### main_loop entered: bootdelay=%d\n\n", bootdelay);
+ 
+ #if defined(CONFIG_MENU_SHOW)
+@@ -379,7 +383,20 @@ void main_loop (void)
+ 	}
+ 	else
+ #endif /* CONFIG_BOOTCOUNT_LIMIT */
+-		s = getenv ("bootcmd");
++#if defined(CONFIG_NANONOTE)
++		if (gd->boot_option & BOOT_FROM_MEMCARD)
++			s = getenv ("bootcmdfromsd");
++		else if (gd->boot_option & BOOT_WITH_F1)
++			s = getenv ("bootcmdf1");
++		else if (gd->boot_option & BOOT_WITH_F2)
++			s = getenv ("bootcmdf2");
++		else if (gd->boot_option & BOOT_WITH_F3)
++			s = getenv ("bootcmdf3");
++		else if (gd->boot_option & BOOT_WITH_F4)
++			s = getenv ("bootcmdf4");
++		else
++#endif
++			s = getenv ("bootcmd");
+ 
+ 	debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
+ 
+diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
+index 7b33be0..52b370c 100644
+--- a/include/configs/qi_lb60.h
++++ b/include/configs/qi_lb60.h
+@@ -31,6 +31,7 @@
+ /*
+  * Miscellaneous configurable options
+  */
++#define CONFIG_NANONOTE
+ #define CONFIG_JZ4740_MMC
+ #define CONFIG_MMC      	1
+ #define CONFIG_FAT      	1
+@@ -39,6 +40,37 @@
+ #define CONFIG_CMD_FAT
+ #define CONFIG_CMD_EXT2
+ 
++#define CONFIG_CMD_UBIFS
++#define CONFIG_CMD_UBI
++#define CONFIG_MTD_PARTITIONS
++#define CONFIG_MTD_DEVICE
++#define CONFIG_CMD_MTDPARTS
++#define CONFIG_CMD_UBI
++#define CONFIG_CMD_UBIFS
++#define CONFIG_LZO
++#define CONFIG_RBTREE
++
++#define MTDIDS_DEFAULT		"nand0=jz4740-nand"
++#define MTDPARTS_DEFAULT	"mtdparts=jz4740-nand:4M@0(uboot)ro,4M@4M(kernel)ro,512M@8M(rootfs)ro,-(data)ro"
++
++#define BOOT_FROM_MEMCARD	1
++#define BOOT_WITH_ENABLE_UART	(1 << 1)	/* Vaule for global_data.h gd->boot_option */
++#define BOOT_WITH_F1		(1 << 2)
++#define BOOT_WITH_F2		(1 << 3)
++#define BOOT_WITH_F3		(1 << 4)
++#define BOOT_WITH_F4		(1 << 5)
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++	"bootcmdfromsd=mmc init; ext2load mmc 0 0x80600000 /boot/uImage; bootm;\0" \
++	"bootargsfromsd=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait\0" \
++	"bootcmdf1=mmc init; ext2load mmc 0:1 0x80600000 /boot/uImage; bootm;\0" \
++	"bootargsf1=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait\0" \
++	"bootcmdf2=mmc init; ext2load mmc 0:2 0x80600000 /boot/uImage; bootm;\0" \
++	"bootargsf2=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootwait\0" \
++	"bootcmdf3=mmc init; ext2load mmc 0:3 0x80600000 /boot/uImage; bootm;\0" \
++	"bootargsf3=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p3 rw rootwait\0" \
++	"bootcmdf4=mtdparts default;ubi part rootfs;ubifsmount rootfs;ubifsload 0x80600000 /boot/uImage; bootm;\0" \
++	"bootargsf4=mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
+ 
+ #define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
+ #define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+-- 
+1.7.9.5
+

package/boot/uboot-xburst/patches/0005-add-nanonote-lcd-support.patch

@@ -0,0 +1,847 @@
+From ca8c5216cfd3ad3fda9867ed2d157ae5a209834b Mon Sep 17 00:00:00 2001
+From: Xiangfu <xiangfu@openmobilefree.net>
+Date: Wed, 10 Oct 2012 22:05:27 +0800
+Subject: [PATCH 5/6] add nanonote lcd support
+
+---
+ arch/mips/include/asm/global_data.h |    1 +
+ arch/mips/include/asm/jz4740.h      |   90 ++++++++
+ arch/mips/lib/board.c               |    6 +
+ common/lcd.c                        |    9 +-
+ drivers/video/Makefile              |    1 +
+ drivers/video/nanonote_gpm940b0.c   |  400 +++++++++++++++++++++++++++++++++++
+ drivers/video/nanonote_gpm940b0.h   |  135 ++++++++++++
+ include/configs/qi_lb60.h           |    7 +
+ include/lcd.h                       |   52 ++++-
+ 9 files changed, 697 insertions(+), 4 deletions(-)
+ create mode 100644 drivers/video/nanonote_gpm940b0.c
+ create mode 100644 drivers/video/nanonote_gpm940b0.h
+
+diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
+index cd03d7e..7cec2de 100644
+--- a/arch/mips/include/asm/global_data.h
++++ b/arch/mips/include/asm/global_data.h
+@@ -44,6 +44,7 @@ typedef	struct	global_data {
+ 	unsigned long	per_clk;	/* Peripheral bus clock */
+ 	unsigned long	mem_clk;	/* Memory bus clock */
+ 	unsigned long	dev_clk;	/* Device clock */
++        unsigned long   fb_base;        /* base address of framebuffer */
+ 	/* "static data" needed by most of timer.c */
+ 	unsigned long	tbl;
+ 	unsigned long	lastinc;
+diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
+index 68287fb..13724a2 100644
+--- a/arch/mips/include/asm/jz4740.h
++++ b/arch/mips/include/asm/jz4740.h
+@@ -1312,5 +1312,95 @@ do { 								\
+  	while (REG_MSC_STAT & MSC_STAT_IS_RESETTING);		\
+ } while (0)
+ 
++/*************************************************************************
++ * LCD (LCD Controller)
++ *************************************************************************/
++#define REG32(addr)	*((volatile u32 *)(addr))
++
++#define	CPM_BASE	0xB0000000
++#define CPM_CPCCR	(CPM_BASE+0x00)
++#define REG_CPM_CPCCR	REG32(CPM_CPCCR)
++
++#define	LCD_BASE	0xB3050000
++#define LCD_CFG		(LCD_BASE + 0x00) /* LCD Configure Register */
++#define LCD_VSYNC	(LCD_BASE + 0x04) /* Vertical Synchronize Register */
++#define LCD_HSYNC	(LCD_BASE + 0x08) /* Horizontal Synchronize Register */
++#define LCD_VAT		(LCD_BASE + 0x0c) /* Virtual Area Setting Register */
++#define LCD_DAH		(LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
++#define LCD_DAV		(LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
++#define LCD_PS		(LCD_BASE + 0x18) /* PS Signal Setting */
++#define LCD_CLS		(LCD_BASE + 0x1c) /* CLS Signal Setting */
++#define LCD_SPL		(LCD_BASE + 0x20) /* SPL Signal Setting */
++#define LCD_REV		(LCD_BASE + 0x24) /* REV Signal Setting */
++#define LCD_CTRL	(LCD_BASE + 0x30) /* LCD Control Register */
++#define LCD_STATE	(LCD_BASE + 0x34) /* LCD Status Register */
++#define LCD_IID		(LCD_BASE + 0x38) /* Interrupt ID Register */
++#define LCD_DA0		(LCD_BASE + 0x40) /* Descriptor Address Register 0 */
++#define LCD_SA0		(LCD_BASE + 0x44) /* Source Address Register 0 */
++#define LCD_FID0	(LCD_BASE + 0x48) /* Frame ID Register 0 */
++#define LCD_CMD0	(LCD_BASE + 0x4c) /* DMA Command Register 0 */
++#define LCD_DA1		(LCD_BASE + 0x50) /* Descriptor Address Register 1 */
++#define LCD_SA1		(LCD_BASE + 0x54) /* Source Address Register 1 */
++#define LCD_FID1	(LCD_BASE + 0x58) /* Frame ID Register 1 */
++#define LCD_CMD1	(LCD_BASE + 0x5c) /* DMA Command Register 1 */
++
++#define REG_LCD_CFG	REG32(LCD_CFG)
++#define REG_LCD_VSYNC	REG32(LCD_VSYNC)
++#define REG_LCD_HSYNC	REG32(LCD_HSYNC)
++#define REG_LCD_VAT	REG32(LCD_VAT)
++#define REG_LCD_DAH	REG32(LCD_DAH)
++#define REG_LCD_DAV	REG32(LCD_DAV)
++#define REG_LCD_PS	REG32(LCD_PS)
++#define REG_LCD_CLS	REG32(LCD_CLS)
++#define REG_LCD_SPL	REG32(LCD_SPL)
++#define REG_LCD_REV	REG32(LCD_REV)
++#define REG_LCD_CTRL	REG32(LCD_CTRL)
++#define REG_LCD_STATE	REG32(LCD_STATE)
++#define REG_LCD_IID	REG32(LCD_IID)
++#define REG_LCD_DA0	REG32(LCD_DA0)
++#define REG_LCD_SA0	REG32(LCD_SA0)
++#define REG_LCD_FID0	REG32(LCD_FID0)
++#define REG_LCD_CMD0	REG32(LCD_CMD0)
++#define REG_LCD_DA1	REG32(LCD_DA1)
++#define REG_LCD_SA1	REG32(LCD_SA1)
++#define REG_LCD_FID1	REG32(LCD_FID1)
++#define REG_LCD_CMD1	REG32(LCD_CMD1)
++
++#define LCD_CTRL_BPP_BIT	0  /* Bits Per Pixel */
++#define LCD_CTRL_BPP_MASK	(0x07 << LCD_CTRL_BPP_BIT)
++  #define LCD_CTRL_BPP_1	(0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
++  #define LCD_CTRL_BPP_2	(1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
++  #define LCD_CTRL_BPP_4	(2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
++  #define LCD_CTRL_BPP_8	(3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
++  #define LCD_CTRL_BPP_16	(4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
++  #define LCD_CTRL_BPP_18_24	(5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
++
++#define LCD_CTRL_BST_BIT	28  /* Burst Length Selection */
++#define LCD_CTRL_BST_MASK	(0x03 << LCD_CTRL_BST_BIT)
++  #define LCD_CTRL_BST_4	(0 << LCD_CTRL_BST_BIT) /* 4-word */
++  #define LCD_CTRL_BST_8	(1 << LCD_CTRL_BST_BIT) /* 8-word */
++  #define LCD_CTRL_BST_16	(2 << LCD_CTRL_BST_BIT) /* 16-word */
++#define LCD_CTRL_RGB565		(0 << 27) /* RGB565 mode */
++#define LCD_CTRL_RGB555		(1 << 27) /* RGB555 mode */
++#define LCD_CTRL_OFUP		(1 << 26) /* Output FIFO underrun protection enable */
++#define LCD_CTRL_FRC_BIT	24  /* STN FRC Algorithm Selection */
++#define LCD_CTRL_FRC_MASK	(0x03 << LCD_CTRL_FRC_BIT)
++  #define LCD_CTRL_FRC_16	(0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
++  #define LCD_CTRL_FRC_4	(1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
++  #define LCD_CTRL_FRC_2	(2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
++
++#define CPM_LPCDR	(CPM_BASE+0x64)
++#define CPM_CLKGR	(CPM_BASE+0x20)
++#define REG_CPM_LPCDR	REG32(CPM_LPCDR)
++#define REG_CPM_CLKGR	REG32(CPM_CLKGR)
++
++#define __cpm_start_tcu()	(REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
++#define __cpm_stop_lcd()	(REG_CPM_CLKGR |= CPM_CLKGR_LCD)
++#define __cpm_set_pixdiv(v) \
++	(REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
++#define __cpm_set_ldiv(v) \
++	(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
++#define __cpm_start_lcd()	(REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
++
+ #endif	/* !__ASSEMBLY__ */
+ #endif	/* __JZ4740_H__ */
+diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
+index b14b33e..c2e64d9 100644
+--- a/arch/mips/lib/board.c
++++ b/arch/mips/lib/board.c
+@@ -172,6 +172,12 @@ void board_init_f(ulong bootflag)
+ 	addr &= ~(4096 - 1);
+ 	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+ 
++#ifdef CONFIG_LCD
++        /* reserve memory for LCD display (always full pages) */
++        addr = lcd_setmem (addr);
++        gd->fb_base = addr;
++#endif /* CONFIG_LCD */
++
+ 	/* Reserve memory for U-Boot code, data & bss
+ 	 * round down to next 16 kB limit
+ 	 */
+diff --git a/common/lcd.c b/common/lcd.c
+index b6be800..af1281a 100644
+--- a/common/lcd.c
++++ b/common/lcd.c
+@@ -263,6 +263,13 @@ static void lcd_drawchars(ushort x, ushort y, uchar *str, int count)
+ 						lcd_color_fg : lcd_color_bg;
+ 				bits <<= 1;
+ 			}
++#elif LCD_BPP == LCD_COLOR32
++                       uint *m = (uint *)d;
++                       for (c=0; c<32; ++c) {
++                               *m++ = (bits & 0x80) ?
++				       lcd_color_fg : lcd_color_bg;
++                               bits <<= 1;
++                       }
+ #endif
+ 		}
+ #if LCD_BPP == LCD_MONOCHROME
+@@ -509,7 +516,7 @@ static inline ushort *configuration_get_cmap(void)
+ 	return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]);
+ #elif defined(CONFIG_ATMEL_LCD)
+ 	return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
+-#elif !defined(CONFIG_ATMEL_HLCD) && !defined(CONFIG_EXYNOS_FB)
++#elif !defined(CONFIG_ATMEL_HLCD) && !defined(CONFIG_EXYNOS_FB) && !defined(CONFIG_VIDEO_GPM940B0)
+ 	return panel_info.cmap;
+ #else
+ #if defined(CONFIG_LCD_LOGO)
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index ebb6da8..03625bc 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -50,6 +50,7 @@ COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
+ COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
+ COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
+ COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
++COBJS-$(CONFIG_VIDEO_GPM940B0) += nanonote_gpm940b0.o
+ 
+ COBJS	:= $(sort $(COBJS-y))
+ SRCS	:= $(COBJS:.o=.c)
+diff --git a/drivers/video/nanonote_gpm940b0.c b/drivers/video/nanonote_gpm940b0.c
+new file mode 100644
+index 0000000..11efb72
+--- /dev/null
++++ b/drivers/video/nanonote_gpm940b0.c
+@@ -0,0 +1,400 @@
++/*
++ * JzRISC lcd controller
++ *
++ * Xiangfu Liu <xiangfu@sharism.cc>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <common.h>
++#include <lcd.h>
++
++#include <asm/io.h>               /* virt_to_phys() */
++#include <asm/jz4740.h>
++
++#include "nanonote_gpm940b0.h"
++
++#define align2(n) (n)=((((n)+1)>>1)<<1)
++#define align4(n) (n)=((((n)+3)>>2)<<2)
++#define align8(n) (n)=((((n)+7)>>3)<<3)
++
++struct jzfb_info {
++	unsigned int cfg;	/* panel mode and pin usage etc. */
++	unsigned int w;
++	unsigned int h;
++	unsigned int bpp;	/* bit per pixel */
++	unsigned int fclk;	/* frame clk */
++	unsigned int hsw;	/* hsync width, in pclk */
++	unsigned int vsw;	/* vsync width, in line count */
++	unsigned int elw;	/* end of line, in pclk */
++	unsigned int blw;	/* begin of line, in pclk */
++	unsigned int efw;	/* end of frame, in line count */
++	unsigned int bfw;	/* begin of frame, in line count */
++};
++
++static struct jzfb_info jzfb = {
++	MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
++	320, 240, 32, 70, 1, 1, 273, 140, 1, 20
++};
++
++vidinfo_t panel_info = {
++	320, 240, LCD_BPP,
++};
++
++void *lcd_base;
++void *lcd_console_address;
++int lcd_line_length;
++int lcd_color_fg;
++int lcd_color_bg;
++short console_col;
++short console_row;
++
++static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
++{
++	u_long palette_mem_size;
++	struct jz_fb_info *fbi = &vid->jz_fb;
++	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
++
++	fbi->screen = (u_long)lcdbase;
++	fbi->palette_size = 256;
++	palette_mem_size = fbi->palette_size * sizeof(u16);
++
++	debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
++	/* locate palette and descs at end of page following fb */
++	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
++
++	return 0;
++}
++
++static void jz_lcd_desc_init(vidinfo_t *vid)
++{
++	struct jz_fb_info * fbi;
++	fbi = &vid->jz_fb;
++	fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
++	fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
++	fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
++
++	#define BYTES_PER_PANEL	 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
++
++	/* populate descriptors */
++	fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
++	fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
++	fbi->dmadesc_fblow->fidr  = 0;
++	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
++
++	fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
++
++	fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
++	fbi->dmadesc_fbhigh->fidr = 0;
++	fbi->dmadesc_fbhigh->ldcmd =  BYTES_PER_PANEL / 4; /* length in word */
++
++	fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
++	fbi->dmadesc_palette->fidr  = 0;
++	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
++
++	if(NBITS(vid->vl_bpix) < 12) {
++		/* assume any mode with <12 bpp is palette driven */
++		fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
++		fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
++		/* flips back and forth between pal and fbhigh */
++		fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
++	} else {
++		/* palette shouldn't be loaded in true-color mode */
++		fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
++		fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
++	}
++}
++
++static int  jz_lcd_hw_init(vidinfo_t *vid)
++{
++	struct jz_fb_info *fbi = &vid->jz_fb;
++	unsigned int val = 0;
++	unsigned int pclk;
++	unsigned int stnH;
++	int pll_div;
++
++	/* Setting Control register */
++	switch (jzfb.bpp) {
++	case 1:
++		val |= LCD_CTRL_BPP_1;
++		break;
++	case 2:
++		val |= LCD_CTRL_BPP_2;
++		break;
++	case 4:
++		val |= LCD_CTRL_BPP_4;
++		break;
++	case 8:
++		val |= LCD_CTRL_BPP_8;
++		break;
++	case 15:
++		val |= LCD_CTRL_RGB555;
++	case 16:
++		val |= LCD_CTRL_BPP_16;
++		break;
++	case 17 ... 32:
++		val |= LCD_CTRL_BPP_18_24;	/* target is 4bytes/pixel */
++		break;
++
++	default:
++		printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
++		val |= LCD_CTRL_BPP_16;
++		break;
++	}
++
++	switch (jzfb.cfg & MODE_MASK) {
++	case MODE_STN_MONO_DUAL:
++	case MODE_STN_COLOR_DUAL:
++	case MODE_STN_MONO_SINGLE:
++	case MODE_STN_COLOR_SINGLE:
++		switch (jzfb.bpp) {
++		case 1:
++			/* val |= LCD_CTRL_PEDN; */
++		case 2:
++			val |= LCD_CTRL_FRC_2;
++			break;
++		case 4:
++			val |= LCD_CTRL_FRC_4;
++			break;
++		case 8:
++		default:
++			val |= LCD_CTRL_FRC_16;
++			break;
++		}
++		break;
++	}
++
++	val |= LCD_CTRL_BST_16;		/* Burst Length is 16WORD=64Byte */
++	val |= LCD_CTRL_OFUP;		/* OutFIFO underrun protect */
++
++	switch (jzfb.cfg & MODE_MASK) {
++	case MODE_STN_MONO_DUAL:
++	case MODE_STN_COLOR_DUAL:
++	case MODE_STN_MONO_SINGLE:
++	case MODE_STN_COLOR_SINGLE:
++		switch (jzfb.cfg & STN_DAT_PINMASK) {
++		case STN_DAT_PIN1:
++			/* Do not adjust the hori-param value. */
++			break;
++		case STN_DAT_PIN2:
++			align2(jzfb.hsw);
++			align2(jzfb.elw);
++			align2(jzfb.blw);
++			break;
++		case STN_DAT_PIN4:
++			align4(jzfb.hsw);
++			align4(jzfb.elw);
++			align4(jzfb.blw);
++			break;
++		case STN_DAT_PIN8:
++			align8(jzfb.hsw);
++			align8(jzfb.elw);
++			align8(jzfb.blw);
++			break;
++		}
++		break;
++	}
++
++	REG_LCD_CTRL = val;
++
++	switch (jzfb.cfg & MODE_MASK) {
++	case MODE_STN_MONO_DUAL:
++	case MODE_STN_COLOR_DUAL:
++	case MODE_STN_MONO_SINGLE:
++	case MODE_STN_COLOR_SINGLE:
++		if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
++		    ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
++			stnH = jzfb.h >> 1;
++		else
++			stnH = jzfb.h;
++
++		REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
++		REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
++
++		/* Screen setting */
++		REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
++		REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
++		REG_LCD_DAV = (0 << 16) | (stnH);
++
++		/* AC BIAs signal */
++		REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
++
++		break;
++
++	case MODE_TFT_GEN:
++	case MODE_TFT_SHARP:
++	case MODE_TFT_CASIO:
++	case MODE_TFT_SAMSUNG:
++	case MODE_8BIT_SERIAL_TFT:
++	case MODE_TFT_18BIT:
++		REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
++		REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
++		REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
++		REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
++		REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
++			| (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
++		break;
++	}
++
++	switch (jzfb.cfg & MODE_MASK) {
++	case MODE_TFT_SAMSUNG:
++	{
++		unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
++		unsigned int rev_s, rev_e, inv_s, inv_e;
++
++		pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
++			(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
++
++		total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
++		tp_s = jzfb.blw + jzfb.w + 1;
++		tp_e = tp_s + 1;
++		ckv_s = tp_s - pclk/(1000000000/4100);
++		ckv_e = tp_s + total;
++		rev_s = tp_s - 11;	/* -11.5 clk */
++		rev_e = rev_s + total;
++		inv_s = tp_s;
++		inv_e = inv_s + total;
++		REG_LCD_CLS = (tp_s << 16) | tp_e;
++		REG_LCD_PS = (ckv_s << 16) | ckv_e;
++		REG_LCD_SPL = (rev_s << 16) | rev_e;
++		REG_LCD_REV = (inv_s << 16) | inv_e;
++		jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
++		break;
++	}
++	case MODE_TFT_SHARP:
++	{
++		unsigned int total, cls_s, cls_e, ps_s, ps_e;
++		unsigned int spl_s, spl_e, rev_s, rev_e;
++		total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
++		spl_s = 1;
++		spl_e = spl_s + 1;
++		cls_s = 0;
++		cls_e = total - 60;	/* > 4us (pclk = 80ns) */
++		ps_s = cls_s;
++		ps_e = cls_e;
++		rev_s = total - 40;	/* > 3us (pclk = 80ns) */
++		rev_e = rev_s + total;
++		jzfb.cfg |= STFT_PSHI; 
++		REG_LCD_SPL = (spl_s << 16) | spl_e;
++		REG_LCD_CLS = (cls_s << 16) | cls_e;
++		REG_LCD_PS = (ps_s << 16) | ps_e;
++		REG_LCD_REV = (rev_s << 16) | rev_e;
++		break;
++	}
++	case MODE_TFT_CASIO:
++		break;
++	}
++
++	/* Configure the LCD panel */
++	REG_LCD_CFG = jzfb.cfg;
++
++	/* Timing setting */
++	__cpm_stop_lcd();
++
++	val = jzfb.fclk; /* frame clk */
++	if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
++		pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
++			(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
++	} else {
++		/* serial mode: Hsync period = 3*Width_Pixel */
++		pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
++			(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
++	}
++
++	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
++	    ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
++		pclk = (pclk * 3);
++
++	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
++	    ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
++	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
++	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
++		pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
++
++	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
++	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
++		pclk >>= 1;
++
++	pll_div = (REG_CPM_CPCCR & CPM_CPCCR_PCS); /* clock source,0:pllout/2 1: pllout */
++	pll_div = pll_div ? 1 : 2;
++	val = (__cpm_get_pllout() / pll_div) / pclk;
++	val--;
++	if (val > 0x1ff) {
++		printf("CPM_LPCDR too large, set it to 0x1ff\n");
++		val = 0x1ff;
++	}
++	__cpm_set_pixdiv(val);
++
++	val = pclk * 3 ;	/* LCDClock > 2.5*Pixclock */
++	if (val > 150000000) {
++		printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
++		printf("Change LCDClock to 150MHz\n");
++		val = 150000000;
++	}
++	val = (__cpm_get_pllout() / pll_div) / val;
++	val--;
++	if (val > 0x1f) {
++		printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
++		val = 0x1f;
++	}
++	__cpm_set_ldiv( val );
++	REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
++
++	__cpm_start_lcd();
++	udelay(1000);
++
++	REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
++
++	if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
++	    ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
++		REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
++
++	return 0;
++}
++
++void lcd_ctrl_init (void *lcdbase)
++{
++	__lcd_display_pin_init();
++	__lcd_display_on() ;
++
++	jz_lcd_init_mem(lcdbase, &panel_info);
++	jz_lcd_desc_init(&panel_info);
++	jz_lcd_hw_init(&panel_info);
++
++}
++
++/*
++ * Before enabled lcd controller, lcd registers should be configured correctly.
++ */
++void lcd_enable (void)
++{
++	REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
++	REG_LCD_CTRL |= 1<<3;    /* LCDCTRL.ENA*/
++}
++
++void lcd_disable (void)
++{
++	REG_LCD_CTRL |= (1<<4);
++}
++
++void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
++{
++}
++
++void lcd_initcolregs (void)
++{
++}
+diff --git a/drivers/video/nanonote_gpm940b0.h b/drivers/video/nanonote_gpm940b0.h
+new file mode 100644
+index 0000000..efe491e
+--- /dev/null
++++ b/drivers/video/nanonote_gpm940b0.h
+@@ -0,0 +1,135 @@
++/*
++ * JzRISC lcd controller
++ *
++ * Xiangfu Liu <xiangfu@sharism.cc>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __QI_LB60_GPM940B0_H__
++#define __QI_LB60_GPM940B0_H__
++
++struct lcd_desc{
++	unsigned int next_desc; /* LCDDAx */
++	unsigned int databuf;   /* LCDSAx */
++	unsigned int frame_id;  /* LCDFIDx */ 
++	unsigned int cmd;       /* LCDCMDx */
++};
++
++#define MODE_MASK		0x0f
++#define MODE_TFT_GEN		0x00
++#define MODE_TFT_SHARP		0x01
++#define MODE_TFT_CASIO		0x02
++#define MODE_TFT_SAMSUNG	0x03
++#define MODE_CCIR656_NONINT	0x04
++#define MODE_CCIR656_INT	0x05
++#define MODE_STN_COLOR_SINGLE	0x08
++#define MODE_STN_MONO_SINGLE	0x09
++#define MODE_STN_COLOR_DUAL	0x0a
++#define MODE_STN_MONO_DUAL	0x0b
++#define MODE_8BIT_SERIAL_TFT    0x0c
++
++#define MODE_TFT_18BIT          (1<<7)
++
++#define STN_DAT_PIN1	(0x00 << 4)
++#define STN_DAT_PIN2	(0x01 << 4)
++#define STN_DAT_PIN4	(0x02 << 4)
++#define STN_DAT_PIN8	(0x03 << 4)
++#define STN_DAT_PINMASK	STN_DAT_PIN8
++
++#define STFT_PSHI	(1 << 15)
++#define STFT_CLSHI	(1 << 14)
++#define STFT_SPLHI	(1 << 13)
++#define STFT_REVHI	(1 << 12)
++
++#define SYNC_MASTER	(0 << 16)
++#define SYNC_SLAVE	(1 << 16)
++
++#define DE_P		(0 << 9)
++#define DE_N		(1 << 9)
++
++#define PCLK_P		(0 << 10)
++#define PCLK_N		(1 << 10)
++
++#define HSYNC_P		(0 << 11)
++#define HSYNC_N		(1 << 11)
++
++#define VSYNC_P		(0 << 8)
++#define VSYNC_N		(1 << 8)
++
++#define DATA_NORMAL	(0 << 17)
++#define DATA_INVERSE	(1 << 17)
++
++
++/* Jz LCDFB supported I/O controls. */
++#define FBIOSETBACKLIGHT	0x4688
++#define FBIODISPON		0x4689
++#define FBIODISPOFF		0x468a
++#define FBIORESET		0x468b
++#define FBIOPRINT_REG		0x468c
++
++/*
++ * LCD panel specific definition
++ */
++#define MODE	(0xc9)		/* 8bit serial RGB */
++
++#define __spi_write_reg1(reg, val)		\
++do {						\
++	unsigned char no;			\
++	unsigned short value;			\
++	unsigned char a=reg;			\
++	unsigned char b=val;			\
++	__gpio_set_pin(SPEN);			\
++	__gpio_set_pin(SPCK);			\
++	__gpio_clear_pin(SPDA);			\
++	__gpio_clear_pin(SPEN);			\
++	value=((a<<8)|(b&0xFF));		\
++	for(no=0;no<16;no++)			\
++	{					\
++		__gpio_clear_pin(SPCK);		\
++		if((value&0x8000)==0x8000)	\
++			__gpio_set_pin(SPDA);	\
++		else				\
++			__gpio_clear_pin(SPDA);	\
++		__gpio_set_pin(SPCK);		\
++		value=(value<<1);		\
++	}					\
++	__gpio_set_pin(SPEN);			\
++} while (0)
++
++#define __lcd_display_pin_init()		\
++do {						\
++	__cpm_start_tcu();			\
++	__gpio_as_output(SPEN); /* use SPDA */	\
++	__gpio_as_output(SPCK); /* use SPCK */	\
++	__gpio_as_output(SPDA); /* use SPDA */	\
++} while (0)
++
++#define __lcd_display_on()			\
++do {						\
++	__spi_write_reg1(0x05, 0x1e);		\
++	__spi_write_reg1(0x05, 0x5e);		\
++	__spi_write_reg1(0x07, 0x8d);		\
++	__spi_write_reg1(0x13, 0x01);		\
++	__spi_write_reg1(0x05, 0x5f);		\
++} while (0)
++
++#define __lcd_display_off()			\
++do {						\
++	__spi_write_reg1(0x05, 0x5e);		\
++} while (0)
++
++#endif /* __QI_LB60_GPM940B0_H__ */
+diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
+index 52b370c..d3e78ad 100644
+--- a/include/configs/qi_lb60.h
++++ b/include/configs/qi_lb60.h
+@@ -32,6 +32,13 @@
+  * Miscellaneous configurable options
+  */
+ #define CONFIG_NANONOTE
++
++#define CONFIG_LCD
++#define CONFIG_SYS_WHITE_ON_BLACK
++#define LCD_BPP			LCD_COLOR32
++#define CONFIG_VIDEO_GPM940B0
++
++
+ #define CONFIG_JZ4740_MMC
+ #define CONFIG_MMC      	1
+ #define CONFIG_FAT      	1
+diff --git a/include/lcd.h b/include/lcd.h
+index 42070d7..6de5482 100644
+--- a/include/lcd.h
++++ b/include/lcd.h
+@@ -263,8 +263,44 @@ typedef struct vidinfo {
+ 
+ void init_panel_info(vidinfo_t *vid);
+ 
+-#else
++#elif defined(CONFIG_JZSOC)
++/*
++ * LCD controller stucture for JZSOC: JZ4740
++ */
++struct jz_fb_dma_descriptor {
++       u_long  fdadr;          /* Frame descriptor address register */
++       u_long  fsadr;          /* Frame source address register */
++       u_long  fidr;           /* Frame ID register */
++       u_long  ldcmd;          /* Command register */
++};
++
++/*
++ * Jz LCD info
++ */
++struct jz_fb_info {
++
++       u_long  fdadr0; /* physical address of frame/palette descriptor */
++       u_long  fdadr1; /* physical address of frame descriptor */
++
++       /* DMA descriptors */
++       struct  jz_fb_dma_descriptor *  dmadesc_fblow;
++       struct  jz_fb_dma_descriptor *  dmadesc_fbhigh;
++       struct  jz_fb_dma_descriptor *  dmadesc_palette;
++       u_long  screen;         /* address of frame buffer */
++       u_long  palette;        /* address of palette memory */
++       u_int   palette_size;
++};
++typedef struct vidinfo {
++       ushort  vl_col;         /* Number of columns (i.e. 640) */
++       ushort  vl_row;         /* Number of rows (i.e. 480) */
++       u_char  vl_bpix;        /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
++
++       struct jz_fb_info jz_fb;
++} vidinfo_t;
++
++extern vidinfo_t panel_info;
+ 
++#else
+ typedef struct vidinfo {
+ 	ushort	vl_col;		/* Number of columns (i.e. 160) */
+ 	ushort	vl_row;		/* Number of rows (i.e. 100) */
+@@ -318,6 +354,7 @@ void lcd_show_board_info(void);
+ #define LCD_COLOR4	2
+ #define LCD_COLOR8	3
+ #define LCD_COLOR16	4
++#define LCD_COLOR32	5
+ 
+ /*----------------------------------------------------------------------*/
+ #if defined(CONFIG_LCD_INFO_BELOW_LOGO)
+@@ -369,7 +406,7 @@ void lcd_show_board_info(void);
+ # define CONSOLE_COLOR_GREY	14
+ # define CONSOLE_COLOR_WHITE	15	/* Must remain last / highest	*/
+ 
+-#else
++#elif LCD_BPP == LCD_COLOR16
+ 
+ /*
+  * 16bpp color definitions
+@@ -377,6 +414,15 @@ void lcd_show_board_info(void);
+ # define CONSOLE_COLOR_BLACK	0x0000
+ # define CONSOLE_COLOR_WHITE	0xffff	/* Must remain last / highest	*/
+ 
++#elif LCD_BPP == LCD_COLOR32
++/*
++ * 18,24,32 bpp color definitions
++ */
++# define CONSOLE_COLOR_BLACK   0x00000000
++# define CONSOLE_COLOR_WHITE   0xffffffff /* Must remain last / highest */
++
++#else
++
+ #endif /* color definitions */
+ 
+ /************************************************************************/
+@@ -406,7 +452,7 @@ void lcd_show_board_info(void);
+ #if LCD_BPP == LCD_MONOCHROME
+ # define COLOR_MASK(c)		((c)	  | (c) << 1 | (c) << 2 | (c) << 3 | \
+ 				 (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
+-#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
++#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || (LCD_BPP == LCD_COLOR32)
+ # define COLOR_MASK(c)		(c)
+ #else
+ # error Unsupported LCD BPP.
+-- 
+1.7.9.5
+

package/boot/uboot-xburst/patches/0006-enable-silent-console.patch

@@ -0,0 +1,60 @@
+From 5eb4d4c598f2806bd1b3d1140e917bfead7851ad Mon Sep 17 00:00:00 2001
+From: Xiangfu <xiangfu@openmobilefree.net>
+Date: Wed, 10 Oct 2012 23:51:26 +0800
+Subject: [PATCH 6/6] enable silent console
+
+---
+ common/console.c          |   16 ++++++++++++++++
+ include/configs/qi_lb60.h |    2 ++
+ 2 files changed, 18 insertions(+)
+
+diff --git a/common/console.c b/common/console.c
+index 1177f7d..e8a2078 100644
+--- a/common/console.c
++++ b/common/console.c
+@@ -685,6 +685,14 @@ done:
+ 
+ 	gd->flags |= GD_FLG_DEVINIT;	/* device initialization completed */
+ 
++#ifdef CONFIG_SILENT_CONSOLE
++	/* Check one more time the contents of the silent environment
++	 * variable, because if the environment is loaded from NAND it was
++	 * not available when console_init_f() was called */
++	if (getenv("silent") != NULL)
++		gd->flags |= GD_FLG_SILENT;
++#endif
++
+ 	stdio_print_current_devices();
+ 
+ #ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+@@ -760,6 +768,14 @@ int console_init_r(void)
+ 
+ 	gd->flags |= GD_FLG_DEVINIT;	/* device initialization completed */
+ 
++#ifdef CONFIG_SILENT_CONSOLE
++	/* Check one more time the contents of the silent environment
++	 * variable, because if the environment is loaded from NAND it was
++	 * not available when console_init_f() was called */
++	if (getenv("silent") != NULL)
++		gd->flags |= GD_FLG_SILENT;
++#endif
++
+ 	stdio_print_current_devices();
+ 
+ 	/* Setting environment variables */
+diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
+index d3e78ad..a3534ff 100644
+--- a/include/configs/qi_lb60.h
++++ b/include/configs/qi_lb60.h
+@@ -102,6 +102,8 @@
+ #define CONFIG_SYS_NO_FLASH
+ #define CONFIG_SYS_FLASH_BASE	0 /* init flash_base as 0 */
+ 
++#define CONFIG_SILENT_CONSOLE		1	/* Enable silent console */
++
+ /*
+  * Command line configuration
+  */
+-- 
+1.7.9.5
+

package/boot/uboot-xburst/patches/005-i2c.patch

@@ -1,13 +0,0 @@
-diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
-index ef32f13..4e234b4 100644
---- a/drivers/i2c/Makefile
-+++ b/drivers/i2c/Makefile
-@@ -36,6 +36,7 @@ COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
- COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
- COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
- COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
-+COBJS-$(CONFIG_JZSOC_I2C) += jz_i2c.o
- 
- COBJS	:= $(COBJS-y)
- SRCS	:= $(COBJS:.o=.c)
-

package/boot/uboot-xburst/patches/009-n516.patch

@@ -1,23 +0,0 @@
-diff --git a/Makefile b/Makefile
-index ed848f5..04cd32e 100644
---- a/Makefile
-+++ b/Makefile
-@@ -3448,6 +3448,18 @@ pavo_nand_config	:	unconfig
- 	@echo "TEXT_BASE = 0x80100000" > $(obj)board/qi_lb60/config.tmp
- 	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- 
-+n516_config		: 	unconfig
-+	@ >include/config.h
-+	@echo "#define CONFIG_N516 1" >>include/config.h
-+	@./mkconfig -a n516 mips mips n516
-+
-+n516_nand_config	:	unconfig
-+	@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
-+	@echo "Compile NAND boot image for n516"
-+	@./mkconfig -a n516 mips mips n516
-+	@echo "TEXT_BASE = 0x80100000" > $(obj)board/n516/config.tmp
-+	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
-+
- #########################################################################
- ## MIPS64 5Kc
- #########################################################################

package/boot/uboot-xburst/patches/010-sakc.patch

@@ -1,32 +0,0 @@
-diff --git a/Makefile b/Makefile
-index a318eb4..7d14b8b 100644
---- a/Makefile
-+++ b/Makefile
-@@ -3448,6 +3448,13 @@ qi_lb60_config	: unconfig
- 	@echo "TEXT_BASE = 0x80100000" > $(obj)board/n516/config.tmp
- 	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- 
-+sakc_config	: unconfig
-+	@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
-+	@echo "Compile NAND boot image for SAKC"
-+	@$(MKCONFIG) -a sakc mips mips sakc
-+	@echo "TEXT_BASE = 0x80100000" > $(obj)board/sakc/config.tmp
-+	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
-+
- #########################################################################
- ## MIPS64 5Kc
- #########################################################################
-diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile
-index 33afb66..a177653 100644
---- a/cpu/mips/Makefile
-+++ b/cpu/mips/Makefile
-@@ -35,7 +35,7 @@ COBJS-$(CONFIG_PURPLE)	+= asc_serial.o
- COBJS-$(CONFIG_JZSOC) += jz_serial.o jz_i2c.o jz_mmc.o
- COBJS-$(CONFIG_JZ4740) += jz4740.o jz4740_nand.o
- COBJS-$(CONFIG_NANONOTE) += nanonote_gpm940b0.o
--
-+COBJS-$(CONFIG_SAKC) += nanonote_gpm940b0.o
- 
- SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
- OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-