mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 07:53:39 +03:00
Move SSB out of brcm47xx target into generic-2.6 target
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7844 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
6598291ff8
commit
5939035634
@ -217,55 +217,6 @@ Index: linux-2.6.22-rc5/drivers/ssb/driver_mipscore.c
|
|||||||
}
|
}
|
||||||
+
|
+
|
||||||
+EXPORT_SYMBOL(ssb_mips_irq);
|
+EXPORT_SYMBOL(ssb_mips_irq);
|
||||||
Index: linux-2.6.22-rc5/drivers/ssb/driver_pcicore.c
|
|
||||||
===================================================================
|
|
||||||
--- linux-2.6.22-rc5.orig/drivers/ssb/driver_pcicore.c 2007-06-10 16:44:31.000000000 +0100
|
|
||||||
+++ linux-2.6.22-rc5/drivers/ssb/driver_pcicore.c 2007-06-24 20:07:15.000000000 +0100
|
|
||||||
@@ -93,6 +93,9 @@
|
|
||||||
|
|
||||||
/* Enable PCI bridge BAR1 prefetch and burst */
|
|
||||||
pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
|
|
||||||
+
|
|
||||||
+ /* Make sure our latency is high enough to handle the devices behind us */
|
|
||||||
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
|
|
||||||
}
|
|
||||||
DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
|
|
||||||
|
|
||||||
@@ -110,7 +113,7 @@
|
|
||||||
|
|
||||||
if (unlikely(pc->cardbusmode && dev > 1))
|
|
||||||
goto out;
|
|
||||||
- if (bus == 0) {
|
|
||||||
+ if (bus == 0) {//FIXME busnumber ok?
|
|
||||||
/* Type 0 transaction */
|
|
||||||
if (unlikely(dev >= SSB_PCI_SLOT_MAX))
|
|
||||||
goto out;
|
|
||||||
@@ -224,7 +227,7 @@
|
|
||||||
val = *((const u32 *)buf);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
- writel(*((const u32 *)buf), mmio);
|
|
||||||
+ writel(val, mmio);
|
|
||||||
|
|
||||||
err = 0;
|
|
||||||
unmap:
|
|
||||||
@@ -307,6 +310,8 @@
|
|
||||||
udelay(150);
|
|
||||||
val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
|
|
||||||
pcicore_write32(pc, SSB_PCICORE_CTL, val);
|
|
||||||
+ val = SSB_PCICORE_ARBCTL_INTERN;
|
|
||||||
+ pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
|
|
||||||
udelay(1);
|
|
||||||
|
|
||||||
//TODO cardbus mode
|
|
||||||
@@ -336,6 +341,7 @@
|
|
||||||
* The following needs change, if we want to port hostmode
|
|
||||||
* to non-MIPS platform. */
|
|
||||||
set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
|
|
||||||
+ mdelay(300);
|
|
||||||
register_pci_controller(&ssb_pcicore_controller);
|
|
||||||
}
|
|
||||||
|
|
||||||
Index: linux-2.6.22-rc5/include/linux/ssb/ssb_driver_chipcommon.h
|
Index: linux-2.6.22-rc5/include/linux/ssb/ssb_driver_chipcommon.h
|
||||||
===================================================================
|
===================================================================
|
||||||
--- linux-2.6.22-rc5.orig/include/linux/ssb/ssb_driver_chipcommon.h 2007-06-10 16:44:47.000000000 +0100
|
--- linux-2.6.22-rc5.orig/include/linux/ssb/ssb_driver_chipcommon.h 2007-06-10 16:44:47.000000000 +0100
|
@ -0,0 +1,49 @@
|
|||||||
|
Index: linux-2.6.22-rc5/drivers/ssb/driver_pcicore.c
|
||||||
|
===================================================================
|
||||||
|
--- linux-2.6.22-rc5.orig/drivers/ssb/driver_pcicore.c 2007-06-10 16:44:31.000000000 +0100
|
||||||
|
+++ linux-2.6.22-rc5/drivers/ssb/driver_pcicore.c 2007-06-24 20:07:15.000000000 +0100
|
||||||
|
@@ -93,6 +93,9 @@
|
||||||
|
|
||||||
|
/* Enable PCI bridge BAR1 prefetch and burst */
|
||||||
|
pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
|
||||||
|
+
|
||||||
|
+ /* Make sure our latency is high enough to handle the devices behind us */
|
||||||
|
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
|
||||||
|
}
|
||||||
|
DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
|
||||||
|
|
||||||
|
@@ -110,7 +113,7 @@
|
||||||
|
|
||||||
|
if (unlikely(pc->cardbusmode && dev > 1))
|
||||||
|
goto out;
|
||||||
|
- if (bus == 0) {
|
||||||
|
+ if (bus == 0) {//FIXME busnumber ok?
|
||||||
|
/* Type 0 transaction */
|
||||||
|
if (unlikely(dev >= SSB_PCI_SLOT_MAX))
|
||||||
|
goto out;
|
||||||
|
@@ -224,7 +227,7 @@
|
||||||
|
val = *((const u32 *)buf);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
- writel(*((const u32 *)buf), mmio);
|
||||||
|
+ writel(val, mmio);
|
||||||
|
|
||||||
|
err = 0;
|
||||||
|
unmap:
|
||||||
|
@@ -307,6 +310,8 @@
|
||||||
|
udelay(150);
|
||||||
|
val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
|
||||||
|
pcicore_write32(pc, SSB_PCICORE_CTL, val);
|
||||||
|
+ val = SSB_PCICORE_ARBCTL_INTERN;
|
||||||
|
+ pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
|
||||||
|
udelay(1);
|
||||||
|
|
||||||
|
//TODO cardbus mode
|
||||||
|
@@ -336,6 +341,7 @@
|
||||||
|
* The following needs change, if we want to port hostmode
|
||||||
|
* to non-MIPS platform. */
|
||||||
|
set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
|
||||||
|
+ mdelay(300);
|
||||||
|
register_pci_controller(&ssb_pcicore_controller);
|
||||||
|
}
|
||||||
|
|
Loading…
Reference in New Issue
Block a user