qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00
Code Activity

Fix memory detection and hcd compilation, thanks Gabor ! (closes #1813)

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7631 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian
2007-06-14 11:59:31 +00:00
parent eb12a445c6
commit 5da973430e
5 changed files with 153 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h
View File

@@ -50,6 +50,8 @@ extern unsigned int adm5120_package;
#define ADM5120_PACKAGE_PQFP 0
#define ADM5120_PACKAGE_BGA 1
extern unsigned long adm5120_memsize;
extern void adm5120_info_init(void);
static inline int adm5120_package_pqfp(void)

13
target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h
View File

@@ -85,6 +85,19 @@
#define CODE_PK_BGA 0 /* BGA package */
#define CODE_PK_PQFP 1 /* PQFP package */
/* MEMCTRL register bits */
#define MEMCTRL_SDRS_MASK BITMASK(3) /* SDRAM bank size */
#define MEMCTRL_SDRS_4M 0x01
#define MEMCTRL_SDRS_8M 0x02
#define MEMCTRL_SDRS_16M 0x03
#define MEMCTRL_SDRS_64M 0x04
#define MEMCTRL_SDRS_128M 0x05
#define MEMCTRL_SDR1_ENABLE ONEBIT(5) /* enable SDRAM bank 1 */
#define MEMCTRL_SR0S_MASK BITMASK(3) /* SRAM0 size */
#define MEMCTRL_SR0S_SHIFT 8
#define MEMCTRL_SR1S_MASK BITMAKS(3) /* SRAM1 size */
#define MEMCTRL_SR1S_SHIFT 16
/* GPIO_CONF0 register bits */
#define GPIO_CONF0_MASK BITMASK(8)
#define GPIO_CONF0_IM_SHIFT 0