mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-29 11:44:04 +02:00
update bcm4710 cache fixes for linux 2.6.16
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@3440 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
5427093f77
commit
5f6ee8dd6c
@ -1,6 +1,6 @@
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diff -urN linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
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diff -urN linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
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--- linux.old/arch/mips/kernel/genex.S 2005-12-04 06:10:42.000000000 +0100
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--- linux.old/arch/mips/kernel/genex.S 2006-03-20 06:53:29.000000000 +0100
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+++ linux.dev/arch/mips/kernel/genex.S 2005-12-18 05:30:48.564937750 +0100
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+++ linux.dev/arch/mips/kernel/genex.S 2006-03-21 12:19:26.000000000 +0100
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@@ -72,6 +72,10 @@
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@@ -72,6 +72,10 @@
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.set push
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.set push
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.set mips3
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.set mips3
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@ -13,8 +13,8 @@ diff -urN linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
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li k0, 31<<2
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li k0, 31<<2
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andi k1, k1, 0x7c
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andi k1, k1, 0x7c
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diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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--- linux.old/arch/mips/mm/c-r4k.c 2005-12-04 06:10:42.000000000 +0100
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--- linux.old/arch/mips/mm/c-r4k.c 2006-03-20 06:53:29.000000000 +0100
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-12-18 06:08:19.112437750 +0100
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+++ linux.dev/arch/mips/mm/c-r4k.c 2006-03-21 12:19:26.000000000 +0100
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@@ -14,6 +14,12 @@
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@@ -14,6 +14,12 @@
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#include <linux/mm.h>
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#include <linux/mm.h>
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#include <linux/bitops.h>
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#include <linux/bitops.h>
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@ -71,48 +71,16 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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r4k_blast_dcache = blast_dcache16;
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r4k_blast_dcache = blast_dcache16;
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else if (dc_lsize == 32)
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else if (dc_lsize == 32)
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r4k_blast_dcache = blast_dcache32;
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r4k_blast_dcache = blast_dcache32;
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@@ -486,6 +501,9 @@
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@@ -660,6 +675,8 @@
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addr = start & ~(dc_lsize - 1);
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aend = (end - 1) & ~(dc_lsize - 1);
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(aend);
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+
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while (1) {
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/* Hit_Writeback_Inv_D */
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protected_writeback_dcache_line(addr);
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@@ -657,6 +675,10 @@
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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+
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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+
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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@@ -702,6 +724,10 @@
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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+
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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+
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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@@ -727,6 +753,8 @@
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unsigned long addr = (unsigned long) arg;
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unsigned long addr = (unsigned long) arg;
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R4600_HIT_CACHEOP_WAR_IMPL;
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R4600_HIT_CACHEOP_WAR_IMPL;
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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if (!cpu_icache_snoops_remote_store)
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if (!cpu_icache_snoops_remote_store && scache_size)
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protected_writeback_scache_line(addr & ~(sc_lsize - 1));
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protected_writeback_scache_line(addr & ~(sc_lsize - 1));
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@@ -1202,6 +1230,16 @@
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@@ -1136,6 +1153,16 @@
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static inline void coherency_setup(void)
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static inline void coherency_setup(void)
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{
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{
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change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
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change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
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@ -129,7 +97,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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/*
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/*
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* c0_status.cu=0 specifies that updates by the sc instruction use
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* c0_status.cu=0 specifies that updates by the sc instruction use
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@@ -1231,6 +1269,15 @@
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@@ -1165,6 +1192,15 @@
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/* Default cache error handler for R4000 and R5000 family */
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/* Default cache error handler for R4000 and R5000 family */
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set_uncached_handler (0x100, &except_vec2_generic, 0x80);
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set_uncached_handler (0x100, &except_vec2_generic, 0x80);
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@ -146,8 +114,8 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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probe_pcache();
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probe_pcache();
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setup_scache();
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setup_scache();
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diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
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diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
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--- linux.old/arch/mips/mm/tlbex.c 2005-12-15 12:57:27.945158000 +0100
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--- linux.old/arch/mips/mm/tlbex.c 2006-03-21 12:12:38.000000000 +0100
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+++ linux.dev/arch/mips/mm/tlbex.c 2005-12-18 06:06:17.916863500 +0100
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+++ linux.dev/arch/mips/mm/tlbex.c 2006-03-21 12:19:26.000000000 +0100
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@@ -28,6 +28,10 @@
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@@ -28,6 +28,10 @@
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/* #define DEBUG_TLB */
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/* #define DEBUG_TLB */
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@ -173,11 +141,11 @@ diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
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* create the plain linear handler
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* create the plain linear handler
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*/
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*/
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diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
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diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
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--- linux.old/include/asm-mips/r4kcache.h 2005-12-17 22:39:19.281320000 +0100
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--- linux.old/include/asm-mips/r4kcache.h 2006-03-20 06:53:29.000000000 +0100
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+++ linux.dev/include/asm-mips/r4kcache.h 2005-12-18 05:22:06.020280750 +0100
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+++ linux.dev/include/asm-mips/r4kcache.h 2006-03-21 18:40:32.000000000 +0100
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@@ -15,6 +15,18 @@
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@@ -16,6 +16,18 @@
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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#include <asm/cacheops.h>
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#include <asm/cpu-features.h>
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+#ifdef CONFIG_BCM4710
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+#ifdef CONFIG_BCM4710
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+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
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+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
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@ -194,7 +162,7 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
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/*
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/*
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* This macro return a properly sign-extended address suitable as base address
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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* for indexed cache operations. Two issues here:
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@@ -45,6 +57,7 @@
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@@ -46,6 +58,7 @@
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static inline void flush_dcache_line_indexed(unsigned long addr)
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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{
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@ -202,7 +170,7 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
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cache_op(Index_Writeback_Inv_D, addr);
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cache_op(Index_Writeback_Inv_D, addr);
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}
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}
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@@ -60,11 +73,13 @@
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@@ -61,11 +74,13 @@
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static inline void flush_dcache_line(unsigned long addr)
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static inline void flush_dcache_line(unsigned long addr)
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{
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{
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@ -216,15 +184,23 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
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cache_op(Hit_Invalidate_D, addr);
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cache_op(Hit_Invalidate_D, addr);
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}
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}
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@@ -104,6 +119,7 @@
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@@ -97,6 +112,7 @@
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*/
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static inline void protected_flush_icache_line(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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protected_cache_op(Hit_Invalidate_I, addr);
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}
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@@ -108,6 +124,7 @@
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*/
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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{
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+ BCM4710_DUMMY_RREG();
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+ BCM4710_DUMMY_RREG();
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__asm__ __volatile__(
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protected_cache_op(Hit_Writeback_Inv_D, addr);
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" .set push \n"
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}
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" .set noreorder \n"
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@@ -166,6 +182,49 @@
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@@ -228,8 +245,52 @@
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: "r" (base), \
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: "r" (base), \
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"i" (op));
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"i" (op));
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@ -271,38 +247,93 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca
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+ }
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+ }
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+}
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+}
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+
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+
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static inline void blast_dcache16(void)
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+
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{
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/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
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unsigned long start = INDEX_BASE;
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-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
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@@ -213,7 +272,8 @@
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+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
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unsigned long ws_end = current_cpu_data.icache.ways <<
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static inline void blast_##pfx##cache##lsize(void) \
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current_cpu_data.icache.waybit;
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{ \
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unsigned long ws, addr;
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unsigned long start = INDEX_BASE; \
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-
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@@ -239,6 +300,7 @@
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+
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current_cpu_data.desc.waybit; \
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+ BCM4710_FILL_TLB(start);
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unsigned long ws, addr; \
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for (ws = 0; ws < ws_end; ws += ws_inc)
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\
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for (addr = start; addr < end; addr += 0x200)
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+ war \
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cache16_unroll32(addr|ws,Index_Invalidate_I);
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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@@ -357,6 +417,7 @@
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for (addr = start; addr < end; addr += lsize * 32) \
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current_cpu_data.icache.waybit;
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cache##lsize##_unroll32(addr|ws,indexop); \
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unsigned long ws, addr;
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@@ -249,6 +311,7 @@
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unsigned long start = page; \
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unsigned long end = page + PAGE_SIZE; \
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\
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+ war \
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do { \
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cache##lsize##_unroll32(start,hitop); \
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start += lsize * 32; \
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@@ -265,29 +328,31 @@
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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+ war \
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws,indexop); \
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}
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+ BCM4710_FILL_TLB(start);
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-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
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for (ws = 0; ws < ws_end; ws += ws_inc)
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
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for (addr = start; addr < end; addr += 0x400)
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
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cache32_unroll32(addr|ws,Index_Invalidate_I);
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-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
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@@ -471,6 +532,7 @@
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
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unsigned long start = page;
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
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unsigned long end = start + PAGE_SIZE;
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
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+ BCM4710_FILL_TLB(start);
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/* build blast_xxx_range, protected_blast_xxx_range */
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do {
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-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
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cache64_unroll32(start,Hit_Invalidate_I);
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+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war) \
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start += 0x800;
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static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
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unsigned long end) \
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{ \
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unsigned long lsize = cpu_##desc##_line_size(); \
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unsigned long addr = start & ~(lsize - 1); \
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unsigned long aend = (end - 1) & ~(lsize - 1); \
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+ war \
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while (1) { \
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prot##cache_op(hitop, addr); \
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if (addr == aend) \
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@@ -296,12 +361,12 @@
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} \
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}
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-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
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-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
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-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
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-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
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-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
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+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);)
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+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
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+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
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+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);)
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+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
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/* blast_inv_dcache_range */
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-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
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+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
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#endif /* _ASM_R4KCACHE_H */
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diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
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diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
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||||||
--- linux.old/include/asm-mips/stackframe.h 2005-12-04 06:10:42.000000000 +0100
|
--- linux.old/include/asm-mips/stackframe.h 2006-03-20 06:53:29.000000000 +0100
|
||||||
+++ linux.dev/include/asm-mips/stackframe.h 2005-12-18 05:33:02.405302250 +0100
|
+++ linux.dev/include/asm-mips/stackframe.h 2006-03-21 12:19:26.000000000 +0100
|
||||||
@@ -285,6 +285,10 @@
|
@@ -285,6 +285,10 @@
|
||||||
.macro RESTORE_SP_AND_RET
|
.macro RESTORE_SP_AND_RET
|
||||||
LONG_L sp, PT_R29(sp)
|
LONG_L sp, PT_R29(sp)
|
||||||
|
Loading…
Reference in New Issue
Block a user