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[ramips] share common INTC code

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17440 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2009-08-30 19:15:58 +00:00
parent b887a6d197
commit 60da4b4a94
14 changed files with 139 additions and 145 deletions
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16
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/common.h Normal file
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@@ -0,0 +1,16 @@
/*
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_RALINK_COMMON_H
#define __ASM_MACH_RALINK_COMMON_H
void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
unsigned irq_base);
u32 ramips_intc_get_status(void);
#endif /* __ASM_MACH_RALINK_COMMON_H */

11
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h
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@@ -53,7 +53,6 @@ extern unsigned long rt288x_mach_type;
#define RT288X_GPIO_COUNT 32
extern void __iomem *rt288x_sysc_base;
extern void __iomem *rt288x_intc_base;
extern void __iomem *rt288x_memc_base;
static inline void rt288x_sysc_wr(u32 val, unsigned reg)
@@ -66,16 +65,6 @@ static inline u32 rt288x_sysc_rr(unsigned reg)
return __raw_readl(rt288x_sysc_base + reg);
}
static inline void rt288x_intc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt288x_intc_base + reg);
}
static inline u32 rt288x_intc_rr(unsigned reg)
{
return __raw_readl(rt288x_intc_base + reg);
}
static inline void rt288x_memc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt288x_memc_base + reg);

10
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
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@@ -75,16 +75,6 @@
#define RT2880_RESET_FE BIT(18)
#define RT2880_RESET_PCM BIT(19)
/* TIMER registers */
/* INTC register */
#define INTC_REG_STATUS0 0x00
#define INTC_REG_STATUS1 0x04
#define INTC_REG_TYPE 0x20
#define INTC_REG_RAW_STATUS 0x30
#define INTC_REG_ENABLE 0x34
#define INTC_REG_DISABLE 0x38
#define RT2880_INTC_INT_TIMER0 BIT(0)
#define RT2880_INTC_INT_TIMER1 BIT(1)
#define RT2880_INTC_INT_UART0 BIT(2)

11
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
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@@ -55,7 +55,6 @@ extern unsigned long rt305x_sys_freq;
#define RT305X_INTC_IRQ_OTG (RT305X_INTC_IRQ_BASE + 18)
extern void __iomem *rt305x_sysc_base;
extern void __iomem *rt305x_intc_base;
extern void __iomem *rt305x_memc_base;
static inline void rt305x_sysc_wr(u32 val, unsigned reg)
@@ -68,16 +67,6 @@ static inline u32 rt305x_sysc_rr(unsigned reg)
return __raw_readl(rt305x_sysc_base + reg);
}
static inline void rt305x_intc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt305x_intc_base + reg);
}
static inline u32 rt305x_intc_rr(unsigned reg)
{
return __raw_readl(rt305x_intc_base + reg);
}
static inline void rt305x_memc_wr(u32 val, unsigned reg)
{
__raw_writel(val, rt305x_memc_base + reg);

10
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
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@@ -79,16 +79,6 @@
#define RT305X_RESET_OTG BIT(22)
#define RT305X_RESET_ESW BIT(23)
/* TIMER registers */
/* INTC register */
#define INTC_REG_STATUS0 0x00
#define INTC_REG_STATUS1 0x04
#define INTC_REG_TYPE 0x20
#define INTC_REG_RAW_STATUS 0x30
#define INTC_REG_ENABLE 0x34
#define INTC_REG_DISABLE 0x38
#define RT305X_INTC_INT_SYSCTL BIT(0)
#define RT305X_INTC_INT_TIMER0 BIT(1)
#define RT305X_INTC_INT_TIMER1 BIT(2)