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[ramips] share common INTC code
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17440 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@@ -17,6 +17,7 @@
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/common.h>
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#include <asm/mach-ralink/rt288x.h>
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#include <asm/mach-ralink/rt288x_regs.h>
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@@ -24,7 +25,7 @@ static void rt288x_intc_irq_dispatch(void)
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{
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u32 pending;
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pending = rt288x_intc_rr(INTC_REG_STATUS0);
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pending = ramips_intc_get_status();
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if (pending & RT2880_INTC_INT_TIMER0)
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do_IRQ(RT2880_INTC_IRQ_TIMER0);
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@@ -47,52 +48,6 @@ static void rt288x_intc_irq_dispatch(void)
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spurious_interrupt();
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}
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static void rt288x_intc_irq_unmask(unsigned int irq)
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{
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irq -= RT288X_INTC_IRQ_BASE;
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rt288x_intc_wr((1 << irq), INTC_REG_ENABLE);
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}
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static void rt288x_intc_irq_mask(unsigned int irq)
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{
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irq -= RT288X_INTC_IRQ_BASE;
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rt288x_intc_wr((1 << irq), INTC_REG_DISABLE);
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}
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struct irq_chip rt288x_intc_irq_chip = {
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.name = "RT288X INTC",
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.unmask = rt288x_intc_irq_unmask,
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.mask = rt288x_intc_irq_mask,
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.mask_ack = rt288x_intc_irq_mask,
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};
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static struct irqaction rt288x_intc_irqaction = {
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.handler = no_action,
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.name = "cascade [RT288X INTC]",
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};
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static void __init rt288x_intc_irq_init(void)
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{
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int i;
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/* disable all interrupts */
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rt288x_intc_wr(~0, INTC_REG_DISABLE);
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/* route all INTC interrupts to MIPS HW0 interrupt */
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rt288x_intc_wr(0, INTC_REG_TYPE);
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for (i = RT288X_INTC_IRQ_BASE;
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i < RT288X_INTC_IRQ_BASE + RT288X_INTC_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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set_irq_chip_and_handler(i, &rt288x_intc_irq_chip,
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handle_level_irq);
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}
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setup_irq(RT288X_CPU_IRQ_INTC, &rt288x_intc_irqaction);
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rt288x_intc_wr(RT2880_INTC_INT_GLOBAL, INTC_REG_ENABLE);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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@@ -121,5 +76,6 @@ asmlinkage void plat_irq_dispatch(void)
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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rt288x_intc_irq_init();
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ramips_intc_irq_init(RT2880_INTC_BASE, RT288X_CPU_IRQ_INTC,
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RT288X_INTC_IRQ_BASE);
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}
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