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[ramips] share common INTC code
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17440 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
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@ -0,0 +1,16 @@
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/*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_RALINK_COMMON_H
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#define __ASM_MACH_RALINK_COMMON_H
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void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
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unsigned irq_base);
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u32 ramips_intc_get_status(void);
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#endif /* __ASM_MACH_RALINK_COMMON_H */
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@ -53,7 +53,6 @@ extern unsigned long rt288x_mach_type;
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#define RT288X_GPIO_COUNT 32
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extern void __iomem *rt288x_sysc_base;
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extern void __iomem *rt288x_intc_base;
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extern void __iomem *rt288x_memc_base;
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static inline void rt288x_sysc_wr(u32 val, unsigned reg)
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@ -66,16 +65,6 @@ static inline u32 rt288x_sysc_rr(unsigned reg)
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return __raw_readl(rt288x_sysc_base + reg);
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}
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static inline void rt288x_intc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt288x_intc_base + reg);
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}
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static inline u32 rt288x_intc_rr(unsigned reg)
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{
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return __raw_readl(rt288x_intc_base + reg);
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}
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static inline void rt288x_memc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt288x_memc_base + reg);
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@ -75,16 +75,6 @@
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#define RT2880_RESET_FE BIT(18)
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#define RT2880_RESET_PCM BIT(19)
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/* TIMER registers */
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/* INTC register */
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#define INTC_REG_STATUS0 0x00
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#define INTC_REG_STATUS1 0x04
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#define INTC_REG_TYPE 0x20
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#define INTC_REG_RAW_STATUS 0x30
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#define INTC_REG_ENABLE 0x34
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#define INTC_REG_DISABLE 0x38
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#define RT2880_INTC_INT_TIMER0 BIT(0)
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#define RT2880_INTC_INT_TIMER1 BIT(1)
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#define RT2880_INTC_INT_UART0 BIT(2)
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@ -55,7 +55,6 @@ extern unsigned long rt305x_sys_freq;
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#define RT305X_INTC_IRQ_OTG (RT305X_INTC_IRQ_BASE + 18)
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extern void __iomem *rt305x_sysc_base;
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extern void __iomem *rt305x_intc_base;
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extern void __iomem *rt305x_memc_base;
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static inline void rt305x_sysc_wr(u32 val, unsigned reg)
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@ -68,16 +67,6 @@ static inline u32 rt305x_sysc_rr(unsigned reg)
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return __raw_readl(rt305x_sysc_base + reg);
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}
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static inline void rt305x_intc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt305x_intc_base + reg);
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}
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static inline u32 rt305x_intc_rr(unsigned reg)
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{
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return __raw_readl(rt305x_intc_base + reg);
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}
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static inline void rt305x_memc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt305x_memc_base + reg);
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@ -79,16 +79,6 @@
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#define RT305X_RESET_OTG BIT(22)
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#define RT305X_RESET_ESW BIT(23)
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/* TIMER registers */
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/* INTC register */
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#define INTC_REG_STATUS0 0x00
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#define INTC_REG_STATUS1 0x04
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#define INTC_REG_TYPE 0x20
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#define INTC_REG_RAW_STATUS 0x30
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#define INTC_REG_ENABLE 0x34
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#define INTC_REG_DISABLE 0x38
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#define RT305X_INTC_INT_SYSCTL BIT(0)
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#define RT305X_INTC_INT_TIMER0 BIT(1)
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#define RT305X_INTC_INT_TIMER1 BIT(2)
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10
target/linux/ramips/files/arch/mips/ralink/common/Makefile
Normal file
10
target/linux/ramips/files/arch/mips/ralink/common/Makefile
Normal file
@ -0,0 +1,10 @@
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#
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# Makefile for the Ralink common stuff
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#
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# Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License version 2 as published
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# by the Free Software Foundation.
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obj-y := intc.o
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98
target/linux/ramips/files/arch/mips/ralink/common/intc.c
Normal file
98
target/linux/ramips/files/arch/mips/ralink/common/intc.c
Normal file
@ -0,0 +1,98 @@
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/*
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* Ralink SoC Interrupt controller routines
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*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/common.h>
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/* INTC register offsets */
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#define INTC_REG_STATUS0 0x00
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#define INTC_REG_STATUS1 0x04
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#define INTC_REG_TYPE 0x20
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#define INTC_REG_RAW_STATUS 0x30
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#define INTC_REG_ENABLE 0x34
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#define INTC_REG_DISABLE 0x38
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#define INTC_INT_GLOBAL BIT(31)
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#define INTC_IRQ_COUNT 32
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static unsigned int ramips_intc_irq_base;
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static void __iomem *ramips_intc_base;
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static inline void ramips_intc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, ramips_intc_base + reg);
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}
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static inline u32 ramips_intc_rr(unsigned reg)
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{
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return __raw_readl(ramips_intc_base + reg);
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}
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static void ramips_intc_irq_unmask(unsigned int irq)
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{
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irq -= ramips_intc_irq_base;
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ramips_intc_wr((1 << irq), INTC_REG_ENABLE);
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}
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static void ramips_intc_irq_mask(unsigned int irq)
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{
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irq -= ramips_intc_irq_base;
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ramips_intc_wr((1 << irq), INTC_REG_DISABLE);
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}
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static struct irq_chip ramips_intc_irq_chip = {
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.name = "INTC",
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.unmask = ramips_intc_irq_unmask,
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.mask = ramips_intc_irq_mask,
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.mask_ack = ramips_intc_irq_mask,
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};
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static struct irqaction ramips_intc_irqaction = {
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.handler = no_action,
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.name = "cascade [INTC]",
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};
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void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
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unsigned irq_base)
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{
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int i;
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ramips_intc_base = ioremap_nocache(intc_base, PAGE_SIZE);
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ramips_intc_irq_base = irq_base;
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/* disable all interrupts */
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ramips_intc_wr(~0, INTC_REG_DISABLE);
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/* route all INTC interrupts to MIPS HW0 interrupt */
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ramips_intc_wr(0, INTC_REG_TYPE);
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for (i = ramips_intc_irq_base;
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i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++) {
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set_irq_chip_and_handler(i, &ramips_intc_irq_chip,
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handle_level_irq);
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}
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setup_irq(irq, &ramips_intc_irqaction);
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ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE);
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}
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u32 ramips_intc_get_status(void)
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{
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return ramips_intc_rr(INTC_REG_STATUS0);
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}
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@ -17,6 +17,7 @@
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/common.h>
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#include <asm/mach-ralink/rt288x.h>
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#include <asm/mach-ralink/rt288x_regs.h>
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@ -24,7 +25,7 @@ static void rt288x_intc_irq_dispatch(void)
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{
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u32 pending;
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pending = rt288x_intc_rr(INTC_REG_STATUS0);
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pending = ramips_intc_get_status();
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if (pending & RT2880_INTC_INT_TIMER0)
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do_IRQ(RT2880_INTC_IRQ_TIMER0);
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@ -47,52 +48,6 @@ static void rt288x_intc_irq_dispatch(void)
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spurious_interrupt();
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}
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static void rt288x_intc_irq_unmask(unsigned int irq)
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{
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irq -= RT288X_INTC_IRQ_BASE;
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rt288x_intc_wr((1 << irq), INTC_REG_ENABLE);
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}
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static void rt288x_intc_irq_mask(unsigned int irq)
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{
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irq -= RT288X_INTC_IRQ_BASE;
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rt288x_intc_wr((1 << irq), INTC_REG_DISABLE);
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}
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struct irq_chip rt288x_intc_irq_chip = {
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.name = "RT288X INTC",
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.unmask = rt288x_intc_irq_unmask,
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.mask = rt288x_intc_irq_mask,
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.mask_ack = rt288x_intc_irq_mask,
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};
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static struct irqaction rt288x_intc_irqaction = {
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.handler = no_action,
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.name = "cascade [RT288X INTC]",
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};
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static void __init rt288x_intc_irq_init(void)
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{
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int i;
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/* disable all interrupts */
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rt288x_intc_wr(~0, INTC_REG_DISABLE);
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/* route all INTC interrupts to MIPS HW0 interrupt */
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rt288x_intc_wr(0, INTC_REG_TYPE);
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for (i = RT288X_INTC_IRQ_BASE;
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i < RT288X_INTC_IRQ_BASE + RT288X_INTC_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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set_irq_chip_and_handler(i, &rt288x_intc_irq_chip,
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handle_level_irq);
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}
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setup_irq(RT288X_CPU_IRQ_INTC, &rt288x_intc_irqaction);
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rt288x_intc_wr(RT2880_INTC_INT_GLOBAL, INTC_REG_ENABLE);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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@ -121,5 +76,6 @@ asmlinkage void plat_irq_dispatch(void)
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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rt288x_intc_irq_init();
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ramips_intc_irq_init(RT2880_INTC_BASE, RT288X_CPU_IRQ_INTC,
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RT288X_INTC_IRQ_BASE);
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}
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@ -26,7 +26,6 @@ EXPORT_SYMBOL_GPL(rt288x_cpu_freq);
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unsigned long rt288x_sys_freq;
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EXPORT_SYMBOL_GPL(rt288x_sys_freq);
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void __iomem * rt288x_intc_base;
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void __iomem * rt288x_sysc_base;
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void __iomem * rt288x_memc_base;
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@ -108,7 +108,6 @@ void __init plat_mem_setup(void)
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{
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set_io_port_base(KSEG1);
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rt288x_intc_base = ioremap_nocache(RT2880_INTC_BASE, RT2880_INTC_SIZE);
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rt288x_sysc_base = ioremap_nocache(RT2880_SYSC_BASE, RT2880_SYSC_SIZE);
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rt288x_memc_base = ioremap_nocache(RT2880_MEMC_BASE, RT2880_MEMC_SIZE);
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@ -16,6 +16,7 @@
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/common.h>
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#include <asm/mach-ralink/rt305x.h>
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#include <asm/mach-ralink/rt305x_regs.h>
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@ -23,7 +24,7 @@ static void rt305x_intc_irq_dispatch(void)
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{
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u32 pending;
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pending = rt305x_intc_rr(INTC_REG_STATUS0);
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pending = ramips_intc_get_status();
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if (pending & RT305X_INTC_INT_TIMER0)
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do_IRQ(RT305X_INTC_IRQ_TIMER0);
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@ -43,52 +44,6 @@ static void rt305x_intc_irq_dispatch(void)
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spurious_interrupt();
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}
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static void rt305x_intc_irq_unmask(unsigned int irq)
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{
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irq -= RT305X_INTC_IRQ_BASE;
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rt305x_intc_wr((1 << irq), INTC_REG_ENABLE);
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}
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static void rt305x_intc_irq_mask(unsigned int irq)
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{
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irq -= RT305X_INTC_IRQ_BASE;
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rt305x_intc_wr((1 << irq), INTC_REG_DISABLE);
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}
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struct irq_chip rt305x_intc_irq_chip = {
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.name = "RT305X INTC",
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.unmask = rt305x_intc_irq_unmask,
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.mask = rt305x_intc_irq_mask,
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.mask_ack = rt305x_intc_irq_mask,
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};
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static struct irqaction rt305x_intc_irqaction = {
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.handler = no_action,
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.name = "cascade [RT305X INTC]",
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};
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static void __init rt305x_intc_irq_init(void)
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{
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int i;
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/* disable all interrupts */
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rt305x_intc_wr(~0, INTC_REG_DISABLE);
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/* route all INTC interrupts to MIPS HW0 interrupt */
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rt305x_intc_wr(0, INTC_REG_TYPE);
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for (i = RT305X_INTC_IRQ_BASE;
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i < RT305X_INTC_IRQ_BASE + RT305X_INTC_IRQ_COUNT; i++) {
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set_irq_chip_and_handler(i, &rt305x_intc_irq_chip,
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handle_level_irq);
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}
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setup_irq(RT305X_CPU_IRQ_INTC, &rt305x_intc_irqaction);
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/* enable interrupt masking */
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rt305x_intc_wr(RT305X_INTC_INT_GLOBAL, INTC_REG_ENABLE);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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@ -114,5 +69,6 @@ asmlinkage void plat_irq_dispatch(void)
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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rt305x_intc_irq_init();
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ramips_intc_irq_init(RT305X_INTC_BASE, RT305X_CPU_IRQ_INTC,
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RT305X_INTC_IRQ_BASE);
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}
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@ -26,7 +26,6 @@ EXPORT_SYMBOL_GPL(rt305x_cpu_freq);
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unsigned long rt305x_sys_freq;
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EXPORT_SYMBOL_GPL(rt305x_sys_freq);
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void __iomem * rt305x_intc_base;
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void __iomem * rt305x_sysc_base;
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void __iomem * rt305x_memc_base;
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@ -103,7 +103,6 @@ void __init plat_mem_setup(void)
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{
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set_io_port_base(KSEG1);
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rt305x_intc_base = ioremap_nocache(RT305X_INTC_BASE, PAGE_SIZE);
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rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE);
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rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE);
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@ -1,21 +1,25 @@
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -603,6 +603,20 @@ else
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@@ -603,6 +603,24 @@ else
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load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
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endif
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+#
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+# Ralink SoC common stuff
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+#
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+core-$(CONFIG_MIPS_RALINK) += arch/mips/ralink/common/
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+cflags-$(CONFIG_MIPS_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
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+
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+#
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+# Ralink RT288x
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+#
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+core-$(CONFIG_RALINK_RT288X) += arch/mips/ralink/rt288x/
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+cflags-$(CONFIG_RALINK_RT288X) += -I$(srctree)/arch/mips/include/asm/mach-ralink
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+load-$(CONFIG_RALINK_RT288X) += 0xffffffff88000000
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+
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+#
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+# Ralink RT305x
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+#
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+core-$(CONFIG_RALINK_RT305X) += arch/mips/ralink/rt305x/
|
||||
+cflags-$(CONFIG_RALINK_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink
|
||||
+load-$(CONFIG_RALINK_RT305X) += 0xffffffff80000000
|
||||
+
|
||||
# temporary until string.h is fixed
|
||||
|
Loading…
Reference in New Issue
Block a user