qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-12-25 12:57:42 +02:00
Code

revert some breakage

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10176 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic 2008-01-12 12:07:33 +00:00
parent 224733bba3
commit 62da27b5f7
2 changed files with 19 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
View File

@ -29,13 +29,6 @@
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
#ifdef CONFIG_IFXMIPS_USE_CONSOLE0
#define ASC_OFFSET 0
#elif CONFIG_IFXMIPS_USE_CONSOLE1
#define ASC_OFFSET IFXMIPS_ASC1_BASE_OFFSET
#else
#error a tty for the console must be selected
#endif
static char buf[1024]; static char buf[1024];
void void
@ -46,11 +39,11 @@ prom_free_prom_memory (void)
void void
prom_putchar (char c) prom_putchar (char c)
{ {
while ((readl(IFXMIPS_ASC0_FSTAT + ASC_OFFSET) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF); while ((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
if (c == '\n') if (c == '\n')
writel('\r', IFXMIPS_ASC0_TBUF + ASC_OFFSET); writel('\r', IFXMIPS_ASC1_TBUF);
writel(c, IFXMIPS_ASC0_TBUF + ASC_OFFSET); writel(c, IFXMIPS_ASC1_TBUF);
} }
void void

33
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
View File

@ -34,18 +34,17 @@
#define IFXMIPS_FLASH_MAX 0x2000000 #define IFXMIPS_FLASH_MAX 0x2000000
/*------------ ASC0 */ /*------------ ASC1 */
#define IFXMIPS_ASC0_BASE_ADDR (KSEG1 + 0x1E400C00) #define IFXMIPS_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
#define IFXMIPS_ASC1_BASE_OFFSET ((0x1E100C00 - 0x1E400C00) / sizeof(u32))
/* FIFO status register */ /* FIFO status register */
#define IFXMIPS_ASC0_FSTAT ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0048)) #define IFXMIPS_ASC1_FSTAT ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0048))
#define ASCFSTAT_TXFFLMASK 0x3F00 #define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8 #define ASCFSTAT_TXFFLOFF 8
/* ASC1 transmit buffer */ /* ASC1 transmit buffer */
#define IFXMIPS_ASC0_TBUF ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0020)) #define IFXMIPS_ASC1_TBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0020))
/* channel operating modes */ /* channel operating modes */
#define ASCOPT_CSIZE 0x3 #define ASCOPT_CSIZE 0x3
@ -57,43 +56,43 @@
#define ASCOPT_CREAD 0x20 #define ASCOPT_CREAD 0x20
/* hardware modified control register */ /* hardware modified control register */
#define IFXMIPS_ASC0_WHBSTATE ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0018)) #define IFXMIPS_ASC1_WHBSTATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0018))
/* receive buffer register */ /* receive buffer register */
#define IFXMIPS_ASC0_RBUF ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0024)) #define IFXMIPS_ASC1_RBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0024))
/* status register */ /* status register */
#define IFXMIPS_ASC0_STATE ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0014)) #define IFXMIPS_ASC1_STATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0014))
/* interrupt control */ /* interrupt control */
#define IFXMIPS_ASC0_IRNCR ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x00F8)) #define IFXMIPS_ASC1_IRNCR ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F8))
#define ASC_IRNCR_TIR 0x4 #define ASC_IRNCR_TIR 0x4
#define ASC_IRNCR_RIR 0x2 #define ASC_IRNCR_RIR 0x2
#define ASC_IRNCR_EIR 0x4 #define ASC_IRNCR_EIR 0x4
/* clock control */ /* clock control */
#define IFXMIPS_ASC0_CLC ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0000)) #define IFXMIPS_ASC1_CLC ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0000))
#define IFXMIPS_ASC0_CLC_DISS 0x2 #define IFXMIPS_ASC1_CLC_DISS 0x2
/* port input select register */ /* port input select register */
#define IFXMIPS_ASC0_PISEL ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0004)) #define IFXMIPS_ASC1_PISEL ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0004))
/* tx fifo */ /* tx fifo */
#define IFXMIPS_ASC0_TXFCON ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0044)) #define IFXMIPS_ASC1_TXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0044))
/* rx fifo */ /* rx fifo */
#define IFXMIPS_ASC0_RXFCON ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0040)) #define IFXMIPS_ASC1_RXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
/* control */ /* control */
#define IFXMIPS_ASC0_CON ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0010)) #define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
/* timer reload */ /* timer reload */
#define IFXMIPS_ASC0_BG ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0050)) #define IFXMIPS_ASC1_BG ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
/* int enable */ /* int enable */
#define IFXMIPS_ASC0_IRNREN ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x00F4)) #define IFXMIPS_ASC1_IRNREN ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F4))
#define ASC_IRNREN_RX_BUF 0x8 #define ASC_IRNREN_RX_BUF 0x8
#define ASC_IRNREN_TX_BUF 0x4 #define ASC_IRNREN_TX_BUF 0x4