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git://projects.qi-hardware.com/openwrt-xburst.git
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[brcm63xx] remove accidental bcm6345 related patches
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27234 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian
parent
ea57f00705
commit
64c718f223
@ -1,74 +0,0 @@
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--- a/arch/mips/bcm63xx/cpu.c
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+++ b/arch/mips/bcm63xx/cpu.c
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@@ -260,8 +260,10 @@ static unsigned int detect_memory_size(v
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unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
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u32 val;
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- if (BCMCPU_IS_6345())
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- return (8 * 1024 * 1024);
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+ if (BCMCPU_IS_6345()) {
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+ val = bcm_sdram_readl(SDRAM_MBASE_REG);
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+ return (val * 8 * 1024 * 1024);
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+ }
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if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
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val = bcm_sdram_readl(SDRAM_CFG_REG);
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -735,6 +735,8 @@
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#define SDRAM_CFG_BANK_SHIFT 13
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#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
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+#define SDRAM_MBASE_REG 0xc
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+
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#define SDRAM_PRIO_REG 0x2C
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#define SDRAM_PRIO_MIPS_SHIFT 29
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#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
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--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
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+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
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@@ -698,15 +698,9 @@ void __init board_prom_init(void)
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char cfe_version[32];
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u32 val;
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- /* read base address of boot chip select (0)
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- * 6345 does not have MPI but boots from standard
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- * MIPS Flash address */
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- if (BCMCPU_IS_6345())
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- val = 0x1fc00000;
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- else {
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- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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- val &= MPI_CSBASE_BASE_MASK;
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- }
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+ /* read base address of boot chip select (0) */
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+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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+ val &= MPI_CSBASE_BASE_MASK;
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boot_addr = (u8 *)KSEG1ADDR(val);
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/* dump cfe version */
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@@ -881,12 +875,9 @@ int __init board_register_devices(void)
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bcm63xx_dsp_register(&board.dsp);
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/* read base address of boot chip select (0) */
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- if (BCMCPU_IS_6345())
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- val = 0x1fc00000;
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- else {
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- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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- val &= MPI_CSBASE_BASE_MASK;
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- }
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+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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+ val &= MPI_CSBASE_BASE_MASK;
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+
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mtd_resources[0].start = val;
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mtd_resources[0].end = 0x1FFFFFFF;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -163,7 +163,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_ENET0_BASE (0xfffe1800)
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#define BCM_6345_ENETDMA_BASE (0xfffe2800)
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#define BCM_6345_PCMCIA_BASE (0xfffe2028)
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-#define BCM_6345_MPI_BASE (0xdeadbeef)
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+#define BCM_6345_MPI_BASE (0xfffe2000)
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#define BCM_6345_OHCI0_BASE (0xfffe2100)
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#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
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@ -1,530 +0,0 @@
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -29,16 +29,15 @@
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CKCTL_6338_SAR_EN | \
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CKCTL_6338_SPI_EN)
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-#define CKCTL_6345_CPU_EN (1 << 0)
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-#define CKCTL_6345_BUS_EN (1 << 1)
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-#define CKCTL_6345_EBI_EN (1 << 2)
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-#define CKCTL_6345_UART_EN (1 << 3)
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-#define CKCTL_6345_ADSLPHY_EN (1 << 4)
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-#define CKCTL_6345_ENET_EN (1 << 7)
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-#define CKCTL_6345_USBH_EN (1 << 8)
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+#define CKCTL_6345_CPU_EN (1 << 16)
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+#define CKCTL_6345_BUS_EN (1 << 17)
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+#define CKCTL_6345_EBI_EN (1 << 18)
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+#define CKCTL_6345_UART_EN (1 << 19)
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+#define CKCTL_6345_ADSLPHY_EN (1 << 20)
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+#define CKCTL_6345_ENET_EN (1 << 23)
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+#define CKCTL_6345_USBH_EN (1 << 24)
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-#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
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- CKCTL_6345_USBH_EN | \
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+#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_USBH_EN | \
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CKCTL_6345_ADSLPHY_EN)
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#define CKCTL_6348_ADSLPHY_EN (1 << 0)
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@@ -548,6 +547,39 @@
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#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
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+/* Broadcom 6345 ENET DMA definitions */
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+#define ENETDMA_6345_CHANCFG_REG(x) (0x00 + (x) * 0x40)
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+#define ENETDMA_6345_CHANCFG_EN_SHIFT 0
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+#define ENETDMA_6345_CHANCFG_EN_MASK (1 << ENETDMA_6345_CHANCFG_EN_SHIFT)
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+#define ENETDMA_6345_PKTHALT_SHIFT 1
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+#define ENETDMA_6345_PKTHALT_MASK (1 << ENETDMA_6345_PKTHALT_SHIFT)
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+#define ENETDMA_6345_CHAINING_SHIFT 2
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+#define ENETDMA_6345_CHAINING_MASK (1 << ENETDMA_6345_CHAINING_SHIFT)
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+#define ENETDMA_6345_WRAP_EN_SHIFT 3
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+#define ENETDMA_6345_WRAP_EN_MASK (1 << ENETDMA_6345_WRAP_EN_SHIFT)
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+#define ENETDMA_6345_FLOWC_EN_SHIFT 4
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+#define ENETDMA_6345_FLOWC_EN_MASK (1 << ENETDMA_6345_FLOWC_EN_SHIFT)
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+
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+#define ENETDMA_6345_MAXBURST_REG(x) (0x04 + (x) * 0x40)
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+
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+#define ENETDMA_6345_RSTART_REG(x) (0x08 + (x) * 0x40)
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+
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+#define ENETDMA_6345_LEN_REG(x) (0x0C + (x) * 0x40)
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+
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+#define ENETDMA_6345_BSTAT_REG(x) (0x10 + (x) * 0x40)
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+
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+#define ENETDMA_6345_IR_REG(x) (0x14 + (x) * 0x40)
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+#define ENETDMA_6345_IR_BUFDONE_MASK (1 << 0)
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+#define ENETDMA_6345_IR_PKTDONE_MASK (1 << 1)
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+#define ENETDMA_6345_IR_NOTOWNER_MASK (1 << 2)
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+
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+#define ENETDMA_6345_IRMASK_REG(x) (0x18 + (x) * 0x40)
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+
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+#define ENETDMA_6345_FC_REG(x) (0x1C + (x) * 0x40)
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+
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+#define ENETDMA_6345_BUFALLOC_REG(x) (0x20 + (x) * 0x40)
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+
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+
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/*************************************************************************
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* _REG relative to RSET_OHCI_PRIV
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*************************************************************************/
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--- a/drivers/net/bcm63xx_enet.c
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+++ b/drivers/net/bcm63xx_enet.c
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@@ -31,6 +31,7 @@
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#include <linux/if_vlan.h>
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#include <bcm63xx_dev_enet.h>
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+#include <bcm63xx_cpu.h>
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#include "bcm63xx_enet.h"
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static char bcm_enet_driver_name[] = "bcm63xx_enet";
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@@ -177,6 +178,7 @@ static void bcm_enet_mdio_write_mii(stru
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static int bcm_enet_refill_rx(struct net_device *dev)
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{
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struct bcm_enet_priv *priv;
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+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
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priv = netdev_priv(dev);
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@@ -205,7 +207,7 @@ static int bcm_enet_refill_rx(struct net
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len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
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len_stat |= DMADESC_OWNER_MASK;
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if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
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- len_stat |= DMADESC_WRAP_MASK;
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+ len_stat |= (DMADESC_WRAP_MASK >> desc_shift);
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priv->rx_dirty_desc = 0;
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} else {
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priv->rx_dirty_desc++;
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@@ -216,7 +218,10 @@ static int bcm_enet_refill_rx(struct net
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priv->rx_desc_count++;
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/* tell dma engine we allocated one buffer */
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- enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
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+ if (!BCMCPU_IS_6345())
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+ enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
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+ else
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+ enet_dma_writel(priv, 1, ENETDMA_6345_BUFALLOC_REG(priv->rx_chan));
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}
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/* If rx ring is still empty, set a timer to try allocating
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@@ -254,6 +259,7 @@ static int bcm_enet_receive_queue(struct
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struct bcm_enet_priv *priv;
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struct device *kdev;
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int processed;
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+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
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priv = netdev_priv(dev);
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kdev = &priv->pdev->dev;
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@@ -292,7 +298,7 @@ static int bcm_enet_receive_queue(struct
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/* if the packet does not have start of packet _and_
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* end of packet flag set, then just recycle it */
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- if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
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+ if ((len_stat & (DMADESC_ESOP_MASK >> desc_shift)) != (DMADESC_ESOP_MASK >> desc_shift)) {
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dev->stats.rx_dropped++;
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continue;
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}
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@@ -352,8 +358,15 @@ static int bcm_enet_receive_queue(struct
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bcm_enet_refill_rx(dev);
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/* kick rx dma */
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- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
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- ENETDMA_CHANCFG_REG(priv->rx_chan));
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+ if (!BCMCPU_IS_6345())
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+ enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
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+ ENETDMA_CHANCFG_REG(priv->rx_chan));
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+ else
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+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
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+ ENETDMA_6345_CHAINING_MASK |
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+ ENETDMA_6345_WRAP_EN_MASK |
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+ ENETDMA_6345_FLOWC_EN_MASK,
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+ ENETDMA_6345_CHANCFG_REG(priv->rx_chan));
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}
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return processed;
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@@ -428,10 +441,21 @@ static int bcm_enet_poll(struct napi_str
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dev = priv->net_dev;
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/* ack interrupts */
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IR_REG(priv->rx_chan));
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IR_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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+ ENETDMA_IR_REG(priv->rx_chan));
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+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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+ ENETDMA_IR_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
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+ ENETDMA_IR_PKTDONE_MASK |
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+ ENETDMA_IR_NOTOWNER_MASK,
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+ ENETDMA_6345_IR_REG(priv->rx_chan));
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+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
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+ ENETDMA_IR_PKTDONE_MASK |
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+ ENETDMA_IR_NOTOWNER_MASK,
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+ ENETDMA_6345_IR_REG(priv->tx_chan));
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+ }
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/* reclaim sent skb */
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tx_work_done = bcm_enet_tx_reclaim(dev, 0);
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@@ -450,10 +474,21 @@ static int bcm_enet_poll(struct napi_str
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napi_complete(napi);
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/* restore rx/tx interrupt */
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IRMASK_REG(priv->rx_chan));
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- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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- ENETDMA_IRMASK_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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+ ENETDMA_IRMASK_REG(priv->rx_chan));
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+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
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+ ENETDMA_IRMASK_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
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+ ENETDMA_IR_PKTDONE_MASK |
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+ ENETDMA_IR_NOTOWNER_MASK,
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+ ENETDMA_6345_IRMASK_REG(priv->rx_chan));
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+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
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+ ENETDMA_IR_PKTDONE_MASK |
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+ ENETDMA_IR_NOTOWNER_MASK,
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+ ENETDMA_6345_IRMASK_REG(priv->tx_chan));
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+ }
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return rx_work_done;
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}
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@@ -496,8 +531,13 @@ static irqreturn_t bcm_enet_isr_dma(int
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priv = netdev_priv(dev);
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/* mask rx/tx interrupts */
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- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
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- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
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+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
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+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
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+ }
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napi_schedule(&priv->napi);
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@@ -513,6 +553,7 @@ static int bcm_enet_start_xmit(struct sk
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struct bcm_enet_desc *desc;
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u32 len_stat;
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int ret;
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+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
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priv = netdev_priv(dev);
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@@ -538,14 +579,13 @@ static int bcm_enet_start_xmit(struct sk
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DMA_TO_DEVICE);
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len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
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- len_stat |= DMADESC_ESOP_MASK |
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- DMADESC_APPEND_CRC |
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- DMADESC_OWNER_MASK;
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+ len_stat |= ((DMADESC_ESOP_MASK >> desc_shift) |
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+ DMADESC_APPEND_CRC | DMADESC_OWNER_MASK);
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priv->tx_curr_desc++;
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if (priv->tx_curr_desc == priv->tx_ring_size) {
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priv->tx_curr_desc = 0;
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- len_stat |= DMADESC_WRAP_MASK;
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+ len_stat |= (DMADESC_WRAP_MASK >> desc_shift);
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}
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priv->tx_desc_count--;
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@@ -556,8 +596,15 @@ static int bcm_enet_start_xmit(struct sk
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wmb();
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/* kick tx dma */
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- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
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- ENETDMA_CHANCFG_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345())
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+ enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
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+ ENETDMA_CHANCFG_REG(priv->tx_chan));
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+ else
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+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
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+ ENETDMA_6345_CHAINING_MASK |
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+ ENETDMA_6345_WRAP_EN_MASK |
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+ ENETDMA_6345_FLOWC_EN_MASK,
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+ ENETDMA_6345_CHANCFG_REG(priv->tx_chan));
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/* stop queue if no more desc available */
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if (!priv->tx_desc_count)
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@@ -685,6 +732,9 @@ static void bcm_enet_set_flow(struct bcm
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val &= ~ENET_RXCFG_ENFLOW_MASK;
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enet_writel(priv, val, ENET_RXCFG_REG);
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+ if (BCMCPU_IS_6345())
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+ return;
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+
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/* tx flow control (pause frame generation) */
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val = enet_dma_readl(priv, ENETDMA_CFG_REG);
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if (tx_en)
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@@ -832,8 +882,13 @@ static int bcm_enet_open(struct net_devi
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/* mask all interrupts and request them */
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enet_writel(priv, 0, ENET_IRMASK_REG);
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- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
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- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
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+ if (!BCMCPU_IS_6345()) {
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+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
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+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
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+ } else {
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+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
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+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
|
||||
+ }
|
||||
|
||||
ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
|
||||
if (ret)
|
||||
@@ -912,8 +967,12 @@ static int bcm_enet_open(struct net_devi
|
||||
priv->rx_curr_desc = 0;
|
||||
|
||||
/* initialize flow control buffer allocation */
|
||||
- enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
|
||||
- ENETDMA_BUFALLOC_REG(priv->rx_chan));
|
||||
+ if (!BCMCPU_IS_6345())
|
||||
+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
|
||||
+ ENETDMA_BUFALLOC_REG(priv->rx_chan));
|
||||
+ else
|
||||
+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
|
||||
+ ENETDMA_6345_BUFALLOC_REG(priv->rx_chan));
|
||||
|
||||
if (bcm_enet_refill_rx(dev)) {
|
||||
dev_err(kdev, "cannot allocate rx skb queue\n");
|
||||
@@ -922,37 +981,62 @@ static int bcm_enet_open(struct net_devi
|
||||
}
|
||||
|
||||
/* write rx & tx ring addresses */
|
||||
- enet_dma_writel(priv, priv->rx_desc_dma,
|
||||
- ENETDMA_RSTART_REG(priv->rx_chan));
|
||||
- enet_dma_writel(priv, priv->tx_desc_dma,
|
||||
- ENETDMA_RSTART_REG(priv->tx_chan));
|
||||
+ if (!BCMCPU_IS_6345()) {
|
||||
+ enet_dma_writel(priv, priv->rx_desc_dma,
|
||||
+ ENETDMA_RSTART_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, priv->tx_desc_dma,
|
||||
+ ENETDMA_RSTART_REG(priv->tx_chan));
|
||||
+ } else {
|
||||
+ enet_dma_writel(priv, priv->rx_desc_dma,
|
||||
+ ENETDMA_6345_RSTART_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, priv->tx_desc_dma,
|
||||
+ ENETDMA_6345_RSTART_REG(priv->tx_chan));
|
||||
+ }
|
||||
|
||||
/* clear remaining state ram for rx & tx channel */
|
||||
- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
|
||||
- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
|
||||
- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
|
||||
- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
|
||||
- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
|
||||
- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
|
||||
+ if (!BCMCPU_IS_6345()) {
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
|
||||
+ } else {
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_6345_FC_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_6345_FC_REG(priv->tx_chan));
|
||||
+ }
|
||||
|
||||
/* set max rx/tx length */
|
||||
enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
|
||||
enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
|
||||
|
||||
/* set dma maximum burst len */
|
||||
- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
|
||||
- ENETDMA_MAXBURST_REG(priv->rx_chan));
|
||||
- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
|
||||
- ENETDMA_MAXBURST_REG(priv->tx_chan));
|
||||
+ if (!BCMCPU_IS_6345()) {
|
||||
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
|
||||
+ ENETDMA_MAXBURST_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
|
||||
+ ENETDMA_MAXBURST_REG(priv->tx_chan));
|
||||
+ } else {
|
||||
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
|
||||
+ ENETDMA_6345_MAXBURST_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
|
||||
+ ENETDMA_6345_MAXBURST_REG(priv->tx_chan));
|
||||
+ }
|
||||
|
||||
/* set correct transmit fifo watermark */
|
||||
enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
|
||||
|
||||
/* set flow control low/high threshold to 1/3 / 2/3 */
|
||||
- val = priv->rx_ring_size / 3;
|
||||
- enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
|
||||
- val = (priv->rx_ring_size * 2) / 3;
|
||||
- enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
|
||||
+ if (!BCMCPU_IS_6345()) {
|
||||
+ val = priv->rx_ring_size / 3;
|
||||
+ enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
|
||||
+ val = (priv->rx_ring_size * 2) / 3;
|
||||
+ enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
|
||||
+ } else {
|
||||
+ enet_dma_writel(priv, 5, ENETDMA_6345_FC_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, priv->rx_ring_size, ENETDMA_6345_LEN_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, priv->tx_ring_size, ENETDMA_6345_LEN_REG(priv->tx_chan));
|
||||
+ }
|
||||
|
||||
/* all set, enable mac and interrupts, start dma engine and
|
||||
* kick rx dma channel */
|
||||
@@ -960,27 +1044,58 @@ static int bcm_enet_open(struct net_devi
|
||||
val = enet_readl(priv, ENET_CTL_REG);
|
||||
val |= ENET_CTL_ENABLE_MASK;
|
||||
enet_writel(priv, val, ENET_CTL_REG);
|
||||
- enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
|
||||
- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
|
||||
- ENETDMA_CHANCFG_REG(priv->rx_chan));
|
||||
+
|
||||
+ if (!BCMCPU_IS_6345()) {
|
||||
+ enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
|
||||
+ enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
|
||||
+ ENETDMA_CHANCFG_REG(priv->rx_chan));
|
||||
+ } else {
|
||||
+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
|
||||
+ ENETDMA_6345_CHAINING_MASK |
|
||||
+ ENETDMA_6345_WRAP_EN_MASK |
|
||||
+ ENETDMA_6345_FLOWC_EN_MASK,
|
||||
+ ENETDMA_6345_CHANCFG_REG(priv->rx_chan));
|
||||
+ }
|
||||
|
||||
/* watch "mib counters about to overflow" interrupt */
|
||||
enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
|
||||
enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
|
||||
|
||||
/* watch "packet transferred" interrupt in rx and tx */
|
||||
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
|
||||
- ENETDMA_IR_REG(priv->rx_chan));
|
||||
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
|
||||
- ENETDMA_IR_REG(priv->tx_chan));
|
||||
+ if (!BCMCPU_IS_6345()) {
|
||||
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
|
||||
+ ENETDMA_IR_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
|
||||
+ ENETDMA_IR_REG(priv->tx_chan));
|
||||
+ } else {
|
||||
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
|
||||
+ ENETDMA_IR_PKTDONE_MASK |
|
||||
+ ENETDMA_IR_NOTOWNER_MASK,
|
||||
+ ENETDMA_6345_IR_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
|
||||
+ ENETDMA_IR_PKTDONE_MASK |
|
||||
+ ENETDMA_IR_NOTOWNER_MASK,
|
||||
+ ENETDMA_6345_IR_REG(priv->tx_chan));
|
||||
+ }
|
||||
|
||||
/* make sure we enable napi before rx interrupt */
|
||||
napi_enable(&priv->napi);
|
||||
|
||||
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
|
||||
- ENETDMA_IRMASK_REG(priv->rx_chan));
|
||||
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
|
||||
- ENETDMA_IRMASK_REG(priv->tx_chan));
|
||||
+ if (!BCMCPU_IS_6345()) {
|
||||
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
|
||||
+ ENETDMA_IRMASK_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
|
||||
+ ENETDMA_IRMASK_REG(priv->tx_chan));
|
||||
+ } else {
|
||||
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
|
||||
+ ENETDMA_IR_PKTDONE_MASK |
|
||||
+ ENETDMA_IR_NOTOWNER_MASK,
|
||||
+ ENETDMA_6345_IRMASK_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
|
||||
+ ENETDMA_IR_PKTDONE_MASK |
|
||||
+ ENETDMA_IR_NOTOWNER_MASK,
|
||||
+ ENETDMA_6345_IRMASK_REG(priv->tx_chan));
|
||||
+ }
|
||||
|
||||
if (priv->has_phy)
|
||||
phy_start(priv->phydev);
|
||||
@@ -1060,13 +1175,19 @@ static void bcm_enet_disable_dma(struct
|
||||
{
|
||||
int limit;
|
||||
|
||||
- enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
|
||||
+ if (!BCMCPU_IS_6345())
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
|
||||
+ else
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_6345_CHANCFG_REG(chan));
|
||||
|
||||
limit = 1000;
|
||||
do {
|
||||
u32 val;
|
||||
|
||||
- val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
|
||||
+ if (!BCMCPU_IS_6345())
|
||||
+ val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
|
||||
+ else
|
||||
+ val = enet_dma_readl(priv, ENETDMA_6345_CHANCFG_REG(chan));
|
||||
if (!(val & ENETDMA_CHANCFG_EN_MASK))
|
||||
break;
|
||||
udelay(1);
|
||||
@@ -1093,8 +1214,13 @@ static int bcm_enet_stop(struct net_devi
|
||||
|
||||
/* mask all interrupts */
|
||||
enet_writel(priv, 0, ENET_IRMASK_REG);
|
||||
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
|
||||
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
|
||||
+ if (!BCMCPU_IS_6345()) {
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
|
||||
+ } else {
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
|
||||
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
|
||||
+ }
|
||||
|
||||
/* make sure no mib update is scheduled */
|
||||
cancel_work_sync(&priv->mib_update_task);
|
||||
@@ -1622,6 +1748,7 @@ static int __devinit bcm_enet_probe(stru
|
||||
const char *clk_name;
|
||||
unsigned int iomem_size;
|
||||
int i, ret;
|
||||
+ unsigned int chan_offset = 0;
|
||||
|
||||
/* stop if shared driver failed, assume driver->probe will be
|
||||
* called in the same order we register devices (correct ?) */
|
||||
@@ -1661,10 +1788,13 @@ static int __devinit bcm_enet_probe(stru
|
||||
priv->irq_tx = res_irq_tx->start;
|
||||
priv->mac_id = pdev->id;
|
||||
|
||||
+ if (BCMCPU_IS_6345())
|
||||
+ chan_offset = 1;
|
||||
+
|
||||
/* get rx & tx dma channel id for this mac */
|
||||
if (priv->mac_id == 0) {
|
||||
- priv->rx_chan = 0;
|
||||
- priv->tx_chan = 1;
|
||||
+ priv->rx_chan = 0 + chan_offset;
|
||||
+ priv->tx_chan = 1 + chan_offset;
|
||||
clk_name = "enet0";
|
||||
} else {
|
||||
priv->rx_chan = 2;
|
||||
--- a/drivers/net/bcm63xx_enet.h
|
||||
+++ b/drivers/net/bcm63xx_enet.h
|
||||
@@ -46,6 +46,9 @@ struct bcm_enet_desc {
|
||||
#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
|
||||
#define DMADESC_WRAP_MASK (1 << 12)
|
||||
|
||||
+/* Shift down for EOP, SOP and WRAP bits */
|
||||
+#define DMADESC_6345_SHIFT (3)
|
||||
+
|
||||
#define DMADESC_UNDER_MASK (1 << 9)
|
||||
#define DMADESC_APPEND_CRC (1 << 8)
|
||||
#define DMADESC_OVSIZE_MASK (1 << 4)
|
||||
--- a/arch/mips/bcm63xx/dev-enet.c
|
||||
+++ b/arch/mips/bcm63xx/dev-enet.c
|
||||
@@ -104,7 +104,7 @@ int __init bcm63xx_enet_register(int uni
|
||||
if (unit > 1)
|
||||
return -ENODEV;
|
||||
|
||||
- if (unit == 1 && BCMCPU_IS_6338())
|
||||
+ if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
|
||||
return -ENODEV;
|
||||
|
||||
if (!shared_device_registered) {
|
||||
@ -1,24 +0,0 @@
|
||||
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
|
||||
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
|
||||
@@ -227,6 +227,13 @@ static struct board_info __initdata boar
|
||||
|
||||
.has_uart0 = 1,
|
||||
};
|
||||
+
|
||||
+static struct board_info __initdata board_ra770bw = {
|
||||
+ .name = "RTA770BW",
|
||||
+ .expected_cpu_id = 0x6345,
|
||||
+
|
||||
+ .has_uart0 = 1,
|
||||
+};
|
||||
#endif
|
||||
|
||||
/*
|
||||
@@ -2050,6 +2057,7 @@ static const struct board_info __initdat
|
||||
#endif
|
||||
#ifdef CONFIG_BCM63XX_CPU_6345
|
||||
&board_96345gw2,
|
||||
+ &board_ra770bw,
|
||||
#endif
|
||||
#ifdef CONFIG_BCM63XX_CPU_6348
|
||||
&board_96348r,
|
||||
Loading…
Reference in New Issue
Block a user