qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-11-27 17:55:55 +02:00
Code

uboot-xburst: update to 2010.06

Browse Source 
uboot-xburst: don't install empty dir
This commit is contained in:
Xiangfu Liu 2011-06-21 15:56:50 +08:00
parent 610823a150
commit 65057cd69b
62 changed files with 2146 additions and 3727 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
package/uboot-xburst/Makefile
View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=u-boot
PKG_VERSION:=2009.11
PKG_VERSION:=2010.06
PKG_RELEASE:=1
PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
@ -51,7 +51,7 @@ define Package/uboot-xburst-$(1)
CATEGORY:=Boot Loaders
DEPENDS:=@TARGET_xburst
TITLE:=$(2)
URL:=http://www.denx.de/wiki/U-Boot
URL:=http://www.denx.de/wiki/UBoot/WebHome
VARIANT:=$(1)
endef
endef
@ -66,13 +66,13 @@ endef
ifdef BUILD_VARIANT
$(eval $(call uboot/$(BUILD_VARIANT)))
UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_VARIANT)-u-boot.bin)
UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_BARIANT)-u-boot.bin)
endif
define Build/Prepare
$(call Build/Prepare/Default)
$(CP) ./files/* $(PKG_BUILD_DIR)
find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
$(call Build/Prepare/Default)
endef
define Build/Configure
@ -87,8 +87,8 @@ endef
define Package/uboot/install/template
define Package/uboot-xburst-$(1)/install
$(INSTALL_DIR) $$(1)
$(CP) $(PKG_BUILD_DIR)/u-boot-nand.bin $(BIN_DIR)/$(2)
rmdir $$(1)
endef
endef

48
package/uboot-xburst/files/arch/mips/cpu/xburst/Makefile Normal file
View File

@ -0,0 +1,48 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
SOBJS-y =
COBJS-y = cpu.o interrupts.o jz4740.o jz_serial.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

263
package/uboot-xburst/files/arch/mips/cpu/xburst/cache.S Normal file
View File

@ -0,0 +1,263 @@
/*
* Cache-handling routined for MIPS CPUs
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#ifndef CONFIG_JzRISC
/* 16KB is the maximum size of instruction and data caches on
* MIPS 4K.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
/*
* cacheop macro to automate cache operations
* first some helpers...
*/
#define _mincache(size, maxsize) \
bltu size,maxsize,9f ; \
move size,maxsize ; \
9:
#define _align(minaddr, maxaddr, linesize) \
.set noat ; \
subu AT,linesize,1 ; \
not AT ; \
and minaddr,AT ; \
addu maxaddr,-1 ; \
and maxaddr,AT ; \
.set at
/* general operations */
#define doop1(op1) \
cache op1,0(a0)
#define doop2(op1, op2) \
cache op1,0(a0) ; \
nop ; \
cache op2,0(a0)
/* specials for cache initialisation */
#define doop1lw(op1) \
lw zero,0(a0)
#define doop1lw1(op1) \
cache op1,0(a0) ; \
lw zero,0(a0) ; \
cache op1,0(a0)
#define doop121(op1,op2) \
cache op1,0(a0) ; \
nop; \
cache op2,0(a0) ; \
nop; \
cache op1,0(a0)
#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
.set noreorder ; \
10: doop##tag##ops ; \
bne minaddr,maxaddr,10b ; \
add minaddr,linesize ; \
.set reorder
/* finally the cache operation macros */
#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
_mincache(n, cacheSize); \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
/*
* mips_cache_reset - low level initialisation of the primary caches
*
* This routine initialises the primary caches to ensure that they
* have good parity. It must be called by the ROM before any cached locations
* are used to prevent the possibility of data with bad parity being written to
* memory.
* To initialise the instruction cache it is essential that a source of data
* with good parity is available. This routine
* will initialise an area of memory starting at location zero to be used as
* a source of parity.
*
* RETURNS: N/A
*/
.globl mips_cache_reset
.ent mips_cache_reset
mips_cache_reset:
li t2, CONFIG_SYS_ICACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
li t4, CONFIG_SYS_CACHELINE_SIZE
move t5, t4
li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero.
*/
li a0, KSEG1
addu a1, a0, v0
2: sw zero, 0(a0)
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
sw zero, 16(a0)
sw zero, 20(a0)
sw zero, 24(a0)
sw zero, 28(a0)
addu a0, 32
bltu a0, a1, 2b
/* Set invalid tag.
*/
mtc0 zero, CP0_TAGLO
/*
* The caches are probably in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
/* Assume bottom of RAM will generate good parity for the cache.
*/
li a0, K0BASE
move a2, t2 # icacheSize
move a3, t4 # icacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
/* To support Orion/R4600, we initialise the data cache in 3 passes.
*/
/* 1: initialise dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
/* 2: fill dcache.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,1lw,(dummy))
/* 3: clear dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
j ra
.end mips_cache_reset
/*
* dcache_status - get cache status
*
* RETURNS: 0 - cache disabled; 1 - cache enabled
*/
.globl dcache_status
.ent dcache_status
dcache_status:
mfc0 v0, CP0_CONFIG
andi v0, v0, 1
j ra
.end dcache_status
/*
* dcache_disable - disable cache
*
* RETURNS: N/A
*/
.globl dcache_disable
.ent dcache_disable
dcache_disable:
mfc0 t0, CP0_CONFIG
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
j ra
.end dcache_disable
/*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
*
* RETURNS: N/A
*/
#if defined(CONFIG_PURPLE)
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
#else
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
li a1, K0BASE - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
li a3, CONFIG_SYS_CACHELINE_SIZE
move a1, a2
icacheop(a0,a1,a2,a3,0x1d)
j ra
.end mips_cache_lock
#endif /* CONFIG_JzRISC */

35
package/uboot-xburst/files/arch/mips/cpu/xburst/config.mk Normal file
View File

@ -0,0 +1,35 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2)
MIPSFLAGS:=$(shell \
if [ "$v" -lt "14" ]; then \
echo "-mcpu=4kc"; \
else \
echo "-march=4kc -mtune=4kc"; \
fi)
ENDIANNESS = -EL
MIPSFLAGS += $(ENDIANNESS) -mabicalls -mips32 -O2
PLATFORM_CPPFLAGS += $(MIPSFLAGS)

172
package/uboot-xburst/files/arch/mips/cpu/xburst/cpu.c Normal file
View File

@ -0,0 +1,172 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mipsregs.h>
#include <asm/cacheops.h>
#include <asm/reboot.h>
#include <asm/jz4740.h>
#if !defined (CONFIG_NAND_SPL) && !defined (CONFIG_MSC_SPL)
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set push \n" \
" .set noreorder \n" \
" .set mips3\n\t \n" \
" cache %0, %1 \n" \
" .set pop \n" \
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
void __attribute__((weak)) _machine_restart(void)
{
__wdt_select_extalclk();
__wdt_select_clk_div64();
__wdt_set_data(100);
__wdt_set_count(0);
__tcu_start_wdt_clock();
__wdt_start();
while(1);
#if defined(CONFIG_JzRISC)
void (*f)(void) = (void *) 0xbfc00000;
f();
#endif
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
_machine_restart();
fprintf(stderr, "*** reset failed ***\n");
return 0;
}
void flush_cache(ulong start_addr, ulong size)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
cache_op(Hit_Invalidate_I, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void flush_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Invalidate_D, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
{
write_c0_entrylo0(low0);
write_c0_pagemask(pagemask);
write_c0_entrylo1(low1);
write_c0_entryhi(hi);
write_c0_index(index);
tlb_write_indexed();
}
#endif /* !CONFIG_NAND_SPL !CONFIG_MSC_SPL */
void flush_icache_all(void)
{
u32 addr, t = 0;
asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
asm volatile (
".set mips3\n\t"
" cache %0, 0(%1)\n\t"
".set mips2\n\t"
:
: "I" (Index_Store_Tag_I), "r"(addr));
}
/* invalicate btb */
asm volatile (
".set mips32\n\t"
"mfc0 %0, $16, 7\n\t"
"nop\n\t"
"ori %0,2\n\t"
"mtc0 %0, $16, 7\n\t"
".set mips2\n\t"
:
: "r" (t));
}
void flush_dcache_all(void)
{
u32 addr;
for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
asm volatile (
".set mips3\n\t"
" cache %0, 0(%1)\n\t"
".set mips2\n\t"
:
: "I" (Index_Writeback_Inv_D), "r"(addr));
}
asm volatile ("sync");
}
void flush_cache_all(void)
{
flush_dcache_all();
flush_icache_all();
}

33
package/uboot-xburst/files/arch/mips/cpu/xburst/interrupts.c Normal file
View File

@ -0,0 +1,33 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
void enable_interrupts(void)
{
}
int disable_interrupts(void)
{
return 0;
}

2
package/uboot-xburst/files/cpu/mips/jz4740.c → package/uboot-xburst/files/arch/mips/cpu/xburst/jz4740.c
View File

@ -454,7 +454,7 @@ void set_timer(ulong t)
timestamp = t;
}
void udelay (unsigned long usec)
void __udelay (unsigned long usec)
{
ulong tmo,tmp;

0
package/uboot-xburst/files/cpu/mips/jz_serial.c → package/uboot-xburst/files/arch/mips/cpu/xburst/jz_serial.c
View File

169
package/uboot-xburst/files/arch/mips/cpu/xburst/start.S Normal file
View File

@ -0,0 +1,169 @@
/*
* Startup Code for MIPS32 XBURST CPU-core
*
* Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#include <asm/jz4740.h>
.set noreorder
.globl _start
.text
_start:
/* Initialize GOT pointer.
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
move gp, ra
lw t1, 0(ra)
move gp, t1
li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la sp, 0(t0)
la t9, board_init_f
j t9
nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
move sp, a0 /* Set new stack pointer */
li t0, TEXT_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
move t1, a2
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - TEXT_BASE) + Destination Address
*/
move t6, gp
sub gp, TEXT_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset*/
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
addu t1, 4 /* delay slot */
/* If caches were enabled, we would have to flush them here.
* flush d-cache */
.set mips32
li t0, KSEG0
addi t1, t0, CONFIG_SYS_DCACHE_SIZE
2:
cache Index_Writeback_Inv_D, 0(t0)
bne t0, t1, 2b
addi t0, CONFIG_SYS_CACHELINE_SIZE
sync
/* flush i-cache */
li t0, KSEG0
addi t1, t0, CONFIG_SYS_ICACHE_SIZE
3:
cache Index_Invalidate_I, 0(t0)
bne t0, t1, 3b
addi t0, CONFIG_SYS_CACHELINE_SIZE
/* Invalidate BTB */
mfc0 t0, CP0_CONFIG, 7
nop
ori t0, 2
mtc0 t0, CP0_CONFIG, 7
nop
.set mips0
/* Jump to where we've relocated ourselves.
*/
addi t0, a2, in_ram - _start
j t0
nop
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT */
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
add t1, t6
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4 /* delay slot */
/* Clear BSS */
lw t1, -12(t0) /* t1 <-- uboot_end_data */
lw t2, -8(t0) /* t2 <-- uboot_end */
add t1, t6 /* adjust pointers */
add t2, t6
sub t1, 4
1: addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
move a0, a1
la t9, board_init_r
j t9
move a1, a2 /* delay slot */
.end relocate_code

63
package/uboot-xburst/files/arch/mips/cpu/xburst/start_spl.S Normal file
View File

@ -0,0 +1,63 @@
/*
* Startup Code for MIPS32 XBURST CPU-core
*
* Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 3 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#include <asm/jz4740.h>
.set noreorder
.globl _start
.text
_start:
.word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
reset:
/*
* STATUS register
* CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
*/
li t0, 0x0040FC04
mtc0 t0, CP0_STATUS
/* CAUSE register
* IV=1, use the specical interrupt vector (0x200) */
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
1:
move gp, ra
lw t1, 0(ra)
move gp, t1
la sp, 0x80004000
la t9, nand_boot
j t9
nop

2
package/uboot-xburst/files/cpu/mips/usb_boot.S → package/uboot-xburst/files/arch/mips/cpu/xburst/usbboot.S
View File

@ -1,7 +1,7 @@
/*
* for jz4740 usb boot
*
* Copyright (c) 2009 Xiangfu Liu <xiangfu.z@gmail.com>
* Copyright (c) 2009 Author: <jlwei@ingenic.cn>
*
* See file CREDITS for list of people who contributed to this
* project.

100
package/uboot-xburst/files/include/asm-mips/jz4740.h → package/uboot-xburst/files/arch/mips/include/asm/jz4740.h
View File

@ -4,22 +4,10 @@
#ifndef __JZ4740_H__
#define __JZ4740_H__
#ifndef __ASSEMBLY__
#define UCOS_CSP 0
#if UCOS_CSP
#define __KERNEL__
#include <bsp.h>
#include <types.h>
#include <sysdefs.h>
#include <cacheops.h>
#define KSEG0 KSEG0BASE
#else
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#endif
#ifndef __ASSEMBLY__
#define cache_unroll(base,op) \
__asm__ __volatile__(" \
.set noreorder; \
@ -57,52 +45,10 @@ static inline void jz_flush_icache(void)
}
}
/* cpu pipeline flush */
static inline void jz_sync(void)
{
__asm__ volatile ("sync");
}
static inline void jz_writeb(u32 address, u8 value)
{
*((volatile u8 *)address) = value;
}
static inline void jz_writew(u32 address, u16 value)
{
*((volatile u16 *)address) = value;
}
static inline void jz_writel(u32 address, u32 value)
{
*((volatile u32 *)address) = value;
}
static inline u8 jz_readb(u32 address)
{
return *((volatile u8 *)address);
}
static inline u16 jz_readw(u32 address)
{
return *((volatile u16 *)address);
}
static inline u32 jz_readl(u32 address)
{
return *((volatile u32 *)address);
}
#define REG8(addr) *((volatile u8 *)(addr))
#define REG16(addr) *((volatile u16 *)(addr))
#define REG32(addr) *((volatile u32 *)(addr))
#else
#define REG8(addr) (addr)
#define REG16(addr) (addr)
#define REG32(addr) (addr)
#endif /* !ASSEMBLY */
/* Boot ROM Specification */
@ -247,7 +193,6 @@ static inline u32 jz_readl(u32 address)
#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
/*************************************************************************
* CPM (Clock reset and Power control Management)
*************************************************************************/
@ -1621,10 +1566,8 @@ static inline u32 jz_readl(u32 address)
#define MSC_CMDAT_IO_ABORT (1 << 11)
#define MSC_CMDAT_BUS_WIDTH_BIT 9
#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
#define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
#define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
#define MSC_CMDAT_DMA_EN (1 << 8)
#define MSC_CMDAT_INIT (1 << 7)
#define MSC_CMDAT_BUSY (1 << 6)
@ -1634,23 +1577,15 @@ static inline u32 jz_readl(u32 address)
#define MSC_CMDAT_DATA_EN (1 << 3)
#define MSC_CMDAT_RESPONSE_BIT 0
#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
#define CMDAT_DMA_EN (1 << 8)
#define CMDAT_INIT (1 << 7)
#define CMDAT_BUSY (1 << 6)
#define CMDAT_STREAM (1 << 5)
#define CMDAT_WRITE (1 << 4)
#define CMDAT_DATA_EN (1 << 3)
#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT)
#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT)
/* MSC Interrupts Mask Register (MSC_IMASK) */
#define MSC_IMASK_SDIO (1 << 7)
#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
@ -1660,7 +1595,6 @@ static inline u32 jz_readl(u32 address)
/* MSC Interrupts Status Register (MSC_IREG) */
#define MSC_IREG_SDIO (1 << 7)
#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
@ -1669,9 +1603,9 @@ static inline u32 jz_readl(u32 address)
#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
/*************************************************************************
/*
* EMC (External Memory Controller)
*************************************************************************/
*/
#define EMC_BCR (EMC_BASE + 0x0) /* BCR */
#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
@ -2810,16 +2744,6 @@ do { \
REG_GPIO_PXPES(3) = 0xc0000000; \
} while (0)
/*
* LCD_D0~LCD_D7, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
*/
#define __gpio_as_lcd_8bit() \
do { \
REG_GPIO_PXFUNS(2) = 0x003c00ff; \
REG_GPIO_PXSELC(2) = 0x003c00ff; \
REG_GPIO_PXPES(2) = 0x003c00ff; \
} while (0)
/*
* LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
*/

4
package/uboot-xburst/files/board/n516/Makefile → package/uboot-xburst/files/board/xburst/n516/Makefile
View File

@ -32,8 +32,8 @@ $(LIB): $(obj).depend $(OBJS) $(SOBJS)
#########################################################################
$(obj).depend: Makefile $(SOBJS:.o=.S) $(COBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(COBJS:.o=.c) > $@
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend

0
package/uboot-xburst/files/board/n516/config.mk → package/uboot-xburst/files/board/xburst/n516/config.mk
View File

0
package/uboot-xburst/files/board/n516/flash.c → package/uboot-xburst/files/board/xburst/n516/flash.c
View File

0
package/uboot-xburst/files/board/n516/n516.c → package/uboot-xburst/files/board/xburst/n516/n516.c
View File

0
package/uboot-xburst/files/board/n516/u-boot-nand.lds → package/uboot-xburst/files/board/xburst/n516/u-boot-nand.lds
View File

0
package/uboot-xburst/files/board/n516/u-boot.lds → package/uboot-xburst/files/board/xburst/n516/u-boot.lds
View File

23
package/uboot-xburst/files/board/nanonote/Makefile → package/uboot-xburst/files/board/xburst/nanonote/Makefile
View File

@ -20,19 +20,26 @@
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
LIB = $(obj)lib$(BOARD).a
OBJS = $(BOARD).o
SOBJS =
COBJS := $(BOARD).o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude .depend
sinclude $(obj).depend
#########################################################################

0
package/uboot-xburst/files/board/nanonote/config.mk → package/uboot-xburst/files/board/xburst/nanonote/config.mk
View File

13
package/uboot-xburst/files/board/nanonote/nanonote.c → package/uboot-xburst/files/board/xburst/nanonote/nanonote.c
View File

@ -24,12 +24,12 @@ static void gpio_init(void)
/*
* Initialize SDRAM pins
*/
__gpio_as_sdram_32bit();
__gpio_as_sdram_16bit_4720();
/*
* Initialize LCD pins
*/
__gpio_as_lcd_8bit();
__gpio_as_lcd_18bit();
/*
* Initialize MSC pins
@ -50,6 +50,9 @@ static void gpio_init(void)
__gpio_clear_pin(GPIO_KEYOUT_BASE + i);
}
/* enable the TP4, TP5 as UART0 */
__gpio_jtag_to_uart0();
/*
* Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the
* same gpio, init the gpio as uart0 cause a keyboard bug. so for
@ -58,10 +61,9 @@ static void gpio_init(void)
if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){
/* if pressed [S] */
printf("[S] pressed, enable UART0\n");
gd->boot_option = 5;
gd->boot_option |= BOOT_WITH_ENABLE_UART;
__gpio_as_uart0();
} else {
printf("[S] not pressed, disable UART0\n");
__gpio_as_input(GPIO_KEYIN_8);
__gpio_enable_pull(GPIO_KEYIN_8);
}
@ -87,7 +89,7 @@ static void gpio_init(void)
if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) {
printf("[M] pressed, boot from sd card\n");
gd->boot_option = 1;
gd->boot_option |= BOOT_FROM_SDCARD;
}
}
@ -115,7 +117,6 @@ void board_early_init(void)
int checkboard (void)
{
printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %d MHz)\n",
gd->cpu_clk / 1000000);

0
package/uboot-xburst/files/board/nanonote/u-boot-nand.lds → package/uboot-xburst/files/board/xburst/nanonote/u-boot-nand.lds
View File

0
package/uboot-xburst/files/board/nanonote/u-boot.lds → package/uboot-xburst/files/board/xburst/nanonote/u-boot.lds
View File

4
package/uboot-xburst/files/board/sakc/Makefile → package/uboot-xburst/files/board/xburst/sakc/Makefile
View File

@ -30,8 +30,8 @@ $(LIB): .depend $(OBJS) $(SOBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude .depend

0
package/uboot-xburst/files/board/sakc/config.mk → package/uboot-xburst/files/board/xburst/sakc/config.mk
View File

0
package/uboot-xburst/files/board/sakc/sakc.c → package/uboot-xburst/files/board/xburst/sakc/sakc.c
View File

0
package/uboot-xburst/files/board/sakc/u-boot-nand.lds → package/uboot-xburst/files/board/xburst/sakc/u-boot-nand.lds
View File

0
package/uboot-xburst/files/board/sakc/u-boot.lds → package/uboot-xburst/files/board/xburst/sakc/u-boot.lds
View File

199
package/uboot-xburst/files/cpu/mips/jz4740_nand.c
View File

@ -1,199 +0,0 @@
/*
* Platform independend driver for JZ4740.
*
* Copyright (c) 2007 Ingenic Semiconductor Inc.
* Author: <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <common.h>
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_JZ4740)
#include <nand.h>
#include <asm/jz4740.h>
#include <asm/io.h>
#define PAR_SIZE 9
#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST )
#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
#define __nand_select_rs_ecc() (REG_EMC_NFECR |= EMC_NFECR_RS)
#define __nand_rs_ecc_encoding() (REG_EMC_NFECR |= EMC_NFECR_RS_ENCODING)
#define __nand_rs_ecc_decoding() (REG_EMC_NFECR |= EMC_NFECR_RS_DECODING)
#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
static void jz_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
/* Change this to use I/O accessors. */
if (ctrl & NAND_NCE)
REG_EMC_NFCSR |= EMC_NFCSR_NFCE1;
else
REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
}
if (cmd == NAND_CMD_NONE)
return;
if (ctrl & NAND_CLE)
nandaddr |= 0x00008000;
else /* must be ALE */
nandaddr |= 0x00010000;
writeb(cmd, (uint8_t *)nandaddr);
}
static int jz_device_ready(struct mtd_info *mtd)
{
int ready;
udelay(20); /* FIXME: add 20us delay */
ready = (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0;
return ready;
}
/*
* EMC setup
*/
static void jz_device_setup(void)
{
/* Set NFE bit */
REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
REG_EMC_SMCR1 = 0x094c4400;
/* REG_EMC_SMCR3 = 0x04444400; */
}
void board_nand_select_device(struct nand_chip *nand, int chip)
{
/*
* Don't use "chip" to address the NAND device,
* generate the cs from the address where it is encoded.
*/
}
static int jzsoc_nand_calculate_rs_ecc(struct mtd_info* mtd, const u_char* dat,
u_char* ecc_code)
{
volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
short i;
__nand_ecc_encode_sync()
__nand_ecc_disable();
for(i = 0; i < PAR_SIZE; i++)
ecc_code[i] = *paraddr++;
return 0;
}
static void jzsoc_nand_enable_rs_hwecc(struct mtd_info* mtd, int mode)
{
__nand_ecc_enable();
__nand_select_rs_ecc();
REG_EMC_NFINTS = 0x0;
if (NAND_ECC_READ == mode){
__nand_rs_ecc_decoding();
}
if (NAND_ECC_WRITE == mode){
__nand_rs_ecc_encoding();
}
}
/* Correct 1~9-bit errors in 512-bytes data */
static void jzsoc_rs_correct(unsigned char *dat, int idx, int mask)
{
int i;
idx--;
i = idx + (idx >> 3);
if (i >= 512)
return;
mask <<= (idx & 0x7);
dat[i] ^= mask & 0xff;
if (i < 511)
dat[i+1] ^= (mask >> 8) & 0xff;
}
static int jzsoc_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
short k;
u32 stat;
/* Set PAR values */
for (k = 0; k < PAR_SIZE; k++) {
*paraddr++ = read_ecc[k];
}
/* Set PRDY */
REG_EMC_NFECR |= EMC_NFECR_PRDY;
/* Wait for completion */
__nand_ecc_decode_sync();
__nand_ecc_disable();
/* Check decoding */
stat = REG_EMC_NFINTS;
if (stat & EMC_NFINTS_ERR) {
if (stat & EMC_NFINTS_UNCOR) {
printk("Uncorrectable error occurred\n");
return -1;
}
else {
u32 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
switch (errcnt) {
case 4:
jzsoc_rs_correct(dat, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 3:
jzsoc_rs_correct(dat, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 2:
jzsoc_rs_correct(dat, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 1:
jzsoc_rs_correct(dat, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
return 0;
default:
break;
}
}
}
/* no error need to be correct */
return 0;
}
/*
* Main initialization routine
*/
int board_nand_init(struct nand_chip *nand)
{
jz_device_setup();
nand->cmd_ctrl = jz_hwcontrol;
nand->dev_ready = jz_device_ready;
/* FIXME: should use NAND_ECC_SOFT */
nand->ecc.hwctl = jzsoc_nand_enable_rs_hwecc;
nand->ecc.correct = jzsoc_nand_rs_correct_data;
nand->ecc.calculate = jzsoc_nand_calculate_rs_ecc;
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = 512;
nand->ecc.bytes = 9;
/* 20 us command delay time */
nand->chip_delay = 20;
return 0;
}
#endif /* (CONFIG_SYS_CMD_NAND) */

484
package/uboot-xburst/files/cpu/mips/jz_lcd.c
View File

@ -1,484 +0,0 @@
/*
* JzRISC lcd controller
*
* xiangfu liu <xiangfu.z@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Fallowing macro may be used:
* CONFIG_LCD : LCD support
* LCD_BPP : Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8
* CONFIG_LCD_LOGO : show logo
*/
#include <config.h>
#include <common.h>
#include <lcd.h>
#include <asm/io.h> /* virt_to_phys() */
#if defined(CONFIG_LCD) && !defined(CONFIG_SLCD)
#if defined(CONFIG_JZ4740)
#include <asm/jz4740.h>
#endif
#include "jz_lcd.h"
struct jzfb_info {
unsigned int cfg; /* panel mode and pin usage etc. */
unsigned int w;
unsigned int h;
unsigned int bpp; /* bit per pixel */
unsigned int fclk; /* frame clk */
unsigned int hsw; /* hsync width, in pclk */
unsigned int vsw; /* vsync width, in line count */
unsigned int elw; /* end of line, in pclk */
unsigned int blw; /* begin of line, in pclk */
unsigned int efw; /* end of frame, in line count */
unsigned int bfw; /* begin of frame, in line count */
};
static struct jzfb_info jzfb = {
#if defined(CONFIG_NANONOTE)
MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
320, 240, 32, 70, 1, 1, 273, 140, 1, 20
#endif
};
/************************************************************************/
vidinfo_t panel_info = {
#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01)
320, 240, LCD_BPP,
#endif
};
/*----------------------------------------------------------------------*/
int lcd_line_length;
int lcd_color_fg;
int lcd_color_bg;
/*
* Frame buffer memory information
*/
void *lcd_base; /* Start of framebuffer memory */
void *lcd_console_address; /* Start of console buffer */
short console_col;
short console_row;
/*----------------------------------------------------------------------*/
void lcd_ctrl_init (void *lcdbase);
void lcd_enable (void);
void lcd_disable (void);
/*----------------------------------------------------------------------*/
static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
static void jz_lcd_desc_init(vidinfo_t *vid);
static int jz_lcd_hw_init( vidinfo_t *vid );
extern int flush_cache_all(void);
#if LCD_BPP == LCD_COLOR8
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
#endif
#if LCD_BPP == LCD_MONOCHROME
void lcd_initcolregs (void);
#endif
/*-----------------------------------------------------------------------*/
void lcd_ctrl_init (void *lcdbase)
{
__lcd_display_pin_init();
jz_lcd_init_mem(lcdbase, &panel_info);
jz_lcd_desc_init(&panel_info);
jz_lcd_hw_init(&panel_info);
__lcd_display_on() ;
}
/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
}
#endif
/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_MONOCHROME
static
void lcd_initcolregs (void)
{
}
#endif
/*
* Before enabled lcd controller, lcd registers should be configured correctly.
*/
void lcd_enable (void)
{
REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
}
void lcd_disable (void)
{
REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
/* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
}
static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
{
u_long palette_mem_size;
struct jz_fb_info *fbi = &vid->jz_fb;
int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
fbi->screen = (u_long)lcdbase;
fbi->palette_size = 256;
palette_mem_size = fbi->palette_size * sizeof(u16);
debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
/* locate palette and descs at end of page following fb */
fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
return 0;
}
static void jz_lcd_desc_init(vidinfo_t *vid)
{
struct jz_fb_info * fbi;
fbi = &vid->jz_fb;
fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
#define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
/* populate descriptors */
fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
fbi->dmadesc_fblow->fidr = 0;
fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
fbi->dmadesc_fbhigh->fidr = 0;
fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
fbi->dmadesc_palette->fidr = 0;
fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
if( NBITS(vid->vl_bpix) < 12)
{
/* assume any mode with <12 bpp is palette driven */
fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
/* flips back and forth between pal and fbhigh */
fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
} else {
/* palette shouldn't be loaded in true-color mode */
fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
}
flush_cache_all();
}
static int jz_lcd_hw_init(vidinfo_t *vid)
{
struct jz_fb_info *fbi = &vid->jz_fb;
unsigned int val = 0;
unsigned int pclk;
unsigned int stnH;
#if defined(CONFIG_MIPS_JZ4740)
int pll_div;
#endif
/* Setting Control register */
switch (jzfb.bpp) {
case 1:
val |= LCD_CTRL_BPP_1;
break;
case 2:
val |= LCD_CTRL_BPP_2;
break;
case 4:
val |= LCD_CTRL_BPP_4;
break;
case 8:
val |= LCD_CTRL_BPP_8;
break;
case 15:
val |= LCD_CTRL_RGB555;
case 16:
val |= LCD_CTRL_BPP_16;
break;
#if defined(CONFIG_MIPS_JZ4740)
case 17 ... 32:
val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
break;
#endif
default:
printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
val |= LCD_CTRL_BPP_16;
break;
}
switch (jzfb.cfg & MODE_MASK) {
case MODE_STN_MONO_DUAL:
case MODE_STN_COLOR_DUAL:
case MODE_STN_MONO_SINGLE:
case MODE_STN_COLOR_SINGLE:
switch (jzfb.bpp) {
case 1:
/* val |= LCD_CTRL_PEDN; */
case 2:
val |= LCD_CTRL_FRC_2;
break;
case 4:
val |= LCD_CTRL_FRC_4;
break;
case 8:
default:
val |= LCD_CTRL_FRC_16;
break;
}
break;
}
val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
switch (jzfb.cfg & MODE_MASK) {
case MODE_STN_MONO_DUAL:
case MODE_STN_COLOR_DUAL:
case MODE_STN_MONO_SINGLE:
case MODE_STN_COLOR_SINGLE:
switch (jzfb.cfg & STN_DAT_PINMASK) {
#define align2(n) (n)=((((n)+1)>>1)<<1)
#define align4(n) (n)=((((n)+3)>>2)<<2)
#define align8(n) (n)=((((n)+7)>>3)<<3)
case STN_DAT_PIN1:
/* Do not adjust the hori-param value. */
break;
case STN_DAT_PIN2:
align2(jzfb.hsw);
align2(jzfb.elw);
align2(jzfb.blw);
break;
case STN_DAT_PIN4:
align4(jzfb.hsw);
align4(jzfb.elw);
align4(jzfb.blw);
break;
case STN_DAT_PIN8:
align8(jzfb.hsw);
align8(jzfb.elw);
align8(jzfb.blw);
break;
}
break;
}
REG_LCD_CTRL = val;
switch (jzfb.cfg & MODE_MASK) {
case MODE_STN_MONO_DUAL:
case MODE_STN_COLOR_DUAL:
case MODE_STN_MONO_SINGLE:
case MODE_STN_COLOR_SINGLE:
if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
stnH = jzfb.h >> 1;
else
stnH = jzfb.h;
REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
/* Screen setting */
REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
REG_LCD_DAV = (0 << 16) | (stnH);
/* AC BIAs signal */
REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
break;
case MODE_TFT_GEN:
case MODE_TFT_SHARP:
case MODE_TFT_CASIO:
case MODE_TFT_SAMSUNG:
case MODE_8BIT_SERIAL_TFT:
case MODE_TFT_18BIT:
REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
REG_LCD_DAV = (0 << 16) | ( jzfb.h );
#else
REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
| (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
break;
}
switch (jzfb.cfg & MODE_MASK) {
case MODE_TFT_SAMSUNG:
{
unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
unsigned int rev_s, rev_e, inv_s, inv_e;
pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
tp_s = jzfb.blw + jzfb.w + 1;
tp_e = tp_s + 1;
/* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
ckv_s = tp_s - pclk/(1000000000/4100);
ckv_e = tp_s + total;
rev_s = tp_s - 11; /* -11.5 clk */
rev_e = rev_s + total;
inv_s = tp_s;
inv_e = inv_s + total;
REG_LCD_CLS = (tp_s << 16) | tp_e;
REG_LCD_PS = (ckv_s << 16) | ckv_e;
REG_LCD_SPL = (rev_s << 16) | rev_e;
REG_LCD_REV = (inv_s << 16) | inv_e;
jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
break;
}
case MODE_TFT_SHARP:
{
unsigned int total, cls_s, cls_e, ps_s, ps_e;
unsigned int spl_s, spl_e, rev_s, rev_e;
total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
#if !defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
spl_s = 1;
spl_e = spl_s + 1;
cls_s = 0;
cls_e = total - 60; /* > 4us (pclk = 80ns) */
ps_s = cls_s;
ps_e = cls_e;
rev_s = total - 40; /* > 3us (pclk = 80ns) */
rev_e = rev_s + total;
jzfb.cfg |= STFT_PSHI;
#else /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
spl_s = total - 5; /* LD */
spl_e = total -3;
cls_s = 32; /* CKV */
cls_e = 145;
ps_s = 0; /* OEV */
ps_e = 45;
rev_s = 0; /* POL */
rev_e = 0;
#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
REG_LCD_SPL = (spl_s << 16) | spl_e;
REG_LCD_CLS = (cls_s << 16) | cls_e;
REG_LCD_PS = (ps_s << 16) | ps_e;
REG_LCD_REV = (rev_s << 16) | rev_e;
break;
}
case MODE_TFT_CASIO:
break;
}
/* Configure the LCD panel */
REG_LCD_CFG = jzfb.cfg;
/* Timing setting */
__cpm_stop_lcd();
val = jzfb.fclk; /* frame clk */
if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
}
else {
/* serial mode: Hsync period = 3*Width_Pixel */
pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
}
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
pclk = (pclk * 3);
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
pclk >>= 1;
pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
pll_div = pll_div ? 1 : 2 ;
val = ( __cpm_get_pllout()/pll_div ) / pclk;
val--;
if ( val > 0x1ff ) {
printf("CPM_LPCDR too large, set it to 0x1ff\n");
val = 0x1ff;
}
__cpm_set_pixdiv(val);
val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
if ( val > 150000000 ) {
printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
printf("Change LCDClock to 150MHz\n");
val = 150000000;
}
val = ( __cpm_get_pllout()/pll_div ) / val;
val--;
if ( val > 0x1f ) {
printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
val = 0x1f;
}
__cpm_set_ldiv( val );
REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
__cpm_start_lcd();
udelay(1000);
REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
return 0;
}

260
package/uboot-xburst/files/cpu/mips/jz_lcd.h
View File

@ -1,260 +0,0 @@
/*
* JzRISC lcd controller
*
* xiangfu liu <xiangfu.z@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __JZLCD_H__
#define __JZLCD_H__
#include <asm/io.h>
/*
* change u-boot macro to celinux macro
*/
/* Chip type */
#if defined(CONFIG_JZ4740)
#define CONFIG_MIPS_JZ4740 1
#endif
/* board type */
#if defined(CONFIG_NANONOTE)
#define CONFIG_MIPS_JZ4740_PI 1
#endif
#define mdelay(n) udelay((n)*1000)
/*
* change u-boot macro to celinux macro
*/
#define NR_PALETTE 256
struct lcd_desc{
unsigned int next_desc; /* LCDDAx */
unsigned int databuf; /* LCDSAx */
unsigned int frame_id; /* LCDFIDx */
unsigned int cmd; /* LCDCMDx */
};
#define MODE_MASK 0x0f
#define MODE_TFT_GEN 0x00
#define MODE_TFT_SHARP 0x01
#define MODE_TFT_CASIO 0x02
#define MODE_TFT_SAMSUNG 0x03
#define MODE_CCIR656_NONINT 0x04
#define MODE_CCIR656_INT 0x05
#define MODE_STN_COLOR_SINGLE 0x08
#define MODE_STN_MONO_SINGLE 0x09
#define MODE_STN_COLOR_DUAL 0x0a
#define MODE_STN_MONO_DUAL 0x0b
#define MODE_8BIT_SERIAL_TFT 0x0c
#define MODE_TFT_18BIT (1<<7)
#define STN_DAT_PIN1 (0x00 << 4)
#define STN_DAT_PIN2 (0x01 << 4)
#define STN_DAT_PIN4 (0x02 << 4)
#define STN_DAT_PIN8 (0x03 << 4)
#define STN_DAT_PINMASK STN_DAT_PIN8
#define STFT_PSHI (1 << 15)
#define STFT_CLSHI (1 << 14)
#define STFT_SPLHI (1 << 13)
#define STFT_REVHI (1 << 12)
#define SYNC_MASTER (0 << 16)
#define SYNC_SLAVE (1 << 16)
#define DE_P (0 << 9)
#define DE_N (1 << 9)
#define PCLK_P (0 << 10)
#define PCLK_N (1 << 10)
#define HSYNC_P (0 << 11)
#define HSYNC_N (1 << 11)
#define VSYNC_P (0 << 8)
#define VSYNC_N (1 << 8)
#define DATA_NORMAL (0 << 17)
#define DATA_INVERSE (1 << 17)
/* Jz LCDFB supported I/O controls. */
#define FBIOSETBACKLIGHT 0x4688
#define FBIODISPON 0x4689
#define FBIODISPOFF 0x468a
#define FBIORESET 0x468b
#define FBIOPRINT_REG 0x468c
/*
* LCD panel specific definition
*/
#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */
#define MODE 0xcd /* 24bit parellel RGB */
#endif
#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
#define MODE 0xc9 /* 8bit serial RGB */
#endif
#if defined(CONFIG_MIPS_JZ4740_PI) /* board pavo */
#define SPEN (32*2+21) /*LCD_SPL */
#define SPCK (32*2+23) /*LCD_CLS */
#define SPDA (32*2+22) /*LCD_D12 */
#define LCD_RET (32*3+27)
#else
#error "cpu/misp/Jzlcd.h, please define SPI pins on your board."
#endif
#define __spi_write_reg1(reg, val) \
do { \
unsigned char no;\
unsigned short value;\
unsigned char a=0;\
unsigned char b=0;\
a=reg;\
b=val;\
__gpio_set_pin(SPEN);\
__gpio_set_pin(SPCK);\
__gpio_clear_pin(SPDA);\
__gpio_clear_pin(SPEN);\
udelay(25);\
value=((a<<8)|(b&0xFF));\
for(no=0;no<16;no++)\
{\
__gpio_clear_pin(SPCK);\
if((value&0x8000)==0x8000)\
__gpio_set_pin(SPDA);\
else\
__gpio_clear_pin(SPDA);\
udelay(25);\
__gpio_set_pin(SPCK);\
value=(value<<1); \
udelay(25);\
}\
__gpio_set_pin(SPEN);\
udelay(100);\
} while (0)
#define __spi_write_reg(reg, val) \
do {\
__spi_write_reg1((reg<<2|2), val);\
udelay(100); \
}while(0)
#define __lcd_special_pin_init() \
do { \
__gpio_as_output(SPEN); /* use SPDA */\
__gpio_as_output(SPCK); /* use SPCK */\
__gpio_as_output(SPDA); /* use SPDA */\
__gpio_as_output(LCD_RET);\
} while (0)
#if defined(CONFIG_NANONOTE)
#define __lcd_special_on() \
do { \
udelay(50);\
__spi_write_reg1(0x05, 0x16); \
__spi_write_reg1(0x04, 0x0b); \
__spi_write_reg1(0x07, 0x8d); \
__spi_write_reg1(0x01, 0x95); \
__spi_write_reg1(0x08, 0xc0); \
__spi_write_reg1(0x03, 0x40); \
__spi_write_reg1(0x06, 0x15); \
__spi_write_reg1(0x05, 0xd7); \
} while (0) /* reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level */
#define __lcd_special_off() \
do { \
__spi_write_reg1(0x05, 0x5e); \
} while (0)
#endif /* CONFIG_NANONOTE */
#endif /* CONFIG_JZLCD_FOXCONN_PT035TN01 or CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL */
#ifndef __lcd_special_pin_init
#define __lcd_special_pin_init()
#endif
#ifndef __lcd_special_on
#define __lcd_special_on()
#endif
#ifndef __lcd_special_off
#define __lcd_special_off()
#endif
/*
* Platform specific definition
*/
#if defined(CONFIG_MIPS_JZ4740_PI)
/* 100 level: 0,1,...,100 */
#define __lcd_set_backlight_level(n)\
do { \
__gpio_as_output(32*3+27); \
__gpio_set_pin(32*3+27); \
} while (0)
#define __lcd_close_backlight() \
do { \
__gpio_as_output(GPIO_PWM); \
__gpio_clear_pin(GPIO_PWM); \
} while (0)
#define __lcd_display_pin_init() \
do { \
__gpio_as_output(GPIO_DISP_OFF_N); \
__cpm_start_tcu(); \
__lcd_special_pin_init(); \
} while (0)
/* __lcd_set_backlight_level(100); \*/
#define __lcd_display_on() \
do { \
__gpio_set_pin(GPIO_DISP_OFF_N); \
__lcd_special_on(); \
} while (0)
#define __lcd_display_off() \
do { \
__lcd_special_off(); \
__gpio_clear_pin(GPIO_DISP_OFF_N); \
} while (0)
#endif /* CONFIG_MIPS_JZ4740_PI) */
/*****************************************************************************
* LCD display pin dummy macros
*****************************************************************************/
#ifndef __lcd_display_pin_init
#define __lcd_display_pin_init()
#endif
#ifndef __lcd_display_on
#define __lcd_display_on()
#endif
#ifndef __lcd_display_off
#define __lcd_display_off()
#endif
#ifndef __lcd_set_backlight_level
#define __lcd_set_backlight_level(n)
#endif

273
package/uboot-xburst/files/cpu/mips/mmc_protocol.h
View File

@ -1,273 +0,0 @@
/*
**********************************************************************
*
* uC/MMC
*
* (c) Copyright 2005 - 2007, Ingenic Semiconductor, Inc
* All rights reserved.
*
***********************************************************************
----------------------------------------------------------------------
File : mmc_protocol.h
Purpose : MMC protocol definitions.
----------------------------------------------------------------------
Version-Date-----Author-Explanation
----------------------------------------------------------------------
1.00.00 20060831 WeiJianli First release
----------------------------------------------------------------------
Known problems or limitations with current version
----------------------------------------------------------------------
(none)
---------------------------END-OF-HEADER------------------------------
*/
#ifndef __MMC_PROTOCOL__
#define __MMC_PROTOCOL__
/* Standard MMC/SD clock speeds */
#define MMC_CLOCK_SLOW 400000 /* 400 kHz for initial setup */
#define MMC_CLOCK_FAST 20000000 /* 20 MHz for maximum for normal operation */
#define SD_CLOCK_FAST 24000000 /* 24 MHz for SD Cards */
/* Extra MMC commands for state control */
/* Use negative numbers to disambiguate */
#define MMC_CIM_RESET -1
/* Standard MMC commands (3.1) type argument response */
/* class 1 */
#define MMC_GO_IDLE_STATE 0 /* bc */
#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
#define MMC_ALL_SEND_CID 2 /* bcr R2 */
#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
#define MMC_SET_DSR 4 /* bc [31:16] RCA */
#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
/* class 2 */
#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
/* class 3 */
#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
/* class 4 */
#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
#define MMC_PROGRAM_CID 26 /* adtc R1 */
#define MMC_PROGRAM_CSD 27 /* adtc R1 */
/* class 6 */
#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
/* class 5 */
#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
#define MMC_ERASE 37 /* ac R1b */
/* class 9 */
#define MMC_FAST_IO 39 /* ac <Complex> R4 */
#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
/* class 7 */
#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
/* class 8 */
#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */
/* SD class */
#define SD_SEND_OP_COND 41 /* bcr [31:0] OCR R3 */
#define SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
#define SEND_SCR 51 /* adtc [31:0] staff R1 */
/* Don't change the order of these; they are used in dispatch tables */
enum mmc_rsp_t {
RESPONSE_NONE = 0,
RESPONSE_R1 = 1,
RESPONSE_R1B = 2,
RESPONSE_R2_CID = 3,
RESPONSE_R2_CSD = 4,
RESPONSE_R3 = 5,
RESPONSE_R4 = 6,
RESPONSE_R5 = 7,
RESPONSE_R6 = 8,
};
/*
MMC status in R1
Type
e : error bit
s : status bit
r : detected and set for the actual command response
x : detected and set during command execution. the host must poll
the card by sending status command in order to read these bits.
Clear condition
a : according to the card state
b : always related to the previous command. Reception of
a valid command will clear it (with a delay of one command)
c : clear by read
*/
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
#define R1_CC_ERROR (1 << 20) /* erx, c */
#define R1_ERROR (1 << 19) /* erx, c */
#define R1_UNDERRUN (1 << 18) /* ex, c */
#define R1_OVERRUN (1 << 17) /* ex, c */
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
#define R1_ERASE_RESET (1 << 13) /* sr, c */
#define R1_STATUS(x) (x & 0xFFFFE000)
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
#define R1_APP_CMD (1 << 7) /* sr, c */
enum card_state {
CARD_STATE_EMPTY = -1,
CARD_STATE_IDLE = 0,
CARD_STATE_READY = 1,
CARD_STATE_IDENT = 2,
CARD_STATE_STBY = 3,
CARD_STATE_TRAN = 4,
CARD_STATE_DATA = 5,
CARD_STATE_RCV = 6,
CARD_STATE_PRG = 7,
CARD_STATE_DIS = 8,
};
/* These are unpacked versions of the actual responses */
struct mmc_response_r1 {
u8 cmd;
u32 status;
};
typedef struct mmc_cid {
u8 mid;
u16 oid;
u8 pnm[7]; /* Product name (we null-terminate) */
u8 prv;
u32 psn;
u8 mdt;
}mmc_cid_t;
typedef struct mmc_csd {
u8 csd_structure;
u8 spec_vers;
u8 taac;
u8 nsac;
u8 tran_speed;
u16 ccc;
u8 read_bl_len;
u8 read_bl_partial;
u8 write_blk_misalign;
u8 read_blk_misalign;
u8 dsr_imp;
u16 c_size;
u8 vdd_r_curr_min;
u8 vdd_r_curr_max;
u8 vdd_w_curr_min;
u8 vdd_w_curr_max;
u8 c_size_mult;
union {
struct { /* MMC system specification version 3.1 */
u8 erase_grp_size;
u8 erase_grp_mult;
} v31;
struct { /* MMC system specification version 2.2 */
u8 sector_size;
u8 erase_grp_size;
} v22;
} erase;
u8 wp_grp_size;
u8 wp_grp_enable;
u8 default_ecc;
u8 r2w_factor;
u8 write_bl_len;
u8 write_bl_partial;
u8 file_format_grp;
u8 copy;
u8 perm_write_protect;
u8 tmp_write_protect;
u8 file_format;
u8 ecc;
}mmc_csd_t;;
struct mmc_response_r3 {
u32 ocr;
};
#define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */
#define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */
#define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */
#define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */
#define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */
#define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */
#define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */
#define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
/* CSD field definitions */
#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 */
#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 */
#if MMC_DEBUG_LEVEL
#define DEBUG(n, args...) \
do { \
if (n <= MMC_DEBUG_LEVEL) { \
printf(args); \
} \
} while(0)
#else
#define DEBUG(n, args...)
#endif /* MMC_DEBUG_EN */
#endif /* __MMC_PROTOCOL__ */

234
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h
View File

@ -1,234 +0,0 @@
/*
* JzRISC lcd controller
*
* xiangfu liu <xiangfu.z@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __QI_LB60_GPM940B0_H__
#define __QI_LB60_GPM940B0_H__
#include <asm/io.h>
#define mdelay(n) udelay((n)*1000)
#define NR_PALETTE 256
struct lcd_desc{
unsigned int next_desc; /* LCDDAx */
unsigned int databuf; /* LCDSAx */
unsigned int frame_id; /* LCDFIDx */
unsigned int cmd; /* LCDCMDx */
};
#define MODE_MASK 0x0f
#define MODE_TFT_GEN 0x00
#define MODE_TFT_SHARP 0x01
#define MODE_TFT_CASIO 0x02
#define MODE_TFT_SAMSUNG 0x03
#define MODE_CCIR656_NONINT 0x04
#define MODE_CCIR656_INT 0x05
#define MODE_STN_COLOR_SINGLE 0x08
#define MODE_STN_MONO_SINGLE 0x09
#define MODE_STN_COLOR_DUAL 0x0a
#define MODE_STN_MONO_DUAL 0x0b
#define MODE_8BIT_SERIAL_TFT 0x0c
#define MODE_TFT_18BIT (1<<7)
#define STN_DAT_PIN1 (0x00 << 4)
#define STN_DAT_PIN2 (0x01 << 4)
#define STN_DAT_PIN4 (0x02 << 4)
#define STN_DAT_PIN8 (0x03 << 4)
#define STN_DAT_PINMASK STN_DAT_PIN8
#define STFT_PSHI (1 << 15)
#define STFT_CLSHI (1 << 14)
#define STFT_SPLHI (1 << 13)
#define STFT_REVHI (1 << 12)
#define SYNC_MASTER (0 << 16)
#define SYNC_SLAVE (1 << 16)
#define DE_P (0 << 9)
#define DE_N (1 << 9)
#define PCLK_P (0 << 10)
#define PCLK_N (1 << 10)
#define HSYNC_P (0 << 11)
#define HSYNC_N (1 << 11)
#define VSYNC_P (0 << 8)
#define VSYNC_N (1 << 8)
#define DATA_NORMAL (0 << 17)
#define DATA_INVERSE (1 << 17)
/* Jz LCDFB supported I/O controls. */
#define FBIOSETBACKLIGHT 0x4688
#define FBIODISPON 0x4689
#define FBIODISPOFF 0x468a
#define FBIORESET 0x468b
#define FBIOPRINT_REG 0x468c
/*
* LCD panel specific definition
*/
#define MODE 0xc9 /* 8bit serial RGB */
#define SPEN (32*2+21) /*LCD_SPL */
#define SPCK (32*2+23) /*LCD_CLS */
#define SPDA (32*2+22) /*LCD_D12 */
#define LCD_RET (32*3+27)
#define __spi_write_reg1(reg, val) \
do { \
unsigned char no;\
unsigned short value;\
unsigned char a=0;\
unsigned char b=0;\
a=reg;\
b=val;\
__gpio_set_pin(SPEN);\
__gpio_set_pin(SPCK);\
__gpio_clear_pin(SPDA);\
__gpio_clear_pin(SPEN);\
udelay(25);\
value=((a<<8)|(b&0xFF));\
for(no=0;no<16;no++)\
{\
__gpio_clear_pin(SPCK);\
if((value&0x8000)==0x8000)\
__gpio_set_pin(SPDA);\
else\
__gpio_clear_pin(SPDA);\
udelay(25);\
__gpio_set_pin(SPCK);\
value=(value<<1); \
udelay(25);\
}\
__gpio_set_pin(SPEN);\
udelay(100);\
} while (0)
#define __spi_write_reg(reg, val) \
do {\
__spi_write_reg1((reg<<2|2), val);\
udelay(100); \
}while(0)
#define __lcd_special_pin_init() \
do { \
__gpio_as_output(SPEN); /* use SPDA */\
__gpio_as_output(SPCK); /* use SPCK */\
__gpio_as_output(SPDA); /* use SPDA */\
__gpio_as_output(LCD_RET);\
} while (0)
#define __lcd_special_on() \
do { \
__spi_write_reg1(0x05, 0x1e); \
udelay(50);\
__spi_write_reg1(0x05, 0x5d); \
__spi_write_reg1(0x0B, 0x81); \
__spi_write_reg1(0x01, 0x95); \
__spi_write_reg1(0x00, 0x07); \
__spi_write_reg1(0x06, 0x15); \
__spi_write_reg1(0x07, 0x8d); \
__spi_write_reg1(0x04, 0x0f); \
__spi_write_reg1(0x0d, 0x3d); \
__spi_write_reg1(0x10, 0x42); \
__spi_write_reg1(0x11, 0x3a); \
__spi_write_reg1(0x05, 0x5f); \
} while (0)
#define __lcd_special_off() \
do { \
__spi_write_reg1(0x05, 0x5e); \
} while (0)
#define __lcd_display_pin_init() \
do { \
__lcd_special_pin_init();\
__gpio_as_pwm();\
__lcd_set_backlight_level(8);\
} while (0)
#define __lcd_display_on() \
do { \
__lcd_set_backlight_level(8); \
__lcd_special_on();\
} while (0)
#define __lcd_display_off() \
do { \
__lcd_set_backlight_level(0); \
__lcd_special_off();\
} while (0)
#define __lcd_set_backlight_level(n)\
do { \
__gpio_as_output(LCD_RET); \
__gpio_set_pin(LCD_RET); \
} while (0)
#if defined(CONFIG_SAKC)
#define __lcd_close_backlight() \
do { \
__gpio_as_output(GPIO_PWM); \
__gpio_clear_pin(GPIO_PWM); \
} while (0)
#endif
#if defined(CONFIG_SAKC)
#define __lcd_display_pin_init() \
do { \
__cpm_start_tcu(); \
__lcd_special_pin_init(); \
} while (0)
#define __lcd_display_on() \
do { \
__lcd_special_on(); \
} while (0)
#define __lcd_display_off() \
do { \
__lcd_special_off(); \
} while (0)
#else
#define __lcd_display_pin_init() \
do { \
__cpm_start_tcu(); \
__lcd_special_pin_init(); \
} while (0)
#define __lcd_display_on() \
do { \
__gpio_set_pin(GPIO_DISP_OFF_N); \
__lcd_special_on(); \
} while (0)
#define __lcd_display_off() \
do { \
__lcd_special_off(); \
__gpio_clear_pin(GPIO_DISP_OFF_N); \
} while (0)
#endif
#endif /* __QI_LB60_GPM940B0_H__ */

582
package/uboot-xburst/files/cpu/mips/jz_mmc.c → package/uboot-xburst/files/drivers/mmc/jz_mmc.c
View File

@ -24,14 +24,28 @@
#include <config.h>
#include <common.h>
#include <part.h>
#include <mmc.h>
#if defined CONFIG_JZ4740
#include <asm-mips/jz4740.h>
#include <asm/jz4740.h>
#include "jz_mmc.h"
#define CFG_MMC_BASE 0x80600000
static int sd2_0 = 0;
static int mmc_ready = 0;
static int use_4bit; /* Use 4-bit data bus */
/*
* MMC Events
*/
#define MMC_EVENT_NONE 0x00 /* No events */
#define MMC_EVENT_RX_DATA_DONE 0x01 /* Rx data done */
#define MMC_EVENT_TX_DATA_DONE 0x02 /* Tx data done */
#define MMC_EVENT_PROG_DONE 0x04 /* Programming is done */
#define MMC_IRQ_MASK() \
do { \
REG_MSC_IMASK = 0xffff; \
REG_MSC_IREG = 0xffff; \
} while (0)
/*
* GPIO definition
@ -76,7 +90,6 @@ do { \
* Local functions
*/
#ifdef CONFIG_MMC
extern int
fat_register_device(block_dev_desc_t *dev_desc, int part_no);
@ -87,29 +100,6 @@ block_dev_desc_t * mmc_get_dev(int dev)
return ((block_dev_desc_t *)&mmc_dev);
}
/*
* FIXME needs to read cid and csd info to determine block size
* and other parameters
*/
static uchar mmc_buf[MMC_BLOCK_SIZE];
static int mmc_ready = 0;
static mmc_csd_t mmc_csd;
static int use_4bit; /* Use 4-bit data bus */
/*
* MMC Events
*/
#define MMC_EVENT_NONE 0x00 /* No events */
#define MMC_EVENT_RX_DATA_DONE 0x01 /* Rx data done */
#define MMC_EVENT_TX_DATA_DONE 0x02 /* Tx data done */
#define MMC_EVENT_PROG_DONE 0x04 /* Programming is done */
#define MMC_IRQ_MASK() \
do { \
REG_MSC_IMASK = 0xffff; \
REG_MSC_IREG = 0xffff; \
} while (0)
/* Stop the MMC clock and wait while it happens */
static inline int jz_mmc_stop_clock(void)
{
@ -119,9 +109,8 @@ static inline int jz_mmc_stop_clock(void)
while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN)) {
timeout--;
if (timeout == 0) {
if (timeout == 0)
return MMC_ERROR_TIMEOUT;
}
udelay(1);
}
return MMC_NO_ERROR;
@ -136,15 +125,14 @@ static inline int jz_mmc_start_clock(void)
static inline u32 jz_mmc_calc_clkrt(int is_sd, u32 rate)
{
u32 clkrt;
u32 clkrt = 0;
u32 clk_src = is_sd ? 24000000 : 16000000;
clkrt = 0;
while (rate < clk_src)
{
while (rate < clk_src) {
clkrt ++;
clk_src >>= 1;
}
return clkrt;
}
@ -186,7 +174,8 @@ static void jz_mmc_get_response(struct mmc_request *request)
u8 *buf;
u32 data;
DEBUG(3, "fetch response for request %d, cmd %d\n", request->rtype, request->cmd);
debug("fetch response for request %d, cmd %d\n",
request->rtype, request->cmd);
buf = request->response;
request->result = MMC_NO_ERROR;
@ -204,7 +193,7 @@ static void jz_mmc_get_response(struct mmc_request *request)
data = REG_MSC_RES;
buf[4] = data & 0xff;
DEBUG(3, "request %d, response [%02x %02x %02x %02x %02x]\n",
debug("request %d, response [%02x %02x %02x %02x %02x]\n",
request->rtype, buf[0], buf[1], buf[2], buf[3], buf[4]);
break;
}
@ -215,7 +204,7 @@ static void jz_mmc_get_response(struct mmc_request *request)
buf[i] = (data >> 8) & 0xff;
buf[i+1] = data & 0xff;
}
DEBUG(3, "request %d, response [", request->rtype);
debug("request %d, response [", request->rtype);
#if CONFIG_MMC_DEBUG_VERBOSE > 2
if (g_mmc_debug >= 3) {
int n;
@ -227,11 +216,11 @@ static void jz_mmc_get_response(struct mmc_request *request)
break;
}
case RESPONSE_NONE:
DEBUG(3, "No response\n");
debug("No response\n");
break;
default:
DEBUG(3, "unhandled response type for request %d\n", request->rtype);
debug("unhandled response type for request %d\n", request->rtype);
break;
}
}
@ -357,8 +346,8 @@ int jz_mmc_exec_cmd(struct mmc_request *request)
/* On reset, stop MMC clock */
jz_mmc_stop_clock();
}
if (request->cmd == MMC_SEND_OP_COND) {
DEBUG(3, "Have an MMC card\n");
if (request->cmd == MMC_CMD_SEND_OP_COND) {
debug("Have an MMC card\n");
/* always use 1bit for MMC */
use_4bit = 0;
}
@ -366,8 +355,7 @@ int jz_mmc_exec_cmd(struct mmc_request *request)
if (request->arg == 0x2) {
printf("Use 4-bit bus width\n");
use_4bit = 1;
}
else {
} else {
printf("Use 1-bit bus width\n");
use_4bit = 0;
}
@ -394,28 +382,28 @@ int jz_mmc_exec_cmd(struct mmc_request *request)
break;
/* bc - broadcast - no response */
case MMC_GO_IDLE_STATE:
case MMC_SET_DSR:
case MMC_CMD_GO_IDLE_STATE:
case MMC_CMD_SET_DSR:
break;
/* bcr - broadcast with response */
case MMC_SEND_OP_COND:
case MMC_ALL_SEND_CID:
case MMC_CMD_SEND_OP_COND:
case MMC_CMD_ALL_SEND_CID:
case MMC_GO_IRQ_STATE:
break;
/* adtc - addressed with data transfer */
case MMC_READ_DAT_UNTIL_STOP:
case MMC_READ_SINGLE_BLOCK:
case MMC_READ_MULTIPLE_BLOCK:
case SEND_SCR:
case MMC_CMD_READ_SINGLE_BLOCK:
case MMC_CMD_READ_MULTIPLE_BLOCK:
case SD_CMD_APP_SEND_SCR:
cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
events = MMC_EVENT_RX_DATA_DONE;
break;
case MMC_WRITE_DAT_UNTIL_STOP:
case MMC_WRITE_BLOCK:
case MMC_WRITE_MULTIPLE_BLOCK:
case MMC_CMD_WRITE_SINGLE_BLOCK:
case MMC_CMD_WRITE_MULTIPLE_BLOCK:
case MMC_PROGRAM_CID:
case MMC_PROGRAM_CSD:
case MMC_SEND_WRITE_PROT:
@ -426,7 +414,7 @@ int jz_mmc_exec_cmd(struct mmc_request *request)
break;
case MMC_STOP_TRANSMISSION:
case MMC_CMD_STOP_TRANSMISSION:
events = MMC_EVENT_PROG_DONE;
break;
@ -468,7 +456,7 @@ int jz_mmc_exec_cmd(struct mmc_request *request)
/* Set command index */
if (request->cmd == MMC_CIM_RESET) {
REG_MSC_CMD = MMC_GO_IDLE_STATE;
REG_MSC_CMD = MMC_CMD_GO_IDLE_STATE;
} else {
REG_MSC_CMD = request->cmd;
}
@ -477,7 +465,7 @@ int jz_mmc_exec_cmd(struct mmc_request *request)
REG_MSC_ARG = request->arg;
/* Set block length and nob */
if (request->cmd == SEND_SCR) { /* get SCR from DataFIFO */
if (request->cmd == SD_CMD_APP_SEND_SCR) { /* get SCR from DataFIFO */
REG_MSC_BLKLEN = 8;
REG_MSC_NOB = 1;
} else {
@ -488,7 +476,7 @@ int jz_mmc_exec_cmd(struct mmc_request *request)
/* Set command */
REG_MSC_CMDAT = cmdat;
DEBUG(1, "Send cmd %d cmdat: %x arg: %x resp %d\n", request->cmd,
debug("Send cmd %d cmdat: %x arg: %x resp %d\n", request->cmd,
cmdat, request->arg, request->rtype);
/* Start MMC/SD clock and send command to card */
@ -520,7 +508,7 @@ int jz_mmc_exec_cmd(struct mmc_request *request)
/* Start data operation */
if (events & (MMC_EVENT_RX_DATA_DONE | MMC_EVENT_TX_DATA_DONE)) {
if (events & MMC_EVENT_RX_DATA_DONE) {
if (request->cmd == SEND_SCR) {
if (request->cmd == SD_CMD_APP_SEND_SCR) {
/* SD card returns SCR register as data.
MMC core expect it in the response buffer,
after normal response. */
@ -556,171 +544,50 @@ int mmc_block_read(u8 *dst, ulong src, ulong len)
struct mmc_request request;
struct mmc_response_r1 r1;
int retval;
int retval = 0;
if (len == 0) {
return 0;
}
mmc_simple_cmd(&request, MMC_SEND_STATUS, mmcinfo.rca, RESPONSE_R1);
if (len == 0)
goto exit;
mmc_simple_cmd(&request, MMC_CMD_SEND_STATUS, mmcinfo.rca, RESPONSE_R1);
retval = mmc_unpack_r1(&request, &r1, 0);
if (retval && (retval != MMC_ERROR_STATE_MISMATCH)) {
if (retval && (retval != MMC_ERROR_STATE_MISMATCH))
goto exit;
mmc_simple_cmd(&request, MMC_CMD_SET_BLOCKLEN, len, RESPONSE_R1);
if (retval = mmc_unpack_r1(&request, &r1, 0))
goto exit;
if (!sd2_0)
src *= mmcinfo.block_len;
mmc_send_cmd(&request, MMC_CMD_READ_SINGLE_BLOCK, src, 1, len, RESPONSE_R1, dst);
if (retval = mmc_unpack_r1(&request, &r1, 0))
goto exit;
exit:
return retval;
}
mmc_simple_cmd(&request, MMC_SET_BLOCKLEN, len, RESPONSE_R1);
if ((retval = mmc_unpack_r1(&request, &r1, 0))) {
return retval;
}
if (sd2_0)
src /= len;
mmc_send_cmd(&request, MMC_READ_SINGLE_BLOCK, src, 1,len, RESPONSE_R1, dst);
if ((retval = mmc_unpack_r1(&request, &r1, 0))) {
return retval;
}
return retval;
}
int mmc_block_write(ulong dst, uchar *src, int len)
ulong mmc_bread(int dev_num, ulong blkstart, ulong blkcnt, ulong *dst)
{
return 0;
}
int mmc_read(ulong src, uchar *dst, int size)
{
ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
ulong mmc_block_size, mmc_block_address;
if (size == 0) {
return 0;
}
if (!mmc_ready) {
printf("MMC card is not ready\n");
printf("Please initial the MMC first\n");
return -1;
}
mmc_block_size = MMC_BLOCK_SIZE;
mmc_block_address = ~(mmc_block_size - 1);
int i = 0;
ulong dst_tmp = dst;
src -= CFG_MMC_BASE;
end = src + size;
part_start = ~mmc_block_address & src;
part_end = ~mmc_block_address & end;
aligned_start = mmc_block_address & src;
aligned_end = mmc_block_address & end;
/* all block aligned accesses */
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
if (part_start) {
part_len = mmc_block_size - part_start;
debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
for (i = 0; i < blkcnt; i++) {
if ((mmc_block_read((uchar *)(dst_tmp), blkstart, mmcinfo.block_len)) < 0)
return -1;
}
memcpy(dst, mmc_buf+part_start, part_len);
dst += part_len;
src += part_len;
}
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) {
return -1;
}
}
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
if (part_end && src < end) {
if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
return -1;
}
memcpy(dst, mmc_buf, part_end);
}
return 0;
dst_tmp += mmcinfo.block_len;
blkstart++;
}
int mmc_write(uchar *src, ulong dst, int size)
{
ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
ulong mmc_block_size, mmc_block_address;
if (size == 0) {
return 0;
}
if (!mmc_ready) {
printf("MMC card is not ready\n");
return -1;
}
mmc_block_size = MMC_BLOCK_SIZE;
mmc_block_address = ~(mmc_block_size - 1);
dst -= CFG_MMC_BASE;
end = dst + size;
part_start = ~mmc_block_address & dst;
part_end = ~mmc_block_address & end;
aligned_start = mmc_block_address & dst;
aligned_end = mmc_block_address & end;
/* all block aligned accesses */
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
if (part_start) {
part_len = mmc_block_size - part_start;
debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
(ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end);
if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
return -1;
}
memcpy(mmc_buf+part_start, src, part_len);
if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) {
return -1;
}
dst += part_len;
src += part_len;
}
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) {
return -1;
}
}
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
if (part_end && dst < end) {
debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
return -1;
}
memcpy(mmc_buf, src, part_end);
if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
return -1;
}
}
return 0;
}
ulong mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst)
{
ulong src;
int mmc_block_size = MMC_BLOCK_SIZE;
src = blknr * mmc_block_size + CFG_MMC_BASE;
mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size);
return blkcnt;
return i;
}
int mmc_select_card(void)
@ -729,14 +596,14 @@ int mmc_select_card(void)
struct mmc_response_r1 r1;
int retval;
mmc_simple_cmd(&request, MMC_SELECT_CARD, mmcinfo.rca, RESPONSE_R1B);
mmc_simple_cmd(&request, MMC_CMD_SELECT_CARD, mmcinfo.rca, RESPONSE_R1B);
retval = mmc_unpack_r1(&request, &r1, 0);
if (retval) {
return retval;
}
if (mmcinfo.sd) {
mmc_simple_cmd(&request, MMC_APP_CMD, mmcinfo.rca, RESPONSE_R1);
mmc_simple_cmd(&request, MMC_CMD_APP_CMD, mmcinfo.rca, RESPONSE_R1);
retval = mmc_unpack_r1(&request,&r1,0);
if (retval) {
return retval;
@ -769,6 +636,20 @@ static void mmc_configure_card(void)
mmcinfo.block_len = 1 << mmcinfo.csd.read_bl_len;
mmc_dev.if_type = IF_TYPE_SD;
mmc_dev.part_type = PART_TYPE_DOS;
mmc_dev.dev = 0;
mmc_dev.lun = 0;
mmc_dev.type = 0;
mmc_dev.blksz = mmcinfo.block_len;
mmc_dev.lba = mmcinfo.block_num;
mmc_dev.removable = 0;
printf("%s Detected: %lu blocks of %lu bytes\n",
sd2_0 == 1 ? "SDHC" : "SD",
mmc_dev.lba,
mmc_dev.blksz);
/* Fix the clock rate */
rate = mmc_tran_speed(mmcinfo.csd.tran_speed);
if (rate < MMC_CLOCK_SLOW)
@ -778,7 +659,8 @@ static void mmc_configure_card(void)
if ((mmcinfo.sd) && (rate > SD_CLOCK_FAST))
rate = SD_CLOCK_FAST;
DEBUG(2,"mmc_configure_card: block_len=%d block_num=%d rate=%d\n", mmcinfo.block_len, mmcinfo.block_num, rate);
debug("%s: block_len=%d block_num=%d rate=%d\n",
__func__, mmcinfo.block_len, mmcinfo.block_num, rate);
jz_mmc_set_clock(mmcinfo.sd, rate);
}
@ -814,147 +696,127 @@ static int mmc_init_card_state(struct mmc_request *request)
int ocr = 0x40300000;
int limit_41 = 0;
DEBUG(2,"mmc_init_card_state\n");
switch (request->cmd) {
case MMC_GO_IDLE_STATE: /* No response to parse */
case MMC_CMD_GO_IDLE_STATE: /* No response to parse */
if (mmcinfo.sd)
mmc_simple_cmd(request, 8, 0x1aa, RESPONSE_R1);
else
mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
mmc_simple_cmd(request, MMC_CMD_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
break;
case 8:
retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
mmc_simple_cmd(request, MMC_APP_CMD, 0, RESPONSE_R1);
mmc_simple_cmd(request, MMC_CMD_APP_CMD, 0, RESPONSE_R1);
break;
case MMC_APP_CMD:
case MMC_CMD_APP_CMD:
retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
if (retval & (limit_41 < 100)) {
DEBUG(0, "mmc_init_card_state: unable to MMC_APP_CMD error=%d (%s)\n",
retval, mmc_result_to_string(retval));
debug("%s: unable to MMC_APP_CMD error=%d (%s)\n",
__func__, retval, mmc_result_to_string(retval));
limit_41++;
mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3);
mmc_simple_cmd(request, SD_CMD_APP_SEND_OP_COND, ocr, RESPONSE_R3);
} else if (limit_41 < 100) {
limit_41++;
mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3);
mmc_simple_cmd(request, SD_CMD_APP_SEND_OP_COND, ocr, RESPONSE_R3);
} else{
/* reset the card to idle*/
mmc_simple_cmd(request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE);
mmc_simple_cmd(request, MMC_CMD_GO_IDLE_STATE, 0, RESPONSE_NONE);
mmcinfo.sd = 0;
}
break;
case SD_SEND_OP_COND:
case SD_CMD_APP_SEND_OP_COND:
retval = mmc_unpack_r3(request, &r3);
if (retval) {
/* Try MMC card */
mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
debug("%s: try MMC card\n", __func__);
mmc_simple_cmd(request, SD_CMD_APP_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
break;
}
DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr);
debug("%s: read ocr value = 0x%08x\n", __func__, r3.ocr);
if(!(r3.ocr & MMC_CARD_BUSY || ocr == 0)){
udelay(10000);
mmc_simple_cmd(request, MMC_APP_CMD, 0, RESPONSE_R1);
}
else {
/* Set the data bus width to 4 bits */
udelay(50000);
mmc_simple_cmd(request, MMC_CMD_APP_CMD, 0, RESPONSE_R1);
} else {
mmcinfo.sd = 1; /* SD Card ready */
mmcinfo.state = CARD_STATE_READY;
mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID);
mmc_simple_cmd(request, MMC_CMD_ALL_SEND_CID, 0, RESPONSE_R2_CID);
}
break;
case MMC_SEND_OP_COND:
case MMC_CMD_SEND_OP_COND:
retval = mmc_unpack_r3(request, &r3);
if (retval) {
DEBUG(0,"mmc_init_card_state: failed SEND_OP_COND error=%d (%s)\n",
retval, mmc_result_to_string(retval));
debug("%s: failed SEND_OP_COND error=%d (%s)\n",
__func__, retval, mmc_result_to_string(retval));
return MMC_INIT_FAILED;
}
DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr);
debug("%s: read ocr value = 0x%08x\n", __func__, r3.ocr);
if (!(r3.ocr & MMC_CARD_BUSY)) {
mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
}
else {
mmc_simple_cmd(request, MMC_CMD_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
} else {
mmcinfo.sd = 0; /* MMC Card ready */
mmcinfo.state = CARD_STATE_READY;
mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID);
mmc_simple_cmd(request, MMC_CMD_ALL_SEND_CID, 0, RESPONSE_R2_CID);
}
break;
case MMC_ALL_SEND_CID:
case MMC_CMD_ALL_SEND_CID:
retval = mmc_unpack_cid( request, &mmcinfo.cid );
mmc_dev.if_type = IF_TYPE_MMC;
mmc_dev.part_type = PART_TYPE_DOS;
mmc_dev.dev = 0;
mmc_dev.lun = 0;
mmc_dev.type = 0;
/* FIXME fill in the correct size (is set to 32MByte) */
mmc_dev.blksz = 512;
mmc_dev.lba = 0x10000;
mmc_dev.removable = 0;
/*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
if ( retval && (retval != MMC_ERROR_CRC)) {
DEBUG(0,"mmc_init_card_state: unable to ALL_SEND_CID error=%d (%s)\n",
debug("mmc_init_card_state: unable to ALL_SEND_CID error=%d (%s)\n",
retval, mmc_result_to_string(retval));
return MMC_INIT_FAILED;
}
mmcinfo.state = CARD_STATE_IDENT;
if(mmcinfo.sd)
mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, 0, RESPONSE_R6);
mmc_simple_cmd(request, MMC_CMD_SET_RELATIVE_ADDR, 0, RESPONSE_R6);
else
mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, ID_TO_RCA(mmcinfo.id) << 16, RESPONSE_R1);
mmc_simple_cmd(request, MMC_CMD_SET_RELATIVE_ADDR, ID_TO_RCA(mmcinfo.id) << 16, RESPONSE_R1);
break;
case MMC_SET_RELATIVE_ADDR:
case MMC_CMD_SET_RELATIVE_ADDR:
if (mmcinfo.sd) {
retval = mmc_unpack_r6(request, &r1, mmcinfo.state, &mmcinfo.rca);
mmcinfo.rca = mmcinfo.rca << 16;
DEBUG(2, "mmc_init_card_state: Get RCA from SD: 0x%04x Status: %x\n", mmcinfo.rca, r1.status);
debug("%s: Get RCA from SD: 0x%04x Status: %x\n",
__func__, mmcinfo.rca, r1.status);
} else {
retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
mmcinfo.rca = ID_TO_RCA(mmcinfo.id) << 16;
}
if (retval) {
DEBUG(0, "mmc_init_card_state: unable to SET_RELATIVE_ADDR error=%d (%s)\n",
retval, mmc_result_to_string(retval));
debug("%s: unable to SET_RELATIVE_ADDR error=%d (%s)\n",
__func__, retval, mmc_result_to_string(retval));
return MMC_INIT_FAILED;
}
mmcinfo.state = CARD_STATE_STBY;
mmc_simple_cmd(request, MMC_SEND_CSD, mmcinfo.rca, RESPONSE_R2_CSD);
mmc_simple_cmd(request, MMC_CMD_SEND_CSD, mmcinfo.rca, RESPONSE_R2_CSD);
break;
case MMC_SEND_CSD:
case MMC_CMD_SEND_CSD:
retval = mmc_unpack_csd(request, &mmcinfo.csd);
mmc_csd_t *csd = (mmc_csd_t *)retval;
memcpy(&mmc_csd, csd, sizeof(csd));
mmc_ready = 1;
printf("MMC card is ready\n");
/* FIXME add verbose printout for csd */
/*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
if (retval && (retval != MMC_ERROR_CRC)) {
DEBUG(0, "mmc_init_card_state: unable to SEND_CSD error=%d (%s)\n",
retval, mmc_result_to_string(retval));
debug("%s: unable to SEND_CSD error=%d (%s)\n",
__func__, retval, mmc_result_to_string(retval));
return MMC_INIT_FAILED;
}
if (mmcinfo.csd.dsr_imp) {
DEBUG(0, "mmc_init_card_state: driver doesn't support setting DSR\n");
debug("%s: driver doesn't support setting DSR\n", __func__);
}
mmc_configure_card();
return MMC_INIT_PASSED;
default:
DEBUG(0, "mmc_init_card_state: error! Illegal last cmd %d\n", request->cmd);
debug("%s: error! Illegal last cmd %d\n", __func__, request->cmd);
return MMC_INIT_FAILED;
}
@ -967,7 +829,7 @@ int mmc_init_card(void)
int retval;
mmc_simple_cmd(&request, MMC_CIM_RESET, 0, RESPONSE_NONE); /* reset card */
mmc_simple_cmd(&request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE);
mmc_simple_cmd(&request, MMC_CMD_GO_IDLE_STATE, 0, RESPONSE_NONE);
mmcinfo.sd = 1; /* assuming a SD card */
while ((retval = mmc_init_card_state(&request)) == MMC_INIT_DOING)
@ -984,11 +846,8 @@ int mmc_legacy_init(int verbose)
if (!__msc_card_detected())
return 1;
printf("MMC card found\n");
/* Step-1: init GPIO */
__gpio_as_msc();
__msc_init_io();
/* Step-2: turn on power of card */
@ -1013,23 +872,9 @@ int mmc_legacy_init(int verbose)
return 0;
}
int mmc_ident(block_dev_desc_t *dev)
{
return 0;
}
int mmc2info(ulong addr)
{
/* FIXME hard codes to 32 MB device */
if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) {
return 1;
}
return 0;
}
/*
* Debugging functions
*/
static char * mmc_result_strings[] = {
"NO_RESPONSE",
"NO_ERROR",
@ -1098,6 +943,9 @@ int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
if (request->result)
return request->result;
if (buf[0] != 0x3f)
return MMC_ERROR_HEADER_MISMATCH;
csd->csd_structure = (buf[1] & 0xc0) >> 6;
if (csd->csd_structure)
sd2_0 = 1;
@ -1105,7 +953,8 @@ int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
sd2_0 = 0;
switch (csd->csd_structure) {
case 0 :
case 0 :/* Version 1.01-1.10
* Version 2.00/Standard Capacity */
csd->taac = buf[2];
csd->nsac = buf[3];
csd->tran_speed = buf[4];
@ -1133,19 +982,8 @@ int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
csd->vdd_w_curr_min = (buf[10] & 0xe0) >> 5;
csd->vdd_w_curr_max = (buf[10] & 0x1c) >> 2;
csd->c_size_mult = ((buf[10] & 0x03) << 1) | ((buf[11] & 0x80) >> 7);
switch (csd->csd_structure) {
case CSD_STRUCT_VER_1_0:
case CSD_STRUCT_VER_1_1:
csd->erase.v22.sector_size = (buf[11] & 0x7c) >> 2;
csd->erase.v22.erase_grp_size = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
break;
case CSD_STRUCT_VER_1_2:
default:
csd->erase.v31.erase_grp_size = (buf[11] & 0x7c) >> 2;
csd->erase.v31.erase_grp_mult = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
break;
}
csd->sector_size = (buf[11] & 0x7c) >> 2;
csd->erase_grp_size = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
csd->wp_grp_size = buf[12] & 0x1f;
csd->wp_grp_enable = (buf[13] & 0x80) ? 1 : 0;
csd->default_ecc = (buf[13] & 0x60) >> 5;
@ -1161,46 +999,8 @@ int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0;
csd->file_format = (buf[15] & 0x0c) >> 2;
csd->ecc = buf[15] & 0x03;
DEBUG(2," csd_structure=%d spec_vers=%d taac=%02x nsac=%02x tran_speed=%02x\n"
" ccc=%04x read_bl_len=%d read_bl_partial=%d write_blk_misalign=%d\n"
" read_blk_misalign=%d dsr_imp=%d c_size=%d vdd_r_curr_min=%d\n"
" vdd_r_curr_max=%d vdd_w_curr_min=%d vdd_w_curr_max=%d c_size_mult=%d\n"
" wp_grp_size=%d wp_grp_enable=%d default_ecc=%d r2w_factor=%d\n"
" write_bl_len=%d write_bl_partial=%d file_format_grp=%d copy=%d\n"
" perm_write_protect=%d tmp_write_protect=%d file_format=%d ecc=%d\n",
csd->csd_structure, csd->spec_vers,
csd->taac, csd->nsac, csd->tran_speed,
csd->ccc, csd->read_bl_len,
csd->read_bl_partial, csd->write_blk_misalign,
csd->read_blk_misalign, csd->dsr_imp,
csd->c_size, csd->vdd_r_curr_min,
csd->vdd_r_curr_max, csd->vdd_w_curr_min,
csd->vdd_w_curr_max, csd->c_size_mult,
csd->wp_grp_size, csd->wp_grp_enable,
csd->default_ecc, csd->r2w_factor,
csd->write_bl_len, csd->write_bl_partial,
csd->file_format_grp, csd->copy,
csd->perm_write_protect, csd->tmp_write_protect,
csd->file_format, csd->ecc);
switch (csd->csd_structure) {
case CSD_STRUCT_VER_1_0:
case CSD_STRUCT_VER_1_1:
DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n",
csd->erase.v22.sector_size,
csd->erase.v22.erase_grp_size);
break;
case CSD_STRUCT_VER_1_2:
default:
DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n",
csd->erase.v31.erase_grp_size,
csd->erase.v31.erase_grp_mult);
break;
}
break;
case 1 :
case 1 : /* Version 2.00/High Capacity */
csd->taac = 0;
csd->nsac = 0;
csd->tran_speed = buf[4];
@ -1212,18 +1012,8 @@ int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
csd->read_blk_misalign = 0;
csd->dsr_imp = (buf[7] & 0x10) ? 1 : 0;
csd->c_size = ((((u16)buf[8]) & 0x3f) << 16) | (((u16)buf[9]) << 8) | ((u16)buf[10]) ;
switch (csd->csd_structure) {
case CSD_STRUCT_VER_1_0:
case CSD_STRUCT_VER_1_1:
csd->erase.v22.sector_size = 0x7f;
csd->erase.v22.erase_grp_size = 0;
break;
case CSD_STRUCT_VER_1_2:
default:
csd->erase.v31.erase_grp_size = 0x7f;
csd->erase.v31.erase_grp_mult = 0;
break;
}
csd->sector_size = 0x7f;
csd->erase_grp_size = 0;
csd->wp_grp_size = 0;
csd->wp_grp_enable = 0;
csd->default_ecc = (buf[13] & 0x60) >> 5;
@ -1237,45 +1027,7 @@ int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0;
csd->file_format = 0;
csd->ecc = buf[15] & 0x03;
DEBUG(2," csd_structure=%d spec_vers=%d taac=%02x nsac=%02x tran_speed=%02x\n"
" ccc=%04x read_bl_len=%d read_bl_partial=%d write_blk_misalign=%d\n"
" read_blk_misalign=%d dsr_imp=%d c_size=%d vdd_r_curr_min=%d\n"
" vdd_r_curr_max=%d vdd_w_curr_min=%d vdd_w_curr_max=%d c_size_mult=%d\n"
" wp_grp_size=%d wp_grp_enable=%d default_ecc=%d r2w_factor=%d\n"
" write_bl_len=%d write_bl_partial=%d file_format_grp=%d copy=%d\n"
" perm_write_protect=%d tmp_write_protect=%d file_format=%d ecc=%d\n",
csd->csd_structure, csd->spec_vers,
csd->taac, csd->nsac, csd->tran_speed,
csd->ccc, csd->read_bl_len,
csd->read_bl_partial, csd->write_blk_misalign,
csd->read_blk_misalign, csd->dsr_imp,
csd->c_size, csd->vdd_r_curr_min,
csd->vdd_r_curr_max, csd->vdd_w_curr_min,
csd->vdd_w_curr_max, csd->c_size_mult,
csd->wp_grp_size, csd->wp_grp_enable,
csd->default_ecc, csd->r2w_factor,
csd->write_bl_len, csd->write_bl_partial,
csd->file_format_grp, csd->copy,
csd->perm_write_protect, csd->tmp_write_protect,
csd->file_format, csd->ecc);
switch (csd->csd_structure) {
case CSD_STRUCT_VER_1_0:
case CSD_STRUCT_VER_1_1:
DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n",
csd->erase.v22.sector_size,
csd->erase.v22.erase_grp_size);
break;
case CSD_STRUCT_VER_1_2:
default:
DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n",
csd->erase.v31.erase_grp_size,
csd->erase.v31.erase_grp_mult);
break;
}
}
if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH;
return 0;
}
@ -1284,12 +1036,13 @@ int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum
{
u8 *buf = request->response;
if (request->result) return request->result;
if (request->result)
return request->result;
r1->cmd = buf[0];
r1->status = PARSE_U32(buf,1);
DEBUG(2, "mmc_unpack_r1: cmd=%d status=%08x\n", r1->cmd, r1->status);
debug("mmc_unpack_r1: cmd=%d status=%08x\n", r1->cmd, r1->status);
if (R1_STATUS(r1->status)) {
if (r1->status & R1_OUT_OF_RANGE) return MMC_ERROR_OUT_OF_RANGE;
@ -1310,7 +1063,8 @@ int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum
if (r1->status & R1_CID_CSD_OVERWRITE) return MMC_ERROR_CID_CSD_OVERWRITE;
}
if (buf[0] != request->cmd) return MMC_ERROR_HEADER_MISMATCH;
if (buf[0] != request->cmd)
return MMC_ERROR_HEADER_MISMATCH;
/* This should be last - it's the least dangerous error */
@ -1320,7 +1074,8 @@ int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum
int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr)
{
u8 *buf = request->response;
if (request->result) return request->result;
if (request->result)
return request->result;
*scr = PARSE_U32(buf, 5); /* Save SCR returned by the SD Card */
return mmc_unpack_r1(request, r1, state);
@ -1331,7 +1086,8 @@ int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum
{
u8 *buf = request->response;
if (request->result) return request->result;
if (request->result)
return request->result;
*rca = PARSE_U16(buf,1); /* Save RCA returned by the SD Card */
@ -1343,26 +1099,34 @@ int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum
int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid)
{
u8 *buf = request->response;
int i;
u8 *buf = request->response;
if (request->result) return request->result;
if (request->result)
return request->result;
cid->mid = buf[1];
cid->oid = PARSE_U16(buf,2);
for (i = 0 ; i < 6 ; i++)
for (i = 0 ; i < 5 ; i++)
cid->pnm[i] = buf[4+i];
cid->pnm[6] = 0;
cid->prv = buf[10];
cid->psn = PARSE_U32(buf,11);
cid->psn = PARSE_U32(buf,10);
cid->mdt = buf[15];
DEBUG(2,"mmc_unpack_cid: mid=%d oid=%d pnm=%s prv=%d.%d psn=%08x mdt=%d/%d\n",
cid->mid, cid->oid, cid->pnm,
(cid->prv>>4), (cid->prv&0xf),
cid->psn, (cid->mdt>>4), (cid->mdt&0xf)+1997);
printf("Man %02x OEM 0x%04x \"%s\" %d.%d 0x%08x "
"Date %02u/%04u\n",
cid->mid,
cid->oid,
cid->pnm,
cid->prv >> 4,
cid->prv & 0xf,
cid->psn,
cid->mdt & 0xf,
(cid->mdt >> 4) + 2000);
if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH;
if (buf[0] != 0x3f)
return MMC_ERROR_HEADER_MISMATCH;
return 0;
}
@ -1370,10 +1134,11 @@ int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3)
{
u8 *buf = request->response;
if (request->result) return request->result;
if (request->result)
return request->result;
r3->ocr = PARSE_U32(buf,1);
DEBUG(2,"mmc_unpack_r3: ocr=%08x\n", r3->ocr);
debug("mmc_unpack_r3: ocr=%08x\n", r3->ocr);
if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH;
return 0;
@ -1391,7 +1156,7 @@ u32 mmc_tran_speed(u8 ts)
u32 rate = ts_exp[(ts & 0x7)] * ts_mul[(ts & 0x78) >> 3];
if (rate <= 0) {
DEBUG(0, "mmc_tran_speed: error - unrecognized speed 0x%02x\n", ts);
debug("%s: error - unrecognized speed 0x%02x\n", __func__, ts);
return 1;
}
@ -1411,6 +1176,3 @@ void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg,
jz_mmc_exec_cmd(request);
}
#endif /* CONFIG_MMC */
#endif /* CONFIG_JZ4740 */

97
package/uboot-xburst/files/cpu/mips/jz_mmc.h → package/uboot-xburst/files/drivers/mmc/jz_mmc.h
View File

@ -13,16 +13,52 @@
#ifndef __MMC_JZMMC_H__
#define __MMC_JZMMC_H__
#include "mmc_protocol.h"
#define MMC_DEBUG_LEVEL 0 /* Enable Debug: 0 - no debug */
#define MMC_BLOCK_SIZE 512 /* MMC/SD Block Size */
#define ID_TO_RCA(x) ((x)+1)
#define MMC_OCR_ARG 0x00ff8000 /* Argument of OCR */
/* Standard MMC/SD clock speeds */
#define MMC_CLOCK_SLOW 400000 /* 400 kHz for initial setup */
#define MMC_CLOCK_FAST 20000000 /* 20 MHz for maximum for normal operation */
#define SD_CLOCK_FAST 24000000 /* 24 MHz for SD Cards */
/* Use negative numbers to disambiguate */
#define MMC_CIM_RESET -1
#define SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
#define R1_CC_ERROR (1 << 20) /* erx, c */
#define R1_ERROR (1 << 19) /* erx, c */
#define R1_UNDERRUN (1 << 18) /* ex, c */
#define R1_OVERRUN (1 << 17) /* ex, c */
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
#define R1_ERASE_RESET (1 << 13) /* sr, c */
#define R1_STATUS(x) (x & 0xFFFFE000)
#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
#define MMC_PROGRAM_CID 26 /* adtc R1 */
#define MMC_PROGRAM_CSD 27 /* adtc R1 */
#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */
#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
enum mmc_result_t {
MMC_NO_RESPONSE = -1,
MMC_NO_ERROR = 0,
@ -49,9 +85,42 @@ enum mmc_result_t {
MMC_ERROR_DRIVER_FAILURE,
};
enum card_state {
CARD_STATE_EMPTY = -1,
CARD_STATE_IDLE = 0,
CARD_STATE_READY = 1,
CARD_STATE_IDENT = 2,
CARD_STATE_STBY = 3,
CARD_STATE_TRAN = 4,
CARD_STATE_DATA = 5,
CARD_STATE_RCV = 6,
CARD_STATE_PRG = 7,
CARD_STATE_DIS = 8,
};
enum mmc_rsp_t {
RESPONSE_NONE = 0,
RESPONSE_R1 = 1,
RESPONSE_R1B = 2,
RESPONSE_R2_CID = 3,
RESPONSE_R2_CSD = 4,
RESPONSE_R3 = 5,
RESPONSE_R4 = 6,
RESPONSE_R5 = 7,
RESPONSE_R6 = 8,
};
struct mmc_response_r1 {
u8 cmd;
u32 status;
};
struct mmc_response_r3 {
u32 ocr;
};
/* the information structure of MMC/SD Card */
typedef struct MMC_INFO
{
struct mmc_info {
int id; /* Card index */
int sd; /* MMC or SD card */
int rca; /* RCA */
@ -65,9 +134,9 @@ typedef struct MMC_INFO
u32 block_num;
u32 block_len;
u32 erase_unit;
} mmc_info;
};
mmc_info mmcinfo;
struct mmc_info mmcinfo;
struct mmc_request {
int index; /* Slot index - used for CS lines */
@ -98,16 +167,10 @@ void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg,
u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer);
u32 mmc_tran_speed(u8 ts);
void jz_mmc_set_clock(int sd, u32 rate);
void jz_mmc_hardware_init(void);
static inline void mmc_simple_cmd(struct mmc_request *request, int cmd, u32 arg, enum mmc_rsp_t rtype)
{
mmc_send_cmd( request, cmd, arg, 0, 0, rtype, 0);
}
int mmc_legacy_init(int verbose);
int mmc_read(ulong src, uchar *dst, int size);
int mmc_write(uchar *src, ulong dst, int size);
int mmc2info(ulong addr);
#endif /* __MMC_JZMMC_H__ */

249
package/uboot-xburst/files/drivers/mtd/nand/jz4740_nand.c Normal file
View File

@ -0,0 +1,249 @@
/*
* Platform independend driver for JZ4740.
*
* Copyright (c) 2007 Ingenic Semiconductor Inc.
* Author: <jlwei@ingenic.cn>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <common.h>
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <asm/io.h>
#include <asm/jz4740.h>
#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST )
#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
#define BIT(x) (1 << (x))
#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
#define JZ_NAND_ECC_CTRL_RS BIT(2)
#define JZ_NAND_ECC_CTRL_RESET BIT(1)
#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
.eccbytes = 72,
.eccpos = {
12, 13, 14, 15, 16, 17, 18, 19,
20, 21, 22, 23, 24, 25, 26, 27,
28, 29, 30, 31, 32, 33, 34, 35,
36, 37, 38, 39, 40, 41, 42, 43,
44, 45, 46, 47, 48, 49, 50, 51,
52, 53, 54, 55, 56, 57, 58, 59,
60, 61, 62, 63, 64, 65, 66, 67,
68, 69, 70, 71, 72, 73, 74, 75,
76, 77, 78, 79, 80, 81, 82, 83},
.oobfree = {
{.offset = 2,
.length = 10},
{.offset = 84,
.length = 44}}
};
static int is_reading;
static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_ALE)
this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
else if (ctrl & NAND_CLE)
this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
else
this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
if (ctrl & NAND_NCE)
REG_EMC_NFCSR |= EMC_NFCSR_NFCE1;
else
REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static int jz_nand_device_ready(struct mtd_info *mtd)
{
udelay(20);
return (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0;
}
void board_nand_select_device(struct nand_chip *nand, int chip)
{
/*
* Don't use "chip" to address the NAND device,
* generate the cs from the address where it is encoded.
*/
}
static int jz_nand_rs_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
u_char* ecc_code)
{
uint32_t reg, status;
int i;
volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
if(is_reading)
return 0;
do {
status = REG_EMC_NFINTS;
} while(!(status & EMC_NFINTS_ENCF));
__nand_ecc_disable();
for(i = 0; i < 9; i++)
ecc_code[i] = *(paraddr + i);
return 0;
}
static void jz_nand_hwctl(struct mtd_info* mtd, int mode)
{
uint32_t reg;
REG_EMC_NFINTS = 0;
reg = REG_EMC_NFECR;
reg |= JZ_NAND_ECC_CTRL_RESET;
reg |= JZ_NAND_ECC_CTRL_ENABLE;
reg |= JZ_NAND_ECC_CTRL_RS;
switch(mode) {
case NAND_ECC_READ:
reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
is_reading = 1;
break;
case NAND_ECC_WRITE:
reg |= JZ_NAND_ECC_CTRL_ENCODING;
is_reading = 0;
break;
default:
break;
}
REG_EMC_NFECR = reg;
}
/* Correct 1~9-bit errors in 512-bytes data */
static void jz_rs_correct(unsigned char *dat, int idx, int mask)
{
int i;
idx--;
i = idx + (idx >> 3);
if (i >= 512)
return;
mask <<= (idx & 0x7);
dat[i] ^= mask & 0xff;
if (i < 511)
dat[i+1] ^= (mask >> 8) & 0xff;
}
static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
int k;
uint32_t reg, status;
volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
/* Set PAR values */
static uint8_t all_ff_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f};
if (read_ecc[0] == 0xff &&
read_ecc[1] == 0xff &&
read_ecc[2] == 0xff &&
read_ecc[3] == 0xff &&
read_ecc[4] == 0xff &&
read_ecc[5] == 0xff &&
read_ecc[6] == 0xff &&
read_ecc[7] == 0xff &&
read_ecc[8] == 0xff) {
for (k = 0; k < 9; k++)
*(paraddr + k) = all_ff_ecc[k];
} else {
for (k = 0; k < 9; k++)
*(paraddr + k) = read_ecc[k];
}
/* Set PRDY */
REG_EMC_NFECR |= EMC_NFECR_PRDY;
/* Wait for completion */
do {
status = REG_EMC_NFINTS;
} while (!(status & EMC_NFINTS_DECF));
__nand_ecc_disable();
/* Check decoding */
if (status & EMC_NFINTS_ERR) {
if (status & EMC_NFINTS_UNCOR) {
printk("uncorrectable ecc\n");
return -1;
}
uint32_t errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
switch (errcnt) {
case 4:
jz_rs_correct(dat,
(REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
(REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 3:
jz_rs_correct(dat,
(REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
(REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 2:
jz_rs_correct(dat,
(REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
(REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
case 1:
jz_rs_correct(dat,
(REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
(REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
return errcnt;
default:
break;
}
}
return 0;
}
/*
* Main initialization routine
*/
int board_nand_init(struct nand_chip *nand)
{
/* EMC setup, Set NFE bit */
REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
REG_EMC_SMCR1 = 0x094c4400;
/* REG_EMC_SMCR3 = 0x04444400; */
nand->IO_ADDR_R = JZ_NAND_DATA_ADDR;
nand->IO_ADDR_W = JZ_NAND_DATA_ADDR;
nand->cmd_ctrl = jz_nand_cmd_ctrl;
nand->dev_ready = jz_nand_device_ready;
nand->ecc.hwctl = jz_nand_hwctl;
nand->ecc.correct = jz_nand_rs_correct_data;
nand->ecc.calculate = jz_nand_rs_calculate_ecc;
nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
nand->ecc.layout = &qi_lb60_ecclayout_2gb;
nand->chip_delay = 50;
return 0;
}
#endif /* (CONFIG_CMD_NAND) */

8
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c → package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.c
View File

@ -1,7 +1,7 @@
/*
* JzRISC lcd controller
*
* xiangfu liu <xiangfu.z@gmail.com>
* Xiangfu Liu <xiangfu@sharism.cc>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -56,7 +56,6 @@ vidinfo_t panel_info = {
};
int lcd_line_length;
int lcd_color_fg;
int lcd_color_bg;
/*
@ -79,19 +78,14 @@ extern int flush_cache_all(void);
void lcd_ctrl_init (void *lcdbase)
{
__lcd_display_pin_init();
jz_lcd_init_mem(lcdbase, &panel_info);
jz_lcd_desc_init(&panel_info);
jz_lcd_hw_init(&panel_info);
__lcd_display_on() ;
}
/*
* Before enabled lcd controller, lcd registers should be configured correctly.
*/
void lcd_enable (void)
{
REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */

135
package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.h Normal file
View File

@ -0,0 +1,135 @@
/*
* JzRISC lcd controller
*
* Xiangfu Liu <xiangfu@sharism.cc>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __QI_LB60_GPM940B0_H__
#define __QI_LB60_GPM940B0_H__
struct lcd_desc{
unsigned int next_desc; /* LCDDAx */
unsigned int databuf; /* LCDSAx */
unsigned int frame_id; /* LCDFIDx */
unsigned int cmd; /* LCDCMDx */
};
#define MODE_MASK 0x0f
#define MODE_TFT_GEN 0x00
#define MODE_TFT_SHARP 0x01
#define MODE_TFT_CASIO 0x02
#define MODE_TFT_SAMSUNG 0x03
#define MODE_CCIR656_NONINT 0x04
#define MODE_CCIR656_INT 0x05
#define MODE_STN_COLOR_SINGLE 0x08
#define MODE_STN_MONO_SINGLE 0x09
#define MODE_STN_COLOR_DUAL 0x0a
#define MODE_STN_MONO_DUAL 0x0b
#define MODE_8BIT_SERIAL_TFT 0x0c
#define MODE_TFT_18BIT (1<<7)
#define STN_DAT_PIN1 (0x00 << 4)
#define STN_DAT_PIN2 (0x01 << 4)
#define STN_DAT_PIN4 (0x02 << 4)
#define STN_DAT_PIN8 (0x03 << 4)
#define STN_DAT_PINMASK STN_DAT_PIN8
#define STFT_PSHI (1 << 15)
#define STFT_CLSHI (1 << 14)
#define STFT_SPLHI (1 << 13)
#define STFT_REVHI (1 << 12)
#define SYNC_MASTER (0 << 16)
#define SYNC_SLAVE (1 << 16)
#define DE_P (0 << 9)
#define DE_N (1 << 9)
#define PCLK_P (0 << 10)
#define PCLK_N (1 << 10)
#define HSYNC_P (0 << 11)
#define HSYNC_N (1 << 11)
#define VSYNC_P (0 << 8)
#define VSYNC_N (1 << 8)
#define DATA_NORMAL (0 << 17)
#define DATA_INVERSE (1 << 17)
/* Jz LCDFB supported I/O controls. */
#define FBIOSETBACKLIGHT 0x4688
#define FBIODISPON 0x4689
#define FBIODISPOFF 0x468a
#define FBIORESET 0x468b
#define FBIOPRINT_REG 0x468c
/*
* LCD panel specific definition
*/
#define MODE (0xc9) /* 8bit serial RGB */
#define __spi_write_reg1(reg, val) \
do { \
unsigned char no; \
unsigned short value; \
unsigned char a=reg; \
unsigned char b=val; \
__gpio_set_pin(SPEN); \
__gpio_set_pin(SPCK); \
__gpio_clear_pin(SPDA); \
__gpio_clear_pin(SPEN); \
value=((a<<8)|(b&0xFF)); \
for(no=0;no<16;no++) \
{ \
__gpio_clear_pin(SPCK); \
if((value&0x8000)==0x8000) \
__gpio_set_pin(SPDA); \
else \
__gpio_clear_pin(SPDA); \
__gpio_set_pin(SPCK); \
value=(value<<1); \
} \
__gpio_set_pin(SPEN); \
} while (0)
#define __lcd_display_pin_init() \
do { \
__cpm_start_tcu(); \
__gpio_as_output(SPEN); /* use SPDA */ \
__gpio_as_output(SPCK); /* use SPCK */ \
__gpio_as_output(SPDA); /* use SPDA */ \
} while (0)
#define __lcd_display_on() \
do { \
__spi_write_reg1(0x05, 0x1e); \
__spi_write_reg1(0x05, 0x5e); \
__spi_write_reg1(0x07, 0x8d); \
__spi_write_reg1(0x13, 0x01); \
__spi_write_reg1(0x05, 0x5f); \
} while (0)
#define __lcd_display_off() \
do { \
__spi_write_reg1(0x05, 0x5e); \
} while (0)
#endif /* __QI_LB60_GPM940B0_H__ */

26
package/uboot-xburst/files/include/configs/avt2.h
View File

@ -1,26 +0,0 @@
#ifndef __CONFIG_AVT2_H
#define __CONFIG_AVT2_H
#include <configs/nanonote.h>
#define CONFIG_AVT2 1
#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait avt2=1"
#define CONFIG_BOOTARGSFROMSD "mem=64M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait avt2=1"
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
/* SDRAM paramters */
#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
#define SDRAM_COL 10 /* Column address: 8 to 12 */
#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
/* SDRAM Timings, unit: ns */
#define SDRAM_TRAS 45 /* RAS# Active Time */
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
#define SDRAM_TPC 20 /* RAS# Precharge Time */
#define SDRAM_TRWL 7 /* Write Latency Time */
#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
#endif /* __CONFIG_AVT_H */

7
package/uboot-xburst/files/include/configs/n516.h
View File

@ -33,6 +33,7 @@
#define CONFIG_JZSOC 1 /* Jz SoC */
#define CONFIG_JZ4740 1 /* Jz4740 SoC */
#define CONFIG_PAVO 1 /* PAVO validation board */
#define CONFIG_NAND_JZ4740
#define CONFIG_BOARD_NAME "n516"
#define CONFIG_BOARD_HWREV "1.0"
@ -128,8 +129,6 @@
/*#define CONFIG_MTD_PARTITIONS*/
#define CONFIG_RBTREE
#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAUL )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#if 0
#define CONFIG_ZERO_BOOTDELAY_CHECK
@ -201,6 +200,7 @@
#define CONFIG_SYS_NAND_BASE 0xB8000000
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 8k from NAND (SPL) into cache and execute it from there.
@ -229,6 +229,9 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
#define CONFIG_SYS_NAND_BADBLOCK_PAGE 63 /* NAND bad block was marked at this page in a block, starting from 0 */
#define CONFIG_SYS_NAND_ECC_POS 6
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 9
#ifdef CONFIG_ENV_IS_IN_NAND
//#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE

43
package/uboot-xburst/files/include/configs/nanonote.h
View File

@ -17,11 +17,17 @@
#define CONFIG_JzRISC 1 /* JzRISC core */
#define CONFIG_JZSOC 1 /* Jz SoC */
#define CONFIG_JZ4740 1 /* Jz4740 SoC */
#define CONFIG_NANONOTE 1
#define CONFIG_NAND_JZ4740
#define CONFIG_JZ4740_MMC
#define CONFIG_NANONOTE
#define BOOT_FROM_SDCARD 1
#define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */
#define CONFIG_LCD 1 /* LCD support */
#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */
#define CONFIG_SYS_WHITE_ON_BLACK 1
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_VIDEO_GPM940B0
#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
@ -38,11 +44,11 @@
#define CONFIG_SKIP_LOWLEVEL_INIT 1
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTFILE "uImage" /* file to load */
/*
* Command line configuration.
*/
@ -62,6 +68,7 @@
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
/*
* Serial download configuration
@ -73,7 +80,7 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "QI# " /* Monitor Command Prompt */
#define CONFIG_SYS_PROMPT "NanoNote# " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print Buffer Size */
@ -96,6 +103,8 @@
/*
* NAND FLASH configuration
*/
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/* NAND Boot config code */
#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
@ -112,11 +121,14 @@
#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
/* ECC offset position in oob area, default value is 6 if it isn't defined */
#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 9
#define CONFIG_SYS_NAND_BASE 0xB8000000
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
/*
* IPL (Initial Program Loader, integrated inside CPU)
@ -143,10 +155,9 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE)
/* environment starts here */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE (4 << 10)
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
/* in board/nanonote/config.mk TEXT_BAS = 0x88000000 */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
@ -167,16 +178,13 @@
* GPIO definition
*/
#define GPIO_LCD_CS (2 * 32 + 21)
#define GPIO_DISP_OFF_N (3 * 32 + 21)
#define GPIO_PWM (3 * 32 + 27)
#define GPIO_AMP_EN (3 * 32 + 4)
#define GPIO_SDPW_EN (3 * 32 + 2)
#define GPIO_SD_DETECT (3 * 32 + 0)
#define GPIO_USB_DETECT (3 * 32 + 27)
#define GPIO_BUZZ_PWM (3 * 32 + 28)
#define GPIO_BUZZ_PWM (3 * 32 + 27)
#define GPIO_USB_DETECT (3 * 32 + 28)
#define GPIO_AUDIO_POP (1 * 32 + 29)
#define GPIO_COB_TEST (1 * 32 + 30)
@ -188,4 +196,7 @@
#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
#define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */
#define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
#define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
#endif /* __CONFIG_NANONOTE_H */

7
package/uboot-xburst/files/include/configs/qi_lb60.h
View File

@ -5,10 +5,11 @@
#define CONFIG_QI_LB60 1
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootwait"
//#define DEBUG
#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
#define CONFIG_BOOTARGSFROMSD "mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
#define CONFIG_BOOTCOMMANDFROMSD "mmc init; fatload mmc 0 0x80600000 uImage; bootm"
#define CONFIG_BOOTCOMMANDFROMSD "mmc init; ext2load mmc 0 0x80600000 /boot/uImage; bootm"
/* SDRAM paramters */
#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */

11
package/uboot-xburst/files/include/configs/sakc.h
View File

@ -17,9 +17,13 @@
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_JzRISC 1 /* JzRISC core */
#define CONFIG_JZSOC 1 /* Jz SoC */
#define CONFIG_JZ4725 1 /* Jz4725 SoC */
#define CONFIG_JZ4740 1 /* Jz4740 SoC */
#define CONFIG_SAKC 1 /* SAKC board */
#define CONFIG_NANONOTE
#define CONFIG_NAND_JZ4740
#define BOOT_FROM_SDCARD 1
#define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */
#define MMC_BUS_WIDTH_1BIT 1 /* 1 for MMC 1Bit Bus Width */
@ -48,7 +52,7 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage" /* file to load */
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
#define CONFIG_EXTRA_ENV_SETTINGS 1
#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
@ -125,6 +129,9 @@
#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
/* ECC offset position in oob area, default value is 6 if it isn't defined */
#define CONFIG_SYS_NAND_ECC_POS (6 * SAKC_NAND_SIZE)
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 9
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xB8000000

17
package/uboot-xburst/files/nand_spl/board/n516/Makefile → package/uboot-xburst/files/nand_spl/board/xburst/n516/Makefile
View File

@ -29,7 +29,7 @@ LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o usb_boot.o
SOBJS = start.o usbboot.o
COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@ -61,27 +61,26 @@ $(nandobj)u-boot-spl: $(OBJS)
-o $(nandobj)u-boot-spl
# create symbolic links for common files
# from cpu directory
$(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S
$(obj)usb_boot.S:
@rm -f $(obj)usb_boot.S
ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
$(obj)usbboot.S:
@rm -f $(obj)usbboot.S
ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $(obj)usbboot.S
$(obj)cpu.c:
@rm -f $(obj)cpu.c
ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $(obj)cpu.c
$(obj)jz4740.c:
@rm -f $(obj)jz4740.c
ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $(obj)jz4740.c
$(obj)jz_serial.c:
@rm -f $(obj)jz_serial.c
ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c
# from nand_spl directory
$(obj)nand_boot_jz4740.c:

0
package/uboot-xburst/files/nand_spl/board/n516/config.mk → package/uboot-xburst/files/nand_spl/board/xburst/n516/config.mk
View File

0
package/uboot-xburst/files/nand_spl/board/n516/u-boot.lds → package/uboot-xburst/files/nand_spl/board/xburst/n516/u-boot.lds
View File

32
package/uboot-xburst/files/nand_spl/board/sakc/Makefile → package/uboot-xburst/files/nand_spl/board/xburst/nanonote/Makefile
View File

@ -22,14 +22,14 @@
#
include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
TEXT_BASE = 0x80000000
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o usb_boot.o
SOBJS = start.o usbboot.o
COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@ -43,11 +43,12 @@ ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
tr '\0' '\377' < /dev/zero | dd bs=1024 count=8 of=$(nandobj)junk1
cat $< $(nandobj)junk1 > $(nandobj)junk2
dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
tr '\0' '\377' < /dev/zero | dd bs=1024 count=256 of=$(nandobj)junk5
cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
rm -f $(nandobj)junk*
@ -61,34 +62,30 @@ $(nandobj)u-boot-spl: $(OBJS)
-o $(nandobj)u-boot-spl
# create symbolic links for common files
# from cpu directory
$(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S
$(obj)usb_boot.S:
@rm -f $(obj)usb_boot.S
ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
$(obj)usbboot.S:
@rm -f $(obj)usbboot.S
ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $(obj)usbboot.S
$(obj)cpu.c:
@rm -f $(obj)cpu.c
ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $(obj)cpu.c
$(obj)jz4740.c:
@rm -f $(obj)jz4740.c
ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $(obj)jz4740.c
$(obj)jz_serial.c:
@rm -f $(obj)jz_serial.c
ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c
# from nand_spl directory
$(obj)nand_boot_jz4740.c:
@rm -f $(obj)nand_boot_jz4740.c
ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
#########################################################################
ln -s $(SRCTREE)/drivers/video/nanonote_gpm940b0.h $(obj)nanonote_gpm940b0.h
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
@ -96,9 +93,6 @@ $(obj)%.o: $(obj)%.S
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

0
package/uboot-xburst/files/nand_spl/board/nanonote/config.mk → package/uboot-xburst/files/nand_spl/board/xburst/nanonote/config.mk
View File

0
package/uboot-xburst/files/nand_spl/board/nanonote/u-boot.lds → package/uboot-xburst/files/nand_spl/board/xburst/nanonote/u-boot.lds
View File

23
package/uboot-xburst/files/nand_spl/board/nanonote/Makefile → package/uboot-xburst/files/nand_spl/board/xburst/sakc/Makefile
View File

@ -29,7 +29,7 @@ LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o usb_boot.o
SOBJS = start.o usbboot.o
COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@ -61,27 +61,32 @@ $(nandobj)u-boot-spl: $(OBJS)
-o $(nandobj)u-boot-spl
# create symbolic links for common files
# from cpu directory
$(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S
$(obj)usb_boot.S:
@rm -f $(obj)usb_boot.S
ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
$(obj)usbboot.S:
@rm -f $(obj)usbboot.S
ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $(obj)usbboot.S
$(obj)cpu.c:
@rm -f $(obj)cpu.c
ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $(obj)cpu.c
$(obj)jz4740.c:
@rm -f $(obj)jz4740.c
ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $(obj)jz4740.c
$(obj)jz_serial.c:
@rm -f $(obj)jz_serial.c
ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c
# from nand_spl directory
$(obj)nand_boot_jz4740.c:
@rm -f $(obj)nand_boot_jz4740.c
ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
# from nand_spl directory
$(obj)nand_boot_jz4740.c:

0
package/uboot-xburst/files/nand_spl/board/sakc/config.mk → package/uboot-xburst/files/nand_spl/board/xburst/sakc/config.mk
View File

0
package/uboot-xburst/files/nand_spl/board/sakc/u-boot.lds → package/uboot-xburst/files/nand_spl/board/xburst/sakc/u-boot.lds
View File

96
package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c
View File

@ -21,8 +21,8 @@
#include <common.h>
#include <nand.h>
#include <asm/io.h>
#include <asm/jz4740.h>
#include "nanonote_gpm940b0.h"
#define KEY_U_OUT (32 * 2 + 16)
#define KEY_U_IN (32 * 3 + 19)
@ -30,15 +30,10 @@
/*
* NAND flash definitions
*/
#define NAND_DATAPORT 0xb8000000
#define NAND_ADDRPORT 0xb8010000
#define NAND_COMMPORT 0xb8008000
#define ECC_BLOCK 512
#define ECC_POS 6
#define PAR_SIZE 9
#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1)
#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
#define __nand_ecc_rs_encoding() \
@ -48,14 +43,6 @@
#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
static inline void __nand_dev_ready(void)
{
unsigned int timeout = 10000;
while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
while (!(REG_GPIO_PXPIN(2) & 0x40000000));
}
#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n))
#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n))
#define __nand_data8() REG8(NAND_DATAPORT)
@ -75,6 +62,13 @@ static inline void __nand_dev_ready(void)
#define NAND_ROW_CYCLE 2
#endif
static inline void __nand_dev_ready(void)
{
unsigned int timeout = 10000;
while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
while (!(REG_GPIO_PXPIN(2) & 0x40000000));
}
/*
* NAND flash parameters
*/
@ -84,7 +78,6 @@ static int ecc_count = 4;
static int page_per_block = 64;
static int bad_block_pos = 0;
static int block_size = 131072;
static unsigned char oob_buf[128] = {0};
/*
@ -167,7 +160,7 @@ static int nand_read_oob(int page_addr, uchar *buf, int size)
/* Send page address */
__nand_addr(page_addr & 0xff);
__nand_addr((page_addr >> 8) & 0xff);
#ifdef NAND_ROW_CYCLE == 3
#if defined NAND_ROW_CYCLE && NAND_ROW_CYCLE == 3
__nand_addr((page_addr >> 16) & 0xff);
#endif
@ -198,7 +191,6 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
/*
* Read page data
*/
/* Send READ0 command */
__nand_cmd(NAND_CMD_READ0);
@ -210,7 +202,7 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
/* Send page address */
__nand_addr(page_addr & 0xff);
__nand_addr((page_addr >> 8) & 0xff);
#if NAND_ROW_CYCLE == 3
#if defined NAND_ROW_CYCLE && NAND_ROW_CYCLE == 3
__nand_addr((page_addr >> 16) & 0xff);
#endif
@ -233,16 +225,11 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
__nand_ecc_rs_decoding();
/* Read data */
nand_read_buf((void *)tmpbuf, ECC_BLOCK);
nand_read_buf((void *)tmpbuf, CONFIG_SYS_NAND_ECCSIZE);
/* Set PAR values */
for (j = 0; j < PAR_SIZE; j++) {
#if defined(CONFIG_SYS_NAND_ECC_POS)
*paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*PAR_SIZE + j];
#else
*paraddr++ = oobbuf[ECC_POS + i*PAR_SIZE + j];
#endif
}
for (j = 0; j < CONFIG_SYS_NAND_ECCBYTES; j++)
*paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*CONFIG_SYS_NAND_ECCBYTES + j];
/* Set PRDY */
REG_EMC_NFECR |= EMC_NFECR_PRDY;
@ -257,12 +244,11 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
stat = REG_EMC_NFINTS;
if (stat & EMC_NFINTS_ERR) {
/* Error occurred */
/* serial_puts("\n Error occurred\n"); */
/* serial_puts("Error occurred\n"); */
if (stat & EMC_NFINTS_UNCOR) {
/* Uncorrectable error occurred */
/* serial_puts("\nUncorrectable error occurred\n"); */
}
else {
/* serial_puts("Uncorrectable error occurred\n"); */
} else {
unsigned int errcnt, index, mask;
errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
@ -292,8 +278,7 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
}
}
}
tmpbuf += ECC_BLOCK;
tmpbuf += CONFIG_SYS_NAND_ECCSIZE;
}
return 0;
@ -333,7 +318,6 @@ static void nand_load(int offs, int uboot_size, uchar *dst)
}
static void jz_nand_init(void) {
/* Optimize the timing of nand */
REG_EMC_SMCR1 = 0x094c4400;
}
@ -343,38 +327,26 @@ static void gpio_init(void)
/*
* Initialize SDRAM pins
*/
#if defined(CONFIG_JZ4720)
__gpio_as_sdram_16bit_4720();
#elif defined(CONFIG_JZ4725)
__gpio_as_sdram_16bit_4725();
#else
__gpio_as_sdram_32bit();
#endif
/*
* Initialize UART0 pins
*/
__gpio_as_uart0();
__gpio_jtag_to_uart0();
}
static int is_usb_boot()
{
int keyU = 0;
__gpio_as_input(KEY_U_IN);
__gpio_enable_pull(KEY_U_IN);
__gpio_as_output(KEY_U_OUT);
__gpio_clear_pin(KEY_U_OUT);
keyU = __gpio_get_pin(KEY_U_IN);
if (__gpio_get_pin(KEY_U_IN) == 0)
return 1;
if (keyU)
serial_puts("[U] not pressed\n");
else
serial_puts("[U] pressed\n");
return !keyU;
return 0;
}
void nand_boot(void)
@ -384,28 +356,30 @@ void nand_boot(void)
/*
* Init hardware
*/
jz_nand_init();
gpio_init();
serial_init();
serial_puts("\n\nNAND Secondary Program Loader\n\n");
pll_init();
__lcd_display_pin_init();
__lcd_display_on() ;
serial_init();
sdram_init();
jz_nand_init();
serial_puts("\nNAND Boot\n");
#if defined(CONFIG_NANONOTE)
if(is_usb_boot()) {
serial_puts("enter USB BOOT mode\n");
serial_puts("[U] pressed, goto USBBOOT mode\n");
usb_boot();
}
#endif
page_size = CONFIG_SYS_NAND_PAGE_SIZE;
block_size = CONFIG_SYS_NAND_BLOCK_SIZE;
page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
bad_block_pos = (page_size == 512) ? 5 : 0;
oob_size = page_size / 32;
ecc_count = page_size / ECC_BLOCK;
ecc_count = page_size / CONFIG_SYS_NAND_ECCSIZE;
/*
* Load U-Boot image from NAND into RAM
@ -417,13 +391,9 @@ void nand_boot(void)
serial_puts("Starting U-Boot ...\n");
/*
* Flush caches
*/
/* Flush caches */
flush_cache_all();
/*
* Jump to U-Boot image
*/
/* Jump to U-Boot image */
(*uboot)();
}

1661
package/uboot-xburst/patches/001-xburst.patch
View File

File diff suppressed because it is too large Load Diff

13
package/uboot-xburst/patches/005-i2c.patch
View File

@ -1,13 +0,0 @@
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index ef32f13..4e234b4 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -36,6 +36,7 @@ COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
+COBJS-$(CONFIG_JZSOC_I2C) += jz_i2c.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)

23
package/uboot-xburst/patches/009-add-n516.patch Normal file
View File

@ -0,0 +1,23 @@
diff --git a/Makefile b/Makefile
index 4ebdb74..5efac12 100644
--- a/Makefile
+++ b/Makefile
@@ -2315,6 +2315,18 @@ qi_lb60_config : unconfig
@echo "TEXT_BASE = 0x80100000" > $(obj)board/xburst/nanonote/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+n516_config : unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_N516 1" >>include/config.h
+ @$(MKCONFIG) -a n516 mips xburst n516 xburst
+
+n516_nand_config: unconfig
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @echo "Compile NAND boot image for n516"
+ @$(MKCONFIG) -a n516 mips xburst n516 xburst
+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/xburst/n516/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
#========================================================================
# Nios
#========================================================================

23
package/uboot-xburst/patches/009-n516.patch
View File

@ -1,23 +0,0 @@
diff --git a/Makefile b/Makefile
index ed848f5..04cd32e 100644
--- a/Makefile
+++ b/Makefile
@@ -3448,6 +3448,18 @@ pavo_nand_config : unconfig
@echo "TEXT_BASE = 0x80100000" > $(obj)board/qi_lb60/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+n516_config : unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_N516 1" >>include/config.h
+ @./mkconfig -a n516 mips mips n516
+
+n516_nand_config : unconfig
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @echo "Compile NAND boot image for n516"
+ @./mkconfig -a n516 mips mips n516
+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/n516/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
#########################################################################
## MIPS64 5Kc
#########################################################################

18
package/uboot-xburst/patches/010-add-sakc.patch Normal file
View File

@ -0,0 +1,18 @@
diff --git a/Makefile b/Makefile
index d71ea8e..8a36045 100644
--- a/Makefile
+++ b/Makefile
@@ -2327,6 +2327,13 @@ n516_nand_config: unconfig
@echo "TEXT_BASE = 0x80100000" > $(obj)board/xburst/n516/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+sakc_config : unconfig
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @echo "Compile NAND boot image for SAKC"
+ @$(MKCONFIG) -a sakc mips xburst sakc xburst
+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/xburst/sakc/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
#========================================================================
# Nios
#========================================================================

32
package/uboot-xburst/patches/010-sakc.patch
View File

@ -1,32 +0,0 @@
diff --git a/Makefile b/Makefile
index a318eb4..7d14b8b 100644
--- a/Makefile
+++ b/Makefile
@@ -3448,6 +3448,13 @@ qi_lb60_config : unconfig
@echo "TEXT_BASE = 0x80100000" > $(obj)board/n516/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+sakc_config : unconfig
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @echo "Compile NAND boot image for SAKC"
+ @$(MKCONFIG) -a sakc mips mips sakc
+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/sakc/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
#########################################################################
## MIPS64 5Kc
#########################################################################
diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile
index 33afb66..a177653 100644
--- a/cpu/mips/Makefile
+++ b/cpu/mips/Makefile
@@ -35,7 +35,7 @@ COBJS-$(CONFIG_PURPLE) += asc_serial.o
COBJS-$(CONFIG_JZSOC) += jz_serial.o jz_i2c.o jz_mmc.o
COBJS-$(CONFIG_JZ4740) += jz4740.o jz4740_nand.o
COBJS-$(CONFIG_NANONOTE) += nanonote_gpm940b0.o
-
+COBJS-$(CONFIG_SAKC) += nanonote_gpm940b0.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

18
package/uboot-xburst/patches/100-fix-c_size.patch Normal file
View File

@ -0,0 +1,18 @@
diff --git a/include/mmc.h b/include/mmc.h
index fcb237e..b913a60 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -189,12 +189,12 @@ struct mmc_csd
u8 tran_speed;
u16 ccc:12,
read_bl_len:4;
+ u32 c_size:22;
u64 read_bl_partial:1,
write_blk_misalign:1,
read_blk_misalign:1,
dsr_imp:1,
rsvd2:2,
- c_size:12,
vdd_r_curr_min:3,
vdd_r_curr_max:3,
vdd_w_curr_min:3,

244
package/uboot-xburst/patches/200-add-more-boot-option.patch Normal file
View File

@ -0,0 +1,244 @@
From 5201aff546faacdf539c03190f1b8ff0de9b2ef8 Mon Sep 17 00:00:00 2001
From: Xiangfu Liu <xiangfu@sharism.cc>
Date: Mon, 7 Feb 2011 14:41:56 +0800
Subject: [PATCH] add-more-boot-option.patch
---
arch/mips/lib/bootm.c | 8 ++++
board/xburst/nanonote/nanonote.c | 81 +++++++++++++++++++++++--------------
common/env_common.c | 6 ---
common/main.c | 8 ++++
include/configs/nanonote.h | 4 ++
include/configs/qi_lb60.h | 15 ++++++-
6 files changed, 82 insertions(+), 40 deletions(-)
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 24a40cc..280e396 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -53,6 +53,14 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
#if defined(CONFIG_NANONOTE)
if (gd->boot_option & BOOT_FROM_SDCARD)
commandline = getenv ("bootargsfromsd");
+ else if (gd->boot_option & BOOT_WITH_F1)
+ commandline = getenv ("bootargsf1");
+ else if (gd->boot_option & BOOT_WITH_F2)
+ commandline = getenv ("bootargsf2");
+ else if (gd->boot_option & BOOT_WITH_F3)
+ commandline = getenv ("bootargsf3");
+ else if (gd->boot_option & BOOT_WITH_F4)
+ commandline = getenv ("bootargsf4");
else
#endif
commandline = getenv ("bootargs");
diff --git a/board/xburst/nanonote/nanonote.c b/board/xburst/nanonote/nanonote.c
index ef9552a..0fc8925 100644
--- a/board/xburst/nanonote/nanonote.c
+++ b/board/xburst/nanonote/nanonote.c
@@ -14,32 +14,12 @@
DECLARE_GLOBAL_DATA_PTR;
-static void gpio_init(void)
+static void boot_option(void)
{
/*
- * Initialize NAND Flash Pins
- */
- __gpio_as_nand();
-
- /*
- * Initialize SDRAM pins
- */
- __gpio_as_sdram_16bit_4720();
-
- /*
- * Initialize LCD pins
- */
- __gpio_as_lcd_18bit();
-
- /*
- * Initialize MSC pins
- */
- __gpio_as_msc();
-
- /*
* Initialize Other pins
*/
- unsigned int i;
+ unsigned int i, j;
for (i = 0; i < 7; i++){
__gpio_as_input(GPIO_KEYIN_BASE + i);
__gpio_enable_pull(GPIO_KEYIN_BASE + i);
@@ -50,16 +30,12 @@ static void gpio_init(void)
__gpio_clear_pin(GPIO_KEYOUT_BASE + i);
}
- /* enable the TP4, TP5 as UART0 */
- __gpio_jtag_to_uart0();
-
/*
* Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the
* same gpio, init the gpio as uart0 cause a keyboard bug. so for
* end user we disable the uart0
*/
if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){
- /* if pressed [S] */
printf("[S] pressed, enable UART0\n");
gd->boot_option |= BOOT_WITH_ENABLE_UART;
__gpio_as_uart0();
@@ -68,6 +44,53 @@ static void gpio_init(void)
__gpio_enable_pull(GPIO_KEYIN_8);
}
+ if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) {
+ printf("[M] pressed, boot from sd card\n");
+ gd->boot_option |= BOOT_FROM_SDCARD;
+ }
+
+ for (j = 0; j < 4; j++) {
+ for (i = 0; i < 4; i++)
+ __gpio_set_pin(GPIO_KEYOUT_BASE + i);
+
+ __gpio_clear_pin(GPIO_KEYOUT_BASE + j);
+
+ if (__gpio_get_pin(GPIO_KEYIN_BASE) == 0) {
+ printf("[F%d] pressed", (j + 1));
+ gd->boot_option |= (1 << (j + 2));
+ /* BOOT_WITH_F1 (1 << 2) */
+ /* BOOT_WITH_F2 (1 << 3) */
+ /* BOOT_WITH_F3 (1 << 4) */
+ /* BOOT_WITH_F4 (1 << 5) */
+ }
+ }
+}
+
+static void gpio_init(void)
+{
+ /*
+ * Initialize NAND Flash Pins
+ */
+ __gpio_as_nand();
+
+ /*
+ * Initialize SDRAM pins
+ */
+ __gpio_as_sdram_16bit_4720();
+
+ /*
+ * Initialize LCD pins
+ */
+ __gpio_as_lcd_18bit();
+
+ /*
+ * Initialize MSC pins
+ */
+ __gpio_as_msc();
+
+ /* enable the TP4, TP5 as UART0 */
+ __gpio_jtag_to_uart0();
+
__gpio_as_output(GPIO_AUDIO_POP);
__gpio_set_pin(GPIO_AUDIO_POP);
@@ -86,11 +109,6 @@ static void gpio_init(void)
__gpio_as_input(GPIO_USB_DETECT);
__gpio_enable_pull(GPIO_USB_DETECT);
-
- if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) {
- printf("[M] pressed, boot from sd card\n");
- gd->boot_option |= BOOT_FROM_SDCARD;
- }
}
static void cpm_init(void)
@@ -111,6 +129,7 @@ void board_early_init(void)
{
gpio_init();
cpm_init();
+ boot_option();
}
/* U-Boot common routines */
diff --git a/common/env_common.c b/common/env_common.c
index 7ac2b6b..439a4a9 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -133,12 +133,6 @@ uchar default_environment[] = {
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0"
#endif
-#ifdef CONFIG_BOOTARGSFROMSD
- "bootargsfromsd=" CONFIG_BOOTARGSFROMSD "\0"
-#endif
-#ifdef CONFIG_BOOTCOMMANDFROMSD
- "bootcmdfromsd=" CONFIG_BOOTCOMMANDFROMSD "\0"
-#endif
#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
diff --git a/common/main.c b/common/main.c
index c64979f..d4f729e 100644
--- a/common/main.c
+++ b/common/main.c
@@ -400,6 +400,14 @@ void main_loop (void)
#if defined(CONFIG_NANONOTE)
if (gd->boot_option & BOOT_FROM_SDCARD)
s = getenv ("bootcmdfromsd");
+ else if (gd->boot_option & BOOT_WITH_F1)
+ s = getenv ("bootcmdf1");
+ else if (gd->boot_option & BOOT_WITH_F2)
+ s = getenv ("bootcmdf2");
+ else if (gd->boot_option & BOOT_WITH_F3)
+ s = getenv ("bootcmdf3");
+ else if (gd->boot_option & BOOT_WITH_F4)
+ s = getenv ("bootcmdf4");
else
#endif
s = getenv ("bootcmd");
diff --git a/include/configs/nanonote.h b/include/configs/nanonote.h
index 6b7d635..dde5cb4 100644
--- a/include/configs/nanonote.h
+++ b/include/configs/nanonote.h
@@ -23,6 +23,10 @@
#define BOOT_FROM_SDCARD 1
#define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */
+#define BOOT_WITH_F1 (1 << 2)
+#define BOOT_WITH_F2 (1 << 3)
+#define BOOT_WITH_F3 (1 << 4)
+#define BOOT_WITH_F4 (1 << 5)
#define CONFIG_LCD 1 /* LCD support */
#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */
diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
index 29ec805..9f08c74 100644
--- a/include/configs/qi_lb60.h
+++ b/include/configs/qi_lb60.h
@@ -6,10 +6,19 @@
#define CONFIG_QI_LB60 1
//#define DEBUG
-#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
-#define CONFIG_BOOTARGSFROMSD "mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
-#define CONFIG_BOOTCOMMANDFROMSD "mmc init; ext2load mmc 0 0x80600000 /boot/uImage; bootm"
+#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootcmdfromsd=mmc init; ext2load mmc 0 0x80600000 /boot/uImage; bootm;\0" \
+ "bootargsfromsd=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait\0" \
+ "bootcmdf1=mmc init; ext2load mmc 0:1 0x80600000 /boot/uImage; bootm;\0" \
+ "bootargsf1=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait\0" \
+ "bootcmdf2=mmc init; ext2load mmc 0:2 0x80600000 /boot/uImage; bootm;\0" \
+ "bootargsf2=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootwait\0" \
+ "bootcmdf3=mmc init; ext2load mmc 0:3 0x80600000 /boot/uImage; bootm;\0" \
+ "bootargsf3=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p3 rw rootwait\0" \
+ "bootcmdf4=mmc init; ext2load mmc 0:4 0x80600000 /boot/uImage; bootm;\0" \
+ "bootargsf4=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p4 rw rootwait\0"
/* SDRAM paramters */
#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
--
1.7.0.4

49
package/uboot-xburst/patches/300-add-ubifs-support.patch Normal file
View File

@ -0,0 +1,49 @@
diff --git a/include/configs/nanonote.h b/include/configs/nanonote.h
index dde5cb4..8e4f6d1 100644
--- a/include/configs/nanonote.h
+++ b/include/configs/nanonote.h
@@ -90,7 +90,7 @@
/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
-#define CONFIG_SYS_MALLOC_LEN 896 * 1024
+#define CONFIG_SYS_MALLOC_LEN 4 * 1024 * 1024
#define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
index 9f08c74..7ed9a1e 100644
--- a/include/configs/qi_lb60.h
+++ b/include/configs/qi_lb60.h
@@ -8,6 +8,20 @@
//#define DEBUG
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
+
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_UBI
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+
+#define MTDIDS_DEFAULT "nand0=jz4740-nand"
+#define MTDPARTS_DEFAULT "mtdparts=jz4740-nand:4M@0(uboot)ro,4M@4M(kernel)ro,512M@8M(rootfs)ro,-(data)ro"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootcmdfromsd=mmc init; ext2load mmc 0 0x80600000 /boot/uImage; bootm;\0" \
"bootargsfromsd=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait\0" \
@@ -17,8 +31,8 @@
"bootargsf2=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootwait\0" \
"bootcmdf3=mmc init; ext2load mmc 0:3 0x80600000 /boot/uImage; bootm;\0" \
"bootargsf3=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p3 rw rootwait\0" \
- "bootcmdf4=mmc init; ext2load mmc 0:4 0x80600000 /boot/uImage; bootm;\0" \
- "bootargsf4=mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p4 rw rootwait\0"
+ "bootcmdf4=mtdparts default;ubi part rootfs;ubifsmount rootfs;ubifsload 0x80600000 /boot/uImage; bootm;\0" \
+ "bootargsf4=mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
/* SDRAM paramters */
#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */