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[toolchain/gcc/4.3.5]: combine all avr32 patches into a single one

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@25566 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
kaloz 2011-02-18 09:25:59 +00:00
parent 12b51493b5
commit 67042730ed
11 changed files with 72 additions and 278 deletions
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100
toolchain/gcc/patches/4.3.5/930-avr32_support.patch
View File

@ -22,7 +22,7 @@
must do it earlier where we know the signedness of the arg. */ must do it earlier where we know the signedness of the arg. */
--- /dev/null --- /dev/null
+++ b/gcc/config/avr32/avr32.c +++ b/gcc/config/avr32/avr32.c
@@ -0,0 +1,7858 @@ @@ -0,0 +1,7869 @@
+/* +/*
+ Target hooks and helper functions for AVR32. + Target hooks and helper functions for AVR32.
+ Copyright 2003-2006 Atmel Corporation. + Copyright 2003-2006 Atmel Corporation.
@ -6526,12 +6526,23 @@
+ continue; + continue;
+ +
+ set = single_set (scan); + set = single_set (scan);
+ if (set && rtx_equal_p (src_reg, SET_DEST (set))) + // Fix for bug #11763 : the following if condition
+ { + // has been modified and else part is included to
+ link = scan; + // set the link to NULL_RTX.
+ break; + // if (set && rtx_equal_p (src_reg, SET_DEST (set)))
+ } + if (set && (REGNO(src_reg) == REGNO(SET_DEST(set))))
+ + {
+ if (rtx_equal_p (src_reg, SET_DEST (set)))
+ {
+ link = scan;
+ break;
+ }
+ else
+ {
+ link = NULL_RTX;
+ break;
+ }
+ }
+ } + }
+ +
+ +
@ -17204,7 +17215,7 @@
+ (set_attr "cc" "none")]) + (set_attr "cc" "none")])
--- /dev/null --- /dev/null
+++ b/gcc/config/avr32/lib1funcs.S +++ b/gcc/config/avr32/lib1funcs.S
@@ -0,0 +1,2874 @@ @@ -0,0 +1,2902 @@
+/* Macro for moving immediate value to register. */ +/* Macro for moving immediate value to register. */
+.macro mov_imm reg, imm +.macro mov_imm reg, imm
+.if (((\imm & 0xfffff) == \imm) || ((\imm | 0xfff00000) == \imm)) +.if (((\imm & 0xfffff) == \imm) || ((\imm | 0xfff00000) == \imm))
@ -18243,6 +18254,7 @@
+ brne __avr32_f64_add_return_nan + brne __avr32_f64_add_return_nan
+ mov r10, 0 /* Generate Inf in r11, r10 */ + mov r10, 0 /* Generate Inf in r11, r10 */
+ mov_imm r11, 0x7ff00000 + mov_imm r11, 0x7ff00000
+ or r11, r12 /* Put sign bit back */
+ ldm sp++, r5, r6, r7, pc/* opL Inf, return Inf */ + ldm sp++, r5, r6, r7, pc/* opL Inf, return Inf */
+__avr32_f64_add_return_nan: +__avr32_f64_add_return_nan:
+ mov r10, -1 /* Generate NaN in r11, r10 */ + mov r10, -1 /* Generate NaN in r11, r10 */
@ -18595,25 +18607,30 @@
+#endif +#endif
+ +
+ /* compare magnitude of op1 and op2 */ + /* compare magnitude of op1 and op2 */
+ st.w --sp, lr
+ st.w --sp, r7
+ lsl r11,1 /* Remove sign bit of op1 */ + lsl r11,1 /* Remove sign bit of op1 */
+ srcs r12 /* Sign op1 to lsb of r12*/ + srcs r12 /* Sign op1 to lsb of r12*/
+ subfeq r10, 0
+ breq 3f /* op1 zero */
+ lsl r9,1 /* Remove sign bit of op2 */ + lsl r9,1 /* Remove sign bit of op2 */
+ srcs r7
+ rol r12 /* Sign op2 to lsb of lr, sign bit op1 bit 1 of r12*/ + rol r12 /* Sign op2 to lsb of lr, sign bit op1 bit 1 of r12*/
+ +
+ +
+ /* Check for Nan */ + /* Check for Nan */
+ pushm lr + mov_imm lr, 0xffe00000
+ mov_imm lr, 0xffe00000
+ cp.w r10,0 + cp.w r10,0
+ cpc r11,lr + cpc r11,lr
+ brhi 0f /* We have NaN */ + brhi 0f /* We have NaN */
+ cp.w r8,0 + cp.w r8,0
+ cpc r9,lr + cpc r9,lr
+ brhi 0f /* We have NaN */ + brhi 0f /* We have NaN */
+ popm lr +
+ + cp.w r11, 0
+ subfeq r10, 0
+ breq 3f /* op1 zero */
+ ld.w r7, sp++
+ ld.w lr, sp++
+
+ cp.w r12,3 /* both operands negative ?*/ + cp.w r12,3 /* both operands negative ?*/
+ breq 1f + breq 1f
+ +
@ -18659,18 +18676,22 @@
+#endif +#endif
+ +
+0: +0:
+ ld.w r7, sp++
+ popm pc, r12=0 + popm pc, r12=0
+#endif +#endif
+ +
+3: +3:
+ lsl r9,1 /* Remove sign bit of op1 */ + cp.w r7, 1 /* Check sign bit from r9 */
+#ifdef L_avr32_f64_cmp_ge +#ifdef L_avr32_f64_cmp_ge
+ srcs r12 /* If op2 is negative then op1 >= op2. */ + sreq r12 /* If op2 is negative then op1 >= op2. */
+#endif +#endif
+#ifdef L_avr32_f64_cmp_lt +#ifdef L_avr32_f64_cmp_lt
+ srcc r12 /* If op2 is positve then op1 <= op2. */ + srne r12 /* If op2 is positve then op1 <= op2. */
+#endif +#endif
+ subfeq r8, 0 + cp.w r9, 0
+ subfeq r8, 0
+ ld.w r7, sp++
+ ld.w lr, sp++
+#ifdef L_avr32_f64_cmp_ge +#ifdef L_avr32_f64_cmp_ge
+ reteq 1 /* Both operands are zero. Return true. */ + reteq 1 /* Both operands are zero. Return true. */
+#endif +#endif
@ -18930,7 +18951,7 @@
+ brne 16f /* Return NaN if op1 is NaN */ + brne 16f /* Return NaN if op1 is NaN */
+ /* Op1 is inf check op2 */ + /* Op1 is inf check op2 */
+ lsr r6, r9, 20 /* Extract exponent */ + lsr r6, r9, 20 /* Extract exponent */
+ cbr r6, 8 /* Clear sign bit */ + cbr r6, 11 /* Clear sign bit */
+ cp r6, 0x7ff + cp r6, 0x7ff
+ brne 17f /* Inf/number gives inf, return inf */ + brne 17f /* Inf/number gives inf, return inf */
+ rjmp 16f /* The rest gives NaN*/ + rjmp 16f /* The rest gives NaN*/
@ -19046,10 +19067,14 @@
+ +
+16: /* Return NaN. */ +16: /* Return NaN. */
+ mov r11, -1 + mov r11, -1
+ mov r10, -1 + mov r10, 0
+ ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
+ +
+17: /* Return INF. */ +17:
+ /* Check if op1 is zero. */
+ or r4, r10, r11
+ breq __avr32_f64_div_op1_zero
+ /* Return INF. */
+ mov r11, lr /*Get correct sign*/ + mov r11, lr /*Get correct sign*/
+ andh r11, 0x8000, COH + andh r11, 0x8000, COH
+ orh r11, 0x7ff0 + orh r11, 0x7ff0
@ -19463,10 +19488,13 @@
+ +
+ /* Unpack */ + /* Unpack */
+ lsl r12,1 + lsl r12,1
+ reteq 0 /* Return zero if op1 is zero */
+ lsl r11,1 + lsl r11,1
+ breq 4f /* Check op2 for zero */ + breq 4f /* Check op2 for zero */
+ +
+ tst r12, r12
+ moveq r9, 0
+ breq 12f
+
+ /* Unpack op1*/ + /* Unpack op1*/
+ /* exp: r9 */ + /* exp: r9 */
+ /* sf: r12 */ + /* sf: r12 */
@ -19485,9 +19513,14 @@
+ breq 13f /*If number is subnormal*/ + breq 13f /*If number is subnormal*/
+ cp r10, 0xff + cp r10, 0xff
+ brhs 3f /* Check op2 for NaN or Inf */ + brhs 3f /* Check op2 for NaN or Inf */
+
+ lsl r11,7 + lsl r11,7
+ sbr r11, 31 /*Implicit bit*/ + sbr r11, 31 /*Implicit bit*/
+
+ cp.w r9, 0
+ subfeq r12, 0
+ reteq 0 /* op1 is zero and op2 is not zero */
+ /* or NaN so return zero */
+
+14: +14:
+ +
+ /* For UC3, store with predecrement is faster than stm */ + /* For UC3, store with predecrement is faster than stm */
@ -19656,9 +19689,14 @@
+ reteq 0 /* Return zero if number/inf*/ + reteq 0 /* Return zero if number/inf*/
+ ret -1 /* Return NaN*/ + ret -1 /* Return NaN*/
+4: +4:
+ /* Op2 is zero ? */ + /* Op1 is zero ? */
+ tst r12,r12 + tst r12,r12
+ reteq -1 /* 0.0/0.0 is NaN */ + reteq -1 /* 0.0/0.0 is NaN */
+ /* Op1 is Nan? */
+ lsr r9, r12, 24
+ breq 11f /*If number is subnormal*/
+ cp r9, 0xff
+ brhs 2b /* Check op1 for NaN or Inf */
+ /* Nonzero/0.0 is Inf. Sign bit will be shifted in before returning*/ + /* Nonzero/0.0 is Inf. Sign bit will be shifted in before returning*/
+ mov_imm r12, 0xff000000 + mov_imm r12, 0xff000000
+ rjmp __divsf_return_op1 + rjmp __divsf_return_op1
@ -20007,6 +20045,7 @@
+ lsl r11,8 /* check mantissa */ + lsl r11,8 /* check mantissa */
+ movne r11, -1 /* Return NaN */ + movne r11, -1 /* Return NaN */
+ moveq r11, r10 /* Return inf */ + moveq r11, r10 /* Return inf */
+ mov r10, 0
+ rjmp __extendsfdf_return_op1 + rjmp __extendsfdf_return_op1
+#endif +#endif
+ +
@ -20054,7 +20093,7 @@
+ /* NaN or inf */ + /* NaN or inf */
+ cbr r12,31 /* clear implicit bit */ + cbr r12,31 /* clear implicit bit */
+ retne -1 /* Return NaN if mantissa not zero */ + retne -1 /* Return NaN if mantissa not zero */
+ mov_imm r12, 0xff000000 + mov_imm r12, 0x7f800000
+ ret r12 /* Return inf */ + ret r12 /* Return inf */
+ +
+3: /* Result is subnormal. Adjust it.*/ +3: /* Result is subnormal. Adjust it.*/
@ -21297,7 +21336,7 @@
;; ;;
+avr32*-*-linux*) +avr32*-*-linux*)
+ tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/avr32.h " + tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/avr32.h "
+ tmake_file="t-linux avr32/t-avr32 avr32/t-elf" + tmake_file="t-linux avr32/t-avr32-linux"
+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" + extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
+ extra_modes=avr32/avr32-modes.def + extra_modes=avr32/avr32-modes.def
+ gnu_ld=yes + gnu_ld=yes
@ -22294,10 +22333,15 @@
// different sentry variables for construction and destruction. // different sentry variables for construction and destruction.
--- a/libgcc/config.host --- a/libgcc/config.host
+++ b/libgcc/config.host +++ b/libgcc/config.host
@@ -240,6 +240,8 @@ arm-*-pe*) @@ -240,6 +240,13 @@ arm-*-pe*)
;; ;;
arm*-*-kaos*) arm*-*-kaos*)
;; ;;
+avr32-*-linux*)
+ # No need to build crtbeginT.o on uClibc systems. Should probably be
+ # moved to the OS specific section above.
+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
+ ;;
+avr32-*-*) +avr32-*-*)
+ ;; + ;;
avr-*-rtems*) avr-*-rtems*)

25
toolchain/gcc/patches/4.3.5/939-avr32_fix_linux_build.patch
View File

@ -1,25 +0,0 @@
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -836,7 +836,7 @@ avr-*-*)
;;
avr32*-*-linux*)
tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/avr32.h "
- tmake_file="t-linux avr32/t-avr32 avr32/t-elf"
+ tmake_file="t-linux avr32/t-avr32-linux"
extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
extra_modes=avr32/avr32-modes.def
gnu_ld=yes
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -240,6 +240,11 @@ arm-*-pe*)
;;
arm*-*-kaos*)
;;
+avr32-*-linux*)
+ # No need to build crtbeginT.o on uClibc systems. Should probably be
+ # moved to the OS specific section above.
+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
+ ;;
avr32-*-*)
;;
avr-*-rtems*)

10
toolchain/gcc/patches/4.3.5/940-avr32_fix_f32_to_f64.patch
View File

@ -1,10 +0,0 @@
--- a/gcc/config/avr32/lib1funcs.S
+++ b/gcc/config/avr32/lib1funcs.S
@@ -2800,6 +2800,7 @@ __extendsfdf_return_op1:
lsl r11,8 /* check mantissa */
movne r11, -1 /* Return NaN */
moveq r11, r10 /* Return inf */
+ mov r10, 0
rjmp __extendsfdf_return_op1
#endif

10
toolchain/gcc/patches/4.3.5/941-avr32_fix_f64_add.patch
View File

@ -1,10 +0,0 @@
--- a/gcc/config/avr32/lib1funcs.S
+++ b/gcc/config/avr32/lib1funcs.S
@@ -1036,6 +1036,7 @@ __avr32_f64_add_opL_nan_or_inf:
brne __avr32_f64_add_return_nan
mov r10, 0 /* Generate Inf in r11, r10 */
mov_imm r11, 0x7ff00000
+ or r11, r12 /* Put sign bit back */
ldm sp++, r5, r6, r7, pc/* opL Inf, return Inf */
__avr32_f64_add_return_nan:
mov r10, -1 /* Generate NaN in r11, r10 */

34
toolchain/gcc/patches/4.3.5/942-avr32_fix_32bit_div.patch
View File

@ -1,34 +0,0 @@
--- a/gcc/config/avr32/lib1funcs.S
+++ b/gcc/config/avr32/lib1funcs.S
@@ -2257,10 +2257,13 @@ __avr32_f32_div:
/* Unpack */
lsl r12,1
- reteq 0 /* Return zero if op1 is zero */
lsl r11,1
breq 4f /* Check op2 for zero */
-
+
+ tst r12, r12
+ moveq r9, 0
+ breq 12
+
/* Unpack op1*/
/* exp: r9 */
/* sf: r12 */
@@ -2279,9 +2282,14 @@ __avr32_f32_div:
breq 13f /*If number is subnormal*/
cp r10, 0xff
brhs 3f /* Check op2 for NaN or Inf */
-
lsl r11,7
sbr r11, 31 /*Implicit bit*/
+
+ cp.w r9, 0
+ subfeq r12, 0
+ reteq 0 /* op1 is zero and op2 is not zero */
+ /* or NaN so return zero */
+
14:
/* For UC3, store with predecrement is faster than stm */

66
toolchain/gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch
View File

@ -1,66 +0,0 @@
--- a/gcc/config/avr32/lib1funcs.S
+++ b/gcc/config/avr32/lib1funcs.S
@@ -1389,25 +1389,30 @@ __avr32_f64_cmp_lt:
#endif
/* compare magnitude of op1 and op2 */
+ st.w --sp, lr
+ st.w --sp, r7
lsl r11,1 /* Remove sign bit of op1 */
srcs r12 /* Sign op1 to lsb of r12*/
- subfeq r10, 0
- breq 3f /* op1 zero */
lsl r9,1 /* Remove sign bit of op2 */
+ srcs r7
rol r12 /* Sign op2 to lsb of lr, sign bit op1 bit 1 of r12*/
/* Check for Nan */
- pushm lr
- mov_imm lr, 0xffe00000
+ mov_imm lr, 0xffe00000
cp.w r10,0
cpc r11,lr
brhi 0f /* We have NaN */
cp.w r8,0
cpc r9,lr
brhi 0f /* We have NaN */
- popm lr
-
+
+ cp.w r11, 0
+ subfeq r10, 0
+ breq 3f /* op1 zero */
+ ld.w r7, sp++
+ ld.w lr, sp++
+
cp.w r12,3 /* both operands negative ?*/
breq 1f
@@ -1453,18 +1458,22 @@ __avr32_f64_cmp_lt:
#endif
0:
+ ld.w r7, sp++
popm pc, r12=0
#endif
3:
- lsl r9,1 /* Remove sign bit of op1 */
+ cp.w r7, 1 /* Check sign bit from r9 */
#ifdef L_avr32_f64_cmp_ge
- srcs r12 /* If op2 is negative then op1 >= op2. */
+ sreq r12 /* If op2 is negative then op1 >= op2. */
#endif
#ifdef L_avr32_f64_cmp_lt
- srcc r12 /* If op2 is positve then op1 <= op2. */
+ srne r12 /* If op2 is positve then op1 <= op2. */
#endif
- subfeq r8, 0
+ cp.w r9, 0
+ subfeq r8, 0
+ ld.w r7, sp++
+ ld.w lr, sp++
#ifdef L_avr32_f64_cmp_ge
reteq 1 /* Both operands are zero. Return true. */
#endif

20
toolchain/gcc/patches/4.3.5/944-avr32_fix_f64_div.patch
View File

@ -1,20 +0,0 @@
--- a/gcc/config/avr32/lib1funcs.S
+++ b/gcc/config/avr32/lib1funcs.S
@@ -1733,7 +1733,7 @@ __avr32_f64_div_round_subnormal:
brne 16f /* Return NaN if op1 is NaN */
/* Op1 is inf check op2 */
lsr r6, r9, 20 /* Extract exponent */
- cbr r6, 8 /* Clear sign bit */
+ cbr r6, 11 /* Clear sign bit */
cp r6, 0x7ff
brne 17f /* Inf/number gives inf, return inf */
rjmp 16f /* The rest gives NaN*/
@@ -1849,7 +1849,7 @@ __avr32_f64_div_res_subnormal:/* Divide
16: /* Return NaN. */
mov r11, -1
- mov r10, -1
+ mov r10, 0
ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
17: /* Return INF. */

11
toolchain/gcc/patches/4.3.5/945-avr32_fix_f64_to_f32.patch
View File

@ -1,11 +0,0 @@
--- a/gcc/config/avr32/lib1funcs.S
+++ b/gcc/config/avr32/lib1funcs.S
@@ -2866,7 +2866,7 @@ __truncdfsf_return_op1:
/* NaN or inf */
cbr r12,31 /* clear implicit bit */
retne -1 /* Return NaN if mantissa not zero */
- mov_imm r12, 0xff000000
+ mov_imm r12, 0x7f800000
ret r12 /* Return inf */
3: /* Result is subnormal. Adjust it.*/

27
toolchain/gcc/patches/4.3.5/946-avr32_fix_32bit_div_2.patch
View File

@ -1,27 +0,0 @@
--- a/gcc/config/avr32/lib1funcs.S
+++ b/gcc/config/avr32/lib1funcs.S
@@ -2271,7 +2271,7 @@ __avr32_f32_div:
tst r12, r12
moveq r9, 0
- breq 12
+ breq 12f
/* Unpack op1*/
/* exp: r9 */
@@ -2467,9 +2467,14 @@ __divsf_return_op1:
reteq 0 /* Return zero if number/inf*/
ret -1 /* Return NaN*/
4:
- /* Op2 is zero ? */
+ /* Op1 is zero ? */
tst r12,r12
reteq -1 /* 0.0/0.0 is NaN */
+ /* Op1 is Nan? */
+ lsr r9, r12, 24
+ breq 11f /*If number is subnormal*/
+ cp r9, 0xff
+ brhs 2b /* Check op1 for NaN or Inf */
/* Nonzero/0.0 is Inf. Sign bit will be shifted in before returning*/
mov_imm r12, 0xff000000
rjmp __divsf_return_op1

32
toolchain/gcc/patches/4.3.5/948-avr32_fix_reorg_opt_bug11763.patch
View File

@ -1,32 +0,0 @@
--- a/gcc/config/avr32/avr32.c
+++ b/gcc/config/avr32/avr32.c
@@ -6501,12 +6501,23 @@ avr32_reorg_optimization (void)
continue;
set = single_set (scan);
- if (set && rtx_equal_p (src_reg, SET_DEST (set)))
- {
- link = scan;
- break;
- }
-
+ // Fix for bug #11763 : the following if condition
+ // has been modified and else part is included to
+ // set the link to NULL_RTX.
+ // if (set && rtx_equal_p (src_reg, SET_DEST (set)))
+ if (set && (REGNO(src_reg) == REGNO(SET_DEST(set))))
+ {
+ if (rtx_equal_p (src_reg, SET_DEST (set)))
+ {
+ link = scan;
+ break;
+ }
+ else
+ {
+ link = NULL_RTX;
+ break;
+ }
+ }
}

15
toolchain/gcc/patches/4.3.5/949-avr32_nan_by_zero_div.patch
View File

@ -1,15 +0,0 @@
--- a/gcc/config/avr32/lib1funcs.S
+++ b/gcc/config/avr32/lib1funcs.S
@@ -1852,7 +1852,11 @@ __avr32_f64_div_res_subnormal:/* Divide
mov r10, 0
ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
-17: /* Return INF. */
+17:
+ /* Check if op1 is zero. */
+ or r4, r10, r11
+ breq __avr32_f64_div_op1_zero
+ /* Return INF. */
mov r11, lr /*Get correct sign*/
andh r11, 0x8000, COH
orh r11, 0x7ff0