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kernel: update ssb and bcma to linux-next next-20110628

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27299 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
hauke
2011-06-28 19:33:50 +00:00
parent e2e4e12a9a
commit 6936562161
6 changed files with 51 additions and 57 deletions
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25
target/linux/brcm47xx/patches-2.6.39/250-ssb_fix_ssb_clock_rate.patch
View File

@@ -1,25 +0,0 @@
From 974353557959d8ec1c022511cd1b3eeaa7ed482a Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sat, 4 Jun 2011 15:55:24 +0200
Subject: [PATCH 15/15] ssb: fix ssb clock rate according to broadcom source
This fix was done according to si_clock_rate function in broadcom siutils.c
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
drivers/ssb/main.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -1002,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
switch (plltype) {
case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
if (m & SSB_CHIPCO_CLK_T6_MMASK)
- return SSB_CHIPCO_CLK_T6_M0;
- return SSB_CHIPCO_CLK_T6_M1;
+ return SSB_CHIPCO_CLK_T6_M1;
+ return SSB_CHIPCO_CLK_T6_M0;
case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */

25
target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch
View File

@@ -1,25 +0,0 @@
From 974353557959d8ec1c022511cd1b3eeaa7ed482a Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sat, 4 Jun 2011 15:55:24 +0200
Subject: [PATCH 15/15] ssb: fix ssb clock rate according to broadcom source
This fix was done according to si_clock_rate function in broadcom siutils.c
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
drivers/ssb/main.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -1002,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
switch (plltype) {
case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
if (m & SSB_CHIPCO_CLK_T6_MMASK)
- return SSB_CHIPCO_CLK_T6_M0;
- return SSB_CHIPCO_CLK_T6_M1;
+ return SSB_CHIPCO_CLK_T6_M1;
+ return SSB_CHIPCO_CLK_T6_M0;
case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */