mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
[ifxmips] cleanup sources and prepare for 2.6.27
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13660 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
thl
@@ -14,36 +14,35 @@
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2005 infineon
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
#ifndef _IFXMIPS_H__
|
||||
#define _IFXMIPS_H__
|
||||
|
||||
#define ifxmips_r32(reg) __raw_readl(reg)
|
||||
#define ifxmips_w32(val,reg) __raw_writel(val,reg)
|
||||
#define ifxmips_r32(reg) __raw_readl(reg)
|
||||
#define ifxmips_w32(val,reg) __raw_writel(val,reg)
|
||||
#define ifxmips_w32_mask(clear,set,reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
|
||||
|
||||
/*------------ GENERAL */
|
||||
|
||||
#define BOARD_SYSTEM_TYPE "IFXMIPS"
|
||||
|
||||
#define IOPORT_RESOURCE_START 0x10000000
|
||||
#define IOPORT_RESOURCE_START 0x10000000
|
||||
#define IOPORT_RESOURCE_END 0xffffffff
|
||||
#define IOMEM_RESOURCE_START 0x10000000
|
||||
#define IOMEM_RESOURCE_START 0x10000000
|
||||
#define IOMEM_RESOURCE_END 0xffffffff
|
||||
|
||||
#define IFXMIPS_FLASH_START 0x10000000
|
||||
#define IFXMIPS_FLASH_MAX 0x2000000
|
||||
#define IFXMIPS_FLASH_START 0x10000000
|
||||
#define IFXMIPS_FLASH_MAX 0x02000000
|
||||
|
||||
/*------------ ASC0/1 */
|
||||
|
||||
/*------------ ASC1 */
|
||||
|
||||
#define IFXMIPS_ASC_BASE_ADDR (KSEG1 + 0x1E100400)
|
||||
#define IFXMIPS_ASC_BASE_DIFF (0x1E100C00 - 0x1E100400)
|
||||
#define IFXMIPS_ASC_BASE_ADDR (KSEG1 + 0x1E100400)
|
||||
#define IFXMIPS_ASC_BASE_DIFF (0x1E100C00 - 0x1E100400)
|
||||
|
||||
#define IFXMIPS_ASC_FSTAT 0x0048
|
||||
#define IFXMIPS_ASC_TBUF 0x0020
|
||||
#define IFXMIPS_ASC_WHBSTATE 0x0018
|
||||
#define IFXMIPS_ASC_WHBSTATE 0x0018
|
||||
#define IFXMIPS_ASC_RBUF 0x0024
|
||||
#define IFXMIPS_ASC_STATE 0x0014
|
||||
#define IFXMIPS_ASC_IRNCR 0x00F8
|
||||
@@ -55,7 +54,7 @@
|
||||
#define IFXMIPS_ASC_BG 0x0050
|
||||
#define IFXMIPS_ASC_IRNREN 0x00F4
|
||||
|
||||
#define IFXMIPS_ASC_CLC_DISS 0x2
|
||||
#define IFXMIPS_ASC_CLC_DISS 0x2
|
||||
#define ASC_IRNREN_RX_BUF 0x8
|
||||
#define ASC_IRNREN_TX_BUF 0x4
|
||||
#define ASC_IRNREN_ERR 0x2
|
||||
@@ -64,29 +63,29 @@
|
||||
#define ASC_IRNCR_RIR 0x2
|
||||
#define ASC_IRNCR_EIR 0x4
|
||||
#define ASCOPT_CSIZE 0x3
|
||||
#define ASCOPT_CS7 0x1
|
||||
#define ASCOPT_CS8 0x2
|
||||
#define ASCOPT_CS7 0x1
|
||||
#define ASCOPT_CS8 0x2
|
||||
#define ASCOPT_PARENB 0x4
|
||||
#define ASCOPT_STOPB 0x8
|
||||
#define ASCOPT_PARODD 0x0
|
||||
#define ASCOPT_CREAD 0x20
|
||||
#define TXFIFO_FL 1
|
||||
#define RXFIFO_FL 1
|
||||
#define TXFIFO_FULL 16
|
||||
#define TXFIFO_FL 1
|
||||
#define RXFIFO_FL 1
|
||||
#define TXFIFO_FULL 16
|
||||
#define ASCCLC_RMCMASK 0x0000FF00
|
||||
#define ASCCLC_RMCOFFSET 8
|
||||
#define ASCCON_M_8ASYNC 0x0
|
||||
#define ASCCON_M_7ASYNC 0x2
|
||||
#define ASCCON_ODD 0x00000020
|
||||
#define ASCCON_STP 0x00000080
|
||||
#define ASCCON_BRS 0x00000100
|
||||
#define ASCCON_FDE 0x00000200
|
||||
#define ASCCON_R 0x00008000
|
||||
#define ASCCON_FEN 0x00020000
|
||||
#define ASCCON_ROEN 0x00080000
|
||||
#define ASCCON_TOEN 0x00100000
|
||||
#define ASCSTATE_PE 0x00010000
|
||||
#define ASCSTATE_FE 0x00020000
|
||||
#define ASCCON_ODD 0x00000020
|
||||
#define ASCCON_STP 0x00000080
|
||||
#define ASCCON_BRS 0x00000100
|
||||
#define ASCCON_FDE 0x00000200
|
||||
#define ASCCON_R 0x00008000
|
||||
#define ASCCON_FEN 0x00020000
|
||||
#define ASCCON_ROEN 0x00080000
|
||||
#define ASCCON_TOEN 0x00100000
|
||||
#define ASCSTATE_PE 0x00010000
|
||||
#define ASCSTATE_FE 0x00020000
|
||||
#define ASCSTATE_ROE 0x00080000
|
||||
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
|
||||
#define ASCWHBSTATE_CLRREN 0x00000001
|
||||
@@ -96,54 +95,54 @@
|
||||
#define ASCWHBSTATE_CLRROE 0x00000020
|
||||
#define ASCTXFCON_TXFEN 0x0001
|
||||
#define ASCTXFCON_TXFFLU 0x0002
|
||||
#define ASCTXFCON_TXFITLMASK 0x3F00
|
||||
#define ASCTXFCON_TXFITLOFF 8
|
||||
#define ASCRXFCON_RXFEN 0x0001
|
||||
#define ASCRXFCON_RXFFLU 0x0002
|
||||
#define ASCRXFCON_RXFITLMASK 0x3F00
|
||||
#define ASCRXFCON_RXFITLOFF 8
|
||||
#define ASCFSTAT_RXFFLMASK 0x003F
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
#define ASCTXFCON_TXFITLMASK 0x3F00
|
||||
#define ASCTXFCON_TXFITLOFF 8
|
||||
#define ASCRXFCON_RXFEN 0x0001
|
||||
#define ASCRXFCON_RXFFLU 0x0002
|
||||
#define ASCRXFCON_RXFITLMASK 0x3F00
|
||||
#define ASCRXFCON_RXFITLOFF 8
|
||||
#define ASCFSTAT_RXFFLMASK 0x003F
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
|
||||
|
||||
|
||||
/*------------ RCU */
|
||||
#define IFXMIPS_RCU_BASE_ADDR 0xBF203000
|
||||
#define IFXMIPS_RCU_BASE_ADDR 0xBF203000
|
||||
|
||||
/* reset request */
|
||||
#define IFXMIPS_RCU_RST ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
|
||||
#define IFXMIPS_RCU_RST_CPU1 (1 << 3)
|
||||
#define IFXMIPS_RCU_RST_CPU1 (1 << 3)
|
||||
#define IFXMIPS_RCU_RST_ALL 0x40000000
|
||||
|
||||
#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7)
|
||||
#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11)
|
||||
#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7)
|
||||
#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11)
|
||||
#define IFXMIPS_RCU_RST_REQ_ARC_JTAG (1 << 20)
|
||||
|
||||
|
||||
/*------------ GPTU */
|
||||
|
||||
#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300
|
||||
#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300
|
||||
|
||||
/* clock control register */
|
||||
#define IFXMIPS_GPTU_GPT_CLC ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))
|
||||
|
||||
/* captur reload register */
|
||||
#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
|
||||
#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
|
||||
|
||||
/* timer 6 control register */
|
||||
#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
|
||||
#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
|
||||
|
||||
|
||||
/*------------ EBU */
|
||||
|
||||
#define IFXMIPS_EBU_BASE_ADDR 0xBE105300
|
||||
#define IFXMIPS_EBU_BASE_ADDR 0xBE105300
|
||||
|
||||
/* bus configuration register */
|
||||
#define IFXMIPS_EBU_BUSCON0 ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0060))
|
||||
#define IFXMIPS_EBU_PCC_CON ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0090))
|
||||
#define IFXMIPS_EBU_PCC_IEN ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))
|
||||
#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
|
||||
#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
|
||||
|
||||
|
||||
/*------------ CGU */
|
||||
@@ -151,34 +150,34 @@
|
||||
#define IFXMIPS_CGU_PLL0_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0004))
|
||||
#define IFXMIPS_CGU_PLL1_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0008))
|
||||
#define IFXMIPS_CGU_PLL2_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x000C))
|
||||
#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
|
||||
#define IFXMIPS_CGU_UPDATE ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0014))
|
||||
#define IFXMIPS_CGU_IF_CLK ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
|
||||
#define IFXMIPS_CGU_OSC_CON ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x001C))
|
||||
#define IFXMIPS_CGU_SMD ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0020))
|
||||
#define IFXMIPS_CGU_CT1SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0028))
|
||||
#define IFXMIPS_CGU_CT2SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x002C))
|
||||
#define IFXMIPS_CGU_PCMCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0030))
|
||||
#define IFXMIPS_CGU_PCI_CR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
|
||||
#define IFXMIPS_CGU_PD_PC ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0038))
|
||||
#define IFXMIPS_CGU_FMR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x003C))
|
||||
#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
|
||||
#define IFXMIPS_CGU_UPDATE ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0014))
|
||||
#define IFXMIPS_CGU_IF_CLK ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
|
||||
#define IFXMIPS_CGU_OSC_CON ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x001C))
|
||||
#define IFXMIPS_CGU_SMD ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0020))
|
||||
#define IFXMIPS_CGU_CT1SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0028))
|
||||
#define IFXMIPS_CGU_CT2SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x002C))
|
||||
#define IFXMIPS_CGU_PCMCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0030))
|
||||
#define IFXMIPS_CGU_PCI_CR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
|
||||
#define IFXMIPS_CGU_PD_PC ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0038))
|
||||
#define IFXMIPS_CGU_FMR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x003C))
|
||||
|
||||
/* clock mux */
|
||||
#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
|
||||
#define IFXMIPS_CGU_IFCCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
|
||||
#define IFXMIPS_CGU_PCICR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
|
||||
|
||||
#define CLOCK_60M 60000000
|
||||
#define CLOCK_83M 83333333
|
||||
#define CLOCK_111M 111111111
|
||||
#define CLOCK_133M 133333333
|
||||
#define CLOCK_167M 166666667
|
||||
#define CLOCK_333M 333333333
|
||||
#define CLOCK_60M 60000000
|
||||
#define CLOCK_83M 83333333
|
||||
#define CLOCK_111M 111111111
|
||||
#define CLOCK_133M 133333333
|
||||
#define CLOCK_167M 166666667
|
||||
#define CLOCK_333M 333333333
|
||||
|
||||
|
||||
/*------------ CGU */
|
||||
|
||||
#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
|
||||
#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
|
||||
|
||||
#define IFXMIPS_PMU_PWDCR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x001C))
|
||||
#define IFXMIPS_PMU_PWDSR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x0020))
|
||||
@@ -186,17 +185,19 @@
|
||||
|
||||
/*------------ ICU */
|
||||
|
||||
#define IFXMIPS_ICU_BASE_ADDR 0xBF880200
|
||||
#define IFXMIPS_ICU_BASE_ADDR 0xBF880200
|
||||
|
||||
|
||||
#define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
|
||||
#define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
|
||||
#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
|
||||
#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
|
||||
#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
|
||||
#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
|
||||
#define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
|
||||
|
||||
#define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
|
||||
#define IFXMIPS_ICU_IM2_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0058))
|
||||
#define IFXMIPS_ICU_IM3_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0080))
|
||||
#define IFXMIPS_ICU_IM4_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00A8))
|
||||
#define IFXMIPS_ICU_IM5_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00D0))
|
||||
|
||||
#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
|
||||
@@ -204,24 +205,24 @@
|
||||
|
||||
/*------------ ETOP */
|
||||
|
||||
#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000
|
||||
#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000
|
||||
|
||||
#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
|
||||
|
||||
#define IFXMIPS_PPE32_MEM_MAP ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10000))
|
||||
#define IFXMIPS_PPE32_MEM_MAP ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10000))
|
||||
#define IFXMIPS_PPE32_SRST ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10080))
|
||||
|
||||
#define MII_MODE 1
|
||||
#define REV_MII_MODE 2
|
||||
#define MII_MODE 1
|
||||
#define REV_MII_MODE 2
|
||||
|
||||
/* mdio access */
|
||||
#define IFXMIPS_PPE32_MDIO_CFG ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11800))
|
||||
#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11804))
|
||||
#define IFXMIPS_PPE32_MDIO_CFG ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11800))
|
||||
#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11804))
|
||||
|
||||
#define MDIO_ACC_REQUEST 0x80000000
|
||||
#define MDIO_ACC_READ 0x40000000
|
||||
#define MDIO_ACC_ADDR_MASK 0x1f
|
||||
#define MDIO_ACC_ADDR_OFFSET 0x15
|
||||
#define MDIO_ACC_ADDR_OFFSET 0x15
|
||||
#define MDIO_ACC_REG_MASK 0xff
|
||||
#define MDIO_ACC_REG_OFFSET 0x10
|
||||
#define MDIO_ACC_VAL_MASK 0xffff
|
||||
@@ -242,7 +243,7 @@
|
||||
/* enet */
|
||||
#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1840))
|
||||
|
||||
#define PPE32_CGEN 0x800
|
||||
#define PPE32_CGEN 0x800
|
||||
|
||||
|
||||
/*------------ DMA */
|
||||
@@ -256,32 +257,32 @@
|
||||
#define IFXMIPS_DMA_CDLEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x24))
|
||||
#define IFXMIPS_DMA_PS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x40))
|
||||
#define IFXMIPS_DMA_PCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x44))
|
||||
#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10))
|
||||
#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10))
|
||||
#define IFXMIPS_DMA_CPOLL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x14))
|
||||
#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20))
|
||||
#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20))
|
||||
|
||||
|
||||
/*------------ PCI */
|
||||
#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
|
||||
|
||||
#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0))
|
||||
#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4))
|
||||
#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8))
|
||||
#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC))
|
||||
#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0))
|
||||
#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4))
|
||||
#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8))
|
||||
#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC))
|
||||
#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0))
|
||||
#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4))
|
||||
#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8))
|
||||
#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC))
|
||||
#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0))
|
||||
#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4))
|
||||
#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8))
|
||||
#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC))
|
||||
#define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000))
|
||||
#define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030))
|
||||
#define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080))
|
||||
#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4))
|
||||
#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4))
|
||||
#define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044))
|
||||
#define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048))
|
||||
#define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C))
|
||||
#define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010))
|
||||
#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064))
|
||||
#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8))
|
||||
#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064))
|
||||
#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8))
|
||||
#define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C))
|
||||
|
||||
#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
|
||||
@@ -296,7 +297,7 @@
|
||||
|
||||
/*------------ WDT */
|
||||
|
||||
#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
|
||||
#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
|
||||
|
||||
#define IFXMIPS_BIU_WDT_CR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))
|
||||
#define IFXMIPS_BIU_WDT_SR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))
|
||||
@@ -304,25 +305,25 @@
|
||||
|
||||
/*------------ LED */
|
||||
|
||||
#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
|
||||
#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000))
|
||||
#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004))
|
||||
#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008))
|
||||
#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C))
|
||||
#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
|
||||
#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000))
|
||||
#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004))
|
||||
#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008))
|
||||
#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C))
|
||||
#define IFXMIPS_LED_AR ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0010))
|
||||
|
||||
#define LED_CON0_SWU (1 << 31)
|
||||
#define LED_CON0_AD1 (1 << 25)
|
||||
#define LED_CON0_AD0 (1 << 24)
|
||||
|
||||
#define IFXMIPS_LED_2HZ (0)
|
||||
#define IFXMIPS_LED_4HZ (1 << 23)
|
||||
#define IFXMIPS_LED_8HZ (2 << 23)
|
||||
#define IFXMIPS_LED_10HZ (3 << 23)
|
||||
#define IFXMIPS_LED_MASK (0xf << 23)
|
||||
#define IFXMIPS_LED_2HZ (0)
|
||||
#define IFXMIPS_LED_4HZ (1 << 23)
|
||||
#define IFXMIPS_LED_8HZ (2 << 23)
|
||||
#define IFXMIPS_LED_10HZ (3 << 23)
|
||||
#define IFXMIPS_LED_MASK (0xf << 23)
|
||||
|
||||
#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31)
|
||||
#define IFXMIPS_LED_UPD_MASK (3 << 30)
|
||||
#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31)
|
||||
#define IFXMIPS_LED_UPD_MASK (3 << 30)
|
||||
#define IFXMIPS_LED_ADSL_SRC (3 << 24)
|
||||
|
||||
#define IFXMIPS_LED_GROUP0 (1 << 0)
|
||||
@@ -331,7 +332,7 @@
|
||||
|
||||
#define IFXMIPS_LED_RISING 0
|
||||
#define IFXMIPS_LED_FALLING (1 << 26)
|
||||
#define IFXMIPS_LED_EDGE_MASK (1 << 26)
|
||||
#define IFXMIPS_LED_EDGE_MASK (1 << 26)
|
||||
|
||||
|
||||
/*------------ GPIO */
|
||||
@@ -344,31 +345,31 @@
|
||||
#define IFXMIPS_GPIO_P1_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
|
||||
#define IFXMIPS_GPIO_P0_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
|
||||
#define IFXMIPS_GPIO_P1_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
|
||||
#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
|
||||
#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
|
||||
#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
|
||||
#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
|
||||
#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
|
||||
#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
|
||||
#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
|
||||
#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
|
||||
#define IFXMIPS_GPIO_P0_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
|
||||
#define IFXMIPS_GPIO_P1_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
|
||||
#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
|
||||
#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
|
||||
#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
|
||||
#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
|
||||
#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
|
||||
#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
|
||||
#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
|
||||
#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
|
||||
#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
|
||||
#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
|
||||
#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
|
||||
#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
|
||||
|
||||
|
||||
/*------------ SSC */
|
||||
|
||||
#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
|
||||
#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
|
||||
|
||||
|
||||
#define IFXMIPS_SSC_CLC ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0000))
|
||||
#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
|
||||
#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
|
||||
#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
|
||||
#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
|
||||
#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
|
||||
#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
|
||||
#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
|
||||
#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
|
||||
#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
|
||||
#define IFXMIPS_SSC_TB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0020))
|
||||
@@ -387,10 +388,10 @@
|
||||
|
||||
/*------------ MEI */
|
||||
|
||||
#define IFXMIPS_MEI_BASE_ADDR (0xBE116000)
|
||||
#define IFXMIPS_MEI_BASE_ADDR (KSEG1 + 0x1E116000)
|
||||
|
||||
#define MEI_DATA_XFR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0000))
|
||||
#define MEI_VERSION ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0004))
|
||||
#define MEI_VERSION ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0004))
|
||||
#define MEI_ARC_GP_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0008))
|
||||
#define MEI_DATA_XFR_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x000C))
|
||||
#define MEI_XFR_ADDR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0010))
|
||||
@@ -402,7 +403,7 @@
|
||||
#define MEI_DEBUG_RAD ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0028))
|
||||
#define MEI_DEBUG_DATA ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x002C))
|
||||
#define MEI_DEBUG_DEC ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0030))
|
||||
#define MEI_CONFIG ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0034))
|
||||
#define MEI_CONFIG ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0034))
|
||||
#define MEI_RST_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0038))
|
||||
#define MEI_DBG_MASTER ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x003C))
|
||||
#define MEI_CLK_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0040))
|
||||
@@ -432,7 +433,7 @@
|
||||
|
||||
/*------------ DEU */
|
||||
|
||||
#define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100)
|
||||
#define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100)
|
||||
#define IFXMIPS_DEU_CLK ((u32 *)(IFXMIPS_DEU_BASE + 0x0000))
|
||||
#define IFXMIPS_DEU_ID ((u32 *)(IFXMIPS_DEU_BASE + 0x0008))
|
||||
|
||||
@@ -471,12 +472,12 @@
|
||||
|
||||
/*------------ FUSE */
|
||||
|
||||
#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354)
|
||||
#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354)
|
||||
|
||||
|
||||
/*------------ MPS */
|
||||
|
||||
#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
|
||||
#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
|
||||
#define IFXMIPS_MPS_SRAM ((u32*)(KSEG1 + 0x1F200000))
|
||||
|
||||
#define IFXMIPS_MPS_CHIPID ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
|
||||
@@ -509,7 +510,7 @@
|
||||
#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
|
||||
#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
|
||||
#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
|
||||
#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
|
||||
#define IFXMIPS_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
|
||||
#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
|
||||
#define IFXMIPS_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -20,12 +20,12 @@
|
||||
#ifndef _IFXMIPS_DMA_H__
|
||||
#define _IFXMIPS_DMA_H__
|
||||
|
||||
#define RCV_INT 1
|
||||
#define RCV_INT 1
|
||||
#define TX_BUF_FULL_INT 2
|
||||
#define TRANSMIT_CPT_INT 4
|
||||
#define IFXMIPS_DMA_CH_ON 1
|
||||
#define IFXMIPS_DMA_CH_OFF 0
|
||||
#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100
|
||||
#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100
|
||||
|
||||
enum attr_t{
|
||||
TX = 0,
|
||||
@@ -34,9 +34,9 @@ enum attr_t{
|
||||
DEFAULT = 3,
|
||||
};
|
||||
|
||||
#define DMA_OWN 1
|
||||
#define CPU_OWN 0
|
||||
#define DMA_MAJOR 250
|
||||
#define DMA_OWN 1
|
||||
#define CPU_OWN 0
|
||||
#define DMA_MAJOR 250
|
||||
|
||||
#define DMA_DESC_OWN_CPU 0x0
|
||||
#define DMA_DESC_OWN_DMA 0x80000000
|
||||
@@ -44,12 +44,12 @@ enum attr_t{
|
||||
#define DMA_DESC_SOP_SET 0x20000000
|
||||
#define DMA_DESC_EOP_SET 0x10000000
|
||||
|
||||
#define MISCFG_MASK 0x40
|
||||
#define RDERR_MASK 0x20
|
||||
#define CHOFF_MASK 0x10
|
||||
#define DESCPT_MASK 0x8
|
||||
#define DUR_MASK 0x4
|
||||
#define EOP_MASK 0x2
|
||||
#define MISCFG_MASK 0x40
|
||||
#define RDERR_MASK 0x20
|
||||
#define CHOFF_MASK 0x10
|
||||
#define DESCPT_MASK 0x8
|
||||
#define DUR_MASK 0x4
|
||||
#define EOP_MASK 0x2
|
||||
|
||||
#define DMA_DROP_MASK (1<<31)
|
||||
|
||||
@@ -57,7 +57,7 @@ enum attr_t{
|
||||
#define IFXMIPS_DMA_TX 1
|
||||
|
||||
typedef struct dma_chan_map {
|
||||
char dev_name[15];
|
||||
const char *dev_name;
|
||||
enum attr_t dir;
|
||||
int pri;
|
||||
int irq;
|
||||
@@ -75,7 +75,7 @@ typedef struct rx_desc{
|
||||
volatile u32 C:1;
|
||||
volatile u32 OWN:1;
|
||||
volatile u32 Data_Pointer;
|
||||
/*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/
|
||||
/* fix me:should be 28 bits here, 32 bits just for host simulation purpose */
|
||||
}_rx_desc;
|
||||
|
||||
typedef struct tx_desc{
|
||||
@@ -86,9 +86,9 @@ typedef struct tx_desc{
|
||||
volatile u32 SoP:1;
|
||||
volatile u32 C:1;
|
||||
volatile u32 OWN:1;
|
||||
volatile u32 Data_Pointer;//fix me:should be 28 bits here
|
||||
volatile u32 Data_Pointer;/* fix me:should be 28 bits here */
|
||||
}_tx_desc;
|
||||
#else //BIG
|
||||
#else /* BIG */
|
||||
typedef struct rx_desc{
|
||||
union
|
||||
{
|
||||
@@ -128,64 +128,64 @@ typedef struct tx_desc{
|
||||
#endif //ENDIAN
|
||||
|
||||
typedef struct dma_channel_info{
|
||||
/*relative channel number*/
|
||||
int rel_chan_no;
|
||||
/*class for this channel for QoS*/
|
||||
int pri;
|
||||
/*specify byte_offset*/
|
||||
int byte_offset;
|
||||
/*direction*/
|
||||
int dir;
|
||||
/*irq number*/
|
||||
int irq;
|
||||
/*descriptor parameter*/
|
||||
int desc_base;
|
||||
int desc_len;
|
||||
int curr_desc;
|
||||
int prev_desc;/*only used if it is a tx channel*/
|
||||
/*weight setting for WFQ algorithm*/
|
||||
int weight;
|
||||
int default_weight;
|
||||
int packet_size;
|
||||
int burst_len;
|
||||
/*on or off of this channel*/
|
||||
int control;
|
||||
/**optional information for the upper layer devices*/
|
||||
/*relative channel number*/
|
||||
int rel_chan_no;
|
||||
/*class for this channel for QoS*/
|
||||
int pri;
|
||||
/*specify byte_offset*/
|
||||
int byte_offset;
|
||||
/*direction*/
|
||||
int dir;
|
||||
/*irq number*/
|
||||
int irq;
|
||||
/*descriptor parameter*/
|
||||
int desc_base;
|
||||
int desc_len;
|
||||
int curr_desc;
|
||||
int prev_desc;/*only used if it is a tx channel*/
|
||||
/*weight setting for WFQ algorithm*/
|
||||
int weight;
|
||||
int default_weight;
|
||||
int packet_size;
|
||||
int burst_len;
|
||||
/*on or off of this channel*/
|
||||
int control;
|
||||
/**optional information for the upper layer devices*/
|
||||
#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
|
||||
void* opt[64];
|
||||
void* opt[64];
|
||||
#else
|
||||
void* opt[25];
|
||||
void* opt[25];
|
||||
#endif
|
||||
/*Pointer to the peripheral device who is using this channel*/
|
||||
void* dma_dev;
|
||||
/*channel operations*/
|
||||
void (*open)(struct dma_channel_info* pCh);
|
||||
void (*close)(struct dma_channel_info* pCh);
|
||||
void (*reset)(struct dma_channel_info* pCh);
|
||||
void (*enable_irq)(struct dma_channel_info* pCh);
|
||||
void (*disable_irq)(struct dma_channel_info* pCh);
|
||||
/*Pointer to the peripheral device who is using this channel*/
|
||||
void* dma_dev;
|
||||
/*channel operations*/
|
||||
void (*open)(struct dma_channel_info* pCh);
|
||||
void (*close)(struct dma_channel_info* pCh);
|
||||
void (*reset)(struct dma_channel_info* pCh);
|
||||
void (*enable_irq)(struct dma_channel_info* pCh);
|
||||
void (*disable_irq)(struct dma_channel_info* pCh);
|
||||
}_dma_channel_info;
|
||||
|
||||
typedef struct dma_device_info{
|
||||
/*device name of this peripheral*/
|
||||
char device_name[15];
|
||||
int reserved;
|
||||
int tx_burst_len;
|
||||
int rx_burst_len;
|
||||
int default_weight;
|
||||
int current_tx_chan;
|
||||
/*device name of this peripheral*/
|
||||
char device_name[15];
|
||||
int reserved;
|
||||
int tx_burst_len;
|
||||
int rx_burst_len;
|
||||
int default_weight;
|
||||
int current_tx_chan;
|
||||
int current_rx_chan;
|
||||
int num_tx_chan;
|
||||
int num_rx_chan;
|
||||
int max_rx_chan_num;
|
||||
int max_tx_chan_num;
|
||||
_dma_channel_info* tx_chan[20];
|
||||
_dma_channel_info* rx_chan[20];
|
||||
/*functions, optional*/
|
||||
u8* (*buffer_alloc)(int len,int* offset, void** opt);
|
||||
void (*buffer_free)(u8* dataptr, void* opt);
|
||||
int (*intr_handler)(struct dma_device_info* info, int status);
|
||||
void * priv; /* used by peripheral driver only */
|
||||
int num_tx_chan;
|
||||
int num_rx_chan;
|
||||
int max_rx_chan_num;
|
||||
int max_tx_chan_num;
|
||||
_dma_channel_info* tx_chan[20];
|
||||
_dma_channel_info* rx_chan[20];
|
||||
/*functions, optional*/
|
||||
u8* (*buffer_alloc)(int len,int* offset, void** opt);
|
||||
void (*buffer_free)(u8* dataptr, void* opt);
|
||||
int (*intr_handler)(struct dma_device_info* info, int status);
|
||||
void * priv; /* used by peripheral driver only */
|
||||
}_dma_device_info;
|
||||
|
||||
_dma_device_info* dma_device_reserve(char* dev_name);
|
||||
@@ -200,3 +200,4 @@ int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
|
||||
|
||||
int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);
|
||||
#endif
|
||||
|
||||
|
||||
@@ -14,7 +14,7 @@
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2005 infineon
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
#ifndef _IFXMIPS_IRQ__
|
||||
#define _IFXMIPS_IRQ__
|
||||
@@ -63,8 +63,8 @@
|
||||
#define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
|
||||
#define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
|
||||
|
||||
#define IFXMIPS_USB_INT (INT_NUM_IM4_IRL0 + 22)
|
||||
#define IFXMIPS_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
|
||||
#define IFXMIPS_USB_INT (INT_NUM_IM4_IRL0 + 22)
|
||||
#define IFXMIPS_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
|
||||
|
||||
|
||||
extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
|
||||
|
||||
@@ -15,11 +15,10 @@
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _IFXMIPS_GPIO_H_
|
||||
#define _IFXMIPS_GPIO_H_
|
||||
|
||||
|
||||
Reference in New Issue
Block a user