mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
lots of ifxmips cleanups
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11596 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
@@ -6,6 +6,7 @@
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#include <linux/mm.h>
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#include <asm/ifxmips/ifxmips.h>
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#include <asm/ifxmips/ifxmips_irq.h>
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#include <asm/ifxmips/ifxmips_cgu.h>
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#include <asm/addrspace.h>
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#include <linux/vmalloc.h>
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@@ -17,26 +18,30 @@
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extern int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
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extern int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
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struct pci_ops ifxmips_pci_ops = {
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struct pci_ops ifxmips_pci_ops =
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{
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.read = ifxmips_pci_read_config_dword,
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.write = ifxmips_pci_write_config_dword
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};
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static struct resource pci_io_resource = {
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static struct resource pci_io_resource =
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{
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.name = "io pci IO space",
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.start = IFXMIPS_PCI_IO_BASE,
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.end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource pci_mem_resource = {
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static struct resource pci_mem_resource =
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{
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.name = "ext pci memory space",
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.start = IFXMIPS_PCI_MEM_BASE,
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.end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_controller ifxmips_pci_controller = {
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static struct pci_controller ifxmips_pci_controller =
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{
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.pci_ops = &ifxmips_pci_ops,
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.mem_resource = &pci_mem_resource,
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.mem_offset = 0x00000000UL,
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@@ -45,12 +50,25 @@ static struct pci_controller ifxmips_pci_controller = {
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};
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u32 ifxmips_pci_mapped_cfg;
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u32 ifxmips_pci_external_clock = 0;
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int pcibios_plat_dev_init(struct pci_dev *dev){
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static int __init
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ifxmips_pci_set_external_clk(char *str)
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{
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printk("cgu: setting up external pci clock\n");
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ifxmips_pci_external_clock = 1;
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return 1;
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}
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__setup("pci_external_clk", ifxmips_pci_set_external_clk);
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int
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pcibios_plat_dev_init(struct pci_dev *dev)
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{
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u8 pin;
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
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switch(pin) {
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switch(pin)
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{
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case 0:
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break;
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case 1:
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@@ -69,12 +87,13 @@ int pcibios_plat_dev_init(struct pci_dev *dev){
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return 0;
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}
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static void __init ifxmips_pci_startup (void){
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static void __init
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ifxmips_pci_startup(void)
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{
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u32 temp_buffer;
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ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
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ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
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ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
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ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
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cgu_setup_pci_clk(ifxmips_pci_external_clock);
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ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
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ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
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ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
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@@ -138,8 +157,10 @@ static void __init ifxmips_pci_startup (void){
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ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
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switch (slot) {
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int __init
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pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
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switch(slot)
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{
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case 13:
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/* IDSEL = AD29 --> USB Host Controller */
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return (INT_NUM_IM1_IRL0 + 17);
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@@ -152,11 +173,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
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}
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}
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int pcibios_init(void){
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int
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pcibios_init(void)
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{
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extern int pci_probe_only;
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pci_probe_only = 0;
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printk ("PCI: Probing PCI hardware on host bus 0.\n");
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printk("PCI: Probing PCI hardware on host bus 0.\n");
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ifxmips_pci_startup ();
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// IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
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ifxmips_pci_mapped_cfg = (u32)ioremap_nocache(0x17000000, 0x800 * 16);
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