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ath9k: clean up pll code for ar9002 to fix 5/10 mhz pll settings for 5ghz
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27362 3c298f89-4303-0410-b956-a3cf2f4a3e73
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42
package/mac80211/patches/541-ath9k_pllclock_fix.patch
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42
package/mac80211/patches/541-ath9k_pllclock_fix.patch
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@ -0,0 +1,42 @@
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--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
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+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
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@@ -447,26 +447,27 @@ static void ar9002_olc_init(struct ath_h
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static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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+ int ref_div = 5;
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+ int pll_div = 0x2c;
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u32 pll;
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- pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
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+ if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) {
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+ if (AR_SREV_9280_20(ah)) {
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+ ref_div = 10;
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+ pll_div = 0x50;
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+ } else {
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+ pll_div = 0x28;
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+ }
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+ }
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+
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+ pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
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+ pll |= SM(pll_div, AR_RTC_9160_PLL_DIV);
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if (chan && IS_CHAN_HALF_RATE(chan))
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pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
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else if (chan && IS_CHAN_QUARTER_RATE(chan))
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pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
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- if (chan && IS_CHAN_5GHZ(chan)) {
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- if (IS_CHAN_A_FAST_CLOCK(ah, chan))
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- pll = 0x142c;
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- else if (AR_SREV_9280_20(ah))
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- pll = 0x2850;
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- else
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- pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
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- } else {
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- pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
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- }
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-
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return pll;
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}
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