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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-26 00:56:47 +02:00
cleanup of register access
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9843 3c298f89-4303-0410-b956-a3cf2f4a3e73
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8eae2749b6
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@ -108,7 +108,7 @@ ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
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{
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{
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unsigned int rmc;
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unsigned int rmc;
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rmc = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
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rmc = (readl(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
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if (rmc == 0)
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if (rmc == 0)
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{
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{
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printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
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printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
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@ -168,24 +168,12 @@ rx_int (struct ifx_ssc_port *info)
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unsigned long *tmp_ptr;
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unsigned long *tmp_ptr;
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unsigned int rx_valid_cnt;
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unsigned int rx_valid_cnt;
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/* number of words waiting in the RX FIFO */
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/* number of words waiting in the RX FIFO */
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fifo_fill_lev = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
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fifo_fill_lev = (readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
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// Note: There are always 32 bits in a fifo-entry except for the last
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// word of a contigous transfer block and except for not in rx-only
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// mode and CON.ENBV set. But for this case it should be a convention
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// in software which helps:
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// In tx or rx/tx mode all transfers from the buffer to the FIFO are
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// 32-bit wide, except for the last three bytes, which could be a
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// combination of 16- and 8-bit access.
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// => The whole block is received as 32-bit words as a contigous stream,
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// even if there was a gap in tx which has the fifo run out of data!
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// Just the last fifo entry *may* be partially filled (0, 1, 2 or 3 bytes)!
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/* free space in the RX buffer */
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bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
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bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
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// transfer with 32 bits per entry
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// transfer with 32 bits per entry
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while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
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while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
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tmp_ptr = (unsigned long *) info->rxbuf_ptr;
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tmp_ptr = (unsigned long *) info->rxbuf_ptr;
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*tmp_ptr = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RB);
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*tmp_ptr = readl(IFXMIPS_SSC_RB);
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info->rxbuf_ptr += 4;
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info->rxbuf_ptr += 4;
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info->stats.rxBytes += 4;
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info->stats.rxBytes += 4;
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fifo_fill_lev--;
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fifo_fill_lev--;
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@ -194,14 +182,14 @@ rx_int (struct ifx_ssc_port *info)
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// now do the rest as mentioned in STATE.RXBV
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// now do the rest as mentioned in STATE.RXBV
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while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
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while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
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rx_valid_cnt = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
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rx_valid_cnt = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
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if (rx_valid_cnt == 0)
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if (rx_valid_cnt == 0)
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break;
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break;
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if (rx_valid_cnt > bytes_in_buf)
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if (rx_valid_cnt > bytes_in_buf)
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rx_valid_cnt = bytes_in_buf;
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rx_valid_cnt = bytes_in_buf;
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tmp_val = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RB);
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tmp_val = readl(IFXMIPS_SSC_RB);
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for (i = 0; i < rx_valid_cnt; i++)
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for (i = 0; i < rx_valid_cnt; i++)
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{
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{
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@ -220,9 +208,9 @@ rx_int (struct ifx_ssc_port *info)
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} else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) == 0))
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} else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) == 0))
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{
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{
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if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
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if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
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WRITE_PERIPHERAL_REGISTER ((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
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writel((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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else
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else
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, info->mapbase + IFX_SSC_RXREQ);
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writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
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}
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}
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}
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}
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@ -231,8 +219,8 @@ tx_int (struct ifx_ssc_port *info)
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{
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{
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int fifo_space, fill, i;
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int fifo_space, fill, i;
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fifo_space = ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
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fifo_space = ((readl(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
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- ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
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- ((readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
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if (fifo_space == 0)
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if (fifo_space == 0)
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return;
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return;
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@ -245,7 +233,7 @@ tx_int (struct ifx_ssc_port *info)
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for (i = 0; i < fill / 4; i++)
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for (i = 0; i < fill / 4; i++)
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{
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{
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// at first 32 bit access
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// at first 32 bit access
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WRITE_PERIPHERAL_REGISTER (*(UINT32 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
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writel(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB);
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info->txbuf_ptr += 4;
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info->txbuf_ptr += 4;
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}
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}
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@ -307,7 +295,7 @@ ifx_ssc_err_int (int irq, void *dev_id)
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unsigned long flags;
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unsigned long flags;
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local_irq_save (flags);
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local_irq_save (flags);
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state = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE);
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state = readl(IFXMIPS_SSC_STATE);
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if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
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if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
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info->stats.rxUnErr++;
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info->stats.rxUnErr++;
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@ -335,7 +323,7 @@ ifx_ssc_err_int (int irq, void *dev_id)
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}
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}
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if (write_back)
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if (write_back)
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WRITE_PERIPHERAL_REGISTER (write_back, info->mapbase + IFX_SSC_WHBSTATE);
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writel(write_back, IFXMIPS_SSC_WHBSTATE);
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local_irq_restore (flags);
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local_irq_restore (flags);
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@ -361,12 +349,12 @@ ifx_ssc_abort (struct ifx_ssc_port *info)
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// complete word. The disable cuts the transmission immediatly and
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// complete word. The disable cuts the transmission immediatly and
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// releases the chip selects. This could result in unpredictable
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// releases the chip selects. This could result in unpredictable
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// behavior of connected external devices!
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// behavior of connected external devices!
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enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
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enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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// flush fifos
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// flush fifos
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_XFCON_FIFO_FLUSH, info->mapbase + IFX_SSC_TXFCON);
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writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_XFCON_FIFO_FLUSH, info->mapbase + IFX_SSC_RXFCON);
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writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
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// free txbuf
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// free txbuf
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if (info->txbuf != NULL)
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if (info->txbuf != NULL)
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@ -385,10 +373,10 @@ ifx_ssc_abort (struct ifx_ssc_port *info)
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mask_and_ack_ifxmips_irq(info->errirq);
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mask_and_ack_ifxmips_irq(info->errirq);
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// clear error flags
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// clear error flags
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ALL_ERROR, info->mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
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if (enabled)
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if (enabled)
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
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}
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}
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@ -427,22 +415,22 @@ ifx_ssc_open (struct inode *inode, struct file *filp)
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disable_irq(info->errirq);
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disable_irq(info->errirq);
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/* Flush and enable TX/RX FIFO */
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/* Flush and enable TX/RX FIFO */
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WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, info->mapbase + IFX_SSC_TXFCON);
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writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
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WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, info->mapbase + IFX_SSC_RXFCON);
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writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
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/* logically flush the software FIFOs */
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/* logically flush the software FIFOs */
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info->rxbuf_ptr = 0;
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info->rxbuf_ptr = 0;
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info->txbuf_ptr = 0;
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info->txbuf_ptr = 0;
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/* clear all error bits */
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/* clear all error bits */
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ALL_ERROR, info->mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
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// clear pending interrupts
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// clear pending interrupts
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mask_and_ack_ifxmips_irq(info->rxirq);
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mask_and_ack_ifxmips_irq(info->rxirq);
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mask_and_ack_ifxmips_irq(info->txirq);
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mask_and_ack_ifxmips_irq(info->txirq);
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mask_and_ack_ifxmips_irq(info->errirq);
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mask_and_ack_ifxmips_irq(info->errirq);
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
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return 0;
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return 0;
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}
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}
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@ -466,7 +454,7 @@ ifx_ssc_close (struct inode *inode, struct file *filp)
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if (!info)
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if (!info)
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return -ENXIO;
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return -ENXIO;
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WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE, info->mapbase + IFX_SSC_WHBSTATE);
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writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
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ifx_ssc_abort(info);
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ifx_ssc_abort(info);
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@ -727,7 +715,7 @@ ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
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{
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{
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unsigned long tmp;
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unsigned long tmp;
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tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFSTAT);
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tmp = readl(IFXMIPS_SSC_SFSTAT);
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info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
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info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
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info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
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info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
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info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
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info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
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@ -1246,7 +1234,7 @@ ifx_ssc_init (void)
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info->txbuf = NULL;
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info->txbuf = NULL;
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/* values specific to SSC1 */
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/* values specific to SSC1 */
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if (i == 0) {
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if (i == 0) {
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info->mapbase = IFXMIPS_SSC1_BASE_ADDR;
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info->mapbase = IFXMIPS_SSC_BASE_ADDR;
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info->txirq = IFXMIPS_SSC_TIR;
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info->txirq = IFXMIPS_SSC_TIR;
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info->rxirq = IFXMIPS_SSC_RIR;
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info->rxirq = IFXMIPS_SSC_RIR;
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info->errirq = IFXMIPS_SSC_EIR;
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info->errirq = IFXMIPS_SSC_EIR;
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