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ar71xx: add support for the watchdog of the AR934x SoCs
Signed-off-by: Jaiganesh Narayanan <jnarayanan@atheros.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26516 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -1,9 +1,12 @@
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/*
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* Driver for the Atheros AR71xx SoC's built-in hardware watchdog timer.
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros 2.6.31 BSP
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*
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* This driver was based on: drivers/watchdog/ixp4xx_wdt.c
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* Author: Deepak Saxena <dsaxena@plexity.net>
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* Copyright 2004 (c) MontaVista, Software, Inc.
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@ -28,6 +31,7 @@
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/watchdog.h>
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#include <linux/delay.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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@ -53,16 +57,18 @@ static unsigned long wdt_flags;
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static int wdt_timeout = WDT_TIMEOUT;
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static int boot_status;
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static int max_timeout;
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static u32 wdt_clk_freq;
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static inline void ar71xx_wdt_keepalive(void)
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{
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ar71xx_reset_wr(AR71XX_RESET_REG_WDOG, ar71xx_ahb_freq * wdt_timeout);
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ar71xx_reset_wr(AR71XX_RESET_REG_WDOG, wdt_clk_freq * wdt_timeout);
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}
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static inline void ar71xx_wdt_enable(void)
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{
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printk(KERN_DEBUG DRV_NAME ": enabling watchdog timer\n");
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ar71xx_wdt_keepalive();
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udelay(2);
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ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
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}
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@ -212,7 +218,19 @@ static int __devinit ar71xx_wdt_probe(struct platform_device *pdev)
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{
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int ret;
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max_timeout = (0xfffffffful / ar71xx_ahb_freq);
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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wdt_clk_freq = ar934x_ref_freq;
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break;
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default:
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wdt_clk_freq = ar71xx_ahb_freq;
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break;
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}
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max_timeout = (0xfffffffful / wdt_clk_freq);
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wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT;
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if (ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET)
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