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mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00

merge another batch of code from michael buesch's wireless-dev tree, fix up extpci support and remove scache probe like on brcm-2.6 - tested on the wgt634u with madwifi

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6213 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
2007-01-26 20:30:32 +00:00
parent 0a87b5ffbf
commit 746bc29e29
6 changed files with 3508 additions and 4819 deletions

File diff suppressed because it is too large Load Diff

View File

@@ -53,7 +53,7 @@ diff -urN linux.old/drivers/mtd/maps/bcm47xx-flash.c linux.dev/drivers/mtd/maps/
+#include <linux/squashfs_fs.h>
+#include <linux/jffs2.h>
+#include <linux/crc32.h>
+#include <linux/ssb.h>
+#include <linux/ssb/ssb.h>
+#include <asm/io.h>
+
+

View File

@@ -17,7 +17,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
+#include <linux/ssb.h>
+#include <linux/ssb/ssb.h>
#include <asm/uaccess.h>
#include <asm/io.h>
@@ -663,7 +663,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
- if (ssb_is_core_up(bp)) {
+ struct ssb_device *sdev = bp->sdev;
+
+ if (ssb_core_is_enabled(bp->sdev)) {
+ if (ssb_device_is_enabled(bp->sdev)) {
bw32(bp, B44_RCV_LAZY, 0);
bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
@@ -679,7 +679,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
- ssb_core_reset(bp);
-
+ ssb_core_enable(bp->sdev, 0);
+ ssb_device_enable(bp->sdev, 0);
b44_clear_stats(bp);
- /* Make PHY accessible. */
@@ -1096,7 +1096,7 @@ diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
- err = b44_read_eeprom(bp, &eeprom[0]);
- if (err)
- goto out;
+ bp->dma_offset = ssb_dma_offset(sdev);
+ bp->dma_offset = ssb_dma_translation(sdev);
- bp->dev->dev_addr[0] = eeprom[79];
- bp->dev->dev_addr[1] = eeprom[78];

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@@ -0,0 +1,94 @@
diff -urN linux-2.6.19.ref/arch/mips/Kconfig linux-2.6.19/arch/mips/Kconfig
--- linux-2.6.19.ref/arch/mips/Kconfig 2006-12-04 21:33:48.000000000 +0100
+++ linux-2.6.19/arch/mips/Kconfig 2006-12-04 21:34:04.000000000 +0100
@@ -283,7 +283,6 @@
select I8259
select MIPS_BOARDS_GEN
select MIPS_BONITO64
- select MIPS_CPU_SCACHE
select MIPS_GT64120
select MIPS_MSC
select SWAP_IO_SPACE
@@ -1434,13 +1433,6 @@
bool
select BOARD_SCACHE
-#
-# Support for a MIPS32 / MIPS64 style S-caches
-#
-config MIPS_CPU_SCACHE
- bool
- select BOARD_SCACHE
-
config R5000_CPU_SCACHE
bool
select BOARD_SCACHE
diff -urN linux-2.6.19.ref/arch/mips/kernel/cpu-probe.c linux-2.6.19/arch/mips/kernel/cpu-probe.c
--- linux-2.6.19.ref/arch/mips/kernel/cpu-probe.c 2006-12-04 21:33:48.000000000 +0100
+++ linux-2.6.19/arch/mips/kernel/cpu-probe.c 2006-12-04 21:34:04.000000000 +0100
@@ -631,6 +631,8 @@
break;
case PRID_IMP_25KF:
c->cputype = CPU_25KF;
+ /* Probe for L2 cache */
+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
break;
case PRID_IMP_34K:
c->cputype = CPU_34K;
diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c
--- linux-2.6.19.ref/arch/mips/mm/c-r4k.c 2006-11-29 22:57:37.000000000 +0100
+++ linux-2.6.19/arch/mips/mm/c-r4k.c 2006-12-04 21:34:04.000000000 +0100
@@ -1038,7 +1038,6 @@
extern int r5k_sc_init(void);
extern int rm7k_sc_init(void);
-extern int mips_sc_init(void);
static void __init setup_scache(void)
{
@@ -1086,29 +1085,17 @@
return;
default:
- if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
- c->isa_level == MIPS_CPU_ISA_M32R2 ||
- c->isa_level == MIPS_CPU_ISA_M64R1 ||
- c->isa_level == MIPS_CPU_ISA_M64R2) {
-#ifdef CONFIG_MIPS_CPU_SCACHE
- if (mips_sc_init ()) {
- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
- scache_size >> 10,
- way_string[c->scache.ways], c->scache.linesz);
- }
-#else
- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
-#endif
- return;
- }
sc_present = 0;
}
if (!sc_present)
return;
+ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
+ c->isa_level == MIPS_CPU_ISA_M64R1) &&
+ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
+ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+
/* compute a couple of other cache variables */
c->scache.waysize = scache_size / c->scache.ways;
diff -urN linux-2.6.19.ref/arch/mips/mm/Makefile linux-2.6.19/arch/mips/mm/Makefile
--- linux-2.6.19.ref/arch/mips/mm/Makefile 2006-11-29 22:57:37.000000000 +0100
+++ linux-2.6.19/arch/mips/mm/Makefile 2006-12-04 21:34:04.000000000 +0100
@@ -30,7 +30,6 @@
obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
-obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
#
# Choose one DMA coherency model