qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00
Code Activity

make atheros wifi cards used on arcaydian 4519 ifxmips based boards work

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11676 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
2008-07-06 00:59:48 +00:00
parent 80c16a1be2
commit 7863ca9afd
6 changed files with 167 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

100
package/madwifi/patches/354-ifxmips_eeprom.patch Normal file
View File

@@ -0,0 +1,100 @@
Index: madwifi-trunk-r3314/ath_hal/ah_os.c
===================================================================
--- madwifi-trunk-r3314.orig/ath_hal/ah_os.c 2008-07-06 02:42:52.000000000 +0200
+++ madwifi-trunk-r3314/ath_hal/ah_os.c 2008-07-06 02:51:53.000000000 +0200
@@ -343,6 +343,46 @@
* NB: see the comments in ah_osdep.h about byte-swapping register
* reads and writes to understand what's going on below.
*/
+
+#ifdef CONFIG_IFXMIPS
+extern int ifxmips_has_brn_block(void);
+static int ifxmips_emulate = 0;
+#define EEPROM_EMULATION 1
+#endif
+
+#ifdef EEPROM_EMULATION
+static int ath_hal_eeprom(struct ath_hal *ah, unsigned long addr, int val, int write)
+{
+ static int addrsel = 0;
+ static int rc = 0;
+
+ if (write) {
+ if(addr == 0x6000) {
+ addrsel = val * 2;
+ rc = 0;
+ }
+ } else {
+ switch(addr)
+ {
+ case 0x600c:
+ if(rc++ < 2)
+ val = 0x00000000;
+ else
+ val = 0x00000002;
+ break;
+ case 0x6004:
+ val = cpu_to_le16(__raw_readw((u16 *) KSEG1ADDR(0xb07f0400 + addrsel)));
+ /* this forces the regdomain to 0x00 (worldwide), as the original setting
+ * causes issues with the HAL */
+ if (addrsel == 0x17e)
+ val = 0;
+ break;
+ }
+ }
+ return val;
+}
+#endif
+
void __ahdecl
ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val)
{
@@ -351,20 +391,33 @@
ath_hal_printf(ah, "%s: WRITE 0x%x <= 0x%x\n",
(ath_hal_func ?: "unknown"), reg, val);
#endif
- _OS_REG_WRITE(ah, reg, val);
+#ifdef EEPROM_EMULATION
+ if((reg >= 0x6000) && (reg <= 0x6010) && ifxmips_emulate)
+ {
+ val = ath_hal_eeprom(ah, reg, val, 1);
+ } else
+#endif
+ _OS_REG_WRITE(ah, reg, val);
}
EXPORT_SYMBOL(ath_hal_reg_write);
+
/* This should only be called while holding the lock, sc->sc_hal_lock. */
u_int32_t __ahdecl
ath_hal_reg_read(struct ath_hal *ah, u_int reg)
{
- u_int32_t val;
+ u_int32_t val;
+#ifdef EEPROM_EMULATION
+ if((reg >= 0x6000) && (reg <= 0x6010) && ifxmips_emulate)
+ {
+ val = ath_hal_eeprom(ah, reg, 0, 0);
+ } else
+#endif
+ val = _OS_REG_READ(ah, reg);
- val = _OS_REG_READ(ah, reg);
#ifdef AH_DEBUG
if (ath_hal_debug > 1)
- ath_hal_printf(ah, "%s: READ 0x%x => 0x%x\n",
+ ath_hal_printf(ah, "%s: READ 0x%x => 0x%x\n",
(ath_hal_func ?: "unknown"), reg, val);
#endif
return val;
@@ -581,7 +634,9 @@
{
const char *sep;
int i;
-
+#ifdef CONFIG_IFXMIPS
+ ifxmips_emulate = ifxmips_has_brn_block();
+#endif
printk(KERN_INFO "%s: %s (", dev_info, ath_hal_version);
sep = "";
for (i = 0; ath_hal_buildopts[i] != NULL; i++) {