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ramips: add watchdog device for RT288x

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@25129 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2011-01-26 20:48:50 +00:00
parent f019ef96de
commit 78f0155856
3 changed files with 33 additions and 0 deletions
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4
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
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@@ -33,6 +33,7 @@
#define RT2880_SDRAM_BASE 0x08000000
#define RT2880_SYSC_SIZE 0x100
#define RT2880_TIMER_SIZE 0x100
#define RT2880_INTC_SIZE 0x100
#define RT2880_MEMC_SIZE 0x100
#define RT2880_UART0_SIZE 0x100
@@ -45,6 +46,7 @@
#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
#define SYSC_REG_CLKCFG 0x030
#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
@@ -62,6 +64,8 @@
#define SYSTEM_CONFIG_CPUCLK_280 0x2
#define SYSTEM_CONFIG_CPUCLK_300 0x3
#define CLKCFG_SRAM_CS_N_WDT BIT(9)
#define RT2880_RESET_SYSTEM BIT(0)
#define RT2880_RESET_TIMER BIT(1)
#define RT2880_RESET_INTC BIT(2)