diff --git a/Config.in b/Config.in index 2ff2862a2..ffe1147f4 100644 --- a/Config.in +++ b/Config.in @@ -170,9 +170,16 @@ choice depends !USE_EGLIBC help This will install binaries stripped using sstrip - endchoice +config BUILD_PATENTED + default y + bool "Compile with support for patented functionality" + help + When this option is disabled, software which provides patented functionality will not be built. + In case software provides optional support for patented functionality, + this optional support will get disabled for this package. + config STRIP_ARGS string prompt "Strip arguments" diff --git a/feeds.conf.default b/feeds.conf.default index 5759575a6..924bc7108 100644 --- a/feeds.conf.default +++ b/feeds.conf.default @@ -1,6 +1,6 @@ src-svn packages svn://svn.openwrt.org/openwrt/packages -#src-svn xwrt http://x-wrt.googlecode.com/svn/trunk/package -#src-svn luci http://svn.luci.subsignal.org/luci/branches/luci-0.9/contrib/package +#src-svn xwrt http://x-wrt.googlecode.com/svn/branches/backfire_10.03/package +#src-svn luci http://svn.luci.subsignal.org/luci/tags/0.9.0/contrib/package src-svn phone svn://svn.openwrt.org/openwrt/feeds/phone src-svn efl svn://svn.openwrt.org/openwrt/feeds/efl src-svn desktop svn://svn.openwrt.org/openwrt/feeds/desktop diff --git a/include/depends.mk b/include/depends.mk index 4c31eb398..65e9b25d5 100644 --- a/include/depends.mk +++ b/include/depends.mk @@ -11,7 +11,7 @@ # 3: tempfile for file listings # 4: find options -DEP_FINDPARAMS := -x "*.svn*" -x ".*" -x "*.svn*" -x "*:*" -x "*\!*" -x "* *" -x "*\\\#*" -x "*/.*_check" +DEP_FINDPARAMS := -x "*/.svn*" -x ".*" -x "*:*" -x "*\!*" -x "* *" -x "*\\\#*" -x "*/.*_check" find_md5=find $(1) -type f $(patsubst -x,-and -not -path,$(DEP_FINDPARAMS) $(2)) | md5s diff --git a/include/prereq-build.mk b/include/prereq-build.mk index 4d1ae891f..84d3f2274 100644 --- a/include/prereq-build.mk +++ b/include/prereq-build.mk @@ -134,7 +134,7 @@ $(eval $(call RequireCommand,svn, \ )) define Require/gnu-find - $(FIND) $(TMP_DIR) -lname foo + $(FIND) --version 2>/dev/null endef $(eval $(call Require,gnu-find, \ diff --git a/include/toplevel.mk b/include/toplevel.mk index fa0bc2587..83b73527d 100644 --- a/include/toplevel.mk +++ b/include/toplevel.mk @@ -6,7 +6,7 @@ # See /LICENSE for more information. # -RELEASE:=Kamikaze +RELEASE:=Backfire SHELL:=/usr/bin/env bash PREP_MK= OPENWRT_BUILD= QUIET=0 diff --git a/package/ar7-atm/Config.in b/package/ar7-atm/Config.in index 395755c59..479b7ad07 100644 --- a/package/ar7-atm/Config.in +++ b/package/ar7-atm/Config.in @@ -1,6 +1,8 @@ +menu "Configuration" + depends on (PACKAGE_kmod-sangam-atm-annex-a || PACKAGE_kmod-sangam-atm-annex-b) + choice prompt "Firmware version" - depends on (PACKAGE_kmod-sangam-atm-annex-a || PACKAGE_kmod-sangam-atm-annex-b) default AR7_ATM_FW_VERSION_704 help This option allows you to switch between firmware/driver versions which @@ -16,3 +18,5 @@ config AR7_ATM_FW_VERSION_703 bool "D7.03.01.00" endchoice + +endmenu diff --git a/package/ar7-atm/Makefile b/package/ar7-atm/Makefile index e5cef0791..fc8b57712 100644 --- a/package/ar7-atm/Makefile +++ b/package/ar7-atm/Makefile @@ -42,6 +42,7 @@ define KernelPackage/sangam-atm/Default TITLE:=AR7 ADSL driver FILES:=$(PKG_BUILD_DIR)/tiatm.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,50,tiatm) + MENU:=1 endef define KernelPackage/sangam-atm/config diff --git a/package/base-files/Makefile b/package/base-files/Makefile index 72e1802bc..c4717a78c 100644 --- a/package/base-files/Makefile +++ b/package/base-files/Makefile @@ -10,7 +10,7 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=base-files -PKG_RELEASE:=42 +PKG_RELEASE:=43 PKG_FILE_DEPENDS:=$(PLATFORM_DIR)/ $(GENERIC_PLATFORM_DIR)/base-files/ @@ -22,10 +22,7 @@ ifneq ($(DUMP),1) TARGET:=$(TARGET)-$(PROFILE) endif LIBGCC_VERSION:=$(GCC_VERSION) - ifeq ($(ARCH),x86_64) - LIB_SUFFIX:=64 - endif - ifneq ($(findstring mips64,$(ARCH)),) + ifneq ($(findstring $(ARCH) , mips64 x86_64 ),) LIB_SUFFIX:=64 endif else @@ -328,11 +325,6 @@ define Build/Compile $(call Build/Compile/Default) endef -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/lib - ln -sf $(TOOLCHAIN_DIR)/usr/lib$(LIB_SUFFIX)/libstdc++.{la,a,so*} $(1)/usr/lib/ -endef - define Package/base-files/install $(CP) ./files/* $(1)/ if [ -d $(GENERIC_PLATFORM_DIR)/base-files/. ]; then \ @@ -400,17 +392,17 @@ ifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),) define Package/libgcc/install $(INSTALL_DIR) $(1)/lib - $(CP) $(TOOLCHAIN_DIR)/lib$(LIB_SUFFIX)/libgcc_s.so.* $(1)/lib/ + $(CP) $(TOOLCHAIN_DIR)/lib/libgcc_s.so.* $(1)/lib/ endef define Package/libssp/install $(INSTALL_DIR) $(1)/lib - $(CP) $(TOOLCHAIN_DIR)/lib$(LIB_SUFFIX)/libssp.so.* $(1)/lib/ + $(CP) $(TOOLCHAIN_DIR)/lib/libssp.so.* $(1)/lib/ endef define Package/libstdcpp/install $(INSTALL_DIR) $(1)/usr/lib - $(CP) $(TOOLCHAIN_DIR)/usr/lib$(LIB_SUFFIX)/libstdc++.so.* $(1)/usr/lib/ + $(CP) $(TOOLCHAIN_DIR)/usr/lib/libstdc++.so.* $(1)/usr/lib/ endef use_libutil=$(if $(CONFIG_USE_GLIBC)$(CONFIG_EGLIBC_OPTION_EGLIBC_UTMP),libutil) @@ -433,7 +425,15 @@ ifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),) define Package/uClibc/install $(INSTALL_DIR) $(1)/lib - for file in ld$(LIB_SUFFIX)-uClibc libc libcrypt libdl libm libnsl libresolv libuClibc libutil; do \ + $(CP) \ + $(TOOLCHAIN_DIR)/lib/ld*-uClibc.so.* \ + $(TOOLCHAIN_DIR)/lib/ld*-uClibc-$(LIBC_SO_VERSION).so \ + $(1)/lib/ + $(CP) \ + $(TOOLCHAIN_DIR)/lib/libc.so.* \ + $(TOOLCHAIN_DIR)/lib/libuClibc-$(LIBC_SO_VERSION).so \ + $(1)/lib/ + for file in libcrypt libdl libm libnsl libresolv libutil; do \ $(CP) $(TOOLCHAIN_DIR)/lib/$$$$file.so.* $(1)/lib/; \ $(CP) $(TOOLCHAIN_DIR)/lib/$$$$file-$(LIBC_SO_VERSION).so $(1)/lib/; \ done diff --git a/package/base-files/files/etc/banner b/package/base-files/files/etc/banner index b8fe7eba5..7b32caf63 100644 --- a/package/base-files/files/etc/banner +++ b/package/base-files/files/etc/banner @@ -3,8 +3,8 @@ | - || _ | -__| || | | || _|| _| |_______|| __|_____|__|__||________||__| |____| |__| W I R E L E S S F R E E D O M - KAMIKAZE (bleeding edge, $R) ------------------ - * 10 oz Vodka Shake well with ice and strain - * 10 oz Triple sec mixture into 10 shot glasses. - * 10 oz lime juice Salute! + Backfire (10.03, $R) -------------------------- + * 1/3 shot Kahlua In a shot glass, layer Kahlua + * 1/3 shot Bailey's on the bottom, then Bailey's, + * 1/3 shot Vodka then Vodka. --------------------------------------------------- diff --git a/package/base-files/files/etc/openwrt_release b/package/base-files/files/etc/openwrt_release new file mode 100644 index 000000000..fc74a4eab --- /dev/null +++ b/package/base-files/files/etc/openwrt_release @@ -0,0 +1,4 @@ +DISTRIB_ID="OpenWrt" +DISTRIB_RELEASE="10.03" +DISTRIB_CODENAME="backfire" +DISTRIB_DESCRIPTION="OpenWrt Backfire 10.03" diff --git a/package/base-files/files/etc/openwrt_version b/package/base-files/files/etc/openwrt_version new file mode 100644 index 000000000..6de207cda --- /dev/null +++ b/package/base-files/files/etc/openwrt_version @@ -0,0 +1 @@ +10.03 diff --git a/package/block-extroot/Makefile b/package/block-extroot/Makefile index d24cbd134..eaf01dad5 100644 --- a/package/block-extroot/Makefile +++ b/package/block-extroot/Makefile @@ -26,7 +26,7 @@ endef define Package/block-extroot $(call Package/block-extroot/Default) MENU:=1 - DEPENDS:=+block-mount @PACKAGE_kmod-ide-core||PACKAGE_kmod-ata-core||PACKAGE_kmod-usb-storage||PACKAGE_kmod-mmc||PACKAGE_kmod-broadcom-sdhc + DEPENDS:=+block-mount @PACKAGE_kmod-ide-core||PACKAGE_kmod-usb-storage||PACKAGE_kmod-mmc||PACKAGE_kmod-broadcom-sdhc endef define Package/block-extroot/config diff --git a/package/block-mount/Makefile b/package/block-mount/Makefile index 38fe49101..a55ea0246 100644 --- a/package/block-mount/Makefile +++ b/package/block-mount/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=block-mount PKG_VERSION:=0.1.0 -PKG_RELEASE:=1 +PKG_RELEASE:=2 include $(INCLUDE_DIR)/package.mk @@ -40,6 +40,10 @@ endef define Build/Compile endef +define Package/block-mount/conffiles +/etc/config/fstab +endef + define Package/block-mount/install $(INSTALL_DIR) $(1)/etc/init.d $(INSTALL_BIN) ./files/fstab.init $(1)/etc/init.d/fstab diff --git a/package/broadcom-diag/src/diag.c b/package/broadcom-diag/src/diag.c index 0871a02a7..38f51cb65 100644 --- a/package/broadcom-diag/src/diag.c +++ b/package/broadcom-diag/src/diag.c @@ -377,7 +377,7 @@ static struct platform_t __initdata platforms[] = { }, .leds = { { .name = "power", .gpio = 1 << 0, .polarity = REVERSE }, - { .name = "usb", .gpio = 1 << 2, .polarity = NORMAL }, + { .name = "usb", .gpio = 1 << 2, .polarity = REVERSE }, }, }, [WL300G] = { diff --git a/package/busybox/target-config.in b/package/busybox/Config.in similarity index 86% rename from package/busybox/target-config.in rename to package/busybox/Config.in index b06556134..1002a5a0d 100644 --- a/package/busybox/target-config.in +++ b/package/busybox/Config.in @@ -1,3 +1,6 @@ +menu "Configuration" + depends on PACKAGE_busybox + config BUSYBOX_CONFIG_FEATURE_DEVFS bool default y if LINUX_2_4 @@ -31,3 +34,6 @@ config BUSYBOX_CONFIG_HUSH default y if NOMMU default n if !NOMMU +source "package/busybox/config/Config.in" + +endmenu diff --git a/package/busybox/Makefile b/package/busybox/Makefile index 214b7f3c9..e6934a6eb 100644 --- a/package/busybox/Makefile +++ b/package/busybox/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2006-2010 OpenWrt.org +# Copyright (C) 2006-2009 OpenWrt.org # # This is free software, licensed under the GNU General Public License v2. # See /LICENSE for more information. @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=busybox -PKG_VERSION:=1.16.1 +PKG_VERSION:=1.15.3 PKG_RELEASE:=2 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:=http://www.busybox.net/downloads \ http://distfiles.gentoo.org/distfiles/ -PKG_MD5SUM:=319486ec65078d07fde26eb620fecde7 +PKG_MD5SUM:=6059ac9456de6fb18dc8ee4cd0ec9240 include $(INCLUDE_DIR)/package.mk @@ -30,7 +30,6 @@ init-$(CONFIG_BUSYBOX_CONFIG_TELNETD) += telnet define Package/busybox SECTION:=base CATEGORY:=Base system - MAINTAINER:=Nicolas Thill TITLE:=Core utilities for embedded Linux URL:=http://busybox.net/ MENU:=1 @@ -42,11 +41,7 @@ define Package/busybox/description endef define Package/busybox/config - menu "Configuration" - depends on PACKAGE_busybox - source "$(SOURCE)/target-config.in" - source "$(SOURCE)/config/Config.in" - endmenu + source "$(SOURCE)/Config.in" endef define Build/Configure diff --git a/package/busybox/config/util-linux/Config.in b/package/busybox/config/util-linux/Config.in index a4fbc0ce6..fb08ca9b2 100644 --- a/package/busybox/config/util-linux/Config.in +++ b/package/busybox/config/util-linux/Config.in @@ -213,12 +213,6 @@ config BUSYBOX_CONFIG_FSCK_MINIX check for and attempt to repair any corruption that occurs to a minix filesystem. -config BUSYBOX_CONFIG_MKFS_EXT2 - bool "mkfs_ext2" - default n - help - Utility to create EXT2 filesystems. - config BUSYBOX_CONFIG_MKFS_MINIX bool "mkfs_minix" default n @@ -239,12 +233,6 @@ config BUSYBOX_CONFIG_FEATURE_MINIX2 this. If you enabled 'mkfs_minix' then you almost certainly want to be using the version 2 filesystem support. -config BUSYBOX_CONFIG_MKFS_REISER - bool "mkfs_reiser" - default n - help - Utility to create ReiserFS filesystems. - config BUSYBOX_CONFIG_MKFS_VFAT bool "mkfs_vfat" default n @@ -348,24 +336,6 @@ config BUSYBOX_CONFIG_LOSETUP file or block device, and to query the status of a loop device. This version does not currently support enabling data encryption. -config BUSYBOX_CONFIG_LSPCI - bool "lspci" - default n - help - lspci is a utility for displaying information about PCI buses in the - system and devices connected to them. - - This version uses sysfs (/sys/bus/pci/devices) only. - -config BUSYBOX_CONFIG_LSUSB - bool "lsusb" - default n - help - lsusb is a utility for displaying information about USB buses in the - system and devices connected to them. - - This version uses sysfs (/sys/bus/usb/devices) only. - config BUSYBOX_CONFIG_MDEV bool "mdev" default n @@ -475,13 +445,6 @@ config BUSYBOX_CONFIG_FEATURE_VOLUMEID_EXT help TODO -config BUSYBOX_CONFIG_FEATURE_VOLUMEID_BTRFS - bool "btrfs filesystem" - default y - depends on BUSYBOX_CONFIG_VOLUMEID - help - TODO - config BUSYBOX_CONFIG_FEATURE_VOLUMEID_REISERFS bool "Reiser filesystem" default y @@ -726,7 +689,6 @@ config BUSYBOX_CONFIG_FEATURE_MOUNT_LABEL help This allows for specifying a device by label or uuid, rather than by name. This feature utilizes the same functionality as blkid/findfs. - This also enables label or uuid support for swapon. config BUSYBOX_CONFIG_FEATURE_MOUNT_NFS bool "Support mounting NFS file systems" diff --git a/package/compcache/Config.in b/package/compcache/Config.in index 9904237ed..11a94d434 100644 --- a/package/compcache/Config.in +++ b/package/compcache/Config.in @@ -1,15 +1,14 @@ -# compcache configuration +menu "Configuration" + depends on PACKAGE_kmod-compcache config COMPCACHE_ENABLE bool "enabled on boot" default n - depends on PACKAGE_kmod-compcache help Enables compressed ram swap devices. config COMPCACHE_RAM_REPORTED string "swap space reported to kernel in kb" - depends on PACKAGE_kmod-compcache default "2048" help This is the amount of memory that will be reported @@ -21,10 +20,10 @@ config COMPCACHE_RAM_REPORTED config COMPCACHE_BACKUP_DEV string "Backup device for compcache" - depends on PACKAGE_kmod-compcache default "" help Compcache will use this as a backup device for swap. Example: /dev/sda5 +endmenu diff --git a/package/compcache/Makefile b/package/compcache/Makefile index 2fec28952..13a9056db 100644 --- a/package/compcache/Makefile +++ b/package/compcache/Makefile @@ -26,6 +26,7 @@ define KernelPackage/compcache VERSION:=$(LINUX_VERSION)-$(BOARD)-$(LINUX_RELEASE)+$(PKG_RELEASE) FILES:=$(PKG_BUILD_DIR)/ramzswap.$(LINUX_KMOD_SUFFIX) \ $(PKG_BUILD_DIR)/sub-projects/compression/lzo-kmod/lzo1x.$(LINUX_KMOD_SUFFIX) + MENU:=1 endef diff --git a/package/cyassl/patches/120-makefile_destdir.patch b/package/cyassl/patches/120-makefile_destdir.patch index d7ad1da67..29b0d0a05 100644 --- a/package/cyassl/patches/120-makefile_destdir.patch +++ b/package/cyassl/patches/120-makefile_destdir.patch @@ -1,6 +1,6 @@ --- a/Makefile.am +++ b/Makefile.am -@@ -8,14 +8,11 @@ basic: +@@ -8,14 +8,11 @@ basic: openssl-links: cd lib; ln -s ../src/.libs/libcyassl.a libcrypto.a; \ diff --git a/package/dnsmasq/Makefile b/package/dnsmasq/Makefile index 895a5c295..77b8f82a6 100644 --- a/package/dnsmasq/Makefile +++ b/package/dnsmasq/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=dnsmasq PKG_VERSION:=2.52 -PKG_RELEASE:=2 +PKG_RELEASE:=4 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=http://thekelleys.org.uk/dnsmasq diff --git a/package/dnsmasq/files/dnsmasq.init b/package/dnsmasq/files/dnsmasq.init index 4cd941cfd..15f856d4e 100644 --- a/package/dnsmasq/files/dnsmasq.init +++ b/package/dnsmasq/files/dnsmasq.init @@ -296,9 +296,17 @@ dhcp_domain_add() { local raddr="${4:+$4.$3.$2.$1.in-addr.arpa}" for name in $names; do - append args "-A /$name${DOMAIN:+.$DOMAIN}/$ip" - [ -n "$raddr" ] && \ - append args "--ptr-record=$raddr,$name${DOMAIN:+.$DOMAIN}" + local fqdn="$name" + + [ "${fqdn%.*}" == "$fqdn" ] && \ + fqdn="$fqdn${DOMAIN:+.$DOMAIN}" + + append args "-A /$fqdn/$ip" + + [ -n "$raddr" ] && { + append args "--ptr-record=$raddr,$fqdn" + raddr="" + } done } diff --git a/package/fuse/patches/100-cross_compile.patch b/package/fuse/patches/100-cross_compile.patch deleted file mode 100644 index e69de29bb..000000000 diff --git a/package/fuse/patches/102-no_depmod.patch b/package/fuse/patches/102-no_depmod.patch deleted file mode 100644 index e69de29bb..000000000 diff --git a/package/fuse/patches/200-disable_compat.patch b/package/fuse/patches/200-disable_compat.patch deleted file mode 100644 index e69de29bb..000000000 diff --git a/package/hostapd/patches/370-basic_rates.patch b/package/hostapd/patches/370-basic_rates.patch new file mode 100644 index 000000000..ef4691bbd --- /dev/null +++ b/package/hostapd/patches/370-basic_rates.patch @@ -0,0 +1,70 @@ +--- a/src/ap/hostapd.c ++++ b/src/ap/hostapd.c +@@ -707,6 +707,16 @@ int hostapd_setup_interface_complete(str + } + } + ++ if (iface->current_mode) { ++ if (hostapd_prepare_rates(hapd, iface->current_mode)) { ++ wpa_printf(MSG_ERROR, "Failed to prepare rates table."); ++ hostapd_logger(hapd, NULL, HOSTAPD_MODULE_IEEE80211, ++ HOSTAPD_LEVEL_WARNING, ++ "Failed to prepare rates table."); ++ return -1; ++ } ++ } ++ + if (hapd->iconf->rts_threshold > -1 && + hostapd_set_rts(hapd, hapd->iconf->rts_threshold)) { + wpa_printf(MSG_ERROR, "Could not set RTS threshold for " +--- a/src/ap/hw_features.c ++++ b/src/ap/hw_features.c +@@ -101,8 +101,8 @@ int hostapd_get_hw_features(struct hosta + } + + +-static int hostapd_prepare_rates(struct hostapd_data *hapd, +- struct hostapd_hw_modes *mode) ++int hostapd_prepare_rates(struct hostapd_data *hapd, ++ struct hostapd_hw_modes *mode) + { + int i, num_basic_rates = 0; + int basic_rates_a[] = { 60, 120, 240, -1 }; +@@ -668,14 +668,6 @@ int hostapd_select_hw_mode(struct hostap + return -1; + } + +- if (hostapd_prepare_rates(iface->bss[0], iface->current_mode)) { +- wpa_printf(MSG_ERROR, "Failed to prepare rates table."); +- hostapd_logger(iface->bss[0], NULL, HOSTAPD_MODULE_IEEE80211, +- HOSTAPD_LEVEL_WARNING, +- "Failed to prepare rates table."); +- return -1; +- } +- + return 0; + } + +--- a/src/ap/hw_features.h ++++ b/src/ap/hw_features.h +@@ -25,6 +25,8 @@ const char * hostapd_hw_mode_txt(int mod + int hostapd_hw_get_freq(struct hostapd_data *hapd, int chan); + int hostapd_hw_get_channel(struct hostapd_data *hapd, int freq); + int hostapd_check_ht_capab(struct hostapd_iface *iface); ++int hostapd_prepare_rates(struct hostapd_data *hapd, ++ struct hostapd_hw_modes *mode); + #else /* NEED_AP_MLME */ + static inline void + hostapd_free_hw_features(struct hostapd_hw_modes *hw_features, +@@ -56,6 +58,11 @@ static inline int hostapd_check_ht_capab + { + return 0; + } ++static inline int hostapd_prepare_rates(struct hostapd_data *hapd, ++ struct hostapd_hw_modes *mode) ++{ ++ return 0; ++} + + #endif /* NEED_AP_MLME */ + diff --git a/package/ifx-tapi/Config.in b/package/ifx-tapi/Config.in index 56defb3dd..e360883fd 100644 --- a/package/ifx-tapi/Config.in +++ b/package/ifx-tapi/Config.in @@ -1,3 +1,6 @@ +menu "Configuration" + depends on PACKAGE_kmod-ifx-tapi + config VOICE_CPE_TAPI_FAX bool "fax relay and modem support" default n @@ -69,3 +72,5 @@ config VOICE_CPE_TAPI_TRACES help enable driver traces with different trace levels to be configured dynamically from the application or during insmod + +endmenu diff --git a/package/ifx-tapi/Makefile b/package/ifx-tapi/Makefile index fe91ad015..e4638186e 100644 --- a/package/ifx-tapi/Makefile +++ b/package/ifx-tapi/Makefile @@ -26,6 +26,7 @@ define KernelPackage/ifx-tapi DEPENDS:=+kmod-ifxos @BROKEN FILES:=$(PKG_BUILD_DIR)/src/drv_tapi.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,20,drv_tapi) + MENU:=1 endef define KernelPackage/ifx-tapi/description @@ -33,9 +34,7 @@ define KernelPackage/ifx-tapi/description endef define KernelPackage/ifx-tapi/config - if PACKAGE_kmod-ifx-tapi - source "$(SOURCE)/Config.in" - endif + source "$(SOURCE)/Config.in" endef CONFIGURE_ARGS += \ diff --git a/package/ifx-tapidemo/Config.in b/package/ifx-tapidemo/Config.in index 32594ba9c..42ec5fa1c 100644 --- a/package/ifx-tapidemo/Config.in +++ b/package/ifx-tapidemo/Config.in @@ -1,3 +1,5 @@ +menu "Configuration" + depends on PACKAGE_ifx-tapidemo choice prompt "board selection" default VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3 if TARGET_ifxmips_platform_danube @@ -34,3 +36,4 @@ config VOICE_CPE_TAPIDEMO_FAX_T.38_FW help enable T.38 fax relay demo. +endmenu diff --git a/package/ifx-tapidemo/Makefile b/package/ifx-tapidemo/Makefile index 217d4641a..b294d9d3a 100644 --- a/package/ifx-tapidemo/Makefile +++ b/package/ifx-tapidemo/Makefile @@ -26,6 +26,7 @@ define Package/ifx-tapidemo URL:=http://www.lantiq.com/ MAINTAINER:=Lantiq DEPENDS:=+kmod-ifx-tapi +kmod-ifx-vmmc @BROKEN + MENU:=1 endef define Package/ifx-tapidemo/description @@ -33,9 +34,7 @@ define Package/ifx-tapidemo/description endef define Package/ifx-tapidemo/config - if PACKAGE_ifx-tapidemo - source "$(SOURCE)/Config.in" - endif + source "$(SOURCE)/Config.in" endef CONFIGURE_ARGS += \ diff --git a/package/ifx-vmmc/Config.in b/package/ifx-vmmc/Config.in index bd3c032d3..2a7894e7f 100644 --- a/package/ifx-vmmc/Config.in +++ b/package/ifx-vmmc/Config.in @@ -1,3 +1,5 @@ +menu "Configuration" + depends on PACKAGE_kmod-ifx-vmmc choice prompt "device selection" default VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract @@ -47,3 +49,5 @@ config VOICE_CPE_VMMC_MPS_HISTORY_SIZE MPS history buffer (default=128 words, maximum=512 words, 0=disable) To opimize the memory footprint in RAM, you might want to set the buffer size to 0. + +endmenu diff --git a/package/ifx-vmmc/Makefile b/package/ifx-vmmc/Makefile index 945d5ba7e..0fa3649e9 100644 --- a/package/ifx-vmmc/Makefile +++ b/package/ifx-vmmc/Makefile @@ -26,6 +26,7 @@ define KernelPackage/ifx-vmmc DEPENDS:=+kmod-ifx-tapi @BROKEN FILES:=$(PKG_BUILD_DIR)/src/drv_vmmc.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,25,drv_vmmc) + MENU:=1 endef define KernelPackage/ifx-vmmc/description @@ -33,9 +34,7 @@ define KernelPackage/ifx-vmmc/description endef define KernelPackage/ifx-vmmc/config - if PACKAGE_kmod-ifx-vmmc - source "$(SOURCE)/Config.in" - endif + source "$(SOURCE)/Config.in" endef CONFIGURE_ARGS += \ diff --git a/package/ifxmips-dsl-api/Config.in b/package/ifxmips-dsl-api/Config.in index 56177d168..72942e6ff 100644 --- a/package/ifxmips-dsl-api/Config.in +++ b/package/ifxmips-dsl-api/Config.in @@ -1,6 +1,8 @@ +menu "Configuration" + depends on PACKAGE_kmod-ifxmips-dsl-api + choice prompt "Firmware" - depends on PACKAGE_kmod-ifxmips-dsl-api default IFXMIPS_ANNEX_B help This option controls which firmware is loaded @@ -20,12 +22,12 @@ endchoice config IFXMIPS_DSL_FIRMWARE bool "ifxmips-dsl firmware extractor" default y - depends on PACKAGE_kmod-ifxmips-dsl-api help Say Y, if you need ifxmips-dsl to auto extract the firmware for you from the a800 firmware image config IFXMIPS_DSL_DEBUG bool "ifxmips-dsl debugging" - depends on PACKAGE_kmod-ifxmips-dsl-api help Say Y, if you need ifxmips-dsl to display debug messages. + +endmenu diff --git a/package/ifxmips-dsl-api/Makefile b/package/ifxmips-dsl-api/Makefile index c0e1cea08..a5cd221a5 100644 --- a/package/ifxmips-dsl-api/Makefile +++ b/package/ifxmips-dsl-api/Makefile @@ -39,6 +39,7 @@ define KernelPackage/ifxmips-dsl-api $(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.$(LINUX_KMOD_SUFFIX) \ $(PKG_BUILD_DIR)/src/mei/ifxmips_atm.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,50,ifxmips_mei drv_dsl_cpe_api ifxmips_atm) + MENU:=1 endef define KernelPackage/ifxmips-dsl-api/description diff --git a/package/kernel/modules/netsupport.mk b/package/kernel/modules/netsupport.mk index 53e218d26..0c0c91244 100644 --- a/package/kernel/modules/netsupport.mk +++ b/package/kernel/modules/netsupport.mk @@ -193,6 +193,11 @@ endef $(eval $(call KernelPackage,ipip)) +IPSEC-m:= \ + key/af_key \ + xfrm/xfrm_ipcomp \ + xfrm/xfrm_user \ + define KernelPackage/ipsec SUBMENU:=$(NETWORK_SUPPORT_MENU) TITLE:=IPsec related modules (IPv4 and IPv6) @@ -201,22 +206,30 @@ define KernelPackage/ipsec CONFIG_NET_KEY \ CONFIG_XFRM_USER \ CONFIG_XFRM_IPCOMP - FILES:= \ - $(LINUX_DIR)/net/key/af_key.$(LINUX_KMOD_SUFFIX) \ - $(LINUX_DIR)/net/xfrm/xfrm_user.$(LINUX_KMOD_SUFFIX) \ - $(LINUX_DIR)/net/xfrm/xfrm_ipcomp.$(LINUX_KMOD_SUFFIX) + FILES:=$(foreach mod,$(IPSEC-m),$(LINUX_DIR)/net/$(mod).$(LINUX_KMOD_SUFFIX)) + AUTOLOAD:=$(call AutoLoad,30,$(notdir $(IPSEC-m))) endef define KernelPackage/ipsec/description Kernel modules for IPsec support in both IPv4 and IPv6. Includes: - af_key + - xfrm_ipcomp - xfrm_user endef $(eval $(call KernelPackage,ipsec)) +IPSEC4-m:= \ + ipv4/ah4 \ + ipv4/esp4 \ + ipv4/xfrm4_mode_beet \ + ipv4/xfrm4_mode_transport \ + ipv4/xfrm4_mode_tunnel \ + ipv4/xfrm4_tunnel \ + ipv4/ipcomp \ + define KernelPackage/ipsec4 SUBMENU:=$(NETWORK_SUPPORT_MENU) TITLE:=IPsec related modules (IPv4) @@ -229,9 +242,8 @@ define KernelPackage/ipsec4 CONFIG_INET_XFRM_MODE_TRANSPORT \ CONFIG_INET_XFRM_MODE_TUNNEL \ CONFIG_INET_XFRM_TUNNEL - FILES:= $(foreach mod,ah4 esp4 ipcomp xfrm4_mode_beet xfrm4_mode_transport xfrm4_mode_tunnel xfrm4_tunnel , \ - $(LINUX_DIR)/net/ipv4/$(mod).$(LINUX_KMOD_SUFFIX) \ - ) + FILES:=$(foreach mod,$(IPSEC4-m),$(LINUX_DIR)/net/$(mod).$(LINUX_KMOD_SUFFIX)) + AUTOLOAD:=$(call AutoLoad,32,$(notdir $(IPSEC4-m))) endef define KernelPackage/ipsec4/description @@ -249,6 +261,15 @@ endef $(eval $(call KernelPackage,ipsec4)) +IPSEC6-m:= \ + ipv6/ah6 \ + ipv6/esp6 \ + ipv6/xfrm6_mode_beet \ + ipv6/xfrm6_mode_transport \ + ipv6/xfrm6_mode_tunnel \ + ipv6/xfrm6_tunnel \ + ipv6/ipcomp6 \ + define KernelPackage/ipsec6 SUBMENU:=$(NETWORK_SUPPORT_MENU) TITLE:=IPsec related modules (IPv6) @@ -261,9 +282,8 @@ define KernelPackage/ipsec6 CONFIG_INET6_XFRM_MODE_TRANSPORT \ CONFIG_INET6_XFRM_MODE_TUNNEL \ CONFIG_INET6_XFRM_TUNNEL - FILES:= $(foreach mod,ah6 esp6 ipcomp6 xfrm6_mode_beet xfrm6_mode_transport xfrm6_mode_tunnel xfrm6_tunnel, \ - $(LINUX_DIR)/net/ipv6/$(mod).$(LINUX_KMOD_SUFFIX) \ - ) + FILES:=$(foreach mod,$(IPSEC6-m),$(LINUX_DIR)/net/$(mod).$(LINUX_KMOD_SUFFIX)) + AUTOLOAD:=$(call AutoLoad,32,$(notdir $(IPSEC6-m))) endef define KernelPackage/ipsec6/description @@ -289,9 +309,7 @@ define KernelPackage/iptunnel4 KCONFIG:= \ CONFIG_NET_IPIP \ CONFIG_INET_TUNNEL - FILES:= $(foreach mod,tunnel4, \ - $(LINUX_DIR)/net/ipv4/$(mod).$(LINUX_KMOD_SUFFIX) \ - ) + FILES:=$(LINUX_DIR)/net/ipv4/tunnel4.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,31,tunnel4) endef @@ -308,9 +326,7 @@ define KernelPackage/iptunnel6 DEPENDS:= @LINUX_2_6 +kmod-ipv6 KCONFIG:= \ CONFIG_INET6_TUNNEL - FILES:= $(foreach mod,tunnel6, \ - $(LINUX_DIR)/net/ipv6/$(mod).$(LINUX_KMOD_SUFFIX) \ - ) + FILES:=$(LINUX_DIR)/net/ipv6/tunnel6.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,31,tunnel6) endef diff --git a/package/kernel/modules/other.mk b/package/kernel/modules/other.mk index a000656bf..97ce3d3b7 100644 --- a/package/kernel/modules/other.mk +++ b/package/kernel/modules/other.mk @@ -261,7 +261,8 @@ $(eval $(call KernelPackage,ssb)) define KernelPackage/bluetooth SUBMENU:=$(OTHER_MENU) TITLE:=Bluetooth support - DEPENDS:=@USB_SUPPORT +kmod-usb-core +!TARGET_x86:kmod-hid + DEPENDS:=@USB_SUPPORT +kmod-crc16 +kmod-usb-core +!TARGET_x86:kmod-hid \ + +(TARGET_x86||TARGET_s3c24xx||TARGET_brcm47xx||TARGET_ar71xx):kmod-rfkill KCONFIG:= \ CONFIG_BLUEZ \ CONFIG_BLUEZ_L2CAP \ @@ -798,7 +799,7 @@ $(eval $(call KernelPackage,mmc-atmelmci,1)) define KernelPackage/cs5535-gpio SUBMENU:=$(OTHER_MENU) TITLE:=AMD CS5535/CS5536 GPIO driver - DEPENDS:=@TARGET_x86||@TARGET_olpc + DEPENDS:=@TARGET_x86 KCONFIG:=CONFIG_CS5535_GPIO FILES:=$(LINUX_DIR)/drivers/char/cs5535_gpio.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,50,cs5535_gpio) @@ -851,7 +852,7 @@ $(eval $(call KernelPackage,textsearch)) define KernelPackage/rfkill SUBMENU:=$(OTHER_MENU) TITLE:=RF switch subsystem support - DEPENDS:=@TARGET_x86||TARGET_olpc||TARGET_s3c24xx||TARGET_brcm47xx||TARGET_ar71xx + DEPENDS:=@TARGET_x86||TARGET_s3c24xx||TARGET_brcm47xx||TARGET_ar71xx KCONFIG:= \ CONFIG_RFKILL \ CONFIG_RFKILL_INPUT=y \ diff --git a/package/kernel/modules/sound.mk b/package/kernel/modules/sound.mk index 46bc6853a..a3d148634 100644 --- a/package/kernel/modules/sound.mk +++ b/package/kernel/modules/sound.mk @@ -10,7 +10,7 @@ SOUND_MENU:=Sound Support define KernelPackage/sound-core SUBMENU:=$(SOUND_MENU) TITLE:=Sound support - DEPENDS:=@AUDIO_SUPPORT + DEPENDS:=@AUDIO_SUPPORT +!TARGET_x86:kmod-input-core KCONFIG:= \ CONFIG_SOUND \ CONFIG_SND \ diff --git a/package/kernel/modules/usb.mk b/package/kernel/modules/usb.mk index c962e340e..3af58441b 100644 --- a/package/kernel/modules/usb.mk +++ b/package/kernel/modules/usb.mk @@ -158,6 +158,24 @@ endef $(eval $(call KernelPackage,usb-octeon)) +define KernelPackage/usb-isp116x-hcd +$(call KernelPackage/usb/Depends,@TARGET_ppc40x) + TITLE:=Support for the ISP116x USB Host Controller + KCONFIG:= \ + CONFIG_USB_ISP116X_HCD \ + CONFIG_USB_ISP116X_HCD_OF=y \ + CONFIG_USB_ISP116X_HCD_PLATFORM=n + FILES:=$(LINUX_DIR)/drivers/usb/host/isp116x-hcd.$(LINUX_KMOD_SUFFIX) + AUTOLOAD:=$(call AutoLoad,50,isp116x-hcd) +endef + +define KernelPackage/usb-isp116x-hcd/description + Kernel support for the ISP116X USB Host Controller +endef + +$(eval $(call KernelPackage,usb-isp116x-hcd)) + + define KernelPackage/usb2 $(call KernelPackage/usb/Depends,) TITLE:=Support for USB2 controllers @@ -451,6 +469,24 @@ endef $(eval $(call KernelPackage,usb-serial-visor)) +define KernelPackage/usb-serial-cypress-m8 +$(call KernelPackage/usb-serial/Depends,) + TITLE:=Support for CypressM8 USB-Serial + KCONFIG:=CONFIG_USB_SERIAL_CYPRESS_M8 + FILES:=$(LINUX_DIR)/drivers/usb/serial/cypress_m8.$(LINUX_KMOD_SUFFIX) + AUTOLOAD:=$(call AutoLoad,65,cypress_m8) +endef + +define KernelPackage/usb-serial-cypress-m8/description + Kernel support for devices with Cypress M8 USB to Serial chip + (for example, the Delorme Earthmate LT-20 GPS) + Supported microcontrollers in the CY4601 family are: + CY7C63741 CY7C63742 CY7C63743 CY7C64013 +endef + +$(eval $(call KernelPackage,usb-serial-cypress-m8)) + + define KernelPackage/usb-serial-keyspan $(call KernelPackage/usb-serial/Depends,) TITLE:=Support for Keyspan USB-to-Serial devices @@ -764,7 +800,7 @@ $(eval $(call KernelPackage,usb-net-cdc-ether)) define KernelPackage/usb-net-rndis $(call KernelPackage/usb-net/Depends,@LINUX_2_6 +kmod-usb-net-cdc-ether) TITLE:=Support for RNDIS connections - KCONFIG:=CONFIG_USB_NET_RNDIS_HOST + KCONFIG:=CONFIG_USB_NET_RNDIS_HOST FILES:= $(LINUX_DIR)/drivers/$(USBNET_DIR)/rndis_host.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,62,rndis_host) endef diff --git a/package/kexec-tools/kexec-config.in b/package/kexec-tools/Config.in similarity index 84% rename from package/kexec-tools/kexec-config.in rename to package/kexec-tools/Config.in index 25fed1b7c..60c819d79 100644 --- a/package/kexec-tools/kexec-config.in +++ b/package/kexec-tools/Config.in @@ -1,7 +1,9 @@ +menu "Configuration" + depends on PACKAGE_kexec-tools config KEXEC_TOOLS_TARGET_NAME string - prompt "Target name for kexec kernel" if PACKAGE_kexec-tools + prompt "Target name for kexec kernel" default EXTRA_TARGET_ARCH_NAME if powerpc64 default ARCH help @@ -12,8 +14,8 @@ config KEXEC_TOOLS_TARGET_NAME config KEXEC_TOOLS_kdump bool prompt "kdump support" - depends on PACKAGE_kexec-tools default n help Include the kdump utility. +endmenu diff --git a/package/kexec-tools/Makefile b/package/kexec-tools/Makefile index d350bb2c8..978bb6fd5 100644 --- a/package/kexec-tools/Makefile +++ b/package/kexec-tools/Makefile @@ -34,7 +34,7 @@ define Package/kexec-tools/description endef define Package/kexec-tools/config - source "$(SOURCE)/kexec-config.in" + source "$(SOURCE)/Config.in" endef KEXEC_TARGET_NAME:=$(call qstrip,$(CONFIG_KEXEC_TOOLS_TARGET_NAME))-linux-$(TARGET_SUFFIX) diff --git a/package/libpcap/Config.in b/package/libpcap/Config.in index 1b9463e6a..ef32c1bc0 100644 --- a/package/libpcap/Config.in +++ b/package/libpcap/Config.in @@ -1,12 +1,15 @@ +menu "Configuration" + depends PACKAGE_libpcap + config PCAP_HAS_USB bool "Include USB support" - depends PACKAGE_libpcap depends PACKAGE_kmod-usb-core default n config PCAP_HAS_BT bool "Include bluetooth support" - depends PACKAGE_libpcap depends PACKAGE_kmod-bluetooth depends BROKEN default n + +endmenu diff --git a/package/libpcap/Makefile b/package/libpcap/Makefile index fcc9987c0..a885f90c7 100644 --- a/package/libpcap/Makefile +++ b/package/libpcap/Makefile @@ -25,6 +25,7 @@ define Package/libpcap CATEGORY:=Libraries TITLE:=Low-level packet capture library URL:=http://www.tcpdump.org/ + MENU:=1 endef define Package/libpcap/description @@ -33,7 +34,7 @@ capture. endef define Package/libpcap/config -source "$(SOURCE)/Config.in" + source "$(SOURCE)/Config.in" endef TARGET_CFLAGS += \ diff --git a/package/mac80211/Config.in b/package/mac80211/Config.in deleted file mode 100644 index 5994ba71e..000000000 --- a/package/mac80211/Config.in +++ /dev/null @@ -1,11 +0,0 @@ -# mac80211 configuration - -config PACKAGE_MAC80211_DEBUGFS - bool "Export mac80211 internals in DebugFS" - depends on PACKAGE_kmod-mac80211 - default y - ---help--- - Select this to see extensive information about - the internal state of mac80211 in debugfs. - - Say N unless you know you need this. diff --git a/package/mac80211/Config.in.ath9k b/package/mac80211/Config.in.ath9k deleted file mode 100644 index 70a36c97c..000000000 --- a/package/mac80211/Config.in.ath9k +++ /dev/null @@ -1,16 +0,0 @@ -# mac80211 configuration - -config PACKAGE_ATH9K_DEBUG - bool "ath9k debugging" - depends PACKAGE_kmod-ath9k && KERNEL_DEBUG_FS - ---help--- - Say Y, if you need ath9k to display debug messages. - Pass the debug mask as a module parameter: - - modprobe ath9k debug=0x00002000 - - Look in ath9k/core.h for possible debug masks - -config PACKAGE_ATH9K_USE_MINSTREL - bool "use the new minstrel_ht rate control for ath9k" - depends PACKAGE_kmod-ath9k diff --git a/package/mac80211/Config.in.b43 b/package/mac80211/Config.in.b43 deleted file mode 100644 index e1f4d37d7..000000000 --- a/package/mac80211/Config.in.b43 +++ /dev/null @@ -1,79 +0,0 @@ -# B43 configuration - -choice - prompt "b43 firmware version" - depends on PACKAGE_kmod-b43 - default B43_EXPERIMENTAL - help - This option allows you to select the version of the b43 firmware. - -config B43_STABLE - bool "4.150.10.5 (stable)" - help - Stable firmware for BCM43xx devices. - - If unsure, select this. - -config B43_EXPERIMENTAL - bool "4.178.10.4 (experimental)" - help - Experimental firmware for BCM43xx devices. - - This firmware is not tested as much as the "stable" firmware. - - If unsure, select the "stable" firmware. - -config B43_OPENFIRMWARE - bool "Open FirmWare for WiFi networks" - help - Opensource firmware for BCM43xx devices. - - Do _not_ select this, unless you know what you are doing. - The Opensource firmware is not suitable for embedded devices, yet. - It does not support QoS, which is bad for AccessPoints. - It does not support hardware crypto acceleration, which is a showstopper - for embedded devices with low CPU resources. - - If unsure, select the "stable" firmware. - -endchoice - -config B43_FW_SQUASH - bool "Remove unnecessary firmware files" - depends on PACKAGE_kmod-b43 && !B43_OPENFIRMWARE - default y - help - This options allows you to remove unnecessary b43 firmware files - from the final rootfs image. This can reduce the rootfs size by - up to 200k. - - If unsure, say Y. - -config B43_FW_SQUASH_COREREVS - string "Core revisions to include" - depends on PACKAGE_kmod-b43 && B43_FW_SQUASH - default "5,6,7,8,9,10,13,14,15" - help - This is a comma seperated list of core revision numbers. - Example (keep files for rev5 only): - 5 - Example (keep files for rev5 and rev11): - 5,11 - -config B43_FW_SQUASH_PHYTYPES - string "PHY types to include" - depends on PACKAGE_kmod-b43 && B43_FW_SQUASH - default "G,LP" - help - This is a comma seperated list of PHY types: - A => A-PHY - AG => Dual A-PHY G-PHY - G => G-PHY - LP => LP-PHY - N => N-PHY - - Example (keep files for G-PHY only): - G - Example (keep files for G-PHY and N-PHY): - G,N - diff --git a/package/mac80211/Config.in.b43legacy b/package/mac80211/Config.in.b43legacy deleted file mode 100644 index 2e2f06e5a..000000000 --- a/package/mac80211/Config.in.b43legacy +++ /dev/null @@ -1,24 +0,0 @@ -# B43 configuration - -config B43LEGACY_FW_SQUASH - bool "Remove unnecessary firmware files" - depends on PACKAGE_kmod-b43legacy - default y - help - This options allows you to remove unnecessary b43legacy firmware files - from the final rootfs image. This can reduce the rootfs size by - up to 50k. - - If unsure, say Y. - -config B43LEGACY_FW_SQUASH_COREREVS - string "Core revisions to include" - depends on PACKAGE_kmod-b43legacy && B43LEGACY_FW_SQUASH - default "1,2,3,4" - help - This is a comma seperated list of core revision numbers. - Example (keep files for rev4 only): - 4 - Example (keep files for rev2 and rev4): - 2,4 - diff --git a/package/mac80211/Config.in.rt2x00 b/package/mac80211/Config.in.rt2x00 deleted file mode 100644 index f9855145b..000000000 --- a/package/mac80211/Config.in.rt2x00 +++ /dev/null @@ -1,15 +0,0 @@ -# rt2x00 configuration - -config PACKAGE_RT2X00_LIB_DEBUGFS - bool "Enable rt2x00 debugfs support" - depends PACKAGE_kmod-rt2x00-lib && PACKAGE_MAC80211_DEBUGFS - ---help--- - Enable creation of debugfs files for the rt2x00 drivers. - These debugfs files support both reading and writing of the - most important register types of the rt2x00 hardware. - -config PACKAGE_RT2X00_DEBUG - bool "Enable rt2x00 debug output" - depends PACKAGE_kmod-rt2x00-lib - ---help--- - Enable debugging output for all rt2x00 modules diff --git a/package/mac80211/Makefile b/package/mac80211/Makefile index 29b855629..2ea39c89a 100644 --- a/package/mac80211/Makefile +++ b/package/mac80211/Makefile @@ -66,10 +66,23 @@ define KernelPackage/mac80211 DEPENDS+= +kmod-crypto-core +kmod-crypto-arc4 +kmod-crypto-aes +kmod-cfg80211 FILES:= $(PKG_BUILD_DIR)/net/mac80211/mac80211.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,21,mac80211) + MENU:=1 endef define KernelPackage/mac80211/config - source "$(SOURCE)/Config.in" + menu "Configuration" + depends on PACKAGE_kmod-mac80211 + + config PACKAGE_MAC80211_DEBUGFS + bool "Export mac80211 internals in DebugFS" + default y + help + Select this to see extensive information about + the internal state of mac80211 in debugfs. + + Say N unless you know you need this. + + endmenu endef define KernelPackage/mac80211/description @@ -186,10 +199,27 @@ $(call KernelPackage/rt2x00/Default) TITLE+= (LIB) FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2x00lib.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,25,rt2x00lib) + MENU:=1 endef define KernelPackage/rt2x00-lib/config - source "$(SOURCE)/Config.in.rt2x00" + menu "Configuration" + depends PACKAGE_kmod-rt2x00-lib + + config PACKAGE_RT2X00_LIB_DEBUGFS + bool "Enable rt2x00 debugfs support" + depends PACKAGE_MAC80211_DEBUGFS + help + Enable creation of debugfs files for the rt2x00 drivers. + These debugfs files support both reading and writing of the + most important register types of the rt2x00 hardware. + + config PACKAGE_RT2X00_DEBUG + bool "Enable rt2x00 debug output" + help + Enable debugging output for all rt2x00 modules + + endmenu endef define KernelPackage/rt2x00-pci @@ -321,24 +351,27 @@ define KernelPackage/zd1211rw endef define KernelPackage/ath/config + menu "Configuration" + depends on PACKAGE_kmod-ath -config ATH_USER_REGD - bool "Force Atheros drivers to respect the user's regdomain settings" - depends on PACKAGE_kmod-ath - help - Atheros' idea of regulatory handling is that the EEPROM of the card defines - the regulatory limits and the user is only allowed to restrict the settings - even further, even if the country allows frequencies or power levels that - are forbidden by the EEPROM settings. - Select this option if you want the driver to respect the user's decision about - regulatory settings. + config ATH_USER_REGD + bool "Force Atheros drivers to respect the user's regdomain settings" + help + Atheros' idea of regulatory handling is that the EEPROM of the card defines + the regulatory limits and the user is only allowed to restrict the settings + even further, even if the country allows frequencies or power levels that + are forbidden by the EEPROM settings. -config PACKAGE_ATH_DEBUG - bool "Atheros wireless debugging" - depends on PACKAGE_kmod-ath - help - Say Y, if you want to debug atheros wireless drivers. - Right now only ath9k makes use of this. + Select this option if you want the driver to respect the user's decision about + regulatory settings. + + config PACKAGE_ATH_DEBUG + bool "Atheros wireless debugging" + help + Say Y, if you want to debug atheros wireless drivers. + Right now only ath9k makes use of this. + + endmenu endef define KernelPackage/ath @@ -347,6 +380,7 @@ define KernelPackage/ath DEPENDS+= @PCI_SUPPORT +kmod-mac80211 FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,26,ath) + MENU:=1 endef define KernelPackage/ath/description @@ -377,6 +411,7 @@ define KernelPackage/ath9k $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k_hw.$(LINUX_KMOD_SUFFIX) \ $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,27,ath9k_hw ath9k_common ath9k) + MENU:=1 endef define KernelPackage/ath9k/description @@ -385,7 +420,13 @@ Atheros IEEE 802.11n AR5008 and AR9001 family of chipsets. endef define KernelPackage/ath9k/config - source "$(SOURCE)/Config.in.ath9k" + menu "Configuration" + depends PACKAGE_kmod-ath9k + + config PACKAGE_ATH9K_USE_MINSTREL + bool "use the new minstrel_ht rate control for ath9k" + + endmenu endef USB8388FW_NAME:=usb8388 @@ -579,10 +620,93 @@ $(call KernelPackage/b43-common) TITLE:=Broadcom 43xx wireless support FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/b43/b43.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,30,b43) + MENU:=1 endef define KernelPackage/b43/config - source "$(SOURCE)/Config.in.b43" + menu "Configuration" + depends on PACKAGE_kmod-b43 + + choice + prompt "b43 firmware version" + default B43_EXPERIMENTAL + help + This option allows you to select the version of the b43 firmware. + + config B43_STABLE + bool "4.150.10.5 (stable)" + help + Stable firmware for BCM43xx devices. + + If unsure, select this. + + config B43_EXPERIMENTAL + bool "4.178.10.4 (experimental)" + help + Experimental firmware for BCM43xx devices. + + This firmware is not tested as much as the "stable" firmware. + + If unsure, select the "stable" firmware. + + config B43_OPENFIRMWARE + bool "Open FirmWare for WiFi networks" + help + Opensource firmware for BCM43xx devices. + + Do _not_ select this, unless you know what you are doing. + The Opensource firmware is not suitable for embedded devices, yet. + It does not support QoS, which is bad for AccessPoints. + It does not support hardware crypto acceleration, which is a showstopper + for embedded devices with low CPU resources. + + If unsure, select the "stable" firmware. + + endchoice + + config B43_FW_SQUASH + bool "Remove unnecessary firmware files" + depends on !B43_OPENFIRMWARE + default y + help + This options allows you to remove unnecessary b43 firmware files + from the final rootfs image. This can reduce the rootfs size by + up to 200k. + + If unsure, say Y. + + config B43_FW_SQUASH_COREREVS + string "Core revisions to include" + depends on B43_FW_SQUASH + default "5,6,7,8,9,10,13,14,15" + help + This is a comma seperated list of core revision numbers. + + Example (keep files for rev5 only): + 5 + + Example (keep files for rev5 and rev11): + 5,11 + + config B43_FW_SQUASH_PHYTYPES + string "PHY types to include" + depends on B43_FW_SQUASH + default "G,LP" + help + This is a comma seperated list of PHY types: + A => A-PHY + AG => Dual A-PHY G-PHY + G => G-PHY + LP => LP-PHY + N => N-PHY + + Example (keep files for G-PHY only): + G + + Example (keep files for G-PHY and N-PHY): + G,N + + endmenu endef define KernelPackage/b43/description @@ -594,10 +718,37 @@ $(call KernelPackage/b43-common) TITLE:=Broadcom 43xx-legacy wireless support FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/b43legacy/b43legacy.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,30,b43legacy) + MENU:=1 endef define KernelPackage/b43legacy/config - source "$(SOURCE)/Config.in.b43legacy" + menu "Configuration" + depends on PACKAGE_kmod-b43legacy + + config B43LEGACY_FW_SQUASH + bool "Remove unnecessary firmware files" + default y + help + This options allows you to remove unnecessary b43legacy firmware files + from the final rootfs image. This can reduce the rootfs size by + up to 50k. + + If unsure, say Y. + + config B43LEGACY_FW_SQUASH_COREREVS + string "Core revisions to include" + depends on B43LEGACY_FW_SQUASH + default "1,2,3,4" + help + This is a comma seperated list of core revision numbers. + + Example (keep files for rev4 only): + 4 + + Example (keep files for rev2 and rev4): + 2,4 + + endmenu endef define KernelPackage/b43legacy/description diff --git a/package/mac80211/patches/550-ath9k_bb_fix.patch b/package/mac80211/patches/550-ath9k_bb_fix.patch index 0cfb6cf65..e97bcacad 100644 --- a/package/mac80211/patches/550-ath9k_bb_fix.patch +++ b/package/mac80211/patches/550-ath9k_bb_fix.patch @@ -15,8 +15,8 @@ + do { + reg = REG_READ(ah, AR_OBS_BUS_1); + -+ if ((reg & 0x7E7FFFEF) != 0x00702400) -+ return true; ++ if ((reg & 0x7E7FFFEF) == 0x00702400) ++ continue; + + switch (reg & 0x7E000B00) { + case 0x1E000000: diff --git a/package/madwifi/Config.in b/package/madwifi/Config.in index 7f1e36d04..7b72eb854 100644 --- a/package/madwifi/Config.in +++ b/package/madwifi/Config.in @@ -1,13 +1,13 @@ -# MadWifi configuration +menu "Configuration" + depends on PACKAGE_kmod-madwifi config MADWIFI_DEBUG bool "Enable compilation of debugging features" - depends on DEVEL && PACKAGE_kmod-madwifi + depends on DEVEL default n config MADWIFI_COMPRESSION bool "Enable Atheros Super A/G Compression" - depends on PACKAGE_kmod-madwifi depends !TARGET_ar71xx default n help @@ -15,7 +15,6 @@ config MADWIFI_COMPRESSION config MADWIFI_SINGLE_MODULE bool "Combine driver and net80211 into a single module" - depends on PACKAGE_kmod-madwifi default y help This option combines all driver and stack related code (except for HAL) @@ -24,7 +23,6 @@ config MADWIFI_SINGLE_MODULE choice prompt "Rate control algorithm selection" - depends on PACKAGE_kmod-madwifi default MADWIFI_RCA_MINSTREL help This option controls how MadWifi chooses its bitrate. @@ -53,3 +51,5 @@ config MADWIFI_RCA_SAMPLERATE average transmission time. endchoice + +endmenu diff --git a/package/madwifi/Makefile b/package/madwifi/Makefile index 4c8415a6b..4f01f008f 100644 --- a/package/madwifi/Makefile +++ b/package/madwifi/Makefile @@ -165,6 +165,7 @@ define KernelPackage/madwifi DEPENDS:=+wireless-tools @LINUX_2_6 @PCI_SUPPORT @(!(TARGET_avr32||TARGET_cobalt||TARGET_ep93xx||TARGET_etrax||TARGET_octeon||TARGET_pxcab||TARGET_sibyte)||BROKEN) FILES:=$(MADWIFI_FILES) AUTOLOAD:=$(call AutoLoad,50,$(MADWIFI_AUTOLOAD)) + MENU:=1 endef define KernelPackage/madwifi/description diff --git a/package/mmc_over_gpio/Makefile b/package/mmc_over_gpio/Makefile index 4c6fdb5a9..5a3ab1d60 100644 --- a/package/mmc_over_gpio/Makefile +++ b/package/mmc_over_gpio/Makefile @@ -21,28 +21,30 @@ define KernelPackage/mmc-over-gpio TITLE:=MMC/SD card over GPIO support FILES:=$(LINUX_DIR)/drivers/mmc/host/gpiommc.$(LINUX_KMOD_SUFFIX) AUTOLOAD:=$(call AutoLoad,93,gpiommc) + MENU:=1 endef define Package/kmod-mmc-over-gpio/config -config KMOD_MMC_OVER_GPIO_DI_PIN - int "GPIO DI PIN" - depends PACKAGE_kmod-mmc-over-gpio - default 1 + menu "Configuration" + depends PACKAGE_kmod-mmc-over-gpio -config KMOD_MMC_OVER_GPIO_DO_PIN - int "GPIO DO PIN" - depends PACKAGE_kmod-mmc-over-gpio - default 3 + config KMOD_MMC_OVER_GPIO_DI_PIN + int "GPIO DI (Data-In) pin" + default 1 -config KMOD_MMC_OVER_GPIO_CLK_PIN - int "GPIO CLK PIN" - depends PACKAGE_kmod-mmc-over-gpio - default 4 + config KMOD_MMC_OVER_GPIO_DO_PIN + int "GPIO DO (Data-Out) pin" + default 3 -config KMOD_MMC_OVER_GPIO_CS_PIN - int "GPIO CS PIN" - depends PACKAGE_kmod-mmc-over-gpio - default 7 + config KMOD_MMC_OVER_GPIO_CLK_PIN + int "GPIO CLK (Clock) pin" + default 4 + + config KMOD_MMC_OVER_GPIO_CS_PIN + int "GPIO CS (Chip-Select) pin" + default 7 + + endmenu endef define KernelPackage/mmc-over-gpio/description diff --git a/package/nvram/Makefile b/package/nvram/Makefile index 6ac11a9be..f064b5fe3 100644 --- a/package/nvram/Makefile +++ b/package/nvram/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=nvram -PKG_RELEASE:=5 +PKG_RELEASE:=6 PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME) diff --git a/package/nvram/src/cli.c b/package/nvram/src/cli.c index 953910cd6..44d4b88fd 100644 --- a/package/nvram/src/cli.c +++ b/package/nvram/src/cli.c @@ -165,20 +165,32 @@ int main( int argc, const char *argv[] ) stat = do_info(nvram); done++; } - else if( !strcmp(argv[i], "get") && ++i < argc ) + else if( !strcmp(argv[i], "get") || !strcmp(argv[i], "unset") || !strcmp(argv[i], "set") ) { - stat = do_get(nvram, argv[i]); - done++; - } - else if( !strcmp(argv[i], "unset") && ++i < argc ) - { - stat = do_unset(nvram, argv[i]); - done++; - } - else if( !strcmp(argv[i], "set") && ++i < argc ) - { - stat = do_set(nvram, argv[i]); - done++; + if( (i+1) < argc ) + { + switch(argv[i++][0]) + { + case 'g': + stat = do_get(nvram, argv[i]); + break; + + case 'u': + stat = do_unset(nvram, argv[i]); + break; + + case 's': + stat = do_set(nvram, argv[i]); + break; + } + done++; + } + else + { + fprintf(stderr, "Command '%s' requires an argument!\n", argv[i]); + done = 0; + break; + } } else if( !strcmp(argv[i], "commit") ) { diff --git a/package/openssl/Config.in b/package/openssl/Config.in index 96cba4916..1d310bdb5 100644 --- a/package/openssl/Config.in +++ b/package/openssl/Config.in @@ -1,9 +1,8 @@ -# OpenSSL configuration - -if PACKAGE_libopenssl +menu "Configuration" + depends on PACKAGE_libopenssl config OPENSSL_ENGINE bool prompt "Crypto acceleration support" -endif +endmenu diff --git a/package/openssl/Makefile b/package/openssl/Makefile index 9f80a98f3..bdeb897e6 100644 --- a/package/openssl/Makefile +++ b/package/openssl/Makefile @@ -46,6 +46,7 @@ $(call Package/openssl/Default) CATEGORY:=Libraries DEPENDS:=+zlib TITLE+= (libraries) + MENU:=1 endef define Package/libopenssl/description diff --git a/package/opkg/files/opkg.conf b/package/opkg/files/opkg.conf index 0e85936ba..d99c80df8 100644 --- a/package/opkg/files/opkg.conf +++ b/package/opkg/files/opkg.conf @@ -1,4 +1,4 @@ -src/gz snapshots http://downloads.openwrt.org/snapshots/trunk/$S/packages +src/gz packages http://downloads.openwrt.org/backfire/10.03/$S/packages dest root / dest ram /tmp lists_dir ext /var/opkg-lists diff --git a/package/ppp/files/ppp.sh b/package/ppp/files/ppp.sh index 62f584fa8..c6440025b 100644 --- a/package/ppp/files/ppp.sh +++ b/package/ppp/files/ppp.sh @@ -65,40 +65,80 @@ start_pppd() { # /dev/ppp fast enough to be used here [ -e /dev/ppp ] || mknod /dev/ppp c 108 0 + local device config_get device "$cfg" device + + local unit config_get unit "$cfg" unit + + local username config_get username "$cfg" username + + local password config_get password "$cfg" password + + local keepalive config_get keepalive "$cfg" keepalive + local connect config_get connect "$cfg" connect + + local disconnect config_get disconnect "$cfg" disconnect + + local pppd_options config_get pppd_options "$cfg" pppd_options + + local defaultroute config_get_bool defaultroute "$cfg" defaultroute 1 [ "$defaultroute" -eq 1 ] && defaultroute="defaultroute replacedefaultroute" || defaultroute="" - interval="${keepalive##*[, ]}" + local interval="${keepalive##*[, ]}" [ "$interval" != "$keepalive" ] || interval=5 - config_get_bool peerdns "$cfg" peerdns 1 - [ "$peerdns" -eq 1 ] && peerdns="usepeerdns" || { + local dns + config_get dns "$config" dns + + local has_dns=0 + local peer_default=1 + [ -n "$dns" ] && { + has_dns=1 + peer_default=0 + } + + local peerdns + config_get_bool peerdns "$cfg" peerdns $peer_default + + echo -n "" > /tmp/resolv.conf.auto + + [ "$peerdns" -eq 1 ] && { + peerdns="usepeerdns" + } || { peerdns="" - config_get dns "$config" dns for dns in $dns; do - grep -q "$dns" /tmp/resolv.conf.auto 2>/dev/null || \ - echo "nameserver $dns" >> /tmp/resolv.conf.auto + echo "nameserver $dns" >> /tmp/resolv.conf.auto done } - config_get demand "$cfg" demand - [ -n "$demand" ] && echo "nameserver 1.1.1.1" > /tmp/resolv.conf.auto + local demand + config_get_bool demand "$cfg" demand 0 + local demandargs + [ "$demand" -eq 1 ] && { + demandargs="precompiled-active-filter /etc/ppp/filter demand idle" + [ "$has_dns" -eq 0 ] && \ + echo "nameserver 1.1.1.1" > /tmp/resolv.conf.auto + } || { + demandargs="persist" + } + + local ipv6 config_get_bool ipv6 "$cfg" ipv6 0 [ "$ipv6" -eq 1 ] && ipv6="+ipv6" || ipv6="" /usr/sbin/pppd "$@" \ ${keepalive:+lcp-echo-interval $interval lcp-echo-failure ${keepalive%%[, ]*}} \ - ${demand:+precompiled-active-filter /etc/ppp/filter demand idle }${demand:-persist} \ + $demandargs \ $peerdns \ $defaultroute \ ${username:+user "$username" password "$password"} \ @@ -117,9 +157,12 @@ setup_interface_ppp() { local iface="$1" local config="$2" + local device config_get device "$config" device + local mtu config_get mtu "$config" mtu + mtu=${mtu:-1492} start_pppd "$config" \ mtu $mtu mru $mtu \ diff --git a/package/swconfig/Makefile b/package/swconfig/Makefile index ef9dbefbe..5880e9828 100644 --- a/package/swconfig/Makefile +++ b/package/swconfig/Makefile @@ -16,7 +16,7 @@ include $(INCLUDE_DIR)/kernel.mk define Package/swconfig SECTION:=base CATEGORY:=Base system - DEPENDS:=@LINUX_2_6 +libuci +libnl-tiny + DEPENDS:=@LINUX_2_6 @!TARGET_brcm47xx +libuci +libnl-tiny TITLE:=Switch configuration utility endef diff --git a/package/swconfig/src/cli.c b/package/swconfig/src/cli.c index 76593ba14..eea88d812 100644 --- a/package/swconfig/src/cli.c +++ b/package/swconfig/src/cli.c @@ -74,7 +74,7 @@ print_attrs(const struct switch_attr *attr) static void list_attributes(struct switch_dev *dev) { - printf("Switch %d: %s(%s), ports: %d, vlans: %d\n", dev->id, dev->dev_name, dev->name, dev->ports, dev->vlans); + printf("Switch %d: %s(%s), ports: %d (cpu @ %d), vlans: %d\n", dev->id, dev->dev_name, dev->name, dev->ports, dev->cpu_port, dev->vlans); printf(" --switch\n"); print_attrs(dev->ops); printf(" --vlan\n"); diff --git a/package/swconfig/src/swlib.c b/package/swconfig/src/swlib.c index 04b3bef49..59456a33d 100644 --- a/package/swconfig/src/swlib.c +++ b/package/swconfig/src/swlib.c @@ -581,11 +581,13 @@ add_switch(struct nl_msg *msg, void *arg) if (tb[SWITCH_ATTR_ID]) dev->id = nla_get_u32(tb[SWITCH_ATTR_ID]); if (tb[SWITCH_ATTR_NAME]) - dev->name = strdup(nla_get_string(tb[SWITCH_ATTR_DEV_NAME])); + dev->name = strdup(nla_get_string(tb[SWITCH_ATTR_NAME])); if (tb[SWITCH_ATTR_PORTS]) dev->ports = nla_get_u32(tb[SWITCH_ATTR_PORTS]); if (tb[SWITCH_ATTR_VLANS]) dev->vlans = nla_get_u32(tb[SWITCH_ATTR_VLANS]); + if (tb[SWITCH_ATTR_CPU_PORT]) + dev->cpu_port = nla_get_u32(tb[SWITCH_ATTR_CPU_PORT]); if (!sa->head) { sa->head = dev; diff --git a/package/swconfig/src/swlib.h b/package/swconfig/src/swlib.h index b3c6769de..2c2fccd39 100644 --- a/package/swconfig/src/swlib.h +++ b/package/swconfig/src/swlib.h @@ -118,6 +118,7 @@ struct switch_dev { const char *dev_name; int ports; int vlans; + int cpu_port; struct switch_attr *ops; struct switch_attr *port_ops; struct switch_attr *vlan_ops; diff --git a/package/uboot-ifxmips/Config.in b/package/uboot-ifxmips/Config.in index 4562fc8ef..afd192087 100644 --- a/package/uboot-ifxmips/Config.in +++ b/package/uboot-ifxmips/Config.in @@ -1,5 +1,9 @@ +menu "Configuration" + depends on PACKAGE_uboot-ifxmips + config IFXMIPS_UBOOT_A800 bool "add ARV452 Switch bringup hack" - depends on PACKAGE_uboot-ifxmips help Say Y, if you have a arv452 board (wav-281, A800, ..) + +endmenu diff --git a/package/uboot-ifxmips/Makefile b/package/uboot-ifxmips/Makefile index 6b78c3d0a..736e322c3 100644 --- a/package/uboot-ifxmips/Makefile +++ b/package/uboot-ifxmips/Makefile @@ -26,6 +26,7 @@ define Package/uboot-ifxmips DEPENDS:=@TARGET_ifxmips @BROKEN TITLE:=U-Boot for Infineon MIPS boards URL:=http://www.denx.de/wiki/U-Boot + MENU:=1 endef define Build/Prepare diff --git a/package/uboot-lantiq/Config.in b/package/uboot-lantiq/Config.in index e2c156d88..578b08864 100644 --- a/package/uboot-lantiq/Config.in +++ b/package/uboot-lantiq/Config.in @@ -1,7 +1,9 @@ +menu "Configuration" + depends on PACKAGE_uboot-lantiq + config UBOOT_TARGET string "target" default "easy50712_DDR166M" - depends on PACKAGE_uboot-lantiq help The configuration reflects the settings for a dedicated board hardware. Select for Danube evaluation board easy50712_DDR166M . @@ -9,7 +11,6 @@ config UBOOT_TARGET config UBOOT_RAMBOOT bool "Enable RAM boot image" - depends on PACKAGE_uboot-lantiq help Using the UART boot mode of the ROM code this image could be loaded to the RAM. While executing the image in the RAM the functionality of the uboot image can be @@ -30,6 +31,7 @@ config UBOOT_RAMBOOT_DDR_CONFIG config UBOOT_A800 bool "add ARV452 Switch bringup hack" - depends on PACKAGE_uboot-lantiq help Say Y, if you have a arv452 board (wav-281, A800, ..) + +endmenu diff --git a/package/uboot-lantiq/Makefile b/package/uboot-lantiq/Makefile index 186490875..8b69fe950 100644 --- a/package/uboot-lantiq/Makefile +++ b/package/uboot-lantiq/Makefile @@ -31,6 +31,7 @@ define Package/uboot-lantiq DEPENDS:=@TARGET_ifxmips TITLE:=U-Boot for Lantiq reference boards URL:=http://www.denx.de/wiki/U-Boot + MENU:=1 endef define Build/Prepare diff --git a/package/uboot-lantiq/files/include/configs/ifx-common.h b/package/uboot-lantiq/files/include/configs/ifx-common.h index 88569ada9..e4e8067d7 100644 --- a/package/uboot-lantiq/files/include/configs/ifx-common.h +++ b/package/uboot-lantiq/files/include/configs/ifx-common.h @@ -48,7 +48,7 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off\0" \ "addmisc=setenv bootargs ${bootargs} init=/etc/preinit " \ - "console=ttyS1,115200 ethaddr=${ethaddr} ${mtdparts}" \ + "console=ttyS1,115200 ethaddr=${ethaddr} " \ "${mtdparts}\0" \ "flash_flash=run flashargs addip addmisc;" \ "bootm ${kernel_addr}\0" \ @@ -113,7 +113,7 @@ #ifndef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ diff --git a/package/uboot-lantiq/patches/300-httpd.patch b/package/uboot-lantiq/patches/300-httpd.patch index d244e2d42..8c4c1ffb6 100644 --- a/package/uboot-lantiq/patches/300-httpd.patch +++ b/package/uboot-lantiq/patches/300-httpd.patch @@ -12,7 +12,7 @@ + +U_BOOT_CMD( + httpd, 1, 1, do_httpd, -+ "httpd\t- start webserver\n", "\n" ++ "httpd\t- start webserver", "" +); +#endif + diff --git a/package/udev/udev-config.in b/package/udev/Config.in similarity index 96% rename from package/udev/udev-config.in rename to package/udev/Config.in index c10bb9cc4..9144c40ed 100644 --- a/package/udev/udev-config.in +++ b/package/udev/Config.in @@ -1,11 +1,10 @@ # udev package config -menu "udev configuration" -depends on PACKAGE_udev +menu "Configuration" + depends on PACKAGE_udev config UDEV_DISABLE_LOGGING bool "Disable udev logging to syslog" - depends on PACKAGE_udev default n help Disable logging of udev messages to the syslog. If @@ -13,7 +12,6 @@ config UDEV_DISABLE_LOGGING config UDEV_ENABLE_DEBUG bool "Enable debug build of the udev package" - depends on PACKAGE_udev default n help Compile in udev debug messages. If unsure, choose diff --git a/package/udev/Makefile b/package/udev/Makefile index f14fb3b8a..26bfe8bba 100644 --- a/package/udev/Makefile +++ b/package/udev/Makefile @@ -26,6 +26,7 @@ define Package/udev TITLE:=Dynamic device management subsystem URL:=http://www.kernel.org/pub/linux/utils/kernel/hotplug/udev.html MAINTAINER:=Geoff Levand + MENU:=1 endef define Package/udev/description @@ -34,7 +35,7 @@ define Package/udev/description endef define Package/udev/config - source "$(SOURCE)/udev-config.in" + source "$(SOURCE)/Config.in" endef udev-args-$(CONFIG_UDEV_DISABLE_LOGGING) += --disable-logging diff --git a/package/uhttpd/Makefile b/package/uhttpd/Makefile index 6b4db3e15..0dcc6a900 100644 --- a/package/uhttpd/Makefile +++ b/package/uhttpd/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uhttpd -PKG_RELEASE:=7 +PKG_RELEASE:=9 PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME) diff --git a/package/uhttpd/files/uhttpd.config b/package/uhttpd/files/uhttpd.config index 79b018cf8..acdd62ea4 100644 --- a/package/uhttpd/files/uhttpd.config +++ b/package/uhttpd/files/uhttpd.config @@ -29,10 +29,16 @@ config uhttpd main # CGI/Lua timeout, if the called script does not # write data within the given amount of seconds, - # the server will temrinate the request with + # the server will terminate the request with # 504 Gateway Timeout response. option script_timeout 60 + # Network timeout, if the current connection is + # blocked for the specified amount of seconds, + # the server will terminate the associated + # request process. + option network_timeout 30 + # Basic auth realm, defaults to local hostname # option realm OpenWrt diff --git a/package/uhttpd/files/uhttpd.init b/package/uhttpd/files/uhttpd.init index 4b747a0da..14f8fc4c4 100755 --- a/package/uhttpd/files/uhttpd.init +++ b/package/uhttpd/files/uhttpd.init @@ -58,6 +58,7 @@ start_instance() append_arg "$cfg" lua_prefix "-l" append_arg "$cfg" lua_handler "-L" append_arg "$cfg" script_timeout "-t" + append_arg "$cfg" network_timeout "-T" config_get http "$cfg" listen_http for listen in $http; do diff --git a/package/uhttpd/src/uhttpd-cgi.c b/package/uhttpd/src/uhttpd-cgi.c index 1a6c6ad4f..855a72f56 100644 --- a/package/uhttpd/src/uhttpd-cgi.c +++ b/package/uhttpd/src/uhttpd-cgi.c @@ -68,7 +68,7 @@ static struct http_response * uh_cgi_header_parse(char *buf, int len, int *off) if( (pos < len) && (buf[pos] == '\n') ) pos++; - if( pos < len ) + if( pos <= len ) { if( (hdrcount + 1) < array_size(res.headers) ) { diff --git a/package/uhttpd/src/uhttpd-file.c b/package/uhttpd/src/uhttpd-file.c index 2a06f8520..81f66a34b 100644 --- a/package/uhttpd/src/uhttpd-file.c +++ b/package/uhttpd/src/uhttpd-file.c @@ -29,23 +29,21 @@ static const char * uh_file_mime_lookup(const char *path) { struct mimetype *m = &uh_mime_types[0]; - char *p, *pd, *ps; + char *e; - ps = strrchr(path, '/'); - pd = strrchr(path, '.'); - - /* use either slash or dot as separator, whatever comes last */ - p = (ps && pd && (ps > pd)) ? ps : pd; - - if( (p != NULL) && (*(++p) != 0) ) + while( m->extn ) { - while( m->extn ) + e = &path[strlen(path)-1]; + + while( e >= path ) { - if( ! strcasecmp(p, m->extn) ) + if( (*e == '.') && !strcasecmp(&e[1], m->extn) ) return m->mime; - m++; + e--; } + + m++; } return "application/octet-stream"; diff --git a/package/uhttpd/src/uhttpd-mimetypes.h b/package/uhttpd/src/uhttpd-mimetypes.h index 1c93f3113..032d3d0c2 100644 --- a/package/uhttpd/src/uhttpd-mimetypes.h +++ b/package/uhttpd/src/uhttpd-mimetypes.h @@ -20,58 +20,61 @@ static struct mimetype uh_mime_types[] = { - { "txt", "text/plain" }, - { "log", "text/plain" }, - { "js", "text/javascript" }, - { "css", "text/css" }, - { "htm", "text/html" }, - { "html", "text/html" }, - { "diff", "text/x-patch" }, - { "patch", "text/x-patch" }, - { "c", "text/x-csrc" }, - { "h", "text/x-chdr" }, - { "o", "text/x-object" }, - { "ko", "text/x-object" }, + { "txt", "text/plain" }, + { "log", "text/plain" }, + { "js", "text/javascript" }, + { "css", "text/css" }, + { "htm", "text/html" }, + { "html", "text/html" }, + { "diff", "text/x-patch" }, + { "patch", "text/x-patch" }, + { "c", "text/x-csrc" }, + { "h", "text/x-chdr" }, + { "o", "text/x-object" }, + { "ko", "text/x-object" }, - { "bmp", "image/bmp" }, - { "gif", "image/gif" }, - { "png", "image/png" }, - { "jpg", "image/jpeg" }, - { "jpeg", "image/jpeg" }, - { "svg", "image/svg+xml" }, + { "bmp", "image/bmp" }, + { "gif", "image/gif" }, + { "png", "image/png" }, + { "jpg", "image/jpeg" }, + { "jpeg", "image/jpeg" }, + { "svg", "image/svg+xml" }, - { "zip", "application/zip" }, - { "pdf", "application/pdf" }, - { "xml", "application/xml" }, - { "xsl", "application/xml" }, - { "doc", "application/msword" }, - { "ppt", "application/vnd.ms-powerpoint" }, - { "xls", "application/vnd.ms-excel" }, - { "odt", "application/vnd.oasis.opendocument.text" }, - { "odp", "application/vnd.oasis.opendocument.presentation" }, - { "pl", "application/x-perl" }, - { "sh", "application/x-shellscript" }, - { "php", "application/x-php" }, - { "deb", "application/x-deb" }, - { "iso", "application/x-cd-image" }, - { "tgz", "application/x-compressed-tar" }, - { "gz", "application/x-gzip" }, - { "bz2", "application/x-bzip" }, - { "tar", "application/x-tar" }, - { "rar", "application/x-rar-compressed" }, + { "zip", "application/zip" }, + { "pdf", "application/pdf" }, + { "xml", "application/xml" }, + { "xsl", "application/xml" }, + { "doc", "application/msword" }, + { "ppt", "application/vnd.ms-powerpoint" }, + { "xls", "application/vnd.ms-excel" }, + { "odt", "application/vnd.oasis.opendocument.text" }, + { "odp", "application/vnd.oasis.opendocument.presentation" }, + { "pl", "application/x-perl" }, + { "sh", "application/x-shellscript" }, + { "php", "application/x-php" }, + { "deb", "application/x-deb" }, + { "iso", "application/x-cd-image" }, + { "tar.gz", "application/x-compressed-tar" }, + { "tgz", "application/x-compressed-tar" }, + { "gz", "application/x-gzip" }, + { "tar.bz2", "application/x-bzip-compressed-tar" }, + { "tbz", "application/x-bzip-compressed-tar" }, + { "bz2", "application/x-bzip" }, + { "tar", "application/x-tar" }, + { "rar", "application/x-rar-compressed" }, - { "mp3", "audio/mpeg" }, - { "ogg", "audio/x-vorbis+ogg" }, - { "wav", "audio/x-wav" }, + { "mp3", "audio/mpeg" }, + { "ogg", "audio/x-vorbis+ogg" }, + { "wav", "audio/x-wav" }, - { "mpg", "video/mpeg" }, - { "mpeg", "video/mpeg" }, - { "avi", "video/x-msvideo" }, + { "mpg", "video/mpeg" }, + { "mpeg", "video/mpeg" }, + { "avi", "video/x-msvideo" }, - { "README", "text/plain" }, - { "log", "text/plain" }, - { "cfg", "text/plain" }, - { "conf", "text/plain" }, + { "README", "text/plain" }, + { "log", "text/plain" }, + { "cfg", "text/plain" }, + { "conf", "text/plain" }, { NULL, NULL } }; diff --git a/package/uhttpd/src/uhttpd-utils.c b/package/uhttpd/src/uhttpd-utils.c index 55b2c410e..caa6b12bc 100644 --- a/package/uhttpd/src/uhttpd-utils.c +++ b/package/uhttpd/src/uhttpd-utils.c @@ -116,8 +116,8 @@ int uh_tcp_send(struct client *cl, const char *buf, int len) FD_ZERO(&writer); FD_SET(cl->socket, &writer); - timeout.tv_sec = 0; - timeout.tv_usec = 500000; + timeout.tv_sec = cl->server->conf->network_timeout; + timeout.tv_usec = 0; if( select(cl->socket + 1, NULL, &writer, NULL, &timeout) > 0 ) { @@ -376,6 +376,79 @@ int uh_b64decode(char *buf, int blen, const unsigned char *src, int slen) return len; } +static char * canonpath(const char *path, char *path_resolved) +{ + char path_copy[PATH_MAX]; + char *path_cpy = path_copy; + char *path_res = path_resolved; + + struct stat s; + + + /* relative -> absolute */ + if( *path != '/' ) + { + getcwd(path_copy, PATH_MAX); + strncat(path_copy, "/", PATH_MAX - strlen(path_copy)); + strncat(path_copy, path, PATH_MAX - strlen(path_copy)); + } + else + { + strncpy(path_copy, path, PATH_MAX); + } + + /* normalize */ + while( (*path_cpy != '\0') && (path_cpy < (path_copy + PATH_MAX - 2)) ) + { + if( *path_cpy == '/' ) + { + /* skip repeating / */ + if( path_cpy[1] == '/' ) + { + path_cpy++; + continue; + } + + /* /./ or /../ */ + else if( path_cpy[1] == '.' ) + { + /* skip /./ */ + if( (path_cpy[2] == '/') || (path_cpy[2] == '\0') ) + { + path_cpy += 2; + continue; + } + + /* collapse /x/../ */ + else if( (path_cpy[2] == '.') && + ((path_cpy[3] == '/') || (path_cpy[3] == '\0')) + ) { + while( (path_res > path_resolved) && (*--path_res != '/') ) + ; + + path_cpy += 3; + continue; + } + } + } + + *path_res++ = *path_cpy++; + } + + /* remove trailing slash if not root / */ + if( (path_res > (path_resolved+1)) && (path_res[-1] == '/') ) + path_res--; + else if( path_res == path_resolved ) + *path_res++ = '/'; + + *path_res = '\0'; + + /* test access */ + if( !stat(path_resolved, &s) && (s.st_mode & S_IROTH) ) + return path_resolved; + + return NULL; +} struct path_info * uh_path_lookup(struct client *cl, const char *url) { @@ -387,6 +460,7 @@ struct path_info * uh_path_lookup(struct client *cl, const char *url) char *docroot = cl->server->conf->docroot; char *pathptr = NULL; + int no_sym = cl->server->conf->no_symlinks; int i = 0; struct stat s; @@ -432,8 +506,9 @@ struct path_info * uh_path_lookup(struct client *cl, const char *url) memset(path_info, 0, sizeof(path_info)); memcpy(path_info, buffer, min(i + 1, sizeof(path_info) - 1)); - if( realpath(path_info, path_phys) ) - { + if( no_sym ? realpath(path_info, path_phys) + : canonpath(path_info, path_phys) + ) { memset(path_info, 0, sizeof(path_info)); memcpy(path_info, &buffer[i], min(strlen(buffer) - i, sizeof(path_info) - 1)); @@ -547,10 +622,14 @@ struct auth_realm * uh_auth_add(char *path, char *user, char *pass) min(strlen(pass), sizeof(new->pass) - 1)); } - uh_realm_count++; + if( new->pass[0] ) + { + uh_realm_count++; + return new; + } } - return new; + return NULL; } int uh_auth_check( diff --git a/package/uhttpd/src/uhttpd.c b/package/uhttpd/src/uhttpd.c index da3779413..152e0b452 100644 --- a/package/uhttpd/src/uhttpd.c +++ b/package/uhttpd/src/uhttpd.c @@ -71,8 +71,8 @@ static void uh_config_parse(const char *path) if( !uh_auth_add(line, user, pass) ) { fprintf(stderr, - "Can not manage more than %i basic auth realms, " - "will skip the rest\n", UH_LIMIT_AUTHREALMS + "Notice: No password set for user %s, ignoring " + "authentication on %s\n", user, line ); break; @@ -416,8 +416,11 @@ int main (int argc, char **argv) /* maximum file descriptor number */ int new_fd, cur_fd, max_fd = 0; +#ifdef HAVE_TLS int tls = 0; int keys = 0; +#endif + int bound = 0; int nofork = 0; @@ -426,9 +429,10 @@ int main (int argc, char **argv) char bind[128]; char *port = NULL; - /* library handles */ - void *tls_lib; - void *lua_lib; +#if defined(HAVE_TLS) || defined(HAVE_LUA) + /* library handle */ + void *lib; +#endif /* clear the master and temp sets */ FD_ZERO(&used_fds); @@ -466,7 +470,7 @@ int main (int argc, char **argv) #ifdef HAVE_TLS /* load TLS plugin */ - if( ! (tls_lib = dlopen("uhttpd_tls.so", RTLD_LAZY | RTLD_GLOBAL)) ) + if( ! (lib = dlopen("uhttpd_tls.so", RTLD_LAZY | RTLD_GLOBAL)) ) { fprintf(stderr, "Notice: Unable to load TLS plugin - disabling SSL support! " @@ -476,14 +480,14 @@ int main (int argc, char **argv) else { /* resolve functions */ - if( !(conf.tls_init = dlsym(tls_lib, "uh_tls_ctx_init")) || - !(conf.tls_cert = dlsym(tls_lib, "uh_tls_ctx_cert")) || - !(conf.tls_key = dlsym(tls_lib, "uh_tls_ctx_key")) || - !(conf.tls_free = dlsym(tls_lib, "uh_tls_ctx_free")) || - !(conf.tls_accept = dlsym(tls_lib, "uh_tls_client_accept")) || - !(conf.tls_close = dlsym(tls_lib, "uh_tls_client_close")) || - !(conf.tls_recv = dlsym(tls_lib, "uh_tls_client_recv")) || - !(conf.tls_send = dlsym(tls_lib, "uh_tls_client_send")) + if( !(conf.tls_init = dlsym(lib, "uh_tls_ctx_init")) || + !(conf.tls_cert = dlsym(lib, "uh_tls_ctx_cert")) || + !(conf.tls_key = dlsym(lib, "uh_tls_ctx_key")) || + !(conf.tls_free = dlsym(lib, "uh_tls_ctx_free")) || + !(conf.tls_accept = dlsym(lib, "uh_tls_client_accept")) || + !(conf.tls_close = dlsym(lib, "uh_tls_client_close")) || + !(conf.tls_recv = dlsym(lib, "uh_tls_client_recv")) || + !(conf.tls_send = dlsym(lib, "uh_tls_client_send")) ) { fprintf(stderr, "Error: Failed to lookup required symbols " @@ -501,7 +505,7 @@ int main (int argc, char **argv) } #endif - while( (opt = getopt(argc, argv, "fC:K:p:s:h:c:l:L:d:r:m:x:t:")) > 0 ) + while( (opt = getopt(argc, argv, "fSC:K:p:s:h:c:l:L:d:r:m:x:t:T:")) > 0 ) { switch(opt) { @@ -592,6 +596,11 @@ int main (int argc, char **argv) } break; + /* don't follow symlinks */ + case 'S': + conf.no_symlinks = 1; + break; + #ifdef HAVE_CGI /* cgi prefix */ case 'x': @@ -618,6 +627,11 @@ int main (int argc, char **argv) break; #endif + /* network timeout */ + case 'T': + conf.network_timeout = atoi(optarg); + break; + /* no fork */ case 'f': nofork = 1; @@ -663,6 +677,7 @@ int main (int argc, char **argv) " -K file ASN.1 server private key file\n" #endif " -h directory Specify the document root, default is '.'\n" + " -S Do not follow symbolic links outside of the docroot\n" #ifdef HAVE_LUA " -l string URL prefix for Lua handler, default is '/lua'\n" " -L file Lua handler script, omit to disable Lua\n" @@ -673,6 +688,7 @@ int main (int argc, char **argv) #if defined(HAVE_CGI) || defined(HAVE_LUA) " -t seconds CGI and Lua script timeout in seconds, default is 60\n" #endif + " -T seconds Network timeout in seconds, default is 30\n" " -d string URL decode given string\n" " -r string Specify basic auth realm\n" " -m string MD5 crypt given string\n" @@ -712,6 +728,10 @@ int main (int argc, char **argv) /* config file */ uh_config_parse(conf.file); + /* default network timeout */ + if( conf.network_timeout <= 0 ) + conf.network_timeout = 30; + #if defined(HAVE_CGI) || defined(HAVE_LUA) /* default script timeout */ if( conf.script_timeout <= 0 ) @@ -726,7 +746,7 @@ int main (int argc, char **argv) #ifdef HAVE_LUA /* load Lua plugin */ - if( ! (lua_lib = dlopen("uhttpd_lua.so", RTLD_LAZY | RTLD_GLOBAL)) ) + if( ! (lib = dlopen("uhttpd_lua.so", RTLD_LAZY | RTLD_GLOBAL)) ) { fprintf(stderr, "Notice: Unable to load Lua plugin - disabling Lua support! " @@ -736,9 +756,9 @@ int main (int argc, char **argv) else { /* resolve functions */ - if( !(conf.lua_init = dlsym(lua_lib, "uh_lua_init")) || - !(conf.lua_close = dlsym(lua_lib, "uh_lua_close")) || - !(conf.lua_request = dlsym(lua_lib, "uh_lua_request")) + if( !(conf.lua_init = dlsym(lib, "uh_lua_init")) || + !(conf.lua_close = dlsym(lib, "uh_lua_close")) || + !(conf.lua_request = dlsym(lib, "uh_lua_request")) ) { fprintf(stderr, "Error: Failed to lookup required symbols " diff --git a/package/uhttpd/src/uhttpd.h b/package/uhttpd/src/uhttpd.h index 0e9f1ee88..32e397007 100644 --- a/package/uhttpd/src/uhttpd.h +++ b/package/uhttpd/src/uhttpd.h @@ -32,7 +32,7 @@ #include #include #include - +#include #include @@ -64,6 +64,8 @@ struct config { char docroot[PATH_MAX]; char *realm; char *file; + int no_symlinks; + int network_timeout; #ifdef HAVE_CGI char *cgi_prefix; #endif diff --git a/package/vsc73x5-ucode/Makefile b/package/vsc73x5-ucode/Makefile index d48af0026..3a0712110 100644 --- a/package/vsc73x5-ucode/Makefile +++ b/package/vsc73x5-ucode/Makefile @@ -10,15 +10,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=vsc73x5-ucode PKG_RELEASE:=1 -PKG_SOURCE_URL:=http://www.tp-link.com/GPL +PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources -PKG_SOURCE:=WirelessNRouer_AP.tar.gz +PKG_SOURCE:=vsc73x5-ucode.tar.bz2 PKG_BUILD_DIR:=$(BUILD_DIR)/vsc73x5-ucode -PKG_MD5SUM:=7dd6069a5f0e44cc9965fc7b43eb3046 - -UCODE_SRC_DIR:=u-boot/board/ar7100/common -UCODE_BUILD_DIR:=$(PKG_BUILD_DIR)/$(UCODE_SRC_DIR) +PKG_MD5SUM:=b32e3debcd118f263c79199a7b5afa68 include $(INCLUDE_DIR)/package.mk @@ -32,7 +29,7 @@ endef define Package/vsc73x5/install $(INSTALL_DIR) $(1)/lib/firmware - $(INSTALL_DATA) $(UCODE_BUILD_DIR)/$(2) $(1)/lib/firmware/$(3) + $(INSTALL_DATA) $(PKG_BUILD_DIR)/$(2) $(1)/lib/firmware/$(3) endef define Package/vsc7385-ucode-ap83 @@ -87,13 +84,8 @@ define Package/vsc7395-ucode-pb44/install $(call Package/vsc73x5/install,$(1),g5e_Plus1_2_29a_unmanaged_Atheros_v3.bin,vsc7395_ucode_pb44.bin) endef -define Build/Prepare - tar -xzf "$(DL_DIR)/$(PKG_SOURCE)" ap-9x-gpl/ap93-u-boot.tar.bz2 -O | tar -C "$(PKG_BUILD_DIR)" -xj $(UCODE_SRC_DIR) - cp files/Makefile $(UCODE_BUILD_DIR) -endef - define Build/Compile - $(MAKE) -C $(UCODE_BUILD_DIR) $(TARGET_CONFIGURE_OPTS) all + endef $(eval $(call BuildPackage,vsc7385-ucode-ap83)) diff --git a/scripts/timestamp.pl b/scripts/timestamp.pl index 3bf057151..e24d8149d 100755 --- a/scripts/timestamp.pl +++ b/scripts/timestamp.pl @@ -14,7 +14,7 @@ sub get_ts($$) { my $ts = 0; my $fn = ""; $path .= "/" if( -d $path); - open FIND, "find $path -type f -and -not -path \\*.svn\\* -and -not -path \\*CVS\\* $options 2>/dev/null |"; + open FIND, "find $path -type f -and -not -path \\*/.svn\\* -and -not -path \\*CVS\\* $options 2>/dev/null |"; while () { chomp; my $file = $_; diff --git a/target/imagebuilder/Makefile b/target/imagebuilder/Makefile index e0b64ead4..42fb7bb69 100644 --- a/target/imagebuilder/Makefile +++ b/target/imagebuilder/Makefile @@ -23,9 +23,10 @@ all: compile $(BIN_DIR)/$(IB_NAME).tar.bz2: clean rm -rf $(PKG_BUILD_DIR) mkdir -p $(IB_KDIR) $(PKG_BUILD_DIR)/staging_dir/host $(PKG_BUILD_DIR)/target + -cp $(TOPDIR)/.config $(PKG_BUILD_DIR)/.config $(CP) \ $(INCLUDE_DIR) $(SCRIPT_DIR) \ - $(TOPDIR)/rules.mk $(TOPDIR)/.config \ + $(TOPDIR)/rules.mk \ ./files/Makefile \ $(TMP_DIR)/.targetinfo \ $(TMP_DIR)/.packageinfo \ diff --git a/target/imagebuilder/files/Makefile b/target/imagebuilder/files/Makefile index 49fd6db94..b72e3f172 100644 --- a/target/imagebuilder/files/Makefile +++ b/target/imagebuilder/files/Makefile @@ -62,8 +62,8 @@ IPKG:= \ define Profile $(eval $(call Profile/Default)) $(eval $(call Profile/$(1))) - ifeq ($(PROFILE),) - PROFILE:=$(1) + ifeq ($(USER_PROFILE),) + USER_PROFILE:=$(1) endif $(1)_NAME:=$(NAME) $(1)_PACKAGES:=$(PACKAGES) @@ -73,7 +73,7 @@ endef include $(INCLUDE_DIR)/target.mk -info: FORCE +_call_info: FORCE echo 'Current Target: "$(BOARD)$(if $(SUBTARGET), ($(BOARDNAME)))"' echo 'Default Packages: $(DEFAULT_PACKAGES)' echo 'Available Profiles:' @@ -84,19 +84,19 @@ $(TOPDIR)/tmp/ipkg.conf: FORCE @echo 'dest root /' > $@ @echo 'src packages file:$(PACKAGE_DIR)' >> $@ -BUILD_PACKAGES:=$(sort $(DEFAULT_PACKAGES) $(PACKAGES) $($(PROFILE)_PACKAGES) kernel) +BUILD_PACKAGES:=$(sort $(DEFAULT_PACKAGES) $(USER_PACKAGES) $($(USER_PROFILE)_PACKAGES) kernel) # "-pkgname" in the package list means remove "pkgname" from the package list BUILD_PACKAGES:=$(filter-out $(filter -%,$(BUILD_PACKAGES)) $(patsubst -%,%,$(filter -%,$(BUILD_PACKAGES))),$(BUILD_PACKAGES)) -image: - echo 'Building images for $(BOARD)$(if $($(PROFILE)_NAME), - $($(PROFILE)_NAME))' +_call_image: + echo 'Building images for $(BOARD)$(if $($(USER_PROFILE)_NAME), - $($(USER_PROFILE)_NAME))' echo 'Packages: $(BUILD_PACKAGES)' echo rm -rf $(TARGET_DIR) mkdir -p $(TARGET_DIR) $(BIN_DIR) $(TMP_DIR) $(MAKE) package_index $(MAKE) package_install -ifneq ($(FILES),) +ifneq ($(USER_FILES),) $(MAKE) copy_files endif $(MAKE) package_postinst @@ -118,7 +118,7 @@ package_install: FORCE copy_files: FORCE @echo @echo Copying extra files - $(CP) $(FILES)/* $(TARGET_DIR)/ + $(CP) $(USER_FILES)/* $(TARGET_DIR)/ package_postinst: FORCE @echo @@ -140,5 +140,15 @@ clean: rm -rf tmp $(TARGET_DIR) $(BIN_DIR) +info: + (unset PROFILE FILES PACKAGES MAKEFLAGS; $(MAKE) -s _call_info) + +image: + (unset PROFILE FILES PACKAGES MAKEFLAGS; \ + $(MAKE) _call_image \ + $(if $(PROFILE),USER_PROFILE="$(PROFILE)") \ + $(if $(FILES),USER_FILES="$(FILES)") \ + $(if $(PACKAGES),USER_PACKAGES="$(PACKAGES)")) + .SILENT: help info image diff --git a/target/linux/adm5120/image/Makefile b/target/linux/adm5120/image/Makefile index cb9af208a..f628456ab 100644 --- a/target/linux/adm5120/image/Makefile +++ b/target/linux/adm5120/image/Makefile @@ -11,6 +11,10 @@ LOADER_MAKE := $(NO_TRACE_MAKE) -C lzma-loader KDIR=$(KDIR) JFFS2BLOCK := $(KDIR)/jffs2.block JFFS2MARK := $(KDIR)/jffs2.mark +define imgname +$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(patsubst jffs2-%,jffs2,$(1)) +endef + define Build/Clean $(LOADER_MAKE) clean endef diff --git a/target/linux/amazon/Makefile b/target/linux/amazon/Makefile deleted file mode 100644 index aae39a00e..000000000 --- a/target/linux/amazon/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=mips -BOARD:=amazon -BOARDNAME:=Infineon Amazon -FEATURES:=squashfs jffs2 broken -LINUX_VERSION:=2.6.30.10 - -include $(INCLUDE_DIR)/target.mk - -define Target/Description - Build firmware images for Infineon Amazon boards -endef - -$(eval $(call BuildTarget)) diff --git a/target/linux/amazon/base-files/etc/config/network b/target/linux/amazon/base-files/etc/config/network deleted file mode 100644 index 72e39f88a..000000000 --- a/target/linux/amazon/base-files/etc/config/network +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (C) 2006 OpenWrt.org - -config interface loopback - option ifname lo - option proto static - option ipaddr 127.0.0.1 - option netmask 255.0.0.0 - -config interface lan - option ifname eth1 - option type bridge - option proto static - option ipaddr 192.168.1.1 - option netmask 255.255.255.0 diff --git a/target/linux/amazon/config-2.6.30 b/target/linux/amazon/config-2.6.30 deleted file mode 100644 index 45f2e6366..000000000 --- a/target/linux/amazon/config-2.6.30 +++ /dev/null @@ -1,152 +0,0 @@ -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_ADM6996_SUPPORT=y -CONFIG_AMAZON_ASC_UART=y -CONFIG_AMAZON_MTD=y -CONFIG_AMAZON_NET_SW=y -CONFIG_AMAZON_PCI=y -CONFIG_AMAZON_WDT=y -CONFIG_AMAZON=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_POPULATES_NODE_MAP=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_BCM47XX is not set -# CONFIG_BINARY_PRINTF is not set -CONFIG_BITREVERSE=y -# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set -# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set -CONFIG_CEVT_R4K_LIB=y -CONFIG_CEVT_R4K=y -CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/bin/sh" -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_CAVIUM_OCTEON is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_CPU_LOONGSON2 is not set -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR2=y -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -CONFIG_CSRC_R4K_LIB=y -CONFIG_CSRC_R4K=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DEVPORT=y -# CONFIG_DM9000 is not set -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_EARLY_PRINTK=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_HAVE_IDE=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_STD_PC_SERIAL_PORT=y -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQ_CPU=y -CONFIG_KALLSYMS=y -# CONFIG_LEMOTE_FULONG is not set -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_MIKROTIK_RB532 is not set -# CONFIG_MIPS_COBALT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MACHINE is not set -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MIPS=y -CONFIG_MTD_AMAZON_BUS_WIDTH_16=y -# CONFIG_MTD_AMAZON_BUS_WIDTH_32 is not set -# CONFIG_MTD_AMAZON_BUS_WIDTH_8 is not set -# CONFIG_MTD_AMAZON_FLASH_SIZE_16 is not set -# CONFIG_MTD_AMAZON_FLASH_SIZE_2 is not set -CONFIG_MTD_AMAZON_FLASH_SIZE_4=y -# CONFIG_MTD_AMAZON_FLASH_SIZE_8 is not set -CONFIG_MTD_CFI_ADV_OPTIONS=y -# CONFIG_MTD_CFI_GEOMETRY is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3 -CONFIG_MTD_REDBOOT_PARTS=y -# CONFIG_NET_PCI is not set -# CONFIG_NO_IOPORT is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_PROBE_INITRD_HEADER is not set -CONFIG_SCHED_OMIT_FRAME_POINTER=y -# CONFIG_SCSI_DMA is not set -# CONFIG_SERIAL_8250 is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SLOW_WORK is not set -CONFIG_SWAP_IO_SPACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_TRACING_SUPPORT=y -CONFIG_TRAD_SIGNALS=y -CONFIG_USB_SUPPORT=y -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/amazon/config-2.6.32 b/target/linux/amazon/config-2.6.32 deleted file mode 100644 index 9239dabc2..000000000 --- a/target/linux/amazon/config-2.6.32 +++ /dev/null @@ -1,155 +0,0 @@ -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_ADM6996_SUPPORT=y -# CONFIG_ALCHEMY_GPIO_INDIRECT is not set -CONFIG_AMAZON_ASC_UART=y -CONFIG_AMAZON_MTD=y -CONFIG_AMAZON_NET_SW=y -CONFIG_AMAZON_PCI=y -CONFIG_AMAZON_WDT=y -CONFIG_AMAZON=y -# CONFIG_AR7 is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_BCM47XX is not set -# CONFIG_BCM63XX is not set -CONFIG_BITREVERSE=y -# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set -# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set -CONFIG_CEVT_R4K_LIB=y -CONFIG_CEVT_R4K=y -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/bin/sh" -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_CAVIUM_OCTEON is not set -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_CPU_LOONGSON2E is not set -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR2=y -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -CONFIG_CSRC_R4K_LIB=y -CONFIG_CSRC_R4K=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DEVPORT=y -# CONFIG_DM9000 is not set -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_EARLY_PRINTK=y -# CONFIG_FSNOTIFY is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_STD_PC_SERIAL_PORT=y -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQ_CPU=y -CONFIG_KALLSYMS=y -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_LOONGSON is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_MIKROTIK_RB532 is not set -# CONFIG_MIPS_COBALT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MACHINE is not set -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MIPS=y -CONFIG_MTD_AMAZON_BUS_WIDTH_16=y -# CONFIG_MTD_AMAZON_BUS_WIDTH_32 is not set -# CONFIG_MTD_AMAZON_BUS_WIDTH_8 is not set -# CONFIG_MTD_AMAZON_FLASH_SIZE_16 is not set -# CONFIG_MTD_AMAZON_FLASH_SIZE_2 is not set -CONFIG_MTD_AMAZON_FLASH_SIZE_4=y -# CONFIG_MTD_AMAZON_FLASH_SIZE_8 is not set -CONFIG_MTD_CFI_ADV_OPTIONS=y -# CONFIG_MTD_CFI_GEOMETRY is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3 -CONFIG_MTD_REDBOOT_PARTS=y -# CONFIG_NET_PCI is not set -# CONFIG_NO_IOPORT is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_PROBE_INITRD_HEADER is not set -CONFIG_SCHED_OMIT_FRAME_POINTER=y -# CONFIG_SCSI_DMA is not set -# CONFIG_SERIAL_8250 is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -CONFIG_SWAP_IO_SPACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_TRAD_SIGNALS=y -# CONFIG_TREE_PREEMPT_RCU is not set -CONFIG_TREE_RCU=y -CONFIG_USB_SUPPORT=y -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/amazon/files/arch/mips/amazon/Kconfig b/target/linux/amazon/files/arch/mips/amazon/Kconfig deleted file mode 100644 index 63055fc2a..000000000 --- a/target/linux/amazon/files/arch/mips/amazon/Kconfig +++ /dev/null @@ -1,67 +0,0 @@ -# copyright 2007 john crispin - -menu "Amazon built-in" - -config AMAZON_ASC_UART - bool "Amazon asc uart" - select SERIAL_CORE - select SERIAL_CORE_CONSOLE - default y - -config AMAZON_PCI - bool "Amazon PCI support" - default y - select HW_HAS_PCI - select PCI - -config AMAZON_NET_SW - bool "Amazon network" - default y - -config AMAZON_WDT - bool "Amazon watchdog timer" - default y - -config AMAZON_MTD - bool "Amazon MTD map" - default y - -config ADM6996_SUPPORT - bool "Amazon ADM6996 Switch driver" - default y - -choice - prompt "Flash Size" - depends on AMAZON_MTD - -config MTD_AMAZON_FLASH_SIZE_2 - bool "2MB" - -config MTD_AMAZON_FLASH_SIZE_4 - bool "4MB" - -config MTD_AMAZON_FLASH_SIZE_8 - bool "8MB" - -config MTD_AMAZON_FLASH_SIZE_16 - bool "16MB" - -endchoice - -choice - prompt "Bus Width" - depends on AMAZON_MTD - -config MTD_AMAZON_BUS_WIDTH_8 - bool "8-bit" - -config MTD_AMAZON_BUS_WIDTH_16 - bool "16-bit" - -config MTD_AMAZON_BUS_WIDTH_32 - bool "32-bit" - -endchoice - - -endmenu diff --git a/target/linux/amazon/files/arch/mips/amazon/Makefile b/target/linux/amazon/files/arch/mips/amazon/Makefile deleted file mode 100644 index 47761a277..000000000 --- a/target/linux/amazon/files/arch/mips/amazon/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright 2007 openwrt.org -# John Crispin -# -# Makefile for Infineon Amazon -# -obj-y := dma-core.o interrupt.o prom.o setup.o board.o -obj-$(CONFIG_PCI) += pci.o - diff --git a/target/linux/amazon/files/arch/mips/amazon/board.c b/target/linux/amazon/files/arch/mips/amazon/board.c deleted file mode 100644 index 330cec608..000000000 --- a/target/linux/amazon/files/arch/mips/amazon/board.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2009 Hauke Mehrtens - */ - - -#include -#include - -#define AMAZON_FLASH_START 0x13000000 -#define AMAZON_FLASH_MAX 0x1000000 - -static struct platform_device amazon_mii = { - .id = 0, - .name = "amazon_mii0", -// .dev = { -// .platform_data = amazon_ethaddr, -// } -}; - -static struct platform_device amazon_wdt = { - .id = 0, - .name = "amazon_wdt", -}; - -static struct platform_device amazon_asc = { - .id = 0, - .name = "amazon_asc", -}; - -static struct resource amazon_mtd_resource = { - .start = AMAZON_FLASH_START, - .end = AMAZON_FLASH_START + AMAZON_FLASH_MAX - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device amazon_mtd = { - .id = 0, - .name = "amazon_mtd", - .num_resources = 1, - .resource = &amazon_mtd_resource, -}; - - -struct platform_device *amazon_devs[] = { - &amazon_mii, &amazon_mtd, &amazon_wdt, &amazon_asc -}; - - -int __init amazon_init_devices(void) -{ - printk(KERN_INFO ""); - return platform_add_devices(amazon_devs, 4); -} - -arch_initcall(amazon_init_devices); diff --git a/target/linux/amazon/files/arch/mips/amazon/dma-core.c b/target/linux/amazon/files/arch/mips/amazon/dma-core.c deleted file mode 100644 index 6362895f8..000000000 --- a/target/linux/amazon/files/arch/mips/amazon/dma-core.c +++ /dev/null @@ -1,1455 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - */ -//----------------------------------------------------------------------- -/* - * Description: - * Driver for Infineon Amazon DMA - */ -//----------------------------------------------------------------------- -/* Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com] - * Created: 7-April-2004 - */ -//----------------------------------------------------------------------- -/* History - * Last changed on: 4-May-2004 - * Last changed by: - * Reason: debug - */ -//----------------------------------------------------------------------- -/* Last changed on: 03-Dec-2004 - * Last changed by: peng.liu@infineon.com - * Reason: recover from TPE bug - */ - -//000004:fchang 2005/6/2 Modified by Linpeng as described below -//----------------------------------------------------------------------- -/* Last changed on: 28-Jan-2004 - * Last changed by: peng.liu@infineon.com - * Reason: - * - handle "out of memory" bug - */ -//000003:tc.chen 2005/06/16 fix memory leak when Tx buffer full (heaving traffic). -//507261:tc.chen 2005/07/26 re-organize code address map to improve performance. - -#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -#define MODVERSIONS -#endif - -#if defined(MODVERSIONS) && !defined(__GENKSYMS__) -#include -#endif - -#ifndef EXPORT_SYMTAB -#define EXPORT_SYMTAB /* need this one 'cause we export symbols */ -#endif - -#undef DMA_NO_POLLING - -/* no TX interrupt handling */ -#define NO_TX_INT -/* need for DMA workaround */ -#undef AMAZON_DMA_TPE_AAL5_RECOVERY - -#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY -#define MAX_SYNC_FAILS 1000000 // 000004:fchang -unsigned int dma_sync_fails = 0; -unsigned int total_dma_tpe_reset = 0; -int (*tpe_reset) (void); -int (*tpe_start) (void); -int (*tpe_inject) (void); -#endif // AMAZON_DMA_TPE_AAL5_RECOVERY - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include "dma-core.h" - -#define AMAZON_DMA_EMSG(fmt, args...) printk( KERN_ERR "%s: " fmt,__FUNCTION__, ## args) - -static irqreturn_t dma_interrupt(int irq, void *dev_id); -extern void mask_and_ack_amazon_irq(unsigned int irq_nr); - -/***************************************** global data *******************************************/ -u64 *g_desc_list; -dev_list *g_current_dev = NULL; -dev_list *g_head_dev = NULL; -dev_list *g_tail_dev = NULL; -channel_info g_log_chan[CHAN_TOTAL_NUM + 1]; -struct proc_dir_entry *g_amazon_dma_dir; -static u8 rx_chan_list_len = 0; -static u8 tx_chan_list_len = 0; -static int rx_chan_list[RX_CHAN_NUM + 1]; -static int tx_chan_list[TX_CHAN_NUM + 1]; -static u32 comb_isr_mask[CHAN_TOTAL_NUM]; - -static inline int is_rx_chan(int chan_no) -/*judge if this is an rx channel*/ -{ - int result = 0; - if (chan_no < RX_CHAN_NUM) - result = 1; - return result; -} - -/* Ugly, Channel ON register is badly mapped to channel no. */ -static u8 ch_on_mapping[CHAN_TOTAL_NUM] = - { 0, 1, 2, 3, 6, 7, 10, 4, 5, 8, 9, 11 }; - -/* Brief: check wether the chan_no is legal - * Parameter: chan_no: logical channel number - * Return: 0 if is not valid - * 1 if is valid - */ -static inline int is_valid_dma_ch(int chan_no) -{ - return ((chan_no >= 0) && (chan_no < CHAN_TOTAL_NUM)); -} - -/* Brief: check whether a channel is open through Channel ON register - * Parameter: chan_no: logical channel number - * Return: 1 channel is open - * 0 not yet - * EINVAL: invalid parameter - */ -static inline int is_channel_open(int chan_no) -{ - return (AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) & - (1 << ch_on_mapping[chan_no])); -} - -/* Brief: add a list entry - * Description: - * always add to the tail and no redundancy allowed. (i.e. entries are unique) - * 0 : entry deleted - * <0 : not deleted (due to not unique) - */ -static inline int _add_list_entry(int *list, int size_of_list, int entry) -{ - int i; - for (i = 0; i < size_of_list; i++) { - if (list[i] == entry) - break; - if (list[i] < 0) { - list[i] = entry; - return 0; - } - } - return -1; -} - -/* Brief: delete a list entry - * Description: - * find the entry and remove it. shift all entries behind it one step forward if necessary\ - * Return: - * 0 : entry deleted - * <0 : not deleted (due to not found?) - */ -static inline int _delete_list_entry(int *list, int size_of_list, - int entry) -{ - int i, j; - for (i = 0; i < size_of_list; i++) { - if (list[i] == entry) { - for (j = i; j < size_of_list; j++) { - list[j] = list[j + 1]; - if (list[j + 1] < 0) { - break; - } - } - return 0; - } - } - return -1; -} - -/* Brief: enable a channel through Channel ON register - * Parameter: chan_no: logical channel number - * Description: - * Please don't open a channel without a valid descriptor (hardware pitfall) - */ -static inline void open_channel(int chan_no) -{ - AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) |= (1 << ch_on_mapping[chan_no]); - if (is_rx_chan(chan_no)) { - if (_add_list_entry(rx_chan_list, RX_CHAN_NUM, chan_no) == 0) { - rx_chan_list_len++; - } else { - AMAZON_DMA_DMSG("cannot add chan %d to open list\n", chan_no); - } - } else { - if (_add_list_entry(tx_chan_list, TX_CHAN_NUM, chan_no) == 0) { - tx_chan_list_len++; - } else { - AMAZON_DMA_DMSG("cannot add chan %d to open list\n", chan_no); - } - } -} - -/* Brief: disable a channel through Channel ON register - * Parameter: chan_no: logical channel number - */ - -static inline void close_channel(int chan_no) -{ - AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &= ~(1 << ch_on_mapping[chan_no]); - if (is_rx_chan(chan_no)) { - if (_delete_list_entry(rx_chan_list, RX_CHAN_NUM, chan_no) == 0) { - rx_chan_list_len--; - } else { - AMAZON_DMA_DMSG("cannot remove chan %d from open list \n", - chan_no); - } - } else { - if (_delete_list_entry(tx_chan_list, TX_CHAN_NUM, chan_no) == 0) { - tx_chan_list_len--; - } else { - AMAZON_DMA_DMSG("cannot remove chan %d from open list \n", - chan_no); - } - } -} - -/* Brief: clear RX interrupt - */ -inline void rx_chan_clear_isr(int chan_no) -{ -#ifdef DMA_NO_POLLING - AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) = - (AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - chan_no * - AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP | DMA_ISR_CMDCPT - | DMA_ISR_DURR)); -#else - AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) = - (AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - chan_no * - AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP | - DMA_ISR_CMDCPT)); -#endif -} - - -/* Brief: hacking function, this will reset all descriptors back to DMA - */ -static void dma_reset_all_descriptors(int chan_no) -{ - volatile struct rx_desc *rx_desc_p = NULL; - int i; - rx_desc_p = - (struct rx_desc *) g_desc_list + - g_log_chan[chan_no].offset_from_base; - for (i = 0; i < g_log_chan[chan_no].desc_len; i++) { - rx_desc_p->status.word &= - (~(DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | DMA_DESC_CPT_SET)); - rx_desc_p->status.word |= - (DMA_DESC_OWN_DMA | g_log_chan[chan_no].packet_size); - rx_desc_p++; - } -} - -#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY -/* Brief: Reset DMA descriptors - */ -static void amazon_dma_reset_tpe_rx(int chan_no) -{ - struct tx_desc *tx_desc_p = NULL; - int j, i = 0; - - // wait until all TX channels stop transmitting - for (j = 9; j <= 10; j++) { - tx_desc_p = - (struct tx_desc *) g_desc_list + - g_log_chan[j].offset_from_base; - for (i = 0; i < g_log_chan[j].desc_len; i++) { - while ((tx_desc_p->status.field.OWN != CPU_OWN)) { - AMAZON_DMA_DMSG("DMA TX in progress\n"); // 000004:fchang - udelay(100); - } - tx_desc_p++; - } - } - - if (tpe_reset) { - total_dma_tpe_reset++; - AMAZON_DMA_DMSG - ("\n===============resetting TPE========================== \n"); - if ((*tpe_reset) ()) { - panic("cannot reset TPE engien\n"); // 000004:fchang - } - } else { - panic("no tpe_reset function\n"); // 000004:fchang - return; - } - dma_reset_all_descriptors(chan_no); - rx_chan_clear_isr(chan_no); - mb(); - - // send EoP - if (tpe_inject) { - if ((*tpe_inject) ()) { - panic("cannot inject a cell\n"); // 000004:fchang - } - } else { - AMAZON_DMA_EMSG("no tpe_inject function\n"); - return; - } - mb(); - while (1) { - if (AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - chan_no * AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT)) { - rx_chan_clear_isr(chan_no); - mb(); - dma_reset_all_descriptors(chan_no); - if (g_log_chan[chan_no].current_desc == - (g_log_chan[chan_no].desc_len - 1)) { - g_log_chan[chan_no].current_desc = 0; - } else { - g_log_chan[chan_no].current_desc++; - } - break; - } - mdelay(1); - } - mb(); -#if 0 - AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &= ~(1 << ch_on_mapping[chan_no]); - while (AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) & - (1 << ch_on_mapping[chan_no])) { - printk("TPE channel still on\n"); - mdelay(1); - } - - // AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = (1<current_rx_chan = - chan_no - g_log_chan[chan_no].dma_dev->logic_rx_chan_base; - - // workaround for DMA pitfall: complete bit set happends before the - // other two bits (own,eop) are ready - if ((rx_desc_p->status.field.EoP != 1) - || (rx_desc_p->status.field.OWN != CPU_OWN) - || (rx_desc_p->status.field.data_length == - g_log_chan[chan_no].packet_size)) { -#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY - if (chan_no == 4 || chan_no == 5) { - dma_sync_fails++; - if (dma_sync_fails > MAX_SYNC_FAILS) { - // detect bug - rx_desc_p0 = - (struct rx_desc *) g_desc_list + - g_log_chan[chan_no].offset_from_base; - rx_desc_p1 = - (struct rx_desc *) g_desc_list + - g_log_chan[chan_no].offset_from_base + 1; - if ((rx_desc_p0->status.field.OWN == CPU_OWN - && rx_desc_p0->status.field.EoP != 1) - && (rx_desc_p1->status.field.OWN == CPU_OWN - && rx_desc_p1->status.field.EoP != 1)) { - amazon_dma_reset_tpe_rx(chan_no); - dma_sync_fails = 0; - return; - } - dma_sync_fails = 0; - AMAZON_DMA_DMSG("too many times ch:%d\n", chan_no); // 000004:fchang - return; - } - udelay(10); // 000004:fchang - } -#endif // //AMAZON_DMA_TPE_AAL5_RECOVERY - return; - } - - /* inform the upper layer to receive the packet */ - g_log_chan[chan_no].intr_handler(g_log_chan[chan_no].dma_dev, RCV_INT); - /* check the next descriptor, if still contains the incoming packet, - then do not clear the interrupt status */ - rx_desc_p = - (struct rx_desc *) g_desc_list + - g_log_chan[chan_no].offset_from_base + - g_log_chan[chan_no].current_desc; - if (! - ((rx_desc_p->status.field.OWN == CPU_OWN) - && (rx_desc_p->status.field.C == 1))) { - rx_chan_clear_isr(chan_no); - } -} - - -/* Brief: TX channel interrupt handler - * Parameter: TX channel no - * Description: the interrupt handler for each TX channel - * 1. check all the descripters,if any of them had transmitted a packet, then free buffer - * because we cannot garantee the which one has already transmitted out, we have to go through all the descriptors here - * 2. clear the interrupt status bit - */ -inline void tx_chan_intr_handler(int chan_no) -{ - struct tx_desc *tx_desc_p = NULL; - int i = 0; - - tx_desc_p = - (struct tx_desc *) g_desc_list + - g_log_chan[chan_no].offset_from_base; - - for (i = 0; i < g_log_chan[chan_no].desc_len; i++) { - if ((tx_desc_p->status.field.OWN == CPU_OWN) - && (tx_desc_p->status.field.C == 1)) { - /* if already transmitted, then free the buffer */ - g_log_chan[chan_no]. - buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), - g_log_chan[chan_no].opt[i]); - tx_desc_p->status.field.C = 0; - /* inform the upper layer about the completion of the - transmitted packet, the upper layer may want to free the - packet */ - g_log_chan[chan_no].intr_handler(g_log_chan[chan_no].dma_dev, - TRANSMIT_CPT_INT); - } - tx_desc_p++; - } - - /* after all these operations, clear the interrupt status bit */ - AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) = - (AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - chan_no * - AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP | - DMA_ISR_CMDCPT)); -} - -/* Brief: DMA interrupt handler - */ -static irqreturn_t dma_interrupt(int irq, void *dev_id) -{ - int i = 0; - int chan_no; - u32 isr = 0; -#ifdef NO_TX_INT // 000004:fchang - static int cnt = 0; // 000004:fchang -#endif // 000004:fchang - while ((isr = - AMAZON_DMA_REG32(AMAZON_DMA_COMB_ISR)) & (COMB_ISR_RX_MASK | - COMB_ISR_TX_MASK)) { - if (isr & COMB_ISR_RX_MASK) { - // RX Channels: start WFQ algorithm - chan_no = CHAN_TOTAL_NUM; - for (i = 0; i < RX_CHAN_NUM; i++) { - if ((isr & (comb_isr_mask[i])) - && (g_log_chan[i].weight > 0)) { - if (g_log_chan[chan_no].weight < g_log_chan[i].weight) { - chan_no = i; - } - } - } - if (chan_no < CHAN_TOTAL_NUM) { - rx_chan_intr_handler(chan_no); - } else { - for (i = 0; i < RX_CHAN_NUM; i++) { - g_log_chan[i].weight = g_log_chan[i].default_weight; - } - } - } -#ifdef NO_TX_INT - cnt++; - if (cnt == 10) { - cnt = 0; - for (i = 0; i < tx_chan_list_len; i++) { - if (AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - tx_chan_list[i] * - AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP)) { - tx_chan_intr_handler(tx_chan_list[i]); - } - } - } -#else - if (isr & COMB_ISR_TX_MASK) { - // TX channels: RR - for (i = 0; i < tx_chan_list_len; i++) { - if (isr & (comb_isr_mask[tx_chan_list[i]])) { - tx_chan_intr_handler(tx_chan_list[i]); - } - } - } -#endif - } // while - return IRQ_HANDLED; -} - - -/* Brief: read a packet from DMA RX channel - * Parameter: - * Return: packet length - * Description: - * This is called back in a context of DMA interrupt - * 1. prepare new descriptor - * 2. read data - * 3. update WFQ weight - */ -//507261:tc.chen int dma_device_read(struct dma_device_info* dma_dev, u8** dataptr, void** opt) -int asmlinkage dma_device_read(struct dma_device_info *dma_dev, - u8 ** dataptr, void **opt) -{ - u8 *buf; - int len; - int chan_no = 0; - int byte_offset = 0; - - struct rx_desc *rx_desc_p; - void *p = NULL; - int current_desc; - - chan_no = dma_dev->logic_rx_chan_base + dma_dev->current_rx_chan; - current_desc = g_log_chan[chan_no].current_desc; - rx_desc_p = - (struct rx_desc *) (g_desc_list + - g_log_chan[chan_no].offset_from_base + - current_desc); - buf = (u8 *) __va(rx_desc_p->Data_Pointer); /* extract the virtual - address of the data - pointer */ - len = rx_desc_p->status.field.data_length; /* extract the data length */ -#ifndef CONFIG_MIPS_UNCACHED - dma_cache_inv((unsigned long) buf, len); -#endif // CONFIG_MIPS_UNCACHED - *(u32 *) dataptr = (u32) buf; - if (opt) { - *(int *) opt = (int) g_log_chan[chan_no].opt[current_desc]; /* read - out - the - opt - information */ - } - - buf = - (u8 *) g_log_chan[chan_no].buffer_alloc(g_log_chan[chan_no]. - packet_size, &byte_offset, - &p); - // should check null!!!! - if (buf == NULL || p == NULL) { - *(u32 *) dataptr = 0; - *(int *) opt = 0; - len = 0; - } else { - g_log_chan[chan_no].opt[current_desc] = p; - /* reduce the weight for WFQ algorithm */ - g_log_chan[chan_no].weight -= len; - rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf); - } - if (current_desc == g_log_chan[chan_no].desc_len - 1) { - current_desc = 0; - } else { - current_desc++; - } - g_log_chan[chan_no].current_desc = current_desc; - - rx_desc_p->status.word = DMA_DESC_OWN_DMA - | (byte_offset << DMA_DESC_BYTEOFF_SHIFT) - | g_log_chan[chan_no].packet_size; - return len; -} - -/* Brief: write a packet through DMA RX channel to peripheral - * Parameter: - * Return: packet length - * Description: - * - */ -u64 dma_tx_drop = 0; -//507261:tc.chen int dma_device_write(struct dma_device_info* dma_dev, u8* dataptr, int len,void* opt) -int asmlinkage dma_device_write(struct dma_device_info *dma_dev, - u8 * dataptr, int len, void *opt) -{ - int chan_no = 0; - struct tx_desc *tx_desc_p; - - int byte_offset = 0; - int current_desc; - static int cnt = 0; // 000004:fchang - - unsigned long flag; - local_irq_save(flag); - - chan_no = dma_dev->logic_tx_chan_base + dma_dev->current_tx_chan; - current_desc = g_log_chan[chan_no].current_desc; - tx_desc_p = - (struct tx_desc *) (g_desc_list + - g_log_chan[chan_no].offset_from_base + - current_desc); - // 000003:tc.chen if(tx_desc_p->status.field.OWN==DMA_OWN){ - if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C == 1) { // 000003:tc.chen - AMAZON_DMA_DMSG("no TX desc for CPU, drop packet\n"); - dma_tx_drop++; - g_log_chan[chan_no].intr_handler(dma_dev, TX_BUF_FULL_INT); - local_irq_restore(flag); - return 0; - } - g_log_chan[chan_no].opt[current_desc] = opt; - - /* byte offset----to adjust the starting address of the data buffer, - should be multiple of the burst length. */ - byte_offset = - ((u32) CPHYSADDR((u32) dataptr)) % (g_log_chan[chan_no].burst_len * - 4); -#ifndef CONFIG_MIPS_UNCACHED - dma_cache_wback((unsigned long) dataptr, len); - wmb(); -#endif // CONFIG_MIPS_UNCACHED - - tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset; - wmb(); - tx_desc_p->status.word = DMA_DESC_OWN_DMA - | DMA_DESC_SOP_SET - | DMA_DESC_EOP_SET | (byte_offset << DMA_DESC_BYTEOFF_SHIFT) - | len; - wmb(); - if (is_channel_open(chan_no) == 0) { - // turn on if necessary - open_channel(chan_no); - } -#ifdef DMA_NO_POLLING - if ((AMAZON_DMA_REG32 - (AMAZON_DMA_CH0_ISR + - chan_no * AMAZON_DMA_CH_STEP) & (DMA_ISR_DURR | DMA_ISR_CPT)) == - (DMA_ISR_DURR)) { - // clear DURR if (CPT is AND set and DURR is set) - AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + - chan_no * AMAZON_DMA_CH_STEP) = DMA_ISR_DURR; - } -#endif - - if (current_desc == (g_log_chan[chan_no].desc_len - 1)) { - current_desc = 0; - } else { - current_desc++; - } - - - g_log_chan[chan_no].current_desc = current_desc; - tx_desc_p = - (struct tx_desc *) (g_desc_list + - g_log_chan[chan_no].offset_from_base + - current_desc); - // 000003:tc.chen if(tx_desc_p->status.field.OWN==DMA_OWN){ - if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C == 1) { // 000003:tc.chen - g_log_chan[chan_no].intr_handler(dma_dev, TX_BUF_FULL_INT); - } -#ifdef NO_TX_INT -//000004:fchang Start - cnt++; - if (cnt == 5) { - cnt = 0; - tx_chan_intr_handler(chan_no); - } -//000004:fchang End -#endif - local_irq_restore(flag); // 000004:fchang - return len; -} - - - -int desc_list_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - int i; - u32 *p = (u32 *) g_desc_list; - int len = 0; - len += sprintf(buf + len, "descriptor list:\n"); - for (i = 0; i < 120; i++) { - len += sprintf(buf + len, "%d\n", i); - len += sprintf(buf + len, "%08x\n", *(p + i * 2 + 1)); - len += sprintf(buf + len, "%08x\n", *(p + i * 2)); - - } - - return len; - -} - -int channel_weight_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - - // int i=0; - int len = 0; - len += sprintf(buf + len, "Qos dma channel weight list\n"); - len += - sprintf(buf + len, - "channel_num default_weight current_weight device Tx/Rx\n"); - len += - sprintf(buf + len, - " 0 %08x %08x Switch Rx0\n", - g_log_chan[0].default_weight, g_log_chan[0].weight); - len += - sprintf(buf + len, - " 1 %08x %08x Switch Rx1\n", - g_log_chan[1].default_weight, g_log_chan[1].weight); - len += - sprintf(buf + len, - " 2 %08x %08x Switch Rx2\n", - g_log_chan[2].default_weight, g_log_chan[2].weight); - len += - sprintf(buf + len, - " 3 %08x %08x Switch Rx3\n", - g_log_chan[3].default_weight, g_log_chan[3].weight); - len += - sprintf(buf + len, - " 4 %08x %08x Switch Tx0\n", - g_log_chan[4].default_weight, g_log_chan[4].weight); - len += - sprintf(buf + len, - " 5 %08x %08x Switch Tx1\n", - g_log_chan[5].default_weight, g_log_chan[5].weight); - /* - len+=sprintf(buf+len," 6 %08x %08x TPE - Rx0\n",g_log_chan[6].default_weight, g_log_chan[6].weight); - len+=sprintf(buf+len," 7 %08x %08x TPE - Rx0\n",g_log_chan[7].default_weight, g_log_chan[7].weight); - len+=sprintf(buf+len," 8 %08x %08x TPE - Tx0\n",g_log_chan[8].default_weight, g_log_chan[8].weight); - len+=sprintf(buf+len," 9 %08x %08x TPE - Rx0\n",g_log_chan[9].default_weight, g_log_chan[9].weight); - len+=sprintf(buf+len," 10 %08x %08x DPLUS - Rx0\n",g_log_chan[10].default_weight, g_log_chan[10].weight); - len+=sprintf(buf+len," 11 %08x %08x DPLUS - Rx0\n",g_log_chan[11].default_weight, g_log_chan[11].weight); */ - return len; -} - -int dma_register_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - dev_list *temp_dev; - int len = 0;; - - len += sprintf(buf + len, "amazon dma driver\n"); - len += sprintf(buf + len, "version 1.0\n"); - len += sprintf(buf + len, "devices registered:\n"); - for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) { - len += sprintf(buf + len, "%s ", temp_dev->dev->device_name); - } - len += sprintf(buf + len, "\n"); - len += sprintf(buf + len, "CH_ON=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH_ON)); - len += sprintf(buf + len, "CH_RST=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH_RST)); - len += sprintf(buf + len, "CH0_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR)); - len += sprintf(buf + len, "CH1_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH1_ISR)); - len += sprintf(buf + len, "CH2_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH2_ISR)); - len += sprintf(buf + len, "CH3_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH3_ISR)); - len += sprintf(buf + len, "CH4_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH4_ISR)); - len += sprintf(buf + len, "CH5_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH5_ISR)); - len += sprintf(buf + len, "CH6_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH6_ISR)); - len += sprintf(buf + len, "CH7_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH7_ISR)); - len += sprintf(buf + len, "CH8_ISR=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH8_ISR)); - len += - sprintf(buf + len, "CH9_ISR=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH9_ISR)); - len += - sprintf(buf + len, "CH10_ISR=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH10_ISR)); - len += - sprintf(buf + len, "CH11_ISR=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH11_ISR)); - len += - sprintf(buf + len, "LCH0_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK)); - len += - sprintf(buf + len, "LCH1_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH1_MSK)); - len += - sprintf(buf + len, "LCH2_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH2_MSK)); - len += - sprintf(buf + len, "LCH3_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH3_MSK)); - len += - sprintf(buf + len, "LCH4_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH4_MSK)); - len += - sprintf(buf + len, "LCH5_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH5_MSK)); - len += - sprintf(buf + len, "LCH6_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH6_MSK)); - len += - sprintf(buf + len, "LCH7_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH7_MSK)); - len += - sprintf(buf + len, "LCH8_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH8_MSK)); - len += - sprintf(buf + len, "LCH9_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH9_MSK)); - len += - sprintf(buf + len, "LCH10_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH10_MSK)); - len += - sprintf(buf + len, "LCH11_MSK=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH11_MSK)); - len += - sprintf(buf + len, "Desc_BA=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_Desc_BA)); - len += - sprintf(buf + len, "LCH0_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN)); - len += - sprintf(buf + len, "LCH1_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_LEN)); - len += - sprintf(buf + len, "LCH2_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH2_DES_LEN)); - len += - sprintf(buf + len, "LCH3_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH3_DES_LEN)); - len += - sprintf(buf + len, "LCH4_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH4_DES_LEN)); - len += - sprintf(buf + len, "LCH5_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH5_DES_LEN)); - len += - sprintf(buf + len, "LCH6_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH6_DES_LEN)); - len += - sprintf(buf + len, "LCH7_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH7_DES_LEN)); - len += - sprintf(buf + len, "LCH8_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH8_DES_LEN)); - len += - sprintf(buf + len, "LCH9_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH9_DES_LEN)); - len += - sprintf(buf + len, "LCH10_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH10_DES_LEN)); - len += - sprintf(buf + len, "LCH11_DES_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH11_DES_LEN)); - len += - sprintf(buf + len, "LCH1_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_OFST)); - len += - sprintf(buf + len, "LCH2_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH2_DES_OFST)); - len += - sprintf(buf + len, "LCH3_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH3_DES_OFST)); - len += - sprintf(buf + len, "LCH4_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH4_DES_OFST)); - len += - sprintf(buf + len, "LCH5_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH5_DES_OFST)); - len += - sprintf(buf + len, "LCH6_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH6_DES_OFST)); - len += - sprintf(buf + len, "LCH7_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH7_DES_OFST)); - len += - sprintf(buf + len, "LCH8_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH8_DES_OFST)); - len += - sprintf(buf + len, "LCH9_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH9_DES_OFST)); - len += - sprintf(buf + len, "LCH10_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH10_DES_OFST)); - len += - sprintf(buf + len, "LCH11_DES_OFST=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH11_DES_OFST)); - len += - sprintf(buf + len, "AMAZON_DMA_SW_BL=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_SW_BL)); - len += - sprintf(buf + len, "AMAZON_DMA_TPE_BL=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_TPE_BL)); - len += - sprintf(buf + len, "DPlus2FPI_BL=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_DPlus2FPI_BL)); - len += - sprintf(buf + len, "GRX_BUF_LEN=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_GRX_BUF_LEN)); - len += - sprintf(buf + len, "DMA_ECON_REG=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG)); - len += - sprintf(buf + len, "POLLING_REG=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG)); - len += - sprintf(buf + len, "CH_WGT=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_CH_WGT)); - len += - sprintf(buf + len, "TX_WGT=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_TX_WGT)); - len += - sprintf(buf + len, "DPlus2FPI_CLASS=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_DPLus2FPI_CLASS)); - len += - sprintf(buf + len, "COMB_ISR=%08x\n", - AMAZON_DMA_REG32(AMAZON_DMA_COMB_ISR)); -#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY - len += sprintf(buf + len, "TPE fails:%u\n", total_dma_tpe_reset); // 000004:fchang -#endif - return len; -} - -/* Brief: initialize DMA registers - * Description: - */ -static void dma_chip_init(void) -{ - int i; - for (i = 0; i < CHAN_TOTAL_NUM; i++) { - AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_OFST + - i * AMAZON_DMA_CH_STEP) = DEFAULT_OFFSET; - } -#ifdef DMA_NO_POLLING - AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG) = 0; -#else - // enable poll mode and set polling counter - AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG) = DMA_POLLING_CNT | DMA_POLLING_ENABLE; -#endif - // to enable DMA drop - AMAZON_DMA_REG32(AMAZON_DMA_GRX_BUF_LEN) = 0x10000; -} - -int insert_dev_list(dev_list * dev) -{ - dev_list *temp_dev; - if (g_head_dev == NULL) { - g_head_dev = dev; - g_tail_dev = dev; - dev->prev = NULL; - dev->next = NULL; - } else { - for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) { - if (temp_dev->weight < dev->weight) { - if (temp_dev->prev) - temp_dev->prev->next = dev; - - dev->prev = temp_dev->prev; - dev->next = temp_dev; - temp_dev->prev = dev; - if (temp_dev == g_head_dev) - g_head_dev = dev; - break; - } - } - - if (!temp_dev) { - g_tail_dev->next = dev; - dev->prev = g_tail_dev; - dev->next = NULL; - g_tail_dev = dev; - } - - } - - return 1; -} - -u8 *common_buffer_alloc(int len, int *byte_offset, void **opt) -{ - u8 *buffer = (u8 *) kmalloc(len * sizeof(u8), GFP_KERNEL); - *byte_offset = 0; - return buffer; - -} - -int common_buffer_free(u8 * dataptr, void *opt) -{ - if (dataptr) - kfree(dataptr); - return 0; -} - - -int register_dev(struct dma_device_info *dma_dev) -{ - int i, j, temp; - int burst_reg = 0; - u8 *buffer; - void *p = NULL; - int byte_offset = 0; - - struct rx_desc *rx_desc_p; - struct tx_desc *tx_desc_p; - if (strcmp(dma_dev->device_name, "switch1") == 0) { - AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = SWITCH1_RST_MASK; // resest - // channel - // 1st - AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG) |= 0x3; // endian - // conversion - // for Switch - burst_reg = AMAZON_DMA_SW_BL; - dma_dev->logic_rx_chan_base = switch_rx_chan_base; - dma_dev->logic_tx_chan_base = switch_tx_chan_base; - } - - else if (strcmp(dma_dev->device_name, "switch2") == 0) { - AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = SWITCH2_RST_MASK; // resest - // channel - // 1st - AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG) |= 0x3; // endian - // conversion - // for Switch - burst_reg = AMAZON_DMA_SW_BL; - dma_dev->logic_rx_chan_base = switch2_rx_chan_base; - dma_dev->logic_tx_chan_base = switch2_tx_chan_base; - - } else if (strcmp(dma_dev->device_name, "TPE") == 0) { - AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = TPE_RST_MASK; // resest - // channel 1st - // - burst_reg = AMAZON_DMA_TPE_BL; - dma_dev->logic_rx_chan_base = TPE_rx_chan_base; - dma_dev->logic_tx_chan_base = TPE_tx_chan_base; - } - - else if (strcmp(dma_dev->device_name, "DPlus") == 0) { - AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = DPlus2FPI_RST_MASK; // resest - // channel - // 1st - dma_dev->logic_rx_chan_base = DPLus2FPI_rx_chan_base; - dma_dev->logic_tx_chan_base = DPLus2FPI_tx_chan_base; - - } - - i = 0; - for (temp = dma_dev->tx_burst_len; temp > 2; temp /= 2) { - i += 1; - } - - - AMAZON_DMA_REG32(burst_reg) = i << 1; - i = 0; - for (temp = dma_dev->rx_burst_len; temp > 2; temp /= 2) { - i += 1; - } - AMAZON_DMA_REG32(burst_reg) += i; - - for (i = 0; i < dma_dev->num_rx_chan; i++) { - - temp = dma_dev->logic_rx_chan_base + i; - g_log_chan[temp].dma_dev = dma_dev; - g_log_chan[temp].weight = dma_dev->rx_chan[i].weight; - g_log_chan[temp].default_weight = dma_dev->rx_chan[i].weight; - g_log_chan[temp].current_desc = 0; - g_log_chan[temp].desc_ofst = DEFAULT_OFFSET; - g_log_chan[temp].desc_len = dma_dev->rx_chan[i].desc_num; - g_log_chan[temp].offset_from_base = temp * DEFAULT_OFFSET; - g_log_chan[temp].packet_size = dma_dev->rx_chan[i].packet_size; - - AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN + temp * AMAZON_DMA_CH_STEP) = dma_dev->rx_chan[i].desc_num; - // enable interrupt mask - if (temp == 4 || temp == 5) { - AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x32; - } else { - AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x36; - } - strcpy(g_log_chan[temp].device_name, dma_dev->device_name); - g_log_chan[temp].burst_len = dma_dev->rx_burst_len; - g_log_chan[temp].control = dma_dev->rx_chan[i].control; - - - /* specify the buffer allocation and free method */ - if (dma_dev->buffer_alloc) - g_log_chan[temp].buffer_alloc = dma_dev->buffer_alloc; - else - g_log_chan[temp].buffer_alloc = common_buffer_alloc; - - if (dma_dev->buffer_free) - g_log_chan[temp].buffer_free = dma_dev->buffer_free; - else - g_log_chan[temp].buffer_free = common_buffer_free; - - if (dma_dev->intr_handler) - g_log_chan[temp].intr_handler = dma_dev->intr_handler; - else - g_log_chan[temp].intr_handler = NULL; - - for (j = 0; j < g_log_chan[temp].desc_len; j++) { - rx_desc_p = (struct rx_desc *) (g_desc_list + g_log_chan[temp].offset_from_base + j); - rx_desc_p->status.word = 0; - rx_desc_p->status.field.data_length = g_log_chan[temp].packet_size; - buffer = (u8 *) g_log_chan[temp].buffer_alloc(g_log_chan[temp].packet_size, &byte_offset, &p); - rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buffer); - rx_desc_p->status.field.byte_offset = byte_offset; - /* fix me, should check if the addresss comply with the burst - lenght requirment */ - g_log_chan[temp].opt[j] = p; - rx_desc_p->status.field.OWN = DMA_OWN; - - } - /* open or close the channel */ - if (g_log_chan[temp].control) - open_channel(temp); - else - close_channel(temp); - } - - for (i = 0; i < dma_dev->num_tx_chan; i++) { - temp = dma_dev->logic_tx_chan_base + i; - g_log_chan[temp].dma_dev = dma_dev; - g_log_chan[temp].weight = dma_dev->tx_chan[i].weight; - g_log_chan[temp].default_weight = dma_dev->tx_chan[i].weight; - g_log_chan[temp].current_desc = 0; - g_log_chan[temp].desc_ofst = DEFAULT_OFFSET; - g_log_chan[temp].desc_len = dma_dev->tx_chan[i].desc_num; - g_log_chan[temp].offset_from_base = temp * DEFAULT_OFFSET; - g_log_chan[temp].packet_size = dma_dev->tx_chan[i].packet_size; - - AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN + temp * AMAZON_DMA_CH_STEP) = dma_dev->tx_chan[i].desc_num; - // enable interrupt mask -#ifdef NO_TX_INT - AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x3e; -#else - AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x36; -#endif - - strcpy(g_log_chan[temp].device_name, dma_dev->device_name); - g_log_chan[temp].burst_len = dma_dev->tx_burst_len; - g_log_chan[temp].control = dma_dev->tx_chan[i].control; - - if (dma_dev->buffer_alloc) - g_log_chan[temp].buffer_alloc = dma_dev->buffer_alloc; - else - g_log_chan[temp].buffer_alloc = common_buffer_alloc; - - if (dma_dev->buffer_free) - g_log_chan[temp].buffer_free = dma_dev->buffer_free; - else - g_log_chan[temp].buffer_free = common_buffer_free; - - if (dma_dev->intr_handler) - g_log_chan[temp].intr_handler = dma_dev->intr_handler; - else - g_log_chan[temp].intr_handler = NULL; - - for (j = 0; j < g_log_chan[temp].desc_len; j++) { - - tx_desc_p = - (struct tx_desc *) (g_desc_list + - g_log_chan[temp].offset_from_base + j); - tx_desc_p->status.word = 0; - tx_desc_p->status.field.data_length = - g_log_chan[temp].packet_size; - tx_desc_p->status.field.OWN = CPU_OWN; - - } - /* workaround DMA pitfall, we never turn on channel if we don't - have proper descriptors */ - if (!g_log_chan[temp].control) { - close_channel(temp); - } - - } - - return 0; -} - -int dma_device_register(struct dma_device_info *dma_dev) -{ - dev_list *temp_dev; - temp_dev = (dev_list *) kmalloc(sizeof(dev_list), GFP_KERNEL); - temp_dev->dev = dma_dev; - temp_dev->weight = dma_dev->weight; - insert_dev_list(temp_dev); - /* check whether this is a known device */ - if ((strcmp(dma_dev->device_name, "switch1") == 0) - || (strcmp(dma_dev->device_name, "TPE") == 0) - || (strcmp(dma_dev->device_name, "switch2") == 0) - || (strcmp(dma_dev->device_name, "DPlus") == 0)) { - register_dev(dma_dev); - } - - return 0; -} - - -int unregister_dev(struct dma_device_info *dma_dev) -{ - int i, j, temp; - u8 *buffer; - struct rx_desc *rx_desc_p; - - for (i = 0; i < dma_dev->num_rx_chan; i++) { - temp = dma_dev->logic_rx_chan_base + i; - close_channel(temp); - for (j = 0; j < g_log_chan[temp].desc_len; j++) { - rx_desc_p = - (struct rx_desc *) (g_desc_list + - g_log_chan[temp].offset_from_base + j); - buffer = (u8 *) __va(rx_desc_p->Data_Pointer); - g_log_chan[temp].buffer_free(buffer, g_log_chan[temp].opt[j]); - } - } - for (i = 0; i < dma_dev->num_tx_chan; i++) { - temp = dma_dev->logic_tx_chan_base + i; - close_channel(temp); - } - return 0; -} - -int dma_device_unregister(struct dma_device_info *dev) -{ - dev_list *temp_dev; - for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) { - if (strcmp(dev->device_name, temp_dev->dev->device_name) == 0) { - if ((strcmp(dev->device_name, "switch1") == 0) - || (strcmp(dev->device_name, "TPE") == 0) - || (strcmp(dev->device_name, "switch2") == 0) - || (strcmp(dev->device_name, "DPlus") == 0)) - unregister_dev(dev); - if (temp_dev == g_head_dev) { - g_head_dev = temp_dev->next; - kfree(temp_dev); - } else { - if (temp_dev == g_tail_dev) - g_tail_dev = temp_dev->prev; - if (temp_dev->prev) - temp_dev->prev->next = temp_dev->next; - if (temp_dev->next) - temp_dev->next->prev = temp_dev->prev; - kfree(temp_dev); - } - break; - } - - } - return 0; -} - -void dma_device_update_rx(struct dma_device_info *dma_dev) -{ - int i, temp; - for (i = 0; i < dma_dev->num_rx_chan; i++) { - temp = dma_dev->logic_rx_chan_base + i; - g_log_chan[temp].control = dma_dev->rx_chan[i].control; - - if (g_log_chan[temp].control) - open_channel(temp); - else - close_channel(temp); - } - -} - -void dma_device_update_tx(struct dma_device_info *dma_dev) -{ - int i, temp; - for (i = 0; i < dma_dev->num_tx_chan; i++) { - temp = dma_dev->logic_tx_chan_base + i; - g_log_chan[temp].control = dma_dev->tx_chan[i].control; - if (g_log_chan[temp].control) { - /* we turn on channel when send out the very first packet */ - // open_channel(temp); - } else - close_channel(temp); - } -} - -int dma_device_update(struct dma_device_info *dma_dev) -{ - dma_device_update_rx(dma_dev); - dma_device_update_tx(dma_dev); - return 0; -} - -static int dma_open(struct inode *inode, struct file *file) -{ - return 0; -} - -static int dma_release(struct inode *inode, struct file *file) -{ - /* release the resources */ - return 0; -} - -static int dma_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -{ - int value = 0; - int result = 0; - int chan_no = 0; - - switch (cmd) { - case 0: /* get register value */ - break; - case 1: /* return channel weight */ - chan_no = *((int *) arg); - *((int *) arg + 1) = g_log_chan[chan_no].default_weight; - break; - case 2: /* set channel weight */ - chan_no = *((int *) arg); - value = *((int *) arg + 1); - printk("new weight=%08x\n", value); - g_log_chan[chan_no].default_weight = value; - break; - default: - break; - } - return result; -} - - -static struct file_operations dma_fops = { - owner:THIS_MODULE, - open:dma_open, - release:dma_release, - ioctl:dma_ioctl, -}; - -static int dma_init(void) -{ - int result = 0; - int i; - printk("initialising dma core\n"); - result = register_chrdev(DMA_MAJOR, "dma-core", &dma_fops); - if (result) { - AMAZON_DMA_EMSG("cannot register device dma-core!\n"); - return result; - } - result = request_irq(AMAZON_DMA_INT, dma_interrupt, IRQF_DISABLED, "dma-core", (void *) &dma_interrupt); - if (result) { - AMAZON_DMA_EMSG("error, cannot get dma_irq!\n"); - free_irq(AMAZON_DMA_INT, (void *) &dma_interrupt); - return -EFAULT; - } - - g_desc_list = (u64 *) KSEG1ADDR(__get_free_page(GFP_DMA)); - - if (g_desc_list == NULL) { - AMAZON_DMA_EMSG("no memory for desriptor\n"); - return -ENOMEM; - } - memset(g_desc_list, 0, PAGE_SIZE); - AMAZON_DMA_REG32(AMAZON_DMA_Desc_BA) = (u32) CPHYSADDR((u32) g_desc_list); - g_amazon_dma_dir = proc_mkdir("amazon_dma", NULL); - create_proc_read_entry("dma_register", 0, g_amazon_dma_dir, dma_register_proc_read, NULL); - create_proc_read_entry("g_desc_list", 0, g_amazon_dma_dir, desc_list_proc_read, NULL); - create_proc_read_entry("channel_weight", 0, g_amazon_dma_dir, channel_weight_proc_read, NULL); - - dma_chip_init(); - for (i = 0; i < (RX_CHAN_NUM + 1); i++) { - rx_chan_list[i] = -1; - } - for (i = 0; i < (TX_CHAN_NUM + 1); i++) { - tx_chan_list[i] = -1; - } - - for (i = 0; i < CHAN_TOTAL_NUM; i++) { - comb_isr_mask[i] = 0x80000000 >> (i); - } - - g_log_chan[CHAN_TOTAL_NUM].weight = 0; - printk("initialising dma core ... done\n"); - - return 0; -} - -arch_initcall(dma_init); - - -void dma_cleanup(void) -{ - dev_list *temp_dev; - - unregister_chrdev(DMA_MAJOR, "dma-core"); - for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) { - kfree(temp_dev); - } - free_page(KSEG0ADDR((unsigned long) g_desc_list)); - remove_proc_entry("channel_weight", g_amazon_dma_dir); - remove_proc_entry("dma_list", g_amazon_dma_dir); - remove_proc_entry("dma_register", g_amazon_dma_dir); - remove_proc_entry("amazon_dma", NULL); - /* release the resources */ - free_irq(AMAZON_DMA_INT, (void *) &dma_interrupt); -} - -EXPORT_SYMBOL(dma_device_register); -EXPORT_SYMBOL(dma_device_unregister); -EXPORT_SYMBOL(dma_device_read); -EXPORT_SYMBOL(dma_device_write); -EXPORT_SYMBOL(dma_device_update); -EXPORT_SYMBOL(dma_device_update_rx); - -MODULE_LICENSE("GPL"); diff --git a/target/linux/amazon/files/arch/mips/amazon/dma-core.h b/target/linux/amazon/files/arch/mips/amazon/dma-core.h deleted file mode 100644 index cb3d456c9..000000000 --- a/target/linux/amazon/files/arch/mips/amazon/dma-core.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef DMA_CORE_H -#define DMA_CORE_H - -#define AMAZON_DMA_REG32(reg_num) *((volatile u32*)(reg_num)) -#define AMAZON_DMA_CH_STEP 4 - -#define COMB_ISR_RX_MASK 0xfe000000 -#define COMB_ISR_TX_MASK 0x01f00000 - - -#define DMA_OWN 1 -#define CPU_OWN 0 -#define DMA_MAJOR 250 - -//Descriptors -#define DMA_DESC_OWN_CPU 0x0 -#define DMA_DESC_OWN_DMA 0x80000000 -#define DMA_DESC_CPT_SET 0x40000000 -#define DMA_DESC_SOP_SET 0x20000000 -#define DMA_DESC_EOP_SET 0x10000000 - -#define switch_rx_chan_base 0 -#define switch_tx_chan_base 7 -#define switch2_rx_chan_base 2 -#define switch2_tx_chan_base 8 -#define TPE_rx_chan_base 4 -#define TPE_tx_chan_base 9 -#define DPLus2FPI_rx_chan_base 6 -#define DPLus2FPI_tx_chan_base 11 - -#define RX_CHAN_NUM 7 -#define TX_CHAN_NUM 5 -#define CHAN_TOTAL_NUM (RX_CHAN_NUM+TX_CHAN_NUM) -#define DEFAULT_OFFSET 20 -#define DESCRIPTOR_SIZE 8 - -typedef struct dev_list{ - struct dma_device_info* dev; - int weight; - struct dev_list* prev; - struct dev_list* next; -}dev_list; - -typedef struct channel_info{ - char device_name[16]; - int occupied; - enum attr_t attr; - int current_desc; - int weight; - int default_weight; - int desc_num; - int burst_len; - int desc_len; - int desc_ofst; - int packet_size; - int offset_from_base; - int control; - void* opt[DEFAULT_OFFSET]; - u8* (*buffer_alloc)(int len,int* offset, void** opt); - int (*buffer_free)(u8* dataptr,void* opt); - int (*intr_handler)(struct dma_device_info* info,int status); - - struct dma_device_info* dma_dev; -}channel_info; - - - -#endif - diff --git a/target/linux/amazon/files/arch/mips/amazon/interrupt.c b/target/linux/amazon/files/arch/mips/amazon/interrupt.c deleted file mode 100644 index e264ca759..000000000 --- a/target/linux/amazon/files/arch/mips/amazon/interrupt.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Gary Jennejohn (C) 2003 - * Copyright (C) 2007 Felix Fietkau - * Copyright (C) 2007 John Crispin - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Routines for generic manipulation of the interrupts found on the - * AMAZON boards. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -static void amazon_disable_irq(unsigned int irq_nr) -{ - int i; - u32 amazon_ier = AMAZON_ICU_IM0_IER; - - if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0) - amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier); - else { - irq_nr -= INT_NUM_IRQ0; - for (i = 0; i <= 4; i++) - { - if (irq_nr <= 31) - amazon_writel(amazon_readl(amazon_ier) & ~(1 << irq_nr ), amazon_ier); - amazon_ier += 0x10; - irq_nr -= 32; - } - } -} - -static void amazon_mask_and_ack_irq(unsigned int irq_nr) -{ - int i; - u32 amazon_ier = AMAZON_ICU_IM0_IER; - u32 amazon_isr = AMAZON_ICU_IM0_ISR; - - if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0){ - amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier); - amazon_writel(AMAZON_DMA_H_MASK, amazon_isr); - } else { - irq_nr -= INT_NUM_IRQ0; - for (i = 0; i <= 4; i++) - { - if (irq_nr <= 31){ - amazon_writel(amazon_readl(amazon_ier) & ~(1 << irq_nr ), amazon_ier); - amazon_writel((1 << irq_nr ), amazon_isr); - } - amazon_ier += 0x10; - amazon_isr += 0x10; - irq_nr -= 32; - } - } -} - -static void amazon_enable_irq(unsigned int irq_nr) -{ - int i; - u32 amazon_ier = AMAZON_ICU_IM0_IER; - - if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0) - amazon_writel(amazon_readl(amazon_ier) | AMAZON_DMA_H_MASK, amazon_ier); - else { - irq_nr -= INT_NUM_IRQ0; - for (i = 0; i <= 4; i++) - { - if (irq_nr <= 31) - amazon_writel(amazon_readl(amazon_ier) | (1 << irq_nr ), amazon_ier); - amazon_ier += 0x10; - irq_nr -= 32; - } - } -} - -static unsigned int amazon_startup_irq(unsigned int irq) -{ - amazon_enable_irq(irq); - return 0; -} - -static void amazon_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { - amazon_enable_irq(irq); - } -} - -static struct irq_chip amazon_irq_type = { - .name = "AMAZON", - .startup = amazon_startup_irq, - .enable = amazon_enable_irq, - .disable = amazon_disable_irq, - .unmask = amazon_enable_irq, - .ack = amazon_mask_and_ack_irq, - .mask = amazon_disable_irq, - .mask_ack = amazon_mask_and_ack_irq, - .end = amazon_end_irq -}; - -/* Cascaded interrupts from IM0-4 */ -static inline void amazon_hw_irqdispatch(u8 line) -{ - u32 irq; - - irq = (amazon_readl(AMAZON_ICU_IM_VEC) >> (line * 5)) & AMAZON_ICU_IM0_VEC_MASK; - if (line == 0 && irq <= 11 && irq >= 0) { - //DMA fixed to IM0_IRL0 - irq = 0; - } - do_IRQ(irq + INT_NUM_IRQ0 + (line * 32)); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - if (pending & CAUSEF_IP7){ - do_IRQ(MIPS_CPU_TIMER_IRQ); - goto out; - } else { - unsigned int i; - for (i = 0; i <= 4; i++) - { - if(pending & (CAUSEF_IP2 << i)){ - amazon_hw_irqdispatch(i); - goto out; - } - } - } - printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); -out: - return; -} - -static struct irqaction cascade = { - .handler = no_action, - .flags = IRQF_DISABLED, - .name = "cascade", -}; - -void __init arch_init_irq(void) -{ - int i; - - /* mask all interrupt sources */ - for(i = 0; i <= 4; i++){ - amazon_writel(0, AMAZON_ICU_IM0_IER + (i * 0x10)); - } - - mips_cpu_irq_init(); - - /* set up irq cascade */ - for (i = 2; i <= 6; i++) { - setup_irq(i, &cascade); - } - - for (i = INT_NUM_IRQ0; i <= INT_NUM_IM4_IRL31; i++) - set_irq_chip_and_handler(i, &amazon_irq_type, - handle_level_irq); - - set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); -} - -void __cpuinit arch_fixup_c0_irqs(void) -{ - /* FIXME: check for CPUID and only do fix for specific chips/versions */ - cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; - cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ; -} diff --git a/target/linux/amazon/files/arch/mips/amazon/pci.c b/target/linux/amazon/files/arch/mips/amazon/pci.c deleted file mode 100644 index 1b2afb9d4..000000000 --- a/target/linux/amazon/files/arch/mips/amazon/pci.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2007 Felix Fietkau - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -/* FIXME: convert nasty volatile register derefs to readl/writel calls */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define AMAZON_PCI_REG32( addr ) (*(volatile u32 *)(addr)) -#ifndef AMAZON_PCI_MEM_BASE -#define AMAZON_PCI_MEM_BASE 0xb2000000 -#endif -#define AMAZON_PCI_MEM_SIZE 0x00400000 -#define AMAZON_PCI_IO_BASE 0xb2400000 -#define AMAZON_PCI_IO_SIZE 0x00200000 - -#define AMAZON_PCI_CFG_BUSNUM_SHF 16 -#define AMAZON_PCI_CFG_DEVNUM_SHF 11 -#define AMAZON_PCI_CFG_FUNNUM_SHF 8 - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -static struct resource pci_io_resource = { - .name = "io pci IO space", -#if 1 - .start = AMAZON_PCI_IO_BASE, - .end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1, -#else - .start = 0, - .end = 0x00002000 - 1, -#endif - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource = { - .name = "ext pci memory space", - .start = AMAZON_PCI_MEM_BASE, - .end = AMAZON_PCI_MEM_BASE + AMAZON_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; - -static int amazon_pci_config_access(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data) -{ - unsigned long flags; - u32 pci_addr; - u32 val; - int ret; - - /* Amazon support slot from 0 to 15 */ - /* devfn 0 & 0x20 is itself */ - if ((bus->number != 0) || (devfn > 0x7f) || (devfn == 0) || (devfn == 0x20)) - return 1; - - local_irq_save(flags); - - pci_addr = AMAZON_PCI_CFG_BASE | - bus->number << AMAZON_PCI_CFG_BUSNUM_SHF | - devfn << AMAZON_PCI_CFG_FUNNUM_SHF | - (where & ~0x3); - - if (access_type == PCI_ACCESS_WRITE) - { -#ifdef CONFIG_SWAP_IO_SPACE - val = swab32(*data); -#endif - ret = put_dbe(val, (u32 *)pci_addr); - } else { - ret = get_dbe(val, (u32 *)pci_addr); -#ifdef CONFIG_SWAP_IO_SPACE - *data = swab32(val); -#else - *data = val; -#endif - } - - amazon_writel(amazon_readl(PCI_MODE) & (~(1<> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - - -static int amazon_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) -{ - u32 data = 0; - - if (size == 4) - { - data = val; - } else { - if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - } - - if (amazon_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops amazon_pci_ops = { - amazon_pci_read, - amazon_pci_write -}; - -static struct pci_controller amazon_pci_controller = { - .pci_ops = &amazon_pci_ops, - .mem_resource = &pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_resource = &pci_io_resource, - .io_offset = 0x00000000UL, -}; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - switch (slot) { - case 13: - /* IDSEL = AD29 --> USB Host Controller */ - return INT_NUM_IM2_IRL15; - case 14: - /* IDSEL = AD30 --> mini PCI connector */ - return INT_NUM_IM2_IRL14; - default: - printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin); - return 0; - } -} - -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - switch(dev->irq) { - case INT_NUM_IM2_IRL15: - /* - * IDSEL = AD29 --> USB Host Controller - * PCI_INTA/B/C--GPIO Port0.2--EXIN3 - * IN/ALT0:1 ALT1:0 - * PULL UP - */ - (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffb; - (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 4; - (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffb; - (*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 4; - (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 4; - //External Interrupt Node - (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x6000; /* Low Level triggered */ - (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x8; - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - break; - case INT_NUM_IM2_IRL14: - /* - * IDSEL = AD30 --> mini PCI connector - * PCI_INTA--GPIO Port0.1--EXIN2 - * IN/ALT0:1 ALT1:0 - * PULL UP - */ - (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffd; - (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 2; - (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffd; - (*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 2; - (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 2; - //External Interrupt Node - (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x600; - (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x4; - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - break; - default: - return 1; - } - return 0; -} - -int __init amazon_pci_init(void) -{ - u32 temp_buffer; - -#ifdef CONFIG_SWAP_IO_SPACE - AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28); - wmb(); -#endif - - AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1< - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void prom_putchar(char c) -{ - /* Wait for FIFO to empty */ - while ((amazon_readl(AMAZON_ASC_FSTAT) >> 8) != 0x00) ; - /* Crude cr/nl handling is better than none */ - if(c == '\n') - amazon_writel('\r', AMAZON_ASC_TBUF); - amazon_writel(c, AMAZON_ASC_TBUF); -} - -void __init prom_init(void) -{ - char **envp = (char **) fw_arg2; - - int memsize = 16; /* assume 16M as default */ - - envp = (char **)KSEG1ADDR((unsigned long)envp); - while (*envp) { - char *e = (char *)KSEG1ADDR(*envp); - - if (!strncmp(e, "memsize=", 8)) { - e += 8; - memsize = simple_strtoul(e, NULL, 10); - } - envp++; - } - memsize *= 1024 * 1024; - - strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2"); - - add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); -} - -void prom_free_prom_memory(void) -{ -} - -const char *get_system_type(void) -{ - return BOARD_SYSTEM_TYPE; -} diff --git a/target/linux/amazon/files/arch/mips/amazon/setup.c b/target/linux/amazon/files/arch/mips/amazon/setup.c deleted file mode 100644 index ff1a109d4..000000000 --- a/target/linux/amazon/files/arch/mips/amazon/setup.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (C) 2004 Peng Liu - * Copyright (C) 2007 John Crispin - * Copyright (C) 2007 Felix Fietkau - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static unsigned int r4k_offset; -static unsigned int r4k_cur; - -/* required in arch/mips/kernel/kspd.c */ -unsigned long cpu_khz; - -static void amazon_reboot_setup(void); - -/* the CPU clock rate - lifted from u-boot */ -unsigned int amazon_get_cpu_hz(void) -{ - /*-----------------------------------*/ - /**CGU CPU Clock Reduction Register***/ - /*-----------------------------------*/ - switch(amazon_readl(AMAZON_CGU_CPUCRD) & 0x3){ - case 0: - /*divider ration 1/1, 235 MHz clock */ - return 235000000; - case 1: - /*divider ration 2/3, 235 MHz clock, clock not accurate, here */ - return 150000000; - case 2: - /*divider ration 1/2, 235 MHz clock */ - return 117500000; - default: - /*divider ration 1/4, 235 MHz clock */ - return 58750000; - } -} - -/* the FPI clock rate - lifted from u-boot */ -unsigned int amazon_get_fpi_hz(void) -{ - unsigned int clkCPU; - clkCPU = amazon_get_cpu_hz(); - - /*-------------------------------------*/ - /***CGU Clock Divider Select Register***/ - /*-------------------------------------*/ - switch (amazon_readl(AMAZON_CGU_DIV) & 0x3) - { - case 1: - return clkCPU >> 1; - case 2: - return clkCPU >> 2; - default: - return clkCPU; - /* '11' is reserved */ - } -} -EXPORT_SYMBOL(amazon_get_fpi_hz); - -/* this doesn't really belong here, but it's a convenient location */ -unsigned int amazon_get_cpu_ver(void) -{ - static unsigned int cpu_ver = 0; - if (cpu_ver == 0) - cpu_ver = amazon_readl(AMAZON_MCD_CHIPID) & 0xFFFFF000; - return cpu_ver; -} - -static inline u32 amazon_get_counter_resolution(void) -{ - u32 res; - __asm__ __volatile__( - ".set push\n" - ".set mips32r2\n" - ".set noreorder\n" - "rdhwr %0, $3\n" - "ehb\n" - ".set pop\n" - : "=&r" (res) - : /* no input */ - : "memory"); - instruction_hazard(); - return res; -} - -void __init plat_time_init(void) -{ - mips_hpt_frequency = amazon_get_cpu_hz() / amazon_get_counter_resolution(); - r4k_offset = mips_hpt_frequency / HZ; - printk("mips_hpt_frequency:%d\n", mips_hpt_frequency); - printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset); - - r4k_cur = (read_c0_count() + r4k_offset); - write_c0_compare(r4k_cur); - - /* enable the timer in the PMU */ - amazon_writel(amazon_readl(AMAZON_PMU_PWDCR)| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI, AMAZON_PMU_PWDCR); - - /* setup the GPTU for timer tick f_fpi == f_gptu*/ - amazon_writel(0x0100, AMAZON_GPTU_CLC); - amazon_writel(0xffff, AMAZON_GPTU_CAPREL); - amazon_writel(0x80C0, AMAZON_GPTU_T6CON); -} - -void __init plat_mem_setup(void) -{ - u32 chipid = 0; - u32 part_no = 0; - - chipid = amazon_readl(AMAZON_MCD_CHIPID); - part_no = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid); - - if(part_no == AMAZON_CHIPID_YANGTSE){ - printk("Yangtse Version\n"); - } else if (part_no == AMAZON_CHIPID_STANDARD) { - printk(SYSTEM_MODEL_NAME "\n"); - } else { - printk("unknown version %8x\n",part_no); - } - - amazon_reboot_setup(); - - //stop reset TPE and DFE - amazon_writel(0, AMAZON_RST_REQ); - //clock - amazon_writel(0x3fff, AMAZON_PMU_PWDCR); - //reenable trace capability - part_no = readl(AMAZON_BCU_ECON); - - ioport_resource.start = IOPORT_RESOURCE_START; - ioport_resource.end = IOPORT_RESOURCE_END; - iomem_resource.start = IOMEM_RESOURCE_START; - iomem_resource.end = IOMEM_RESOURCE_END; -} - -static void amazon_machine_restart(char *command) -{ - local_irq_disable(); - amazon_writel(AMAZON_RST_ALL, AMAZON_RST_REQ); - for (;;) ; -} - -static void amazon_machine_halt(void) -{ - printk(KERN_NOTICE "System halted.\n"); - local_irq_disable(); - for (;;) ; -} - -static void amazon_machine_power_off(void) -{ - printk(KERN_NOTICE "Please turn off the power now.\n"); - local_irq_disable(); - for (;;) ; -} - -static void amazon_reboot_setup(void) -{ - _machine_restart = amazon_machine_restart; - _machine_halt = amazon_machine_halt; - pm_power_off = amazon_machine_power_off; -} diff --git a/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/irq.h b/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/irq.h deleted file mode 100644 index e72b7d5c1..000000000 --- a/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/irq.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __AMAZON_IRQ_H -#define __AMAZON_IRQ_H - -#define NR_IRQS 256 -#include_next - -#endif diff --git a/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/mangle-port.h b/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/mangle-port.h deleted file mode 100644 index af8c3e939..000000000 --- a/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/mangle-port.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Ralf Baechle - */ -#ifndef __ASM_MACH_AMAZON_MANGLE_PORT_H -#define __ASM_MACH_AMAZON_MANGLE_PORT_H - -#define __swizzle_addr_b(port) (port) -#define __swizzle_addr_w(port) ((port) ^ 2) -#define __swizzle_addr_l(port) (port) -#define __swizzle_addr_q(port) (port) - -/* - * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware; - * less sane hardware forces software to fiddle with this... - * - * Regardless, if the host bus endianness mismatches that of PCI/ISA, then - * you can't have the numerical value of data and byte addresses within - * multibyte quantities both preserved at the same time. Hence two - * variations of functions: non-prefixed ones that preserve the value - * and prefixed ones that preserve byte addresses. The latters are - * typically used for moving raw data between a peripheral and memory (cf. - * string I/O functions), hence the "__mem_" prefix. - */ -#if defined(CONFIG_SWAP_IO_SPACE) - -# define ioswabb(a, x) (x) -# define __mem_ioswabb(a, x) (x) -# define ioswabw(a, x) le16_to_cpu(x) -# define __mem_ioswabw(a, x) (x) -# define ioswabl(a, x) le32_to_cpu(x) -# define __mem_ioswabl(a, x) (x) -# define ioswabq(a, x) le64_to_cpu(x) -# define __mem_ioswabq(a, x) (x) - -#else - -# define ioswabb(a, x) (x) -# define __mem_ioswabb(a, x) (x) -# define ioswabw(a, x) (x) -# define __mem_ioswabw(a, x) cpu_to_le16(x) -# define ioswabl(a, x) (x) -# define __mem_ioswabl(a, x) cpu_to_le32(x) -# define ioswabq(a, x) (x) -# define __mem_ioswabq(a, x) cpu_to_le32(x) - -#endif - -#endif /* __ASM_MACH_AMAZON_MANGLE_PORT_H */ diff --git a/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/war.h b/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/war.h deleted file mode 100644 index da42ee5a2..000000000 --- a/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/war.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ -#ifndef __ASM_MIPS_MACH_AMAZON_WAR_H -#define __ASM_MIPS_MACH_AMAZON_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif diff --git a/target/linux/amazon/files/drivers/atm/amazon_tpe.c b/target/linux/amazon/files/drivers/atm/amazon_tpe.c deleted file mode 100644 index b50749440..000000000 --- a/target/linux/amazon/files/drivers/atm/amazon_tpe.c +++ /dev/null @@ -1,3074 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - */ -//----------------------------------------------------------------------- -/* - * Description: - * Driver for Infineon Amazon TPE - */ -//----------------------------------------------------------------------- -/* Author: peng.liu@infineon.com - * Created: 12-April-2004 - */ -//----------------------------------------------------------------------- -/* History - * Last changed on: 13 Oct. 2004 - * Last changed by: peng.liu@infineon.com - * Last changed on: 28 Jan. 2004 - * Last changed by: peng.liu@infineon.com - * Last changed Reason: - * - AAL5R may send more bytes than expected in MFL (so far, confirmed as 64 bytes) - */ -// 507261:tc.chen 2005/07/26 re-organize code address map to improve performance. -// 507281:tc.chen 2005/07/28 fix f4 segment isssue -/* 511045:linmars 2005/11/04 from Liu.Peng: change NRT_VBR bandwidth calculation based on scr instead of pcr */ - -#ifndef __KERNEL__ -#define __KERNEL__ -#endif -#ifndef EXPORT_SYMTAB -#define EXPORT_SYMTAB -#endif - -/*TPE level loopback, bypass AWARE DFE */ -#undef TPE_LOOPBACK - -/* enable debug options */ -#undef AMAZON_ATM_DEBUG - -/* enable rx error packet analysis */ -#undef AMAZON_ATM_DEBUG_RX - -/* test AAL5 Interrupt */ -#undef AMAZON_TPE_TEST_AAL5_INT - -/* dump packet */ -#undef AMAZON_TPE_DUMP - -/* read ARC register*/ -/* this register is located in side DFE module*/ -#undef AMAZON_TPE_READ_ARC - -/* software controlled reassembly */ -#undef AMAZON_TPE_SCR - -/* recovery from AAL5 bug */ -#undef AMAZON_TPE_AAL5_RECOVERY - -#if defined(AMAZON_TPE_READ_ARC) || defined(AMAZON_TPE_AAL5_RECOVERY) -#define ALPHAEUS_BASE_ADDR 0x31c00 -#define A_CFG_ADDR (ALPHAEUS_BASE_ADDR+0x04) -#define AR_CB0_STATUS_ADDR (ALPHAEUS_BASE_ADDR+0x2c) -#define AR_CB1_STATUS_ADDR (ALPHAEUS_BASE_ADDR+0x30) -#define AT_CELL0_ADDR (ALPHAEUS_BASE_ADDR+0x90) -#define AR_CELL0_ADDR (ALPHAEUS_BASE_ADDR+0x1a0) -#define AR_CD_CNT0_ADDR (ALPHAEUS_BASE_ADDR+0x1c8) -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(AMAZON_TPE_READ_ARC) || defined(AMAZON_TPE_AAL5_RECOVERY) -#include -#include -#endif - -#define AMAZON_TPE_EMSG(fmt, args...) printk( KERN_ERR "%s: " fmt,__FUNCTION__, ## args) - -/***************************************** External Functions *******************************************/ -extern unsigned int amazon_get_fpi_hz(void); -extern void mask_and_ack_amazon_irq(unsigned int irq_nr); -extern void amz_push_oam(unsigned char *); - -//amazon_mei.c -#if defined(AMAZON_TPE_READ_ARC) || defined(AMAZON_TPE_AAL5_RECOVERY) -extern MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize); -extern MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize); -#endif - -/***************************************** Internal Functions *******************************************/ -int amazon_atm_read_procmem(char *buf, char **start, off_t offset,int count, int *eof, void *data); -/***************************************** Global Data *******************************************/ -amazon_atm_dev_t g_atm_dev; //device data -static struct tq_struct swex_start_task; //BH task -static struct tq_struct swex_complete_task; //BH task -#ifdef AMAZON_TPE_SCR -static struct tq_struct a5r_task; //BH task -#endif -static struct dma_device_info g_dma_dev; //for DMA -static struct atm_dev * amazon_atm_devs[AMAZON_ATM_PORT_NUM]; -static struct oam_last_activity g_oam_time_stamp[AMAZON_ATM_MAX_VCC_NUM]; -static u8 g_oam_cell[AMAZON_AAL0_SDU+4]; //for OAM cells -#ifdef AMAZON_CHECK_LINK -static int adsl_link_status; //ADSL link status, 0:down, 1:up -#endif //AMAZON_CHECK_LINK -/***************************************** Module Parameters *************************************/ -// Parameter Definition for module -static int port_enable0 = 1; // Variable for parameter port_enable0 -static int port_enable1 = 0; // Variable for parameter port_enable1 -static int port_max_conn0 = 15; // Variable for parameter port_max_conn0 -static int port_max_conn1 = 0; // Variable for parameter port_max_conn1 -static int port_cell_rate_up0 = 7500; // Variable for parameter port_cell_rate_up0 -static int port_cell_rate_up1 = 7500; // Variable for parameter port_cell_rate_up1 - - -static int qsb_tau = 1; // Variable for parameter qsb_tau -static int qsb_srvm = 0xf; // Variable for parameter qsb_srvm -static int qsb_tstep = 4 ; // Variable for parameter qsb_tstep - -static int cbm_nrt = 3900; // Variable for parameter cbm_nrt -static int cbm_clp0 =3500; // Variable for parameter cbm_clp0 -static int cbm_clp1 =3200; // Variable for parameter cbm_clp1 -static int cbm_free_cell_no = AMAZON_ATM_FREE_CELLS; // Variable for parameter cbm_free_cell_no - -static int a5_fill_pattern = 0x7e; // Variable for parameter a5_fill_pattern '~' -static int a5s_mtu = 0x700; // mtu for tx -static int a5r_mtu = 0x700; // mtu for rx - -static int oam_q_threshold = 64; // oam queue threshold, minium value 64 -static int rx_q_threshold = 1000; // rx queue threshold, minium value 64 -static int tx_q_threshold = 800; // tx queue threshold, minium value 64 - -MODULE_PARM(port_max_conn0, "i"); -MODULE_PARM_DESC(port_max_conn0, "Maximum atm connection for port #0"); -MODULE_PARM(port_max_conn1, "i"); -MODULE_PARM_DESC(port_max_conn1, "Maximum atm connection for port #1"); -MODULE_PARM(port_enable0, "i"); -MODULE_PARM_DESC(port_enable0, "0 -> port disabled, 1->port enabled"); -MODULE_PARM(port_enable1, "i"); -MODULE_PARM_DESC(port_enable1, "0 -> port disabled, 1->port enabled"); -MODULE_PARM(port_cell_rate_up0, "i"); -MODULE_PARM_DESC(port_cell_rate_up0, "ATM port upstream rate in cells/s"); -MODULE_PARM(port_cell_rate_up1, "i"); -MODULE_PARM_DESC(port_cell_rate_up1, "ATM port upstream rate in cells/s"); - -MODULE_PARM(qsb_tau,"i"); -MODULE_PARM_DESC(qsb_tau, "Cell delay variation. value must be > 0"); -MODULE_PARM(qsb_srvm, "i"); -MODULE_PARM_DESC(qsb_srvm, "Maximum burst size"); -MODULE_PARM(qsb_tstep, "i"); -MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4"); - -MODULE_PARM(cbm_nrt, "i"); -MODULE_PARM_DESC(cbm_nrt, "Non real time threshold for cell buffer"); -MODULE_PARM(cbm_clp0, "i"); -MODULE_PARM_DESC(cbm_clp0, "Threshold for cells with cell loss priority 0"); -MODULE_PARM(cbm_clp1, "i"); -MODULE_PARM_DESC(cbm_clp1, "Threshold for cells with cell loss priority 1"); -MODULE_PARM(cbm_free_cell_no, "i"); -MODULE_PARM_DESC(cbm_free_cell_no, "Number of cells in the cell buffer manager"); - -MODULE_PARM(a5_fill_pattern, "i"); -MODULE_PARM_DESC(a5_fill_pattern, "filling pattern (PAD) for aal5 frames"); -MODULE_PARM(a5s_mtu, "i"); -MODULE_PARM_DESC(a5s_mtu, "max. SDU for upstream"); -MODULE_PARM(a5r_mtu, "i"); -MODULE_PARM_DESC(a5r_mtu, "max. SDU for downstream"); - -MODULE_PARM(oam_q_threshold, "i"); -MODULE_PARM_DESC(oam_q_threshold, "oam queue threshold"); - -MODULE_PARM(rx_q_threshold, "i"); -MODULE_PARM_DESC(rx_q_threshold, "downstream/rx queue threshold"); - -MODULE_PARM(tx_q_threshold, "i"); -MODULE_PARM_DESC(tx_q_threshold, "upstream/tx queue threshold"); - -/***************************************** local functions *************************************/ -/* Brief: valid QID - * Return: 1 if valid - * 0 if not - */ -static inline int valid_qid(int qid) -{ - return ( (qid>0) && (qiddata)) & 15) != 0){ - AMAZON_TPE_DMSG("need to adjust the alignment manually\n"); - skb_reserve(skb, 16 - (((u32) (skb->data)) & 15) ); - } - -} - -/* - * Brief: initialize the device according to the module paramters - * Return: not NULL - ok - * NULL - fails - * Description: arrange load parameters and call the hardware initialization routines - */ -static void atm_init_parameters(amazon_atm_dev_t *dev) -{ - //port setting - dev->ports[0].enable = port_enable0; - dev->ports[0].max_conn = port_max_conn0; - dev->ports[0].tx_max_cr = port_cell_rate_up0; - if (port_enable1){ - dev->ports[1].enable = port_enable1; - dev->ports[1].max_conn = port_max_conn1; - dev->ports[1].tx_max_cr = port_cell_rate_up1; - } - - //aal5 - dev->aal5.padding_byte = a5_fill_pattern; - dev->aal5.tx_max_sdu = a5s_mtu; - dev->aal5.rx_max_sdu = a5r_mtu; - - //cbm - dev->cbm.nrt_thr = cbm_nrt; - dev->cbm.clp0_thr = cbm_clp0; - dev->cbm.clp1_thr = cbm_clp1; - dev->cbm.free_cell_cnt = cbm_free_cell_no; - - //qsb - dev->qsb.tau = qsb_tau; - dev->qsb.tstepc =qsb_tstep; - dev->qsb.sbl = qsb_srvm; - - //allocate on the fly - dev->cbm.mem_addr = NULL; - dev->cbm.qd_addr = NULL; -} - - -/* Brief: Find QID for VCC - * Parameters: vcc - VCC data structure - * Return Value: -EINVAL - VCC not found - * qid - QID for this VCC - * Description: - * This function returns the QID of a given VCC - */ -static int amazon_atm_get_queue(struct atm_vcc* vcc) -{ - int i; - for (i=0;ivpi == vpi) && (vcc->vci == vci)) return i; - } - } - return -EINVAL; -} - -/* Brief: Find QID for VPI - * Parameters: vpi - VPI to found - * Return Value: -EINVAL - VPI not found - * qid - QID for this VPI - * - * Description: - * This function returns the QID for a given VPI. itf and VCI don't matter - */ -static int amazon_atm_find_vpi(u8 vpi) -{ - int i; - for (i=0;ivpi == vpi) return i; - } - } - return -EINVAL; -} - -/* - * Brief: Clears QID entries for VCC - * - * Parameters: vcc - VCC to found - * - * Description: - * This function searches for the given VCC and sets it to NULL if found. - */ -static inline void amazon_atm_clear_vcc(int i) -{ - g_atm_dev.queues[i].vcc = NULL; - g_atm_dev.queues[i].free = 1; -} - - -/* - * Brief: dump skb data - */ -static inline void dump_skb(u32 len, char * data) -{ -#ifdef AMAZON_TPE_DUMP - int i; - for(i=0;ipop != NULL) { - vcc->pop(vcc, skb); - } else { - dev_kfree_skb_any(skb); - } -} -/* - * Brief: release TX skbuff - */ -static inline void amazon_atm_free_tx_skb(struct sk_buff *skb) -{ - struct atm_vcc* vcc = ATM_SKB(skb)->vcc; - if (vcc!=NULL){ - amazon_atm_free_tx_skb_vcc(vcc,skb); - } else { - dev_kfree_skb_any(skb);//fchang:Added - } -} - -/* Brief: divide by 64 and round up - */ -static inline u32 divide_by_64_round_up(int input) -{ - u32 tmp1; - tmp1 = (u32) input; - tmp1 = (tmp1%64)?(tmp1/64 + 1): (tmp1/64); - if (tmp1 == 0) tmp1 = 1; - return tmp1; -} - -/* - * Brief: statistics - */ -#ifdef AMAZON_ATM_DEBUG -static inline void queue_statics(int qid, qs_t idx) -{ - if (valid_qid(qid)){ - g_atm_dev.queues[qid].qs[idx]++; - } -} -#else //not AMAZON_ATM_DEBUG -static inline void queue_statics(int qid, qs_t idx){} -#endif //AMAZON_ATM_DEBUG - - -/* Brief: set dma tx full, i.e. there is no available descriptors - */ -static void inline atm_dma_full(void) -{ - AMAZON_TPE_DMSG("ch0 is full\n"); - atomic_set(&g_atm_dev.dma_tx_free_0,0); -} - -/* - * Brief set dma tx free (at least one descript is available) - */ -inline static void atm_dma_free(void) -{ - AMAZON_TPE_DMSG("ch0 is free\n"); - atomic_set(&g_atm_dev.dma_tx_free_0,1); -} - - -/* Brief: return the status of DMA TX descriptors - * Parameters: TX channel (DMA_TX_CH0, TX_CH1) - * Return: - * 1: there are availabel TX descriptors - * 0: no available - * Description: - * - */ -inline int dma_may_send(int ch) -{ - if (atomic_read(&g_atm_dev.dma_tx_free_0)){ - return 1; - } - return 0; -} - -/******************************* global functions *********************************/ -/* - * Brief: SWIE Cell Extraction Start Routine - * and task routine for swex_complete_task - * Parameters: irq_stat - interrupt status - * - * Description: - * This is the routine for extracting cell. It will schedule itself if the hardware is busy. - * This routine runs in interrupt context - */ -void amazon_atm_swex(void * irq_stat) -{ - u32 ex_stat=0; - u32 addr; - // Read extraction status register - ex_stat = readl(CBM_HWEXSTAT0_ADDR); - - // Check if extraction/insertion is in progress - if ( (ex_stat & CBM_EXSTAT_SCB) || (ex_stat & CBM_EXSTAT_FB) || (test_and_set_bit(SWIE_LOCK, &(g_atm_dev.swie.lock))!=0)) { - AMAZON_TPE_DMSG(" extraction in progress. Will wait\n"); - swex_start_task.data = irq_stat; - queue_task(&swex_start_task, &tq_immediate); - mark_bh(IMMEDIATE_BH); - }else { - // Extract QID - g_atm_dev.swie.qid = (((u32)irq_stat) >> 24); - AMAZON_TPE_DMSG("extracting from qid=%u\n",g_atm_dev.swie.qid); - //read status word - addr = KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr); - addr = readl((addr + g_atm_dev.swie.qid * 0x10 + 4) & 0xFFFFFFC0); - addr = KSEG1ADDR(addr); - g_atm_dev.swie.sw = readl(addr+52)&SWIE_ADDITION_DATA_MASK; - AMAZON_TPE_DMSG("cell addition word: %8x \n", g_atm_dev.swie.sw); - - // Start extraction - AMAZON_WRITE_REGISTER_L(g_atm_dev.swie.qid | SWIE_CBM_PID_SUBADDR, CBM_HWEXPAR0_ADDR); - AMAZON_WRITE_REGISTER_L(SWIE_CBM_SCE0, CBM_HWEXCMD_ADDR); - } -} -#ifdef AMAZON_TPE_SCR -u32 g_a5r_wait=0; -/* - * Brief: AAL5 Packet Extraction Routine and task routine for a5r_task - * Parameters: irq_stat - interrupt status - * - * Description: - * This is the routine for extracting frame. It will schedule itself if the hardware is busy. - * This routine runs in interrupt context - */ -void amazon_atm_a5r(void* qid) -{ - volatile u32 ex_stat=0; - u32 addr; - u32 a5r_wait=0; - - ex_stat = readl(CBM_HWEXSTAT0_ADDR); -#if 0 - // Check if extraction/insertion is in progress - if ( (ex_stat & CBM_EXSTAT_SCB) || (ex_stat & CBM_EXSTAT_FB) ) { - AMAZON_TPE_DMSG(" extraction in progress. Will wait\n"); - a5r_task.data = qid; - queue_task(&a5r_task, &tq_immediate); - mark_bh(IMMEDIATE_BH); - }else { - AMAZON_TPE_DMSG("extracting from qid=%u\n",(u8)qid); - // Start extraction - AMAZON_WRITE_REGISTER_L(((u8)qid) | CBM_HWEXPAR_PN_A5, CBM_HWEXPAR0_ADDR); - AMAZON_WRITE_REGISTER_L(CBM_HWEXCMD_FE0, CBM_HWEXCMD_ADDR); - } -#else - //while ( (ex_stat & CBM_EXSTAT_SCB) || (ex_stat & CBM_EXSTAT_FB) ) { - while ( ex_stat != 0x80){ - a5r_wait++; - ex_stat = readl(CBM_HWEXSTAT0_ADDR); -#if 0 - if (a5r_wait >= 0xffffff){ - a5r_wait=0; - printk("."); - } -#endif - } - if (a5r_wait > g_a5r_wait){ - g_a5r_wait = a5r_wait; - } - AMAZON_WRITE_REGISTER_L(((u8)qid) | CBM_HWEXPAR_PN_A5, CBM_HWEXPAR0_ADDR); - AMAZON_WRITE_REGISTER_L(CBM_HWEXCMD_FE0, CBM_HWEXCMD_ADDR); -#endif -} - -#endif //AMAZON_TPE_SCR - -/* Brief: Handle F4/F5 OAM cell - * Return: - * 0 ok - * <0 fails - */ -static int inline amazon_handle_oam_cell(void *data, u8 vpi, u16 vci,u32 status) -{ - struct atm_vcc* vcc=NULL; - int qid; - if (!status&SWIE_EOAM_MASK){ - AMAZON_TPE_EMSG("unknown cell received, discarded\n"); - goto amazon_handle_oam_cell_err_exit; - }else if (status&SWIE_ECRC10ERROR_MASK){ - AMAZON_TPE_EMSG("CRC-10 Error Status:%8x, discarded\n", status); - goto amazon_handle_oam_cell_err_exit; - }else{ - if(status & (SWIE_EVCI3_MASK |SWIE_EVCI4_MASK)){ - //F4 level (VPI) OAM, Assume duplex - qid = amazon_atm_find_vpi(vpi)+CBM_RX_OFFSET; - }else if (status & (SWIE_EPTI4_MASK|SWIE_EPTI5_MASK)){ - //F5 level (VCI) OAM, Assume duplex - qid = amazon_atm_find_vpivci(vpi,vci)+CBM_RX_OFFSET; - }else{ - qid = -1; - AMAZON_TPE_EMSG("non-F4/F5 OAM cells?, discarded\n"); - goto amazon_handle_oam_cell_err_exit; - } - } - if (valid_qid(qid) && ((vcc = g_atm_dev.queues[qid].vcc)!=NULL)){ - //TODO, should we do this for ALL OAM types? (Actually only User and CC) - g_atm_dev.queues[qid].access_time=xtime; - if (vcc->push_oam){ - (*vcc->push_oam)(vcc,data); - }else{ - amz_push_oam(data); - } - }else{ - AMAZON_TPE_EMSG("no VCC yet\n"); - goto amazon_handle_oam_cell_err_exit; - } - return 0; -amazon_handle_oam_cell_err_exit: - dump_skb(AMAZON_AAL0_SDU,(char *)data); - return -1; -} - -/* Brief: SWIE Cell Extraction Finish Routine - * and task routine for swex_complete_task - * Description: - * 1.Allocate a buffer of type struct sk_buff - * 2.Copy the data from the temporary memory to this buffer - * 3.Push the data to upper layer - * 4.Update the statistical data if necessary - * 5.Release the temporary data - - */ -void amazon_atm_swex_push(void * data) -{ - struct atm_vcc* vcc=NULL; - struct sk_buff* skb=NULL; - struct amazon_atm_cell_header * cell_header; - u32 status; - int qid; - if (!data){ - AMAZON_TPE_EMSG("data is NULL\n"); - return; - } - qid = ((u8*)data)[AMAZON_AAL0_SDU]; - status = ((u32*)data)[ATM_AAL0_SDU/4]; - cell_header = (struct amazon_atm_cell_header *) data; - if (valid_qid(qid) != 1){ - AMAZON_TPE_EMSG("error qid: %u\n",qid); - AMAZON_TPE_EMSG("unknown cells recieved\n"); - }else if (qid == AMAZON_ATM_OAM_Q_ID){ - //OAM or RM or OTHER cell - //Find real connection - -#ifdef IKOS_MINI_BOOT - //for OAM loop back test - dump_skb(56,(char *)data); - //kfree(data); using g_oam_cell - return; -#endif //IKOS_MINI_BOOT -#ifdef TPE_LOOPBACK - amz_push_oam(data); - return; -#endif//TPE_LOOPBACK - int ret = 0; - ret = amazon_handle_oam_cell(data,cell_header->bit.vpi,cell_header->bit.vci,status); - if (ret == 0) - return; - }else{ - //should be normal AAL0 cells - // Get VCC - vcc = g_atm_dev.queues[qid].vcc; - if (vcc != NULL) { - AMAZON_TPE_DMSG("push to upper layer\n"); - skb = dev_alloc_skb(AMAZON_AAL0_SDU); - if (skb != NULL) { - //skb->dev=vcc->dev; - memcpy(skb_put(skb, AMAZON_AAL0_SDU), data, AMAZON_AAL0_SDU); - skb->stamp = xtime; - ATM_SKB(skb)->vcc = vcc; - (*g_atm_dev.queues[qid].push)(vcc,skb,0); - }else{ - AMAZON_TPE_EMSG(" No memory left for incoming AAL0 cell! Cell discarded!\n"); - //inform the upper layer - (*g_atm_dev.queues[qid].push)(vcc,skb,-ENOMEM); - atomic_inc(&vcc->stats->rx_drop); - } - }else{ - AMAZON_TPE_EMSG("invalid qid %u\n",qid); - } - } - //kfree(data); using g_oam_cell -} - -/* - * Brief: Interrupt handler for software cell extraction (done) - * Parameters: irq - CPPN for this interrupt - * data - Device ID for this interrupt - * regs - Register file - * - * Description: - * When a software extraction is finished this interrupt is issued. - * It reads the cell data and sends it to the ATM stack. - */ -void amazon_atm_swex_isr(int irq, void *data, struct pt_regs *regs) -{ - u32 * cell = NULL; - int i; - //ATM_AAL0 SDU + QID - AMAZON_TPE_DMSG("SWIE extraction done\n"); - cell = (u32 *) g_oam_cell; - if (cell != NULL){ - //convert to host byte order from big endian - for(i=0;i>CBM_INTINF0_QID_SHIFT); -#ifdef AMAZON_TPE_SCR - if (irq_stat & CBM_INTINF0_EF){ - amazon_atm_a5r((void*)qid); - } -#endif - // Check if Any Cell Arrived - if (irq_stat & CBM_INTINF0_ACA) { - amazon_atm_swex((void *)irq_stat); - } - //TX AAL5 PDU discard - if (irq_stat & CBM_INTINF0_OPF){ - if ( (qid) < CBM_RX_OFFSET ){ - g_atm_dev.mib_counter.tx_drop++; - } - queue_statics(qid, QS_HW_DROP); - } - if (irq_stat & (CBM_INTINF0_ERR|CBM_INTINF0_Q0E|CBM_INTINF0_Q0I|CBM_INTINF0_RDE)){ - AMAZON_TPE_EMSG("CBM INT status: %8x\n",irq_stat); - if (irq_stat & CBM_INTINF0_ERR){ - AMAZON_TPE_EMSG("CBM Error: FPI Bus Error\n"); - } - if (irq_stat & CBM_INTINF0_Q0E){ - AMAZON_TPE_EMSG("CBM Error: Queue 0 Extract\n"); - } - if (irq_stat & CBM_INTINF0_Q0I){ - AMAZON_TPE_EMSG("CBM Error: Queue 0 Extract\n"); - } - if (irq_stat & CBM_INTINF0_RDE){ - AMAZON_TPE_EMSG("CBM Error: Read Empty Queue %u\n",qid); - dump_qd(qid); - } - } - } - mask_and_ack_amazon_irq(AMAZON_CBM_INT); -} - -/* Brief: check the status word after AAL SDU after reassembly - */ -static inline void check_aal5_error(u8 stw0, u8 stw1, int qid) -{ - if (stw0 & AAL5_STW0_MFL){ - AMAZON_TPE_DMSG("Maximum Frame Length\n"); - g_atm_dev.queues[qid].aal5VccOverSizedSDUs++; - } - if (stw0 & AAL5_STW0_CRC){ - AMAZON_TPE_DMSG("CRC\n"); - g_atm_dev.queues[qid].aal5VccCrcErrors++; - } -#ifdef AMAZON_ATM_DEBUG_RX - AMAZON_TPE_EMSG("qid:%u stw0:%8x stw1:%8x\n",qid,stw0,stw1); -#endif -} - -/* Brief: Process DMA rx data - * Parameters: - dma_dev: pointer to the dma_device_info, provided by us when register the dma device - * Return: no - * Description: DMA interrupt handerl with OoS support. It is called when there is some data in rx direction. - * - */ -//507261:tc.chen void atm_process_dma_rx(struct dma_device_info* dma_dev) -void __system atm_process_dma_rx(struct dma_device_info* dma_dev) -{ - u8 * head=NULL; - u32 length=0; - u8 stw0=0; - u8 stw1=0; - - struct sk_buff * skb=NULL; - struct atm_vcc * vcc=NULL; - int qid=0; -#ifdef AMAZON_ATM_DEBUG_RX - static int dma_rx_dump=0; - static u32 seq=0; - - seq++; - if (dma_rx_dump>0){ - printk("\n=========================[%u]=========================\n",seq); - } -#endif - length=dma_device_read(dma_dev,&head,(void**)&skb); - AMAZON_TPE_DMSG("receive %8p[%u] from DMA\n", head,length); - if (head == NULL||length<=0) { - AMAZON_TPE_DMSG("dma_read null \n"); - goto error_exit; - } - - if (length > (g_atm_dev.aal5.rx_max_sdu+64)){ - AMAZON_TPE_EMSG("received packet too large (%u)\n",length); - goto error_exit; - } - //check AAL5R trail for error and qid - //last byte is qid - length--; - qid = (int) head[length]; - AMAZON_TPE_DMSG("head[%u] qid %u\n",length, qid); - //STW0 is always 4 bytes before qid - length -= 4; - stw0 = head[length]&0xff; - AMAZON_TPE_DMSG("head[%u] stw0 %8x\n",length, stw0); - //position of STW1 depends on the BE bits - length = length-4 + (stw0&AAL5_STW0_BE); - stw1 = head[length]&0xff; - AMAZON_TPE_DMSG("head[%u] stw1 %8x\n",length, stw1); - if ( (stw0 & AAL5_STW0_MASK) || (stw1 & AAL5_STW1_MASK) ){ - //AAL5 Error - check_aal5_error(stw0, stw1,qid); - goto error_exit; - } - //make data pointers consistent - //UU + CPI - length -= 2; - AMAZON_TPE_DMSG("packet length %u\n", length); - - //error: cannot restore the qid - if (valid_qid(qid) != 1){ - AMAZON_TPE_EMSG("received frame in invalid qid %u!\n", qid); - goto error_exit; - } - vcc = g_atm_dev.queues[qid].vcc; - if (vcc == NULL){ - AMAZON_TPE_EMSG("received frame in invalid vcc, qid=%u!\n",qid); - goto error_exit; - } - if (skb == NULL){ - AMAZON_TPE_EMSG("cannot restore skb pointer!\n"); - goto error_exit; - } - skb_put(skb,length); - skb->stamp = xtime; - g_atm_dev.queues[qid].access_time=xtime; - if ((*g_atm_dev.queues[qid].push)(vcc,skb,0)){ - g_atm_dev.mib_counter.rx_drop++; - queue_statics(qid, QS_SW_DROP); - }else{ - g_atm_dev.mib_counter.rx++; - adsl_led_flash();//joelin adsl led - queue_statics(qid, QS_PKT); - AMAZON_TPE_DMSG("push successful!\n"); - } -#ifdef AMAZON_ATM_DEBUG_RX - if (dma_rx_dump>0){ - printk("\nOK packet [dump=%u] length=%u\n",dma_rx_dump,length); - dump_skb(length+7, head); - } - if (dma_rx_dump >0) dma_rx_dump--; -#endif - return ; -error_exit: -#ifdef AMAZON_ATM_DEBUG_RX - if ( (head!=NULL) && (length >0)){ - AMAZON_TPE_EMSG("length=%u\n",length); - dump_skb(length+5, head); - } - dma_rx_dump++; -#endif - g_atm_dev.mib_counter.rx_err++; - queue_statics(qid, QS_ERR); - /* - if (vcc){ - (*g_atm_dev.queues[qid].push)(vcc,skb,1); - } - */ - if (skb != NULL) { - dev_kfree_skb_any(skb); - } - return; -} - -/*Brief: ISR for DMA pseudo interrupt - *Parameter: - dma_dev: pointer to the dma_device_info, provided by us when register the dma device - intr_status: - RCV_INT: rx data available - TX_BUF_FULL_INT: tx descriptor run out of - TRANSMIT_CPT_INT: tx descriptor available again - *Return: - 0 for success??? - */ -//507261:tc.chen int amazon_atm_dma_handler(struct dma_device_info* dma_dev, int intr_status) -int __system amazon_atm_dma_handler(struct dma_device_info* dma_dev, int intr_status) -{ - AMAZON_TPE_DMSG("status:%u\n",intr_status); - switch (intr_status) { - case RCV_INT: - atm_process_dma_rx(dma_dev); - break; - case TX_BUF_FULL_INT: - //TX full: no descriptors - atm_dma_full(); - break; - case TRANSMIT_CPT_INT: - //TX free: at least one descriptor - atm_dma_free(); - break; - default: - AMAZON_TPE_EMSG("unknown status!\n"); - } - return 0; -} - -/*Brief: free buffer for DMA tx - *Parameter: - dataptr: pointers to data buffer - opt: optional parameter, used to convey struct skb pointer, passwd in dma_device_write - *Return: - 0 for success??? - *Description: - called by DMA module to release data buffer after DMA tx transaction - *Error: - cannot restore skb pointer - */ -int amazon_atm_free_tx(u8*dataptr, void* opt) -{ - struct sk_buff *skb; - if (opt){ - AMAZON_TPE_DMSG("free skb%8p\n",opt); - skb = (struct sk_buff *)opt; - amazon_atm_free_tx_skb(skb); - }else{ - AMAZON_TPE_EMSG("BUG: cannot restore skb pointer!\n"); - } - return 0; -} - -/*Brief: allocate buffer & do alignment - */ -inline struct sk_buff * amazon_atm_alloc_buffer(int len) -{ - struct sk_buff *skb; - skb = dev_alloc_skb(len+16); - if (skb){ - //alignment requriements (4x32 bits (16 bytes) boundary) - alloc_align_16(skb); - } - return skb; -} - -/*Brief: allocate buffer for DMA rx - *Parameter: - len: length - opt: optional data to convey the skb pointer, which will be returned to me in interrupt handler, - *Return: - pointer to buffer, NULL means error? - *Description: - must make sure byte alignment - */ - -u8* amazon_atm_alloc_rx(int len, int* offset, void **opt) -{ - struct sk_buff *skb; - *offset = 0; - skb = amazon_atm_alloc_buffer(len); - if (skb){ - AMAZON_TPE_DMSG("alloc skb->data:%8p len:%u\n",skb->data,len); - *(struct sk_buff**)opt = skb; - }else{ - AMAZON_TPE_DMSG("no memory for receiving atm frame!\n"); - return NULL; - } - return skb->data; -} - - - - -/* Brief: Allocate kernel memory for sending a datagram. - * Parameters - * vcc virtual connection - * size data buffer size - * Return: - * NULL fail - * sk_buff a pointer to a sk_buff - * Description: - * This function can allocate our own additional memory for AAL5S inbound - * header (8bytes). We have to replace the protocol default one (alloc_tx in /net/atm/common.c) - * when we open the device. - * byte alignment is done is DMA driver. - */ -struct sk_buff *amazon_atm_alloc_tx(struct atm_vcc *vcc,unsigned int size) -{ - struct sk_buff *skb; - - if (!dma_may_send(DMA_TX_CH0)){ - AMAZON_TPE_EMSG("no DMA descriptor available!\n"); - return NULL; - } - //AAL5 inbound header space + alignment extra buffer - size+=8+AAL5S_INBOUND_HEADER; - - if (atomic_read(&vcc->tx_inuse) && !atm_may_send(vcc,size)) { - AMAZON_TPE_EMSG("Sorry tx_inuse = %u, size = %u, sndbuf = %u\n", - atomic_read(&vcc->tx_inuse),size,vcc->sk->sndbuf); - return NULL; - } - - skb = amazon_atm_alloc_buffer(size); - if (skb == NULL){ - AMAZON_TPE_EMSG("no memory\n"); - return NULL; - } - AMAZON_TPE_DMSG("dev_alloc_skb(%u) = %x\n", skb->len, (u32)skb); - AMAZON_TPE_DMSG("tx_inuse %u += %u\n",atomic_read(&vcc->tx_inuse),skb->truesize); - atomic_add(skb->truesize+ATM_PDU_OVHD,&vcc->tx_inuse); - - //reserve for AAL5 inbound header - skb_reserve(skb,AAL5S_INBOUND_HEADER); - return skb; -} - - -/* Brief: change per queue QSB setting according to vcc qos parameters - * Paramters: - * vcc: atm_vcc pointer - * qid: CBM queue id (1~15) - * Return: - */ -static inline void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, int qid) -{ - qsb_qptl_t qptl; - qsb_qvpt_t qvpt; - u32 tmp=0; - unsigned int qsb_clk; - - qsb_clk = amazon_get_fpi_hz()>>1; - - AMAZON_TPE_EMSG("Class=%u MAX_PCR=%u PCR=%u MIN_PCR=%u SCR=%u MBS=%u CDV=%u\n" - ,qos->txtp.traffic_class - ,qos->txtp.max_pcr - ,qos->txtp.pcr - ,qos->txtp.min_pcr - ,qos->txtp.scr - ,qos->txtp.mbs - ,qos->txtp.cdv - ); - - // PCR limiter - if (qos->txtp.max_pcr == 0){ - qptl.bit.tprs = 0; /* 0 disables the PCR limiter */ - }else { - // peak cell rate will be slightly lower than requested (maximum rate / pcr)= (qsbclock/2^3 * timestep/4)/pcr - tmp = (( (qsb_clk * g_atm_dev.qsb.tstepc)>>5)/ qos->txtp.max_pcr ) + 1; - // check if an overfow occured - if (tmp > QSB_TP_TS_MAX) { - AMAZON_TPE_EMSG("max_pcr is too small, max_pcr:%u tprs:%u\n",qos->txtp.max_pcr, tmp); - qptl.bit.tprs = QSB_TP_TS_MAX; - }else{ - qptl.bit.tprs = tmp; - } - } - //WFQ - if (qos->txtp.traffic_class == ATM_CBR || qos->txtp.traffic_class ==ATM_VBR_RT){ - // real time queue gets weighted fair queueing bypass - qptl.bit.twfq = 0; - }else if (qos->txtp.traffic_class ==ATM_VBR_NRT ||qos->txtp.traffic_class ==ATM_UBR_PLUS ){ - // wfq calculation here are based on virtual cell rates, to reduce granularity for large rates - // wfq factor is maximum cell rate / garenteed cell rate. - //qptl.bit.twfq = g_atm_dev.qsb.min_cr * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr; - if (qos->txtp.min_pcr == 0) { - AMAZON_TPE_EMSG(" MIN_PCR should not be zero\n"); - qptl.bit.twfq = QSB_WFQ_NONUBR_MAX; - }else{ - tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr; - if (tmp == 0 ){ - qptl.bit.twfq = 1; - }else if (tmp > QSB_WFQ_NONUBR_MAX){ - AMAZON_TPE_EMSG("min_pcr is too small, min_pcr:%u twfq:%u\n",qos->txtp.min_pcr, tmp); - qptl.bit.twfq = QSB_WFQ_NONUBR_MAX; - }else{ - qptl.bit.twfq = tmp; - } - } - }else if (qos->txtp.traffic_class == ATM_UBR){ - // ubr bypass, twfq set to maximum value - qptl.bit.twfq = QSB_WFQ_UBR_BYPASS; - }else{ - //tx is diabled, treated as UBR - AMAZON_TPE_EMSG(" unsupported traffic class %u \n", qos->txtp.traffic_class); - qos->txtp.traffic_class = ATM_UBR; - qptl.bit.twfq = QSB_WFQ_UBR_BYPASS; - } - - //SCR Leaky Bucket Shaper VBR.0/VBR.1 - if (qos->txtp.traffic_class ==ATM_VBR_RT || qos->txtp.traffic_class ==ATM_VBR_NRT){ - if (qos->txtp.scr == 0){ - //SCR == 0 disable the shaper - qvpt.bit.ts = 0; - qvpt.bit.taus = 0; - }else{ - //CLP - if (vcc->atm_options&ATM_ATMOPT_CLP){ - //CLP1 - qptl.bit.vbr = 1; - }else{ - //CLP0 - qptl.bit.vbr = 0; - } - //TS and TauS - tmp = (( (qsb_clk * g_atm_dev.qsb.tstepc)>>5)/ qos->txtp.scr ) + 1; - if (tmp > QSB_TP_TS_MAX) { - AMAZON_TPE_EMSG("scr is too small, scr:%u ts:%u\n",qos->txtp.scr, tmp); - qvpt.bit.ts = QSB_TP_TS_MAX; - }else{ - qvpt.bit.ts = tmp; - } - tmp = (qos->txtp.mbs - 1)*(qvpt.bit.ts - qptl.bit.tprs)/64; - if (tmp > QSB_TAUS_MAX){ - AMAZON_TPE_EMSG("mbs is too large, mbr:%u taus:%u\n",qos->txtp.mbs, tmp); - qvpt.bit.taus = QSB_TAUS_MAX; - }else if (tmp == 0){ - qvpt.bit.taus = 1; - }else{ - qvpt.bit.taus = tmp; - } - } - }else{ - qvpt.w0 = 0; - } - //write the QSB Queue Parameter Table (QPT) - AMAZON_WRITE_REGISTER_L(QSB_QPT_SET_MASK,QSB_RTM_ADDR); - AMAZON_WRITE_REGISTER_L(qptl.w0, QSB_RTD_ADDR); - AMAZON_WRITE_REGISTER_L((QSB_TABLESEL_QPT<itf; - u32 dma_qos=0; - u8 * qd_addr=NULL; - - tx_config|=CBM_QD_W3_WM_EN|CBM_QD_W3_CLPt; - //RT: check if the connection is a real time connection - if (vcc->qos.txtp.traffic_class == ATM_CBR || vcc->qos.txtp.traffic_class == ATM_VBR_RT){ - tx_config|= CBM_QD_W3_RT; - }else{ - tx_config|= CBM_QD_W3_AAL5; //don't set the AAL5 flag if it is a RT service - } - rx_config = tx_config; - - if(vcc->qos.aal == ATM_AAL5){ - //QoS: DMA QoS according to the traffic class - switch (vcc->qos.txtp.traffic_class){ - case ATM_CBR: dma_qos = CBR_DMA_QOS;break; - case ATM_VBR_RT: dma_qos = VBR_RT_DMA_QOS;break; - case ATM_VBR_NRT: dma_qos = VBR_NRT_DMA_QOS;break; - case ATM_UBR_PLUS: dma_qos = UBR_PLUS_DMA_QOS;break; - case ATM_UBR: dma_qos = UBR_DMA_QOS;break; - } - - //TX: upstream, AAL5(EPD or PPD), NOINT, SBid - tx_config |= CBM_QD_W3_DIR_UP|CBM_QD_W3_INT_NOINT|(itf&CBM_QD_W3_SBID_MASK); - //RX: DMA QoS, downstream, no interrupt, AAL5(EPD, PPD), NO INT, HCR -#ifdef AMAZON_TPE_SCR - rx_config |= dma_qos|CBM_QD_W3_DIR_DOWN|CBM_QD_W3_INT_EOF; -#else - rx_config |= dma_qos|CBM_QD_W3_DIR_DOWN|CBM_QD_W3_INT_NOINT|CBM_QD_W3_HCR; -#endif - }else { - //should be AAL0 - //upstream, NOINT, SBid - tx_config |= CBM_QD_W3_DIR_UP|CBM_QD_W3_INT_NOINT|(itf&CBM_QD_W3_SBID_MASK); - //RX: downstream, ACA interrupt, - rx_config |= CBM_QD_W3_DIR_DOWN|CBM_QD_W3_INT_ACA; - } - - //Threshold: maximum threshold for tx/rx queue, which is adjustable in steps of 64 cells - tx_config |= ( (divide_by_64_round_up(tx_q_threshold)&0xffff)< 1024) - { - AMAZON_TPE_EMSG("timeout\n"); - return -EIO; - } - // write address register, - AMAZON_WRITE_REGISTER_L(idx, HTU_RAMADDR_ADDR); - // configure transmit queue - tmp1 = vpi<<24|vci<<8; - tmp1|= HTU_RAMDAT1_VCON // valid connection the entry is not validated here !!!!!!!!!!!!!!!! - |HTU_RAMDAT1_VCI3 // vci3 -> oam queue - |HTU_RAMDAT1_VCI4 // vci4 -> oam queue - |HTU_RAMDAT1_VCI6 // vci6 -> rm queue - |HTU_RAMDAT1_PTI4 // pti4 -> oam queue - |HTU_RAMDAT1_PTI5; // pti5 -> oam queue - - // ramdat 1 (in params & oam handling) - AMAZON_WRITE_REGISTER_L( tmp1, HTU_RAMDAT1_ADDR); - // ramdat 2 (out params & oam handling) - tmp1 = ((qid+CBM_RX_OFFSET)&HTU_RAMDAT2_QID_MASK) - |HTU_RAMDAT2_PTI6 - |HTU_RAMDAT2_PTI7 - |HTU_RAMDAT2_F4U - |HTU_RAMDAT2_F5U - ; - AMAZON_WRITE_REGISTER_L( tmp1, HTU_RAMDAT2_ADDR); - wmb(); - // write HTU entry - AMAZON_WRITE_REGISTER_L(HTU_RAMCMD_WR, HTU_RAMCMD_ADDR); - return 0; -} -/* - * Brief: add HTU table entry - * Parameter: - * vcc: atm_vcc pointer - * qid: CBM queue id - * Return: - * 0: sucessful - * EIO: HTU table entry cannot be written - */ -inline static int set_htu(struct atm_vcc *vcc, u32 qid) -{ - return set_htu_entry(vcc->vpi, vcc->vci, qid, (qid - CBM_DEFAULT_Q_OFFSET)); -} - -/* - * Brief: allocate a queue - * Return: - * <=0 no available queues - * >0 qid - */ -static int atm_allocate_q(short itf) -{ - int i; - u32 tmp1=0; - int qid=0; - amazon_atm_port_t * dev; - dev = &g_atm_dev.ports[itf]; - //find start queue id for this interface - for (i=0; i< itf; i++) - { - qid+= g_atm_dev.ports[i].max_conn; - } - // apply default queue offset ( oam, free cell queue, others, rm ) - qid += CBM_DEFAULT_Q_OFFSET; - tmp1 = qid; - // search for a free queue - while ( (qidmax_conn) - && ( g_atm_dev.queues[qid].free != 1)) { - qid++;; - } - // if none was found, send failure message and return - if ( tmp1+dev->max_conn == qid) - { - return -EFAULT; - } - return qid; - -} -/* Brief: open a aal5 or aal0 connection - */ -static int atm_open(struct atm_vcc *vcc, push_back_t push) -{ - int err=0; - int qid=0; - amazon_atm_port_t * port = & g_atm_dev.ports[vcc->itf]; - unsigned long flags; - /***************** check bandwidth ******************/ - /* 511045:linmars change ATM_VBR_NRT to use scr instead of pcr */ - if ((vcc->qos.txtp.traffic_class==ATM_CBR&&vcc->qos.txtp.max_pcr>port->tx_rem_cr) - ||(vcc->qos.txtp.traffic_class==ATM_VBR_RT&&vcc->qos.txtp.max_pcr>port->tx_rem_cr) - ||(vcc->qos.txtp.traffic_class==ATM_VBR_NRT&&vcc->qos.txtp.scr>port->tx_rem_cr) - ||(vcc->qos.txtp.traffic_class==ATM_UBR_PLUS&&vcc->qos.txtp.min_pcr>port->tx_rem_cr) - ) { - AMAZON_TPE_EMSG("not enough bandwidth left (%u) cells per seconds \n",port->tx_rem_cr); - return -EINVAL; - } - if ( (qid = amazon_atm_find_vpivci(vcc->vpi, vcc->vci)) >0 ){ - AMAZON_TPE_EMSG("vpi:%u vci:%u is alreay open on queue:%u\n", vcc->vpi, vcc->vci, qid); - return -EADDRINUSE; - } - - /***************** allocate entry queueID for this port *****************/ - if ( (qid=atm_allocate_q(vcc->itf)) <= 0){ - AMAZON_TPE_EMSG("port: %u max:%u qid: %u\n", vcc->itf, port->max_conn, qid); - AMAZON_TPE_EMSG("no availabel connections for this port:%u\n",vcc->itf); - return -EINVAL; - } - /**************QSB parameters and CBM descriptors*************/ - set_qsb(vcc, &vcc->qos, qid); - set_qd(vcc, qid); - mb(); - err=set_htu(vcc,qid); - if (err){ - AMAZON_TPE_EMSG("set htu entry fails %u\n",err); - return err; - } - /************set internal mapping*************/ - local_irq_save(flags); - g_atm_dev.queues[qid].free = 0; - g_atm_dev.queues[qid].vcc = vcc; - g_atm_dev.queues[qid].push = push; - g_atm_dev.queues[qid+CBM_RX_OFFSET].free = 0; - g_atm_dev.queues[qid+CBM_RX_OFFSET].vcc = vcc; - g_atm_dev.queues[qid+CBM_RX_OFFSET].push = push; - /******************reserve bandwidth**********************/ - if (vcc->qos.txtp.traffic_class == ATM_CBR){ - //CBR, real time connection, reserve PCR - port->tx_cur_cr += vcc->qos.txtp.max_pcr; - port->tx_rem_cr -= vcc->qos.txtp.max_pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_VBR_RT){ - //VBR_RT, real time connection, reserve PCR - port->tx_cur_cr += vcc->qos.txtp.max_pcr; - port->tx_rem_cr -= vcc->qos.txtp.max_pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_VBR_NRT){ - //VBR_NRT, reserve SCR - port->tx_cur_cr += vcc->qos.txtp.pcr; - port->tx_rem_cr -= vcc->qos.txtp.pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS){ - //UBR_PLUS, reserve MCR - port->tx_cur_cr += vcc->qos.txtp.min_pcr; - port->tx_rem_cr -= vcc->qos.txtp.min_pcr; - } - local_irq_restore(flags); - return err; -} -/* Brief: Open ATM connection - * Parameters: atm_vcc - Pointer to VCC data structure - * vpi - VPI value for new connection - * vci - VCI value for new connection - * - * Return: 0 - sucessful - * -ENOMEM - No memory available - * -EINVAL - No bandwidth/queue/ or unsupported AAL type - * Description: - * This function opens an ATM connection on a specific device/interface - * - */ -int amazon_atm_open(struct atm_vcc *vcc,push_back_t push) -{ - int err=0; - - AMAZON_TPE_DMSG("vpi %u vci %u itf %u aal %u\n" - ,vcc->vpi - ,vcc->vci - ,vcc->itf - ,vcc->qos.aal - ); - - AMAZON_TPE_DMSG("tx cl %u bw %u mtu %u\n" - ,vcc->qos.txtp.traffic_class - ,vcc->qos.txtp.max_pcr - ,vcc->qos.txtp.max_sdu - ); - AMAZON_TPE_DMSG("rx cl %u bw %u mtu %u\n" - ,vcc->qos.rxtp.traffic_class - ,vcc->qos.rxtp.max_pcr - ,vcc->qos.rxtp.max_sdu - ); - if (vcc->qos.aal == ATM_AAL5 || vcc->qos.aal == ATM_AAL0){ - err = atm_open(vcc,push); - }else{ - AMAZON_TPE_EMSG("unsupported aal type %u\n", vcc->qos.aal); - err = -EPROTONOSUPPORT; - }; - if (err == 0 ){ - //replace the default memory allocation function with our own - vcc->alloc_tx = amazon_atm_alloc_tx; - set_bit(ATM_VF_READY,&vcc->flags); - } - return err; -} - -/* Brief: Send ATM OAM cell - * Parameters: atm_vcc - Pointer to VCC data structure - * skb - Pointer to sk_buff structure, that contains the data - * Return: 0 - sucessful - * -ENOMEM - No memory available - * -EINVAL - Not supported - * Description: - * This function sends a cell over and ATM connection - * We always release the skb - * TODO: flags handling (ATM_OF_IMMED, ATM_OF_INRATE) - */ -int amazon_atm_send_oam(struct atm_vcc *vcc, void * cell, int flags) -{ - int err=0; - int qid=0; - struct amazon_atm_cell_header * cell_header; - // Get cell header - cell_header = (struct amazon_atm_cell_header*) cell; - if ((cell_header->bit.pti == ATM_PTI_SEGF5) || (cell_header->bit.pti == ATM_PTI_E2EF5)) { - qid = amazon_atm_find_vpivci( cell_header->bit.vpi, cell_header->bit.vci); - }else if (cell_header->bit.vci == 0x3 || cell_header->bit.vci == 0x4) { - //507281:tc.chen qid = amazon_atm_find_vpi((int) cell_header->bit.vpi); - // 507281:tc.chen start - u8 f4_vpi; - f4_vpi = cell_header->bit.vpi; - qid = amazon_atm_find_vpi(f4_vpi ); - // 507281:tc.chen end - }else{ - //non-OAM cells, always invalid - qid = -EINVAL; - } - if (qid == -EINVAL) { - err = -EINVAL; - AMAZON_TPE_EMSG("not valid AAL0 packet\n"); - }else{ - //send the cell using swie -#ifdef TPE_LOOPBACK - err = amazon_atm_swin(AMAZON_ATM_OAM_Q_ID, cell); -#else - err = amazon_atm_swin(qid, cell); -#endif - } - //kfree(cell); - return err; -} - -/* Brief: Send AAL5 frame through DMA - * Parameters: vpi - virtual path id - * vci - virtual circuit id - * clp - cell loss priority - * qid - CBM queue to be sent to - * skb - packet to be sent - * Return: 0 - sucessful - * -ENOMEM - No memory available - * -EINVAL - Not supported - * Description: - * This function sends a AAL5 frame over and ATM connection - * 1. make sure that the data is aligned to 4x32-bit boundary - * 2. provide the inbound data (CPCS-UU and CPI, not used here) - * 3. set CLPn - * 4. send the frame by DMA - * 5. release the buffer ??? - ** use our own allocation alloc_tx - ** we make sure the alignment and additional memory - *** we always release the skb - - */ -int amazon_atm_dma_tx(u8 vpi, u16 vci, u8 clp, u8 qid, struct sk_buff *skb) -{ - int err=0,need_pop=1; - u32 * data=NULL; - int nwrite=0; - struct sk_buff *skb_tmp; - u32 len=skb->len; - - //AAL5S inbound header 8 bytes - if (skb->len > g_atm_dev.aal5.tx_max_sdu - AAL5S_INBOUND_HEADER) { - AMAZON_TPE_DMSG("tx_max_sdu:%u\n",g_atm_dev.aal5.tx_max_sdu); - AMAZON_TPE_DMSG("skb too large [%u]!\n",skb->len); - err = -EMSGSIZE; - goto atm_dma_tx_error_exit; - } - - //Check the byte alignment requirement and header space - if ( ( ((u32)(skb->data)%16) !=AAL5S_INBOUND_HEADER)|| (skb_headroom(skb)len+16); - if (skb_tmp==NULL){ - err = - ENOMEM; - goto atm_dma_tx_error_exit; - } - alloc_align_16(skb_tmp); - g_atm_dev.aal5.cnt_cpy++; - skb_reserve(skb_tmp,AAL5S_INBOUND_HEADER); - memcpy(skb_put(skb_tmp,skb->len), skb->data, skb->len); - amazon_atm_free_tx_skb(skb); - need_pop=0; - skb = skb_tmp; - } - //Provide AAL5S inbound header - data = (u32 *)skb_push(skb,8); - data[0] = __be32_to_cpu(vpi<<20|vci<<4|clp); - data[1] = __be32_to_cpu(g_atm_dev.aal5.padding_byte<<8|qid); - - len = skb->len; - - //send through DMA - AMAZON_TPE_DMSG("AAL5S header 0 %8x\n", data[0]); - AMAZON_TPE_DMSG("AAL5S header 0 %8x\n", data[1]); - AMAZON_TPE_DMSG("about to call dma_write len: %u\n", len); - nwrite=dma_device_write( &g_dma_dev,skb->data,len,skb); - if (nwrite != len) { - //DMA descriptors full -// AMAZON_TPE_EMSG("AAL5 packet drop due to DMA nwrite:%u skb->len:%u\n", nwrite,len); - AMAZON_TPE_DMSG("AAL5 packet drop due to DMA nwrite:%u skb->len:%u\n", nwrite,len); - err = -EAGAIN; - goto atm_dma_tx_drop_exit; - } - AMAZON_TPE_DMSG("just finish call dma_write\n"); - //release in the "dma done" call-back - return 0; -atm_dma_tx_error_exit: - g_atm_dev.mib_counter.tx_err++; - queue_statics(qid, QS_ERR); - goto atm_dma_tx_exit; - -atm_dma_tx_drop_exit: - g_atm_dev.mib_counter.tx_drop++; - queue_statics(qid, QS_SW_DROP); -atm_dma_tx_exit: - if (need_pop){ - amazon_atm_free_tx_skb(skb); - }else{ - dev_kfree_skb_any(skb); - } - return err; -} - -/* Brief: Send AAL0/AAL5 packet - * Parameters: atm_vcc - Pointer to VCC data structure - * skb - Pointer to sk_buff structure, that contains the data - * Return: 0 - sucessful - * -ENOMEM - No memory available - * -EINVAL - Not supported - * Description: - * See amazon_atm_dma_tx - */ -int amazon_atm_send(struct atm_vcc *vcc,struct sk_buff *skb) -{ - int qid=0; - u8 clp=0; - int err=0; - u32 wm=0; - - if (vcc == NULL || skb == NULL){ - AMAZON_TPE_EMSG("invalid parameter\n"); - return -EINVAL; - } - ATM_SKB(skb)->vcc = vcc; - qid = amazon_atm_get_queue(vcc); - if (valid_qid(qid) != 1) { - AMAZON_TPE_EMSG("invalid vcc!\n"); - err = -EINVAL; - goto atm_send_err_exit; - } - - //Send AAL0 using SWIN - if (vcc->qos.aal == ATM_AAL0){ -#ifdef TPE_LOOPBACK - err=amazon_atm_swin((qid+CBM_RX_OFFSET), skb->data); -#else - err=amazon_atm_swin(qid, skb->data); -#endif - if (err){ - goto atm_send_err_exit; - } - goto atm_send_exit; - } - - //Should be AAl5 - //MIB counter - g_atm_dev.mib_counter.tx++; - adsl_led_flash();//joelin adsl led - queue_statics(qid, QS_PKT); - -#ifdef AMAZON_CHECK_LINK - //check adsl link - if (adsl_link_status == 0){ - //link down - AMAZON_TPE_DMSG("ADSL link down, discarded!\n"); - err=-EFAULT; - goto atm_send_drop_exit; - } -#endif - clp = (vcc->atm_options&ATM_ATMOPT_CLP)?1:0; - //check watermark first - wm = readl(CBM_WMSTAT0_ADDR); - if ( (wm & (1<qos.txtp.traffic_class != ATM_CBR - &&vcc->qos.txtp.traffic_class != ATM_VBR_RT) - &(wm & (CBM_WM_NRT_MASK | (clp&CBM_WM_CLP1_MASK)) ))){ - //wm hit: discard - AMAZON_TPE_DMSG("watermark hit, discarded!\n"); - err=-EFAULT; - goto atm_send_drop_exit; - } -#ifdef TPE_LOOPBACK - return amazon_atm_dma_tx(vcc->vpi, vcc->vci,clp, (qid+CBM_RX_OFFSET),skb); -#else - return amazon_atm_dma_tx(vcc->vpi, vcc->vci,clp, qid,skb); -#endif - -atm_send_exit: - amazon_atm_free_tx_skb_vcc(vcc,skb); - return 0; - -atm_send_drop_exit: - g_atm_dev.mib_counter.tx_drop++; - queue_statics(qid,QS_SW_DROP); -atm_send_err_exit: - amazon_atm_free_tx_skb_vcc(vcc,skb); - return err; -} - -/* Brief: Return ATM port related MIB - * Parameter: interface number - atm_cell_ifEntry_t - */ -int amazon_atm_cell_mib(atm_cell_ifEntry_t* to,u32 itf) -{ - g_atm_dev.mib_counter.htu_unp += readl(HTU_MIBCIUP); - to->ifInUnknownProtos = g_atm_dev.mib_counter.htu_unp; -#ifdef AMAZON_TPE_READ_ARC - u32 reg_val=0; - meiDebugRead((AR_CELL0_ADDR+itf*4),®_val,1); - g_atm_dev.mib_counter.rx_cells += reg_val; - reg_val=0; - meiDebugWrite((AR_CELL0_ADDR+itf*4),®_val,1); - to->ifHCInOctets_h = (g_atm_dev.mib_counter.rx_cells * 53)>>32; - to->ifHCInOctets_l = (g_atm_dev.mib_counter.rx_cells * 53) & 0xffff; - - meiDebugRead((AT_CELL0_ADDR+itf*4),®_val,1); - g_atm_dev.mib_counter.tx_cells += reg_val; - reg_val=0; - meiDebugWrite((AT_CELL0_ADDR+itf*4),®_val,1); - to->ifHCOutOctets_h = (g_atm_dev.mib_counter.tx_cells * 53)>>32; - to->ifHCOutOctets_l = (g_atm_dev.mib_counter.rx_cells * 53) & 0xffff; - - meiDebugRead((AR_CD_CNT0_ADDR+itf*4),®_val,1); - g_atm_dev.mib_counter.rx_err_cells += reg_val; - reg_val=0; - meiDebugWrite((AR_CD_CNT0_ADDR+itf*4),®_val,1); - to->ifInErrors = g_atm_dev.mib_counter.rx_err_cells; - - to->ifOutErrors = 0; -#else - to->ifHCInOctets_h = 0; - to->ifHCInOctets_l = 0; - to->ifHCOutOctets_h = 0; - to->ifHCOutOctets_l = 0; - to->ifInErrors = 0; - to->ifOutErrors = 0; -#endif - return 0; -} - -/* Brief: Return ATM AAL5 related MIB - * Parameter: - atm_aal5_ifEntry_t - */ -int amazon_atm_aal5_mib(atm_aal5_ifEntry_t* to) -{ - u32 reg_l,reg_h; - //AAL5R received Octets from ATM - reg_l = readl(AAL5_RIOL_ADDR); - reg_h = readl(AAL5_RIOM_ADDR); - g_atm_dev.mib_counter.rx_cnt_h +=reg_h; - if (reg_l + g_atm_dev.mib_counter.rx_cnt_l < reg_l){ - g_atm_dev.mib_counter.rx_cnt_h++; - } - - g_atm_dev.mib_counter.rx_cnt_l+= reg_l; - //AAL5S sent Octets to ATM - reg_l = readl(AAL5_SOOL_ADDR); - reg_h = readl(AAL5_SOOM_ADDR); - g_atm_dev.mib_counter.tx_cnt_h +=reg_h; - if (reg_l + g_atm_dev.mib_counter.tx_cnt_l < reg_l){ - g_atm_dev.mib_counter.tx_cnt_h++; - } - g_atm_dev.mib_counter.tx_cnt_l+= reg_l; - - - g_atm_dev.mib_counter.tx_ppd += readl(CBM_AAL5ODIS_ADDR); - g_atm_dev.mib_counter.rx_drop += readl(CBM_AAL5IDIS_ADDR); - - //store - to->ifHCInOctets_h = g_atm_dev.mib_counter.rx_cnt_h; - to->ifHCInOctets_l = g_atm_dev.mib_counter.rx_cnt_l; - to->ifHCOutOctets_h = g_atm_dev.mib_counter.tx_cnt_h; - to->ifHCOutOctets_l = g_atm_dev.mib_counter.tx_cnt_l; - to->ifOutDiscards = g_atm_dev.mib_counter.tx_drop; - to->ifInDiscards = g_atm_dev.mib_counter.rx_drop; - - //Software provided counters - //packets passed to higher layer - to->ifInUcastPkts = g_atm_dev.mib_counter.rx; - //packets passed from higher layer - to->ifOutUcastPkts = g_atm_dev.mib_counter.tx; - //number of wrong downstream packets - to->ifInErrors = g_atm_dev.mib_counter.rx_err; - //number of wrong upstream packets - to->ifOutErros = g_atm_dev.mib_counter.tx_err; - - return 0; -} -/* Brief: Return ATM AAL5 VCC related MIB from internale use - * Parameter: - * qid - * atm_aal5_vcc_t - */ -static int __amazon_atm_vcc_mib(int qid, atm_aal5_vcc_t* to) -{ - //aal5VccCrcErrors - to->aal5VccCrcErrors = g_atm_dev.queues[qid].aal5VccCrcErrors; - to->aal5VccOverSizedSDUs =g_atm_dev.queues[qid].aal5VccOverSizedSDUs; - to->aal5VccSarTimeOuts = 0; //not supported yet - return 0; -} -/* Brief: Return ATM AAL5 VCC related MIB from vpi/vci - * Parameter: atm_vcc - * atm_aal5_vcc_t - */ -int amazon_atm_vcc_mib_x(int vpi, int vci,atm_aal5_vcc_t* to) -{ - int qid=0; - int err=0; - qid = amazon_atm_find_vpivci(vpi, vci); - if (qid >0 ){ - err = __amazon_atm_vcc_mib(qid,to); - }else{ - return -EINVAL; - } - return err; -} - - -/* Brief: Return ATM AAL5 VCC related MIB - * Parameter: atm_vcc - * atm_aal5_vcc_t - */ -int amazon_atm_vcc_mib(struct atm_vcc *vcc,atm_aal5_vcc_t* to) -{ - int qid=0; - int err=0; - qid = amazon_atm_get_queue(vcc); - if (qid >0 ){ - err = __amazon_atm_vcc_mib(qid,to); - }else{ - return -EINVAL; - } - return err; -} - -/* Brief: Close ATM connection - * Parameters: atm_vcc - Pointer to VCC data structure - * Return: no - * Description: - * This function closes the given ATM connection - */ -void amazon_atm_close(struct atm_vcc *vcc){ - int i; - int qid=0; - u32 tmp1; - u8 * qd_addr; - unsigned long flags; - if (vcc == NULL){ - AMAZON_TPE_EMSG("invalid parameter. vcc is null\n"); - return; - } - u32 itf = (u32) vcc->itf; - //release bandwidth - if (vcc->qos.txtp.traffic_class == ATM_CBR){ - g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.max_pcr; - g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.max_pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_VBR_RT){ - g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.max_pcr; - g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.max_pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_VBR_NRT){ - g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.pcr; - g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.pcr; - }else if (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS){ - g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.min_pcr; - g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.min_pcr; - } - - qid = amazon_atm_get_queue(vcc); - if (qid == -EINVAL){ - AMAZON_TPE_EMSG("unknown vcc %u.%u.%u\n", vcc->itf, vcc->vpi, vcc->vci); - return; - } - local_irq_save(flags); - //Disable HTU entry - i=0; - while ((tmp1 = readl(HTU_RAMSTAT_ADDR))!=0 && i < HTU_RAM_ACCESS_MAX) i++; - if (i == HTU_RAM_ACCESS_MAX){ - AMAZON_TPE_EMSG("HTU RAM ACCESS out of time\n"); - } - - // write address register - AMAZON_WRITE_REGISTER_L(qid - CBM_DEFAULT_Q_OFFSET, HTU_RAMADDR_ADDR); - // invalidate the connection - AMAZON_WRITE_REGISTER_L(0, HTU_RAMDAT1_ADDR); - // write command - AMAZON_WRITE_REGISTER_L(HTU_RAMCMD_WR,HTU_RAMCMD_ADDR); - - qd_addr = (u8 *) KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr); -#ifdef AMAZON_ATM_DEBUG - tmp1 = readl(qd_addr+qid*CBM_QD_SIZE+0x8) & 0xffff; - AMAZON_TPE_DMSG("TX queue has %u cells \n", tmp1); - tmp1 = readl( qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE+0x08)&0xffff; - AMAZON_TPE_DMSG("RX queue has %u cells \n", tmp1); -#endif - // set threshold of txqueue to 0 - tmp1 = readl(qd_addr+qid*CBM_QD_SIZE+0x0c); - tmp1&= (~ CBM_QD_W3_THRESHOLD_MASK); - AMAZON_WRITE_REGISTER_L(tmp1, (qd_addr+qid*CBM_QD_SIZE+0x0c)); - // set threshold of rxqueue to 0 - tmp1 = readl( qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE+0x0c); - tmp1&= (~ CBM_QD_W3_THRESHOLD_MASK); - AMAZON_WRITE_REGISTER_L(tmp1,(qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE+0x0c)); - - //clear internal mapping - amazon_atm_clear_vcc(qid); - amazon_atm_clear_vcc(qid+CBM_RX_OFFSET); - - local_irq_restore(flags); -} - - -/* Brief: initialize internal data structure - */ -static void atm_constructor(amazon_atm_dev_t * dev) -{ - int i; - memset(dev,0,sizeof(amazon_atm_dev_t)); - atm_init_parameters(dev); - //internal: queue "free" flag - for(i=1;iqueues[i].vcc=NULL; - dev->queues[i].free = 1; - } - for(i=0;iports[i].tx_rem_cr = dev->ports[i].tx_max_cr; - } - //MIB - atomic_set(&dev->dma_tx_free_0,1); //initially there should be free descriptors -} - -/* Brief: return round up base-2 logarithm - */ -static inline int get_log_2(u32 value) -{ - int i=0,j=1; - while (i<11){ - if (j>=value) break; - j=j<<1; - i++; - } - AMAZON_TPE_DMSG("round up base-2 logarithm of %u is %u\n", value, i); - return i; -} - -/* Brief: TPE hardware initialization - * Parameter: specifiy the configurations of the hardware - */ -static inline int atm_init_hard(amazon_atm_dev_t * dev) -{ - int i; - u32 tmp1, tmp2, tmp3; - u8 * mem_addr=NULL; - u8 * qd_addr=NULL; - //PMU power on the module 1st - *(AMAZON_PMU_PWDCR) = (*AMAZON_PMU_PWDCR) | (AMAZON_PMU_PWDCR_TPE); - //Reset the module - *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) | (AMAZON_RST_REQ_TPE); - mb(); - mdelay(100); - *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) & (~(AMAZON_RST_REQ_TPE)); - mb(); - - unsigned long qsb_clk = amazon_get_fpi_hz()>>1; - /*********allocate & arrange memory for CBM *********/ - if (dev->cbm.mem_addr == NULL){ - dev->cbm.allocated = 1; - mem_addr = (u8 *)__get_free_pages(GFP_KERNEL, get_log_2(((CBM_CELL_SIZE * dev->cbm.free_cell_cnt) >>PAGE_SHIFT) + 1)); - if (mem_addr != NULL){ - dev->cbm.mem_addr = mem_addr; - } else { - goto init_no_mem; - } - } - if (dev->cbm.qd_addr == NULL){ -#ifdef CONFIG_USE_VENUS - //to work around a bug, bit15 of QDOFF address should be 1,Aug4, 2004 - //thus, we allocate 64k memory - qd_addr = (u8 *)__get_free_pages(GFP_KERNEL, 4); - if (qd_addr != NULL) { - dev->cbm.qd_addr_free = (u8*) (((unsigned long) qd_addr)); - dev->cbm.qd_addr = (u8*) (((unsigned long) qd_addr) | 0x8000); - }else{ - goto init_no_mem; - } -#else //CONFIG_USE_VENUS - qd_addr = (u8 *)kmalloc( CBM_QD_SIZE * AMAZON_ATM_MAX_QUEUE_NUM, GFP_KERNEL); - if (qd_addr != NULL) { - dev->cbm.qd_addr = qd_addr; - }else { - goto init_no_mem; - } -#endif //CONFIG_USE_VENUS - } -//#ifndef CONFIG_MIPS_UNCACHED - mem_addr = (u8 *)KSEG1ADDR((unsigned long)dev->cbm.mem_addr); - qd_addr = (u8 *)KSEG1ADDR((unsigned long)dev->cbm.qd_addr); -//#endif - //CBM reset cell queue memory, 64 bytes / cell - memset_io(mem_addr, 0, CBM_CELL_SIZE * dev->cbm.free_cell_cnt); - //make a link list, last 4 bytes is pointer - for(i=1;icbm.free_cell_cnt;i++){ - AMAZON_WRITE_REGISTER_L(CPHYSADDR((mem_addr + CBM_CELL_SIZE * i)),(mem_addr + CBM_CELL_SIZE * (i-1) + 0x3c)); - } - //reset queue descriptor - memset_io(qd_addr, 0, CBM_QD_SIZE * AMAZON_ATM_MAX_QUEUE_NUM); - //init word 0-2 of q0 (free cell list) - //address of last cell - AMAZON_WRITE_REGISTER_L(CPHYSADDR((mem_addr + CBM_CELL_SIZE * (dev->cbm.free_cell_cnt-1))), qd_addr); - //address of first cell - AMAZON_WRITE_REGISTER_L(CPHYSADDR((mem_addr)), (qd_addr + 4)); - //no. of free cells - AMAZON_WRITE_REGISTER_L(dev->cbm.free_cell_cnt,(qd_addr + 8)); - //init q descriptor for OAM receiving - AMAZON_WRITE_REGISTER_L((CBM_QD_W3_INT_ACA | (divide_by_64_round_up(oam_q_threshold)&0xff)<< CBM_QD_W3_THRESHOLD_SHIFT), (qd_addr + AMAZON_ATM_OAM_Q_ID * CBM_QD_SIZE + 0x0c)); -// AMAZON_WRITE_REGISTER_L((CBM_QD_W3_INT_ACA | (u32)oam_q_threshold<< CBM_QD_W3_THRESHOLD_SHIFT), (qd_addr + AMAZON_ATM_OAM_Q_ID * CBM_QD_SIZE + 0x0c)); - //config CBM - //set offset address and threshold - AMAZON_WRITE_REGISTER_L(CPHYSADDR(qd_addr), CBM_QDOFF_ADDR); - AMAZON_WRITE_REGISTER_L(((dev->cbm.nrt_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_NRTTHR_ADDR); - AMAZON_WRITE_REGISTER_L(((dev->cbm.clp0_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_CLP0THR_ADDR); - AMAZON_WRITE_REGISTER_L(((dev->cbm.clp1_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_CLP1THR_ADDR); - //config interrupts - AMAZON_WRITE_REGISTER_L( CBM_IMR_MASK & (~(CBM_IMR_ACA|CBM_IMR_Q0E|CBM_IMR_Q0I|CBM_IMR_RDE|CBM_IMR_OPF|CBM_IMR_ERR -#ifdef AMAZON_ATM_DEBUG - |CBM_IMR_DISC|CBM_IMR_QFD|CBM_IMR_NFCA|CBM_IMR_CLP1TR|CBM_IMR_CLP0TR|CBM_IMR_NRTTR|CBM_IMR_QTR -#endif -#ifdef AMAZON_TPE_SCR - |CBM_IMR_EF -#endif - )), CBM_IMR0_ADDR); - AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_CBM_INT, CBM_SRC0_ADDR); - - //HTU - //RAM entry for number of possible connections per interface - tmp1 = dev->ports[0].max_conn?dev->ports[0].max_conn-1:0; - AMAZON_WRITE_REGISTER_L(tmp1, HTU_RX0_ADDR); - for(i=1;iports[i].max_conn; - AMAZON_WRITE_REGISTER_L(tmp1, HTU_RX0_ADDR + 4 * i); - } - dev->cbm.max_q_off = tmp1+1; - //Queue ID for OAM/RM/Other cells - AMAZON_WRITE_REGISTER_L (AMAZON_ATM_OAM_Q_ID, HTU_DESTOAM_ADDR); - AMAZON_WRITE_REGISTER_L( AMAZON_ATM_RM_Q_ID, HTU_DESTRM_ADDR); - AMAZON_WRITE_REGISTER_L( AMAZON_ATM_OTHER_Q_ID, HTU_DESTOTHER_ADDR); - //Timeout - AMAZON_WRITE_REGISTER_L((u32) HTUTIMEOUT, HTU_TIMEOUT_ADDR); -#ifdef AMAZON_ATM_DEBUG - AMAZON_WRITE_REGISTER_L((u32) HTU_ISR_MASK - &(~(HTU_ISR_NE|HTU_ISR_TORD|HTU_ISR_OTOC|HTU_ISR_ONEC|HTU_ISR_PNE|HTU_ISR_PT)), HTU_IMR0_ADDR); - AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS|SRC_SRE_ENABLE|AMAZON_HTU_INT,HTU_SRC0_ADDR); -#endif - //QSB - //global setting, TstepC, SBL, Tau - //Tau - AMAZON_WRITE_REGISTER_L(dev->qsb.tau, QSB_TAU_ADDR); - //SBL - AMAZON_WRITE_REGISTER_L(dev->qsb.sbl, QSB_SBL_ADDR); - //tstep - AMAZON_WRITE_REGISTER_L(dev->qsb.tstepc>>1, QSB_CONFIG_ADDR); - - //port settting - for(i=0;iports[i].enable) && (dev->ports[i].tx_max_cr!=0) ){ - tmp1 = ((qsb_clk * dev->qsb.tstepc) >>1) / dev->ports[i].tx_max_cr; - tmp2 = tmp1 / 64; //integer value of Tsb - tmp3 = tmp1%64 + 1; //fractional part of Tsb - //carry over to integer part (?) - if (tmp3 == 64) { - tmp3 = 0; - tmp2++; - } - if (tmp2 == 0){ - tmp2 = 1; - tmp3 = 1; - } - //1. set mask 2. write value to data transfer register 3. start the transfer - //SCT(FracRate) - AMAZON_WRITE_REGISTER_L(QSB_SET_SCT_MASK, QSB_RTM_ADDR); - AMAZON_WRITE_REGISTER_L(tmp3,QSB_RTD_ADDR); - AMAZON_WRITE_REGISTER_L(((QSB_TABLESEL_SCT<aal5.tx_max_sdu,AAL5_SMFL_ADDR); - AMAZON_WRITE_REGISTER_L(dev->aal5.rx_max_sdu,AAL5_RMFL_ADDR); - AMAZON_WRITE_REGISTER_L(AAL5_SCMD_MODE_POLL // enable polling mode - |AAL5_SCMD_SS - |AAL5_SCMD_AR - ,AAL5_SCMD_ADDR); - //start CBM - AMAZON_WRITE_REGISTER_L(CBM_CFG_START,CBM_CFG_ADDR); - wmb(); - return 0; -init_no_mem: - if (mem_addr != NULL) free_pages((unsigned long)mem_addr,get_log_2(((CBM_CELL_SIZE * dev->cbm.free_cell_cnt) >>PAGE_SHIFT) + 1)); - -#ifdef CONFIG_USE_VENUS - //to work around a bug, bit15 of QDOFF address should be 1 - if (qd_addr != NULL) free_pages((unsigned long)qd_addr,4); -#else //CONFIG_USE_VENUS - if (qd_addr != NULL) kfree(qd_addr); -#endif //CONFIG_USE_VENUS - return -ENOMEM; -} - -/* - * Brief: Create entry in /proc for status information - */ -void atm_create_proc(void) -{ - create_proc_read_entry("amazon_atm", 0,NULL, amazon_atm_read_procmem,(void*)PROC_ATM); - create_proc_read_entry("amazon_atm_mib", 0,NULL, amazon_atm_read_procmem,(void*)PROC_MIB); - create_proc_read_entry("amazon_atm_vcc", 0,NULL, amazon_atm_read_procmem,(void*)PROC_VCC); -#if 0 - create_proc_read_entry("amazon_atm_aal5", 0,NULL, amazon_atm_read_procmem,(void*)PROC_AAL5); - create_proc_read_entry("amazon_atm_cbm", 0,NULL, amazon_atm_read_procmem,(void*)PROC_CBM); - create_proc_read_entry("amazon_atm_htu", 0,NULL, amazon_atm_read_procmem,(void*)PROC_HTU); - create_proc_read_entry("amazon_atm_qsb", 0,NULL, amazon_atm_read_procmem,(void*)PROC_QSB); - create_proc_read_entry("amazon_atm_swie", 0,NULL, amazon_atm_read_procmem,(void*)PROC_SWIE); -#endif -} - -/* - * Brief: Delete entry in /proc for status information - */ -void atm_delete_proc(void) -{ - remove_proc_entry("amazon_atm", NULL); - remove_proc_entry("amazon_atm_mib", NULL); - remove_proc_entry("amazon_atm_vcc", NULL); -#if 0 - remove_proc_entry("amazon_atm_aal5", NULL); - remove_proc_entry("amazon_atm_cbm", NULL); - remove_proc_entry("amazon_atm_htu", NULL); - remove_proc_entry("amazon_atm_qsb", NULL); - remove_proc_entry("amazon_atm_swie", NULL); -#endif -} -/* Brief: Initialize ATM module - * Parameters: no - * Return: &g_atm_dev - sucessful - * NULL - fails: - * 1. invalid parameter - * 2. No memory available - * Description: - * This function configure the TPE components according to the input info, - * -CBM - * -HTU - * -QSB - * -AAL5 - * - */ -amazon_atm_dev_t * amazon_atm_create(void) -{ - int i; - AMAZON_TPE_DMSG("atm_init\n"); - /************initialize global data structure****************/ - atm_constructor(&g_atm_dev); - /***********allocate kernel resources****************/ - //bottom halfs for SWEX - swex_start_task.routine = amazon_atm_swex; - swex_start_task.data = NULL; - swex_complete_task.routine = amazon_atm_swex_push; - swex_complete_task.data = NULL; -#ifdef AMAZON_TPE_SCR - a5r_task.routine = amazon_atm_a5r; - a5r_task.data = NULL; -#endif //AMAZON_TPE_SCR - //SWIN semaphore - sema_init(&(g_atm_dev.swie.in_sem), 1); - //SWIE lock - clear_bit(SWIE_LOCK, &(g_atm_dev.swie.lock)); - //SWIE wait queue - init_waitqueue_head(&(g_atm_dev.swie.sleep)); - atm_create_proc(); - - //register DMA - memset(&g_dma_dev,0,sizeof(struct dma_device_info)); - strcpy(g_dma_dev.device_name,"TPE"); - g_dma_dev.weight=1; - g_dma_dev.num_tx_chan=2; - g_dma_dev.num_rx_chan=2; - g_dma_dev.ack=1; - g_dma_dev.tx_burst_len=4; - g_dma_dev.rx_burst_len=4; - //DMA TX - - for(i=0;i<1;i++){ - g_dma_dev.tx_chan[i].weight=QOS_DEFAULT_WGT; - g_dma_dev.tx_chan[i].desc_num=10; - g_dma_dev.tx_chan[i].packet_size=g_atm_dev.aal5.tx_max_sdu + AAL5S_INBOUND_HEADER; - g_dma_dev.tx_chan[i].control=1; - } - //DMA RX - for(i=0;i<2;i++){ - g_dma_dev.rx_chan[i].weight=QOS_DEFAULT_WGT; - /* BingTao's suggestion, change from 5->10 will prevent packet loss in NO_TX_INT mode */ - g_dma_dev.rx_chan[i].desc_num=10; - g_dma_dev.rx_chan[i].packet_size=(g_atm_dev.aal5.rx_max_sdu + AAL5R_TRAILER_LEN+0x10f)&(~0xf); - g_dma_dev.rx_chan[i].control=1; - } - g_dma_dev.intr_handler=amazon_atm_dma_handler; - g_dma_dev.buffer_alloc=amazon_atm_alloc_rx; - g_dma_dev.buffer_free=amazon_atm_free_tx; - dma_device_register(&g_dma_dev); -/***********intialize the atm hardware ****************/ - if ( atm_init_hard(&g_atm_dev) != 0){ - return NULL; - } - //start CBM - AMAZON_WRITE_REGISTER_L(CBM_CFG_START,CBM_CFG_ADDR); - wmb(); - - //Start HTU - AMAZON_WRITE_REGISTER_L(HTU_CFG_START ,HTU_CFG_ADDR); - wmb(); - - - // Register interrupts for insertion and extraction - request_irq(AMAZON_SWIE_INT, amazon_atm_swie_isr, IRQF_DISABLED, "tpe_swie", NULL); - request_irq(AMAZON_CBM_INT, amazon_atm_cbm_isr, IRQF_DISABLED, "tpe_cbm", NULL); -#ifdef AMAZON_ATM_DEBUG - request_irq(AMAZON_HTU_INT , amazon_atm_htu_isr, IRQF_DISABLED, "tpe_htu", NULL); -#endif -#ifdef AMAZON_TPE_TEST_AAL5_INT - request_irq(AMAZON_AAL5_INT, amazon_atm_aal5_isr, IRQF_DISABLED, "tpe_aal5", NULL); -#endif - return &g_atm_dev; -} - -/* Brief: clean up atm - * Parameters: no - * Return: no - * Description: - * Disable the device. - */ -void amazon_atm_cleanup(void){ - int i; - clear_bit(SWIE_LOCK, &(g_atm_dev.swie.lock)); - wake_up(&g_atm_dev.swie.sleep); - up(&g_atm_dev.swie.in_sem); - // diable SWIE interrupts - AMAZON_WRITE_REGISTER_L(0, SWIE_ISRC_ADDR); - AMAZON_WRITE_REGISTER_L(0, SWIE_ESRC_ADDR); - wmb(); - - // Disable schedulers ( including interrupts )----------------------- - for (i = 0; i < AMAZON_ATM_PORT_NUM; i++); - { - AMAZON_WRITE_REGISTER_L(QSB_SET_SPT_SBVALID_MASK, QSB_RTM_ADDR); - AMAZON_WRITE_REGISTER_L( 0 ,QSB_RTD_ADDR); - AMAZON_WRITE_REGISTER_L( (QSB_TABLESEL_SPT<>PAGE_SHIFT)+1)); -#ifdef CONFIG_USE_VENUS - //to work around a bug, bit15 of QDOFF address should be 1 - free_pages((unsigned long)g_atm_dev.cbm.qd_addr_free,4); -#else //CONFIG_USE_VENUS - kfree(g_atm_dev.cbm.qd_addr); -#endif //CONFIG_USE_VENUS - } - atm_delete_proc(); - // free interrupts for insertion and extraction - dma_device_unregister(&g_dma_dev); - free_irq(AMAZON_SWIE_INT, NULL); - free_irq(AMAZON_CBM_INT, NULL); -#ifdef AMAZON_ATM_DEBUG - free_irq(AMAZON_HTU_INT, NULL); -#endif -#ifdef AMAZON_TPE_TEST_AAL5_INT - free_irq(AMAZON_AAL5_INT, NULL); -#endif - -} - -/************************ ATM network interface ***********************************************/ -/* Brief: getsockopt - */ -int amazon_atm_getsockopt(struct atm_vcc *vcc, int level, int optname, char *optval, int optlen) -{ - int err=0; - atm_aal5_vcc_t mib_vcc; - AMAZON_TPE_DMSG("1\n"); - switch (optname){ - case SO_AMAZON_ATM_MIB_VCC: - AMAZON_TPE_DMSG("2\n"); - err = amazon_atm_vcc_mib(vcc, &mib_vcc); - AMAZON_TPE_DMSG("%u\n",mib_vcc.aal5VccCrcErrors); - err = copy_to_user((void *)optval,&mib_vcc, sizeof(mib_vcc)); - AMAZON_TPE_DMSG("err %u\n",err); - break; - default: - return -EFAULT; - } - return err; -} - -/* Brief: IOCTL - */ - -int amazon_atm_ioctl(struct atm_dev *dev,unsigned int cmd,void *arg) -{ - int err=0; - //MIB - atm_cell_ifEntry_t mib_cell; - atm_aal5_ifEntry_t mib_aal5; - atm_aal5_vcc_x_t mib_vcc; - if (_IOC_TYPE(cmd) != AMAZON_ATM_IOC_MAGIC) return -ENOTTY; - if (_IOC_NR(cmd) > AMAZON_ATM_IOC_MAXNR) return -ENOTTY; - - if (_IOC_DIR(cmd) & _IOC_READ) - err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd)); - else if (_IOC_DIR(cmd) & _IOC_WRITE) - err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd)); - if (err) { - AMAZON_TPE_EMSG("acess verification fails \n"); - return -EFAULT; - } - switch(cmd) { - case AMAZON_ATM_MIB_CELL: - err = amazon_atm_cell_mib(&mib_cell,(u32)arg); - if (err==0){ - err = __copy_to_user((void *)arg,&mib_cell,sizeof(mib_cell)); - }else{ - AMAZON_TPE_EMSG("cannot get MIB ATM_CELL\n"); - } - break; - case AMAZON_ATM_MIB_AAL5: - err = amazon_atm_aal5_mib(&mib_aal5); - if (err==0){ - err=__copy_to_user(arg, &mib_aal5, sizeof(mib_aal5)); - }else{ - AMAZON_TPE_EMSG("cannot get MIB ATM_AAL5\n"); - } - break; - case AMAZON_ATM_MIB_VCC: - err=__copy_from_user(&mib_vcc,arg, sizeof(mib_vcc)); - AMAZON_TPE_DMSG("return of copy_from_user %x\n",err); - err = amazon_atm_vcc_mib_x(mib_vcc.vpi, mib_vcc.vci, &(mib_vcc.mib_vcc)); - if (err==0){ - err=__copy_to_user(arg, &mib_vcc, sizeof(mib_vcc)); - }else{ - AMAZON_TPE_EMSG("cannot get MIB ATM_VCC\n"); - } - - default: - return -ENOTTY; - } - return err; -} -/* Brief: return a link list of OAM related time stamp info - * Parameter: none - * Return: - a link list of "struct oam_last_activity" data - * Description: - Each time, a F4/F5 cell or AAL5 packet is received, the time stamp is updated. - Through this call, u get a list of this time stamp for all active connection. - Please note that u have read-only access. - */ -const struct oam_last_activity* get_oam_time_stamp() -{ - int i,j; - for(i=CBM_DEFAULT_Q_OFFSET+CBM_RX_OFFSET,j=0;ivpi; - g_oam_time_stamp[j].vci = g_atm_dev.queues[i].vcc->vci; - g_oam_time_stamp[j].stamp = g_atm_dev.queues[i].access_time; - g_oam_time_stamp[j].next = NULL; - j++; - } - } - if (j==0) { - return NULL; - }else{ - return g_oam_time_stamp; - } -} - - -/* Brief: call back routine for rx - * Parameter: - * vcc atm_vcc pointer - * skb data if no error - err error flag, 0: no error, 1:error - * Return: - * 0 - * <>0 cannot push up - * Description: - * release the packet if cannot push up - */ -static int amazon_atm_net_push(struct atm_vcc *vcc,struct sk_buff *skb, int err) -{ - if (err){ - if (vcc && vcc->stats) { - atomic_inc(&vcc->stats->rx_err); - } - }else{ - ATM_SKB(skb)->vcc = vcc; - - if (!atm_charge(vcc, skb->truesize)){ - //no space this vcc - AMAZON_TPE_EMSG("no space for this vcc\n"); - dev_kfree_skb_any(skb); - return -ENOMEM; - } - atomic_inc(&vcc->stats->rx); - AMAZON_TPE_DMSG("push to vcc\n"); - vcc->push(vcc,skb); - } - return 0; -} -int amazon_atm_net_send_oam(struct atm_vcc*vcc, void *cell, int flags) -{ - return amazon_atm_send_oam(vcc,cell,flags); -} - -int amazon_atm_net_send(struct atm_vcc *vcc,struct sk_buff *skb) -{ - int err=0; - if (vcc->qos.aal == ATM_AAL0 || vcc->qos.aal == ATM_AAL5) { - err=amazon_atm_send(vcc,skb); - }else{ - //not supported - err = -EPROTONOSUPPORT; - } - if (err){ - atomic_inc(&vcc->stats->tx_err); - }else{ - atomic_inc(&vcc->stats->tx); - } - AMAZON_TPE_DMSG("sent, tx_inuse:%u\n", atomic_read(&vcc->tx_inuse)); - return err; -} - -int amazon_atm_net_open(struct atm_vcc *vcc,short vpi, int vci) -{ - vcc->itf = (int) vcc->dev->dev_data; - vcc->vpi = vpi; - vcc->vci = vci; - return(amazon_atm_open(vcc,amazon_atm_net_push)); -} - -static int amazon_atm_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flgs) -{ - int qid; - - if (vcc == NULL || qos == NULL){ - AMAZON_TPE_EMSG("invalid parameters\n"); - return -EINVAL; - } - qid = amazon_atm_get_queue(vcc); - if (valid_qid(qid) != 1) { - AMAZON_TPE_EMSG("no vcc connection opened\n"); - return -EINVAL; - } - set_qsb(vcc,qos,qid); - return 0; -} - -static struct atmdev_ops amazon_atm_ops = { - open: amazon_atm_net_open, - close: amazon_atm_close, - ioctl: amazon_atm_ioctl, - send: amazon_atm_net_send, - send_oam: amazon_atm_net_send_oam, -// getsockopt: amazon_atm_getsockopt, - change_qos: amazon_atm_change_qos, -// proc_read: amazon_atm_proc_read, - owner: THIS_MODULE, -}; // ATM device callback functions - -/* - * brief "/proc" function - */ -int amazon_atm_read_procmem(char *buf, char **start, off_t offset,int count, int *eof, void *data) -{ - int buf_off=0; /* for buf */ - int i=0,j=0; - int type= (u32)data;//which module - atm_aal5_ifEntry_t mib_aal5; - atm_cell_ifEntry_t mib_cell; - atm_aal5_vcc_t mib_vcc; - switch(type){ - case PROC_MIB: - //MIB counter - amazon_atm_aal5_mib(&mib_aal5); - //TX: - buf_off+=sprintf(buf+buf_off,"\n============= AAL5 Upstream =========\n"); - buf_off+=sprintf(buf+buf_off,"received %u (pkts) from upper layer\n", mib_aal5.ifOutUcastPkts); - buf_off+=sprintf(buf+buf_off,"errors: %u (pkts)\n",mib_aal5.ifOutErros); - buf_off+=sprintf(buf+buf_off,"discards: %u (ptks)\n", mib_aal5.ifOutDiscards); - buf_off+=sprintf(buf+buf_off,"transmitted: %x-%x (bytes) \n", - mib_aal5.ifHCOutOctets_h, mib_aal5.ifHCOutOctets_l); - //RX: - buf_off+=sprintf(buf+buf_off,"\n============= AAL5 Downstream =========\n"); - buf_off+=sprintf(buf+buf_off,"received %x-%x (bytes)\n", - mib_aal5.ifHCInOctets_h,mib_aal5.ifHCInOctets_l); - buf_off+=sprintf(buf+buf_off,"discards: %u (ptks)\n",mib_aal5.ifInDiscards); - buf_off+=sprintf(buf+buf_off,"errors: %u (ptks)\n",mib_aal5.ifInErrors); - buf_off+=sprintf(buf+buf_off,"passed %u (ptks) to upper layer\n",mib_aal5.ifInUcastPkts); - - //Cell level - buf_off+=sprintf(buf+buf_off,"\n============= ATM Cell =========\n"); - amazon_atm_cell_mib(&mib_cell,0); -#ifdef AMAZON_TPE_READ_ARC - buf_off+=sprintf(buf+buf_off,"Port 0: downstream received: %x-%x (bytes)\n",mib_cell.ifHCInOctets_h,mib_cell.ifHCInOctets_l); - buf_off+=sprintf(buf+buf_off,"Port 0: upstream transmitted: %x-%x (bytes)\n",mib_cell.ifHCOutOctets_h,mib_cell.ifHCOutOctets_l); - buf_off+=sprintf(buf+buf_off,"Port 0: downstream errors: %u (cells)\n",mib_cell.ifInErrors); - amazon_atm_cell_mib(&mib_cell,1); - buf_off+=sprintf(buf+buf_off,"Port 1: downstream received: %x-%x (bytes)\n",mib_cell.ifHCInOctets_h,mib_cell.ifHCInOctets_l); - buf_off+=sprintf(buf+buf_off,"Port 1: upstream transmitted: %x-%x (bytes)\n",mib_cell.ifHCOutOctets_h,mib_cell.ifHCOutOctets_l); - buf_off+=sprintf(buf+buf_off,"Port 1: downstream errors: %u (cells)\n",mib_cell.ifInErrors); -#endif - buf_off+=sprintf(buf+buf_off,"HTU discards: %u (cells)\n",mib_cell.ifInUnknownProtos); - - buf_off+=sprintf(buf+buf_off,"\n====== Specials =====\n"); - buf_off+=sprintf(buf+buf_off,"AAL5S PPD: %u (cells)\n",g_atm_dev.mib_counter.tx_ppd); -#ifdef AMAZON_TPE_SCR - buf_off+=sprintf(buf+buf_off,"Reassembly wait: %u \n",g_a5r_wait); -#endif - break; - case PROC_ATM: - //Interface (Port) - buf_off+=sprintf(buf+buf_off,"[Interfaces]\n"); - for(i=0;ivpi - ,g_atm_dev.queues[i].vcc->vci - ,g_atm_dev.queues[i].vcc->itf - ,i - ,(u32)g_atm_dev.queues[i+CBM_RX_OFFSET].access_time.tv_sec - ,(u32)g_atm_dev.queues[i+CBM_RX_OFFSET].access_time.tv_usec - ); - buf_off+=sprintf(buf+buf_off,"\tqos_tx class=%u max_pcr=%u pcr=%u min_pcr=%u scr=%u mbs=%u cdv=%u\n" - ,g_atm_dev.queues[i].vcc->qos.txtp.traffic_class - ,g_atm_dev.queues[i].vcc->qos.txtp.max_pcr - ,g_atm_dev.queues[i].vcc->qos.txtp.pcr - ,g_atm_dev.queues[i].vcc->qos.txtp.min_pcr - ,g_atm_dev.queues[i].vcc->qos.txtp.scr - ,g_atm_dev.queues[i].vcc->qos.txtp.mbs - ,g_atm_dev.queues[i].vcc->qos.txtp.cdv - ); - buf_off+=sprintf(buf+buf_off,"\tqos_rx class=%u max_pcr=%u pcr=%u min_pcr=%u scr=%u mbs=%u cdv=%u\n" - ,g_atm_dev.queues[i].vcc->qos.rxtp.traffic_class - ,g_atm_dev.queues[i].vcc->qos.rxtp.max_pcr - ,g_atm_dev.queues[i].vcc->qos.rxtp.pcr - ,g_atm_dev.queues[i].vcc->qos.rxtp.min_pcr - ,g_atm_dev.queues[i].vcc->qos.rxtp.scr - ,g_atm_dev.queues[i].vcc->qos.rxtp.mbs - ,g_atm_dev.queues[i].vcc->qos.rxtp.cdv - ); - __amazon_atm_vcc_mib((i+CBM_RX_OFFSET),&mib_vcc); - buf_off+=sprintf(buf+buf_off,"\tCRC error=%u\n", mib_vcc.aal5VccCrcErrors); - buf_off+=sprintf(buf+buf_off,"\toversized packet=%u\n", mib_vcc.aal5VccOverSizedSDUs); -#ifdef AMAZON_ATM_DEBUG - if ( valid_qid(i+CBM_RX_OFFSET)){ - buf_off+=sprintf(buf+buf_off,"\tdownstream statics\n" ); - buf_off+=sprintf(buf+buf_off,"\t\tpackets=%u\n",g_atm_dev.queues[i+CBM_RX_OFFSET].qs[QS_PKT]); - buf_off+=sprintf(buf+buf_off,"\t\terr_packets=%u\n",g_atm_dev.queues[i+CBM_RX_OFFSET].qs[QS_ERR] ); - buf_off+=sprintf(buf+buf_off,"\t\tsw_dropped=%u\n",g_atm_dev.queues[i+CBM_RX_OFFSET].qs[QS_SW_DROP] ); - } - - buf_off+=sprintf(buf+buf_off,"\tupstream statics\n" ); - buf_off+=sprintf(buf+buf_off,"\t\tpackets=%u\n",g_atm_dev.queues[i].qs[QS_PKT]); - buf_off+=sprintf(buf+buf_off,"\t\terr_packets=%u\n",g_atm_dev.queues[i].qs[QS_ERR] ); - buf_off+=sprintf(buf+buf_off,"\t\thw_dropped=%u\n",g_atm_dev.queues[i].qs[QS_HW_DROP] ); - buf_off+=sprintf(buf+buf_off,"\t\tsw_dropped=%u\n",g_atm_dev.queues[i].qs[QS_SW_DROP] ); - -#endif - - } - - } - break; - default: - break; - } - if(buf_off>0) *eof = 1; - return buf_off; -} - -#ifdef AMAZON_TPE_AAL5_RECOVERY -extern int (*tpe_reset)(void); -extern int (*tpe_start)(void); -extern int (*tpe_inject)(void); -/* Brief: Reset TPE hardware - * Description - * This is a wordaround for AAL5 bug. It tries to reset TPE. - * take care of software - * setup all previous connection - */ -int amazon_tpe_reset(void) -{ - struct atm_vcc * vcc; - int err=0; - int i; - u8 * qd_addr; - u32 reg_l, reg_h; - unsigned int a_cfg_value=0; - unsigned int a_cfg_old_value=0; - atm_aal5_ifEntry_t mib_aal5; - atm_cell_ifEntry_t mib_cell; - - //make sure all cells transmitting out first - //Segmentation done - amazon_atm_aal5_mib(&mib_aal5); - reg_l = g_atm_dev.mib_counter.tx_cnt_l; - reg_h = g_atm_dev.mib_counter.tx_cnt_h; - while(1){ - mdelay(10); - amazon_atm_aal5_mib(&mib_aal5); - if( (reg_l == g_atm_dev.mib_counter.tx_cnt_l) && (reg_h == g_atm_dev.mib_counter.tx_cnt_h) ){ - break; - } - AMAZON_TPE_DMSG("AAL5 Segmentation still in progress!\n"); - reg_l = g_atm_dev.mib_counter.tx_cnt_l; - reg_h = g_atm_dev.mib_counter.tx_cnt_h; - } - //QSB done - qd_addr = (u8 *) KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr); - for (i=1;i<15;i++){ - while ( (err=readl(qd_addr+i*CBM_QD_SIZE+0x8)&0xffff) !=0 ){ - mdelay(20); - AMAZON_TPE_DMSG("queue %u not empty (%u)\n",i,err); - } - } - //insurance for interfaces between Aware and CARB - mdelay(100); - amazon_atm_cell_mib(&mib_cell,0); - amazon_atm_cell_mib(&mib_cell,1); - amazon_atm_aal5_mib(&mib_aal5); - - mb(); - while ( (AMAZON_READ_REGISTER_L(AR_CELLRDY_BC0) != 0 ) || (AMAZON_READ_REGISTER_L(AR_CELLRDY_BC0) != 0 ) ){ - AMAZON_TPE_EMSG("\nwaiting for AWARE"); - AMAZON_TPE_EMSG(" BC0 %u ", AMAZON_READ_REGISTER_L(AR_CELLRDY_BC0)); - AMAZON_TPE_EMSG(" BC1 %u ", AMAZON_READ_REGISTER_L(AR_CELLRDY_BC1)); - AMAZON_TPE_EMSG("\n"); - mdelay(1); - } - // disable AAI module - meiDebugRead(A_CFG_ADDR,&a_cfg_value,1); - a_cfg_old_value=a_cfg_value; - a_cfg_value &= (~(0x2800)); - meiDebugWrite(A_CFG_ADDR,&a_cfg_value,1); - //clear buffer - a_cfg_value = 0x1; - meiDebugWrite(AR_CB0_STATUS_ADDR,&a_cfg_value,1); - meiDebugWrite(AR_CB1_STATUS_ADDR,&a_cfg_value,1); - - if ( atm_init_hard(&g_atm_dev) != 0){ - return -EIO; - } - sema_init(&(g_atm_dev.swie.in_sem), 1); - //SWIE lock - clear_bit(SWIE_LOCK, &(g_atm_dev.swie.lock)); - //SWIE wait queue - init_waitqueue_head(&(g_atm_dev.swie.sleep)); - - for (i=CBM_DEFAULT_Q_OFFSET;iqos, i); - set_qd(vcc, i); - mb(); - err=set_htu(vcc,i); - if (err){ - AMAZON_TPE_EMSG("set htu entry fails %u\n",err); - } - } - } - meiDebugWrite(A_CFG_ADDR,&a_cfg_old_value,1); -#if 0 - //reset DFE - *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) | (AMAZON_RST_REQ_DFE); - mb(); - *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) & (~AMAZON_RST_REQ_DFE); - mb(); -#endif - - return 0; -} - -/* Brief: Send a ATM EoP packet to save DMA channel - */ -int amazon_tpe_inject_debug_cell(void) -{ - //Send a ATM cell to save DMA channel - u8 qid; - unsigned char atm_cell[48]; - qid = 0x11; - AMAZON_TPE_DMSG("qid = %d\n",qid); - memset(atm_cell,0,48); - atm_cell[3] = 0x2; - if ( amazon_atm_swin(qid,atm_cell)) { - AMAZON_TPE_EMSG("cannot insert EoP cell\n"); - return -1; - } - return 0; -} - -/* Brief: start HTU (TPE) - */ - -int amazon_tpe_start(void) -{ - AMAZON_WRITE_REGISTER_L(HTU_CFG_START ,HTU_CFG_ADDR); - wmb(); - return 0; -} -#endif //AMAZON_TPE_AAL5_RECOVERY - -#ifdef AMAZON_CHECK_LINK -extern int (*adsl_link_notify)(int); -/* Brief: notify link status of ADSL link - * Parameters: 0 link down - * 1 link up - * Returns: 0 OK - * Details: called by MEI driver - * should update status and inform upper layer - */ -int amazon_tpe_link_notify(int status) -{ - adsl_link_status = status; - AMAZON_TPE_DMSG("link status %s\n",(status==1)?"Up":"Down"); - if (status == 0){ - //wait until no cells in upstream queues - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(2*HZ); - } - return 0; -} -#endif //ifdef AMAZON_CHECK_LINK - -/* - * Brief: Initialize ATM module - * - * Return Value: ENOMEM - No memory available - * EBUSY - Cannot register atm device - * ERESTARTSYS - Process interrupted by other signal - * 0 - OK, module initialized - * - * Description: - * This function registers an atm device for all UTOPIA devices. - * It also allocates memory for the private device data structures - */ -int __init amazon_atm_net_init(void) -{ - int i; - int err=0; - amazon_atm_dev_t *dev = NULL; - - if ((dev=amazon_atm_create()) != NULL){ - for(i=0;iports[i].enable){ - amazon_atm_devs[i] = NULL; - continue; - } - amazon_atm_devs[i] =atm_dev_register("amazon_atm",&amazon_atm_ops,-1,0UL); - if (amazon_atm_devs[i] == NULL){ - AMAZON_TPE_EMSG("atm_dev_register fails\n"); - err = -EIO; - goto amazon_atm_net_init_exit; - }else{ - AMAZON_TPE_DMSG("registering device %u\n",i); - amazon_atm_devs[i]->ci_range.vpi_bits = 8; - amazon_atm_devs[i]->ci_range.vci_bits = 16; - amazon_atm_devs[i]->link_rate = dev->ports[i].tx_max_cr; - amazon_atm_devs[i]->dev_data = (void *) i; - } - } - - }else{ - err = -ENOMEM; - AMAZON_TPE_EMSG("cannot init atm device\n"); - goto amazon_atm_net_init_exit; - } -#ifdef AMAZON_TPE_AAL5_RECOVERY - tpe_reset = & amazon_tpe_reset; - tpe_start = & amazon_tpe_start; - tpe_inject = & amazon_tpe_inject_debug_cell; -#endif //AMAZON_TPE_AAL5_RECOVERY -#ifdef AMAZON_CHECK_LINK - adsl_link_notify=amazon_tpe_link_notify; -#endif //AMAZON_CHECK_LINK -amazon_atm_net_init_exit: - return err; -} - -void __exit amazon_atm_net_cleanup(void) -{ - int i; - amazon_atm_cleanup(); - for(i=0;i -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - -extern void mask_and_ack_amazon_irq(unsigned int irq_nr); - -#ifdef AMAZON_CHECK_LINK -//amazon_tpe.c -extern int (*adsl_link_notify)(int); -#endif //AMAZON_CHECK_LINK - -// for ARC memory access -#define WHILE_DELAY 20000 -#define AMAZON_DMA_DEBUG_MUTEX - - -//TODO -#undef DFE_LOOPBACK -#define ARC_READY_ACK - -static amazon_mei_mib * current_intvl; -static struct list_head interval_list; -static amazon_mei_mib * mei_mib; - -static int reboot_firsttime=1;//000002:fchang - - //PCM -#define PCM_CHANNEL_NUM 2 //1 rx, 1 tx -static pcm_data_struct pcm_data[PCM_CHANNEL_NUM]__attribute__ ((aligned(4))); //0=tx0, 1=rx0, 2=tx1, 3=rx1 -static u32 pcm_start_addr; -//#define PCM_HRT_TIME_HZ 4000 //?us -#define PCM_ACCESS_DEBUG -static int irqtimes=0; -#undef DATA_LED_ON_MODE -#define ADSL_LED_SUPPORT //joelin for adsl led -#ifdef ADSL_LED_SUPPORT -static int firmware_support_led=0; //joelin version check for adsl led -static int stop_led_module=0; //wakeup and clean led module -static int led_support_check=0; //1.1.2.7.1.1 -#endif //ADSL_LED_SUPPORT -#define IFX_DYING_GASP -#ifdef IFX_DYING_GASP -static wait_queue_head_t wait_queue_dying_gasp; //dying gasp -//struct tq_struct dying_gasp_task; //dying gasp -static wait_queue_head_t wait_queue_uas_poll; //joelin 04/16/2005 -static u16 unavailable_seconds=0; //joelin 04/16/2005 -static meidebug lop_debugwr; //dying gasp -#endif //IFX_DYING_GASP -static int dbg_int=0; -//#define DEBUG_ACCESS_DELAY for(dbg_int=0;dbg_int<100;dbg_int++){;} -#define DEBUG_ACCESS_DELAY -static u8 sampledata[512]; -static int firsttime[PCM_CHANNEL_NUM]={0,1}; -static int num_cmp[PCM_CHANNEL_NUM]={0,0}; -static int pcm_start_loc[PCM_CHANNEL_NUM]={0,0}; - - // for clearEoC -//#define MEI_CLREOC_BUFF_SIZE 512 //double the receive fifo size, bytes -//static u8 clreoc[MEI_CLREOC_BUFF_SIZE]__attribute__ ((aligned(4))); //buffer to hold clearEoC data in bytes -#undef AMAZON_CLEAR_EOC -#ifdef AMAZON_CLEAR_EOC -extern void ifx_push_eoc(struct sk_buff * pkt); -#endif -static int meiResetArc(void); -#define IFX_POP_EOC_DONE 0 -#define IFX_POP_EOC_FAIL -1 -static struct list_head clreoc_list; -static amazon_clreoc_pkt * clreoc_pkt; -#define CLREOC_BUFF_SIZE 12 //number of clreoc commands being buffered -//static int clreoc_wr=0; -//static int clreoc_rd=0; //used to control clreoc circular buffer -static wait_queue_head_t wait_queue_clreoc; -#ifdef ADSL_LED_SUPPORT -static wait_queue_head_t wait_queue_led; //adsl led -static wait_queue_head_t wait_queue_led_polling;// adsl led -struct tq_struct led_task; // adsl led -static DECLARE_TASK_QUEUE(tq_ifx_led); // task -int adsl_led_flash_task(void *ptr); // adsl led -#endif //ADSL_LED_SUPPORT -static void * clreoc_command_pkt=NULL; -static int clreoc_max_tx_len=0; - -// 603221:tc.chen start -#define ME_HDLC_IDLE 0 -#define ME_HDLC_INVALID_MSG 1 -#define ME_HDLC_MSG_QUEUED 2 -#define ME_HDLC_MSG_SENT 3 -#define ME_HDLC_RESP_RCVD 4 -#define ME_HDLC_RESP_TIMEOUT 5 -#define ME_HDLC_RX_BUF_OVERFLOW 6 -#define ME_HDLC_UNRESOLVED 1 -#define ME_HDLC_RESOLVED 2 -// 603221:tc.chen end - -#ifdef LOCK_RETRY -static int reboot_lock=0; -#endif - -static mib_previous_read mib_pread={0,0,0,0,0,0,0,0,0,0,0,0}; -static mib_flags_pretime mib_pflagtime;// initialized when module loaded - - static u32 ATUC_PERF_LOFS=0; - static u32 ATUC_PERF_LOSS=0; - static u32 ATUC_PERF_ESS=0; - static u32 ATUC_PERF_INITS=0; - static u32 ATUR_PERF_LOFS=0; - static u32 ATUR_PERF_LOSS=0; - static u32 ATUR_PERF_LPR=0; - static u32 ATUR_PERF_ESS=0; - static u32 ATUR_CHAN_RECV_BLK=0; - static u32 ATUR_CHAN_TX_BLK=0; - static u32 ATUR_CHAN_CORR_BLK=0; - static u32 ATUR_CHAN_UNCORR_BLK=0; - //RFC-3440 - static u32 ATUC_PERF_STAT_FASTR=0; - static u32 ATUC_PERF_STAT_FAILED_FASTR=0; - static u32 ATUC_PERF_STAT_SESL=0; - static u32 ATUC_PERF_STAT_UASL=0; - static u32 ATUR_PERF_STAT_SESL=0; - static u32 ATUR_PERF_STAT_UASL=0; - - static adslChanPrevTxRate PrevTxRate={0,0}; - static adslPhysCurrStatus CurrStatus={0,0}; - static ChanType chantype={0,0}; - static adslLineAlarmConfProfileEntry AlarmConfProfile={"No Name\0",0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}; -// 603221:tc.chen start - static adslFarEndPerfStats FarendStatsData; - struct timeval FarendData_acquire_time={0}; - static u32 adsl_mode,adsl_mode_extend; // adsl mode : adsl/ 2/ 2+ - static adslInitStats AdslInitStatsData; -//603221:tc.chen end -static u32 loop_diagnostics_mode=0; -static wait_queue_head_t wait_queue_loop_diagnostic; -#ifdef AMAZON_MEI_MIB_RFC3440 - static adslLineAlarmConfProfileExtEntry AlarmConfProfileExt={"No Name\0",0,0,0,0,0,0}; -#endif - -static int showtime=0; -static int loop_diagnostics_completed=0; -////////////////////////////////////////////////////////////////////////////////// -static int phy_mei_net_init(struct net_device * dev); -static int interleave_mei_net_init(struct net_device * dev); -static int fast_mei_net_init(struct net_device * dev); -static struct net_device_stats * phy_mei_net_get_stats(struct net_device * dev); -static struct net_device_stats * interleave_mei_net_get_stats(struct net_device * dev); -static struct net_device_stats * fast_mei_net_get_stats(struct net_device * dev); - -typedef struct mei_priv{ - struct net_device_stats stats; -}mei_priv; - -static struct net_device phy_mei_net = { init: phy_mei_net_init, name: "MEI_PHY"}; -static struct net_device interleave_mei_net = { init: interleave_mei_net_init, name: "MEI_INTL"}; -static struct net_device fast_mei_net = { init: fast_mei_net_init, name: "MEI_FAST"}; -/////////////////////////////////////////////////////////////////////////////////// - -static int major=AMAZON_MEI_MAJOR; - -static struct semaphore mei_sema; - -// Mei to ARC CMV count, reply count, ARC Indicator count -static int indicator_count=0; -static int cmv_count=0; -static int reply_count=0; -static u16 Recent_indicator[MSG_LENGTH]; - -// Used in interrupt handler as flags -static int arcmsgav=0; -static int cmv_reply=0; -static int cmv_waiting=0; - -#define PROC_ITEMS 8 - -long mei_debug_mode = 0; //509221:tc.chen for adsl firmware debug - -// to wait for arc cmv reply, sleep on wait_queue_arcmsgav; -static wait_queue_head_t wait_queue_arcmsgav; -static wait_queue_head_t wait_queue_codeswap; -static wait_queue_head_t wait_queue_mibdaemon; -static wait_queue_head_t wait_queue_reboot; -static u32 * image_buffer=NULL; // holding adsl firmware image -static u16 RxMessage[MSG_LENGTH]__attribute__ ((aligned(4))); -static u16 TxMessage[MSG_LENGTH]__attribute__ ((aligned(4))); -static u32 * mei_arc_swap_buff=NULL; // holding swap pages -static ARC_IMG_HDR * img_hdr; -static int reboot_flag; - -#ifdef DFE_LOOPBACK -#include "arc_pm.h" -#endif - - -///////////////// net device /////////////////////////////////////////////////// -static int phy_mei_net_init(struct net_device * dev) -{ - //ether_setup(dev); - dev->get_stats = phy_mei_net_get_stats; - dev->ip_ptr = NULL; - dev->type = 94; - -// dev->mtu=12345; - dev->flags=IFF_UP; - - dev->priv = kmalloc(sizeof(struct mei_priv), GFP_KERNEL); - if(dev->priv == NULL) - return -ENOMEM; - memset(dev->priv, 0, sizeof(struct mei_priv)); - return 0; -} - -static int interleave_mei_net_init(struct net_device * dev) -{ - //ether_setup(dev); - dev->get_stats = interleave_mei_net_get_stats; - dev->ip_ptr = NULL; - dev->type = 124; - dev->flags=IFF_UP; - dev->priv = kmalloc(sizeof(struct mei_priv), GFP_KERNEL); - if(dev->priv == NULL) - return -ENOMEM; - memset(dev->priv, 0, sizeof(struct mei_priv)); - return 0; -} - -static int fast_mei_net_init(struct net_device * dev) -{ - //ether_setup(dev); - dev->get_stats = fast_mei_net_get_stats; - dev->ip_ptr = NULL; - dev->type = 125; - dev->flags=IFF_UP; - dev->priv = kmalloc(sizeof(struct mei_priv), GFP_KERNEL); - if(dev->priv == NULL) - return -ENOMEM; - memset(dev->priv, 0, sizeof(struct mei_priv)); - return 0; -} - -static struct net_device_stats * phy_mei_net_get_stats(struct net_device * dev) -{ - struct mei_priv * priv; - priv = (struct mei_priv *)dev->priv; - // update statistics - (priv->stats).rx_packets = ATUR_CHAN_RECV_BLK; - (priv->stats).tx_packets = ATUR_CHAN_TX_BLK; - (priv->stats).rx_errors = ATUR_CHAN_CORR_BLK + ATUR_CHAN_UNCORR_BLK; - (priv->stats).rx_dropped = ATUR_CHAN_UNCORR_BLK; - - return &(priv->stats); -} - -static struct net_device_stats * interleave_mei_net_get_stats(struct net_device * dev) -{ - struct mei_priv * priv; - priv = (struct mei_priv *)dev->priv; - // update statistics - (priv->stats).rx_packets = ATUR_CHAN_RECV_BLK; - (priv->stats).tx_packets = ATUR_CHAN_TX_BLK; - (priv->stats).rx_errors = ATUR_CHAN_CORR_BLK + ATUR_CHAN_UNCORR_BLK; - (priv->stats).rx_dropped = ATUR_CHAN_UNCORR_BLK; - - return &(priv->stats); -} - -static struct net_device_stats * fast_mei_net_get_stats(struct net_device * dev) -{ - struct mei_priv * priv; - priv = (struct mei_priv *)dev->priv; - // update statistics - (priv->stats).rx_packets = ATUR_CHAN_RECV_BLK; - (priv->stats).tx_packets = ATUR_CHAN_TX_BLK; - (priv->stats).rx_errors = ATUR_CHAN_CORR_BLK + ATUR_CHAN_UNCORR_BLK; - (priv->stats).rx_dropped = ATUR_CHAN_UNCORR_BLK; - - return &(priv->stats); -} -///////////////// mei access Rd/Wr methods /////////////////////////////////////////////////// -void meiLongwordWrite(u32 ul_address, u32 ul_data) -{ - *((volatile u32 *)ul_address) = ul_data; - asm("SYNC"); - return; -} // end of "meiLongwordWrite(..." - -void meiLongwordRead(u32 ul_address, u32 *pul_data) -{ - *pul_data = *((volatile u32 *)ul_address); - asm("SYNC"); - return; -} // end of "meiLongwordRead(..." - -MEI_ERROR meiDMAWrite(u32 destaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( destaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the write transfer address - meiLongwordWrite(MEI_XFR_ADDR, destaddr); - - // Write the data pushed across DMA - while (databuffsize--) - { - temp = *p; - if(databuff==(u32 *)TxMessage) // swap half word - temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16); - meiLongwordWrite(MEI_DATA_XFR, temp); - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMAWrite(..." - -MEI_ERROR meiDMAWrite_16(u32 destaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( destaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the write transfer address - meiLongwordWrite(MEI_XFR_ADDR, destaddr); - - // Write the data pushed across DMA - while (databuffsize--) - { - temp = *p; - temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16);//swap half word - meiLongwordWrite(MEI_DATA_XFR, temp); - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMAWrite_16(..." - -MEI_ERROR meiDMAWrite_8(u32 destaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( destaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the write transfer address - meiLongwordWrite(MEI_XFR_ADDR, destaddr); - - // Write the data pushed across DMA - while (databuffsize--) - { - temp = *p; - temp = ((temp & 0xff)<<24) + ((temp & 0xff00)<<8)+ ((temp & 0xff0000)>>8)+ ((temp & 0xff000000)>>24);//swap byte - meiLongwordWrite(MEI_DATA_XFR, temp); - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMAWrite_8(..." - -MEI_ERROR meiDMARead(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( srcaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the read transfer address - meiLongwordWrite(MEI_XFR_ADDR, srcaddr); - - // Read the data popped across DMA - while (databuffsize--) - { - meiLongwordRead(MEI_DATA_XFR, &temp); - if(databuff==(u32 *)RxMessage) // swap half word - temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16); - *p=temp; - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMARead(..." - -MEI_ERROR meiDMARead_16(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( srcaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the read transfer address - meiLongwordWrite(MEI_XFR_ADDR, srcaddr); - - // Read the data popped across DMA - while (databuffsize--) - { - meiLongwordRead(MEI_DATA_XFR, &temp); - temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16); - *p=temp; - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMARead_16(..." - -MEI_ERROR meiDMARead_8(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - u32 flags; - - if( srcaddr & 3) - return MEI_FAILURE; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Set the read transfer address - meiLongwordWrite(MEI_XFR_ADDR, srcaddr); - - // Read the data popped across DMA - while (databuffsize--) - { - meiLongwordRead(MEI_DATA_XFR, &temp); - temp = ((temp & 0xff)<<24) + ((temp & 0xff00)<<8)+ ((temp & 0xff0000)>>8)+ ((temp & 0xff000000)>>24);//swap byte - *p=temp; - p++; - } // end of "while(..." - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - return MEI_SUCCESS; - -} // end of "meiDMARead_8(..." - -void meiPollForDbgDone(void) -{ - u32 query = 0; - int i=0; - while (i>8)+ ((temp & 0xff000000)>>24);//swap byte - meiLongwordWrite(MEI_DEBUG_DATA, temp); - DEBUG_ACCESS_DELAY; - meiPollForDbgDone(); - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory write - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugWrite_8(..." - -MEI_ERROR meiDebugRead_8(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - u32 flags; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Open the debug port before DMP memory read - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP2_MASK); - DEBUG_ACCESS_DELAY; - - // For the requested length, write the address and read the data - address = srcaddr; - buffer = databuff; - for (i=0; i>8)+ ((temp & 0xff000000)>>24);//swap byte - *buffer=temp; - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory read - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugRead_8(..." - -MEI_ERROR meiDebugWrite_16(u32 destaddr, u32 *databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - u32 flags; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Open the debug port before DMP memory write - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK); - DEBUG_ACCESS_DELAY; - - // For the requested length, write the address and write the data - address = destaddr; - buffer = databuff; - for (i=0; i < databuffsize; i++) - { - meiLongwordWrite(MEI_DEBUG_WAD, address); - DEBUG_ACCESS_DELAY; - temp=*buffer; - temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16);//swap half word - meiLongwordWrite(MEI_DEBUG_DATA, temp); - DEBUG_ACCESS_DELAY; - meiPollForDbgDone(); - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory write - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugWrite_16(..." - -MEI_ERROR meiDebugRead_16(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - u32 flags; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Open the debug port before DMP memory read - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP2_MASK); - DEBUG_ACCESS_DELAY; - - // For the requested length, write the address and read the data - address = srcaddr; - buffer = databuff; - for (i=0; i>16);//swap half word - *buffer=temp; - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory read - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugRead_16(..." - -MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - u32 flags; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Open the debug port before DMP memory write - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK); - DEBUG_ACCESS_DELAY; - - // For the requested length, write the address and write the data - address = destaddr; - buffer = databuff; - for (i=0; i < databuffsize; i++) - { - meiLongwordWrite(MEI_DEBUG_WAD, address); - DEBUG_ACCESS_DELAY; - temp=*buffer; - meiLongwordWrite(MEI_DEBUG_DATA, temp); - DEBUG_ACCESS_DELAY; - meiPollForDbgDone(); - address += 4; - buffer++; - } // end of "for(..." - - // Close the debug port after DMP memory write - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - restore_flags(flags); -#endif - - // Return - return MEI_SUCCESS; - -} // end of "meiDebugWrite(..." - -MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - u32 flags; - -#ifdef AMAZON_DMA_DEBUG_MUTEX - save_flags(flags); - cli(); -#endif - - - // Open the debug port before DMP memory read - meiLongwordRead(MEI_CONTROL, &temp); - DEBUG_ACCESS_DELAY; - temp |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, temp); - DEBUG_ACCESS_DELAY; - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP2_MASK); - DEBUG_ACCESS_DELAY; - - // For the requested length, write the address and read the data - address = srcaddr; - buffer = databuff; - for (i=0; icount; boot_loop++) - { - if( img_hdr->page[boot_loop].p_size & BOOT_FLAG) - { - page_size = meiGetPage( boot_loop, GET_PROG, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( page_size > 0) - { - meiDMAWrite(dest_addr, mei_arc_swap_buff, page_size); - } - } - if( img_hdr->page[boot_loop].d_size & BOOT_FLAG) - { - page_size = meiGetPage( boot_loop, GET_DATA, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( page_size > 0) - { - meiDMAWrite( dest_addr, mei_arc_swap_buff, page_size); - } - } - } -#ifdef AMAZON_MEI_DEBUG_ON -// printk("\n\n pages downloaded"); -#endif - return MEI_SUCCESS; - -} // end of "meiDownloadBootCode(..." - -MEI_ERROR meiRunArc(void) -{ - u32 arc_control_mode = 0x0; - u32 arc_debug_addr = 0x0; - u32 arc_debug_data = 0x0; - - // Switch arc control from JTAG mode to MEI mode- write '1' to bit0 - meiLongwordRead(MEI_CONTROL, &arc_control_mode); - arc_control_mode |= (HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, arc_control_mode); - - // Write arc aux reg access mask (0x0) into debug addr decode reg - meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_AUX_MASK); - - // Write arc status aux reg addr (0x0) into debug read addr reg - meiLongwordWrite(MEI_DEBUG_RAD, arc_debug_addr); - meiPollForDbgDone(); - - // Read debug data reg and save content - meiLongwordRead(MEI_DEBUG_DATA, &arc_debug_data); - - // Write arc status aux reg addr (0x0) into debug write addr reg - meiLongwordWrite(MEI_DEBUG_WAD, arc_debug_addr); - - // Write debug data reg with content ANDd with 0xFDFFFFFF (halt bit cleared) - arc_debug_data &= ~(BIT25); - meiLongwordWrite(MEI_DEBUG_DATA, arc_debug_data); - meiPollForDbgDone(); - - // Switch arc control from MEI mode to JTAG mode- write '0' to bit0 - meiLongwordRead(MEI_CONTROL, &arc_control_mode); - arc_control_mode &= ~(HOST_MSTR); - meiLongwordWrite(MEI_CONTROL, arc_control_mode); - - // Enable mask for arc codeswap interrupts - meiMailboxInterruptsEnable(); - - // Return - return MEI_SUCCESS; - -} // end of "meiActivate(..." - -int meiGetPage( u32 Page, u32 data, u32 MaxSize, u32 *Buffer, u32 *Dest) -{ - u32 size; - u32 i; - u32 *p; - - if( Page > img_hdr->count) - return -2; - - /* - ** Get program or data size, depending on "data" flag - */ - size = (data == GET_DATA) ? img_hdr->page[ Page].d_size : img_hdr->page[ Page].p_size; - - size &= BOOT_FLAG_MASK; // Clear boot bit! - if( size > MaxSize) - return -1; - - if( size == 0) - return 0; - /* - ** Get program or data offset, depending on "data" flag - */ - i = data ? img_hdr->page[ Page].d_offset : img_hdr->page[ Page].p_offset; - - /* - ** Copy data/program to buffer - */ - - i /= 4; // Adjust offset for byte-to-UINT for array operation - - p = (u32 *)img_hdr + i; - for(i = 0; i < size; i++) - Buffer[i] = *p++; - /* - ** Pass back data/program destination address - */ - *Dest = data ? img_hdr->page[Page].d_dest : img_hdr->page[Page].p_dest; - - return size; -} - -MEI_ERROR meiCMV(u16 * request, int reply) // write cmv to arc, if reply needed, wait for reply -{ - MEI_ERROR meierror; - wait_queue_t wait; - - cmv_reply=reply; - - meierror = meiMailboxWrite(request, MSG_LENGTH); - - if(meierror != MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n MailboxWrite Fail."); -#endif - return meierror; - } - else{ - cmv_count++; - } - - if(cmv_reply == NO_REPLY) - return MEI_SUCCESS; - - init_waitqueue_entry(&wait, current); - add_wait_queue(&wait_queue_arcmsgav, &wait); - set_current_state(TASK_INTERRUPTIBLE); -// cmv_waiting=1; - - if(arcmsgav==1){ - set_current_state(TASK_RUNNING); - remove_wait_queue(&wait_queue_arcmsgav, &wait); - } - else{ - schedule_timeout(CMV_TIMEOUT); - remove_wait_queue(&wait_queue_arcmsgav, &wait); - } - if(arcmsgav==0){//CMV_timeout - cmv_waiting=0; - arcmsgav=0; -#ifdef AMAZON_MEI_DEBUG_ON - printk("\nmeiCMV: MEI_MAILBOX_TIMEOUT\n"); -#endif - return MEI_MAILBOX_TIMEOUT; - } - else{ - arcmsgav=0; - reply_count++; - return MEI_SUCCESS; - } -} - -//TODO, for loopback test -#ifdef DFE_LOOPBACK -#define mte_reg_base (0x4800*4+0x20000) - -/* Iridia Registers Address Constants */ -#define MTE_Reg(r) (int)(mte_reg_base + (r*4)) - -#define IT_AMODE MTE_Reg(0x0004) - - -#define OMBOX_BASE 0x15F80 -#define IMBOX_BASE 0x15FC0 - -#define TIMER_DELAY (1024) -#define BC0_BYTES (32) -#define BC1_BYTES (30) -#define NUM_MB (12) -#define TIMEOUT_VALUE 2000 - -void BFMWait (u32 cycle) { - u32 i; - for (i = 0 ; i< cycle ; i++); -} - -void WriteRegLong(u32 addr, u32 data){ - //printk("[%8x] <= %8x \n\n", addr, data); - *((volatile u32 *)(addr)) = data; -} - -u32 ReadRegLong (u32 addr) { - u32 rd_val; - - rd_val = *((volatile u32 *)(addr)); - //printk("[%8x] => %8x \n\n", addr, rd_val); - return rd_val; - -} - -/* This routine writes the mailbox with the data in an input array */ -void WriteMbox(u32 *mboxarray,u32 size) { - u32 i; - - WriteRegLong(MEI_XFR_ADDR,IMBOX_BASE); - for (i=0;if_dentry->d_inode)->i_ino; - char outputbuf[64]; - int count=0; - int i; - u32 version=0; - reg_entry_t* current_reg=NULL; - - for (i=0;iflag == (int *) 8){ - ///proc/mei/version - //format: - //Firmware version: major.minor.sub_version.int_version.rel_state.spl_appl - //Firmware Date Time Code: date/month min:hour - if (*ppos>0) /* Assume reading completed in previous read*/ - return 0; // indicates end of file - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - //if (indicator_count != 1){ - if (indicator_count < 1){ - up(&mei_sema); - return -EAGAIN; - } - //major:bits 0-7 - //minor:bits 8-15 - makeCMV(H2D_CMV_READ, INFO, 54, 0, 1, NULL); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#if 0 -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n WINHOST CMV fail"); -#endif -#endif - up(&mei_sema); - return -EIO; - } - version = RxMessage[4]; - count = sprintf(outputbuf, "%d.%d.",(version)&0xff,(version>>8)&0xff); - - //sub_version:bits 4-7 - //int_version:bits 0-3 - //spl_appl:bits 8-13 - //rel_state:bits 14-15 - makeCMV(H2D_CMV_READ, INFO, 54, 1, 1, NULL); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#if 0 -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n WINHOST CMV fail"); -#endif -#endif - up(&mei_sema); - return -EFAULT; - } - version =RxMessage[4]; - count += sprintf(outputbuf+count, "%d.%d.%d.%d", - (version>>4)&0xf, - version&0xf, - (version>>14)&0x3, - (version>>8)&0x3f); -#ifdef ADSL_LED_SUPPORT -// version check -start for adsl led - if ((((version>>4)&0xf)==2)&&((version&0xf)>=3)&&((version&0xf)<7)) firmware_support_led=1; - else if ((((version>>4)&0xf)==2)&&((version&0xf)>=7)) firmware_support_led=2; - else if (((version>>4)&0xf)>2) firmware_support_led=2; - -//165001:henryhsu:20050906:Modify for adsl firmware version 1.2.1.2.0.1 DATA_LED can't flash. - //else firmware_support_led=0; - else firmware_support_led=2; -//165001 - - -// version check -end -#endif - //Date:bits 0-7 - //Month:bits 8-15 - makeCMV(H2D_CMV_READ, INFO, 55, 0, 1, NULL); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#if 0 -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n WINHOST CMV fail"); -#endif -#endif - up(&mei_sema); - return -EIO; - } - version = RxMessage[4]; - - //Hour:bits 0-7 - //Minute:bits 8-15 - makeCMV(H2D_CMV_READ, INFO, 55, 1, 1, NULL); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#if 0 -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n WINHOST CMV fail"); -#endif -#endif - up(&mei_sema); - return -EFAULT; - } - version += (RxMessage[4]<<16); - count += sprintf(outputbuf+count, " %d/%d %d:%d\n" - ,version&0xff - ,(version>>8)&0xff - ,(version>>25)&0xff - ,(version>>16)&0xff); - - up(&mei_sema); - - *ppos+=count; - }else if(current_reg->flag != (int *)Recent_indicator){ - if (*ppos>0) /* Assume reading completed in previous read*/ - return 0; // indicates end of file - count = sprintf(outputbuf, "0x%08X\n\n", *(current_reg->flag)); - *ppos+=count; - if (count>nbytes) /* Assume output can be read at one time */ - return -EINVAL; - }else{ - if((int)(*ppos)/((int)7)==16) - return 0; // indicate end of the message - count = sprintf(outputbuf, "0x%04X\n\n", *(((u16 *)(current_reg->flag))+ (int)(*ppos)/((int)7))); - *ppos+=count; - } - if (copy_to_user(buf, outputbuf, count)) - return -EFAULT; - return count; -} - -static ssize_t proc_write(struct file * file, const char * buffer, size_t count, loff_t *ppos) -{ - int i_ino = (file->f_dentry->d_inode)->i_ino; - reg_entry_t* current_reg=NULL; - int i; - unsigned long newRegValue; - char *endp; - - for (i=0;iflag == (int *)Recent_indicator)) - return -EINVAL; - - newRegValue = simple_strtoul(buffer,&endp,0); - *(current_reg->flag)=(int)newRegValue; - return (count+endp-buffer); -} -////////////////makeCMV(Opcode, Group, Address, Index, Size, Data), CMV in u16 TxMessage[MSG_LENGTH]/////////////////////////// -void makeCMV(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data) -{ - memset(TxMessage, 0, MSG_LENGTH*2); - TxMessage[0]= (opcode<<4) + (size&0xf); - TxMessage[1]= (((index==0)?0:1)<<7) + (group&0x7f); - TxMessage[2]= address; - TxMessage[3]= index; - if(opcode == H2D_CMV_WRITE) - memcpy(TxMessage+4, data, size*2); - return; -} - -////////////////makeCMV(Opcode, Group, Address, Index, Size, Data), CMV in u16 TxMessage[MSG_LENGTH]/////////////////////////// -void makeCMV_local(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data,u16 *CMVMSG) -{ - memset(CMVMSG, 0, MSG_LENGTH*2); - CMVMSG[0]= (opcode<<4) + (size&0xf); - CMVMSG[1]= (((index==0)?0:1)<<7) + (group&0x7f); - CMVMSG[2]= address; - CMVMSG[3]= index; - if(opcode == H2D_CMV_WRITE) - memcpy(CMVMSG+4, data, size*2); - return; -} - -//////////////// Driver Structure ///////////////////////////////////////////////////////////////////////////// -static ssize_t mei_write(struct file *, const char *, size_t, loff_t *); -static int mei_ioctl(struct inode *, struct file *, unsigned int, unsigned long); - -static struct file_operations mei_operations = { - write: mei_write, - ioctl: mei_ioctl, -}; - - -static ssize_t mei_write(struct file * filp, const char * buf, size_t size, loff_t * loff) -{ -// printk("\n\n mei_write entered"); -// image_buffer = (u32 *)kmalloc(size, GFP_KERNEL); - image_buffer = (u32 *)vmalloc(size); -// printk("\n\n image_buffer kmalloc done"); - if(image_buffer == NULL){ -#ifdef AMAZON_MEI_DEBUG_ON -// printk("\n\n kmalloc for firmware image fail"); - printk("\n\n vmalloc for firmware image fail"); -#endif - return -1; - } - copy_from_user((char *)image_buffer, buf, size); -// printk("\n\n copy_from_user done"); - return size; -} - - ////////// ISR GPTU Timer 6 for high resolution timer ///////////// -void amazon_timer6_interrupt_MEI(int irq, void *dev_id, struct pt_regs *regs) -{ - int i,j; - u32 temp; - u16 temp16; - u16 rdindex, wrindex; - u16 num_rd=0; //num of byte can be read - u16 bytes_to_wr=0; - -// printk("\n\nenter timer\n\n"); - irqtimes++; -// printk("\n%d\n",irqtimes); - - -/* -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_8(0x30f20, &temp, 1); -#else - meiDMARead_8(0x30f20, &temp, 1); -#endif - if((temp&0x4000)!=0){ - printk("\nER_ERR"); -#ifdef PCM_ACCESS_DEBUG - meiDebugWrite_8(0x30f20, &temp, 1); -#else - meiDMAWrite_8(0x30f20, &temp, 1); -#endif -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_8(0x30f20, &temp, 1); -#else - meiDMARead_8(0x30f20, &temp, 1); -#endif - if((temp&0x4000)!=0) - printk("\nER_ERR not cleared"); - } -*/ - - for(i=PCM_CHANNEL_NUM-1;i>=0;i--){// start from last channel, which is rx -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_16(pcm_start_addr+i*16+12, &temp, 1); -#else - meiDMARead_16(pcm_start_addr+i*16+12, &temp, 1); -#endif - wrindex = (u16)((temp & 0xffff0000)>>16); -// printk(" %d",wrindex); -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_16(pcm_start_addr+i*16+8, &temp, 1); -#else - meiDMARead_16(pcm_start_addr+i*16+8, &temp, 1); -#endif - rdindex = (u16)(temp & 0xffff); -// printk(" %d",rdindex); - if(rdindex<=wrindex) - num_rd=((wrindex-rdindex)/4)*4; //read multiply of 4 bytes - else - num_rd=((pcm_data[i].len-(rdindex-wrindex))/4)*4; //read multiply of 4 bytes - - if(i%2!=0){//rx channel - pcm_data[i].point=0; - for(j=0;j=pcm_data[i].len) - temp16=(rdindex+j*4) - pcm_data[i].len; - else - temp16=rdindex+j*4; -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16, (u32*)(pcm_data[i].buff+pcm_data[i].point), 1); -#else - meiDMARead_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16, (u32*)(pcm_data[i].buff+pcm_data[i].point), 1); -#endif - // printk(" %8x", *((u32*)(pcm_data[i].buff+pcm_data[i].point))); - /* if(pcm_data[i].point==0){ - if(pcm_data[i].buff[0]==0xA5){// start of loopback data - pcm_data[i].point+=4; - printk("\nstart receive data"); - } - } - else*/ - pcm_data[i].point+=4; - /* if(pcm_data[i].point==PCM_BUFF_SIZE){ //finish rx - pcm_data[i].finish=1; - printk("\nchannel[%d] finished", i); - } */ - } - } - if(firsttime[i]==1){ - for(j=0;j=256) - pcm_start_loc[i]=pcm_start_loc[i]-256; - } - } - - rdindex +=num_rd; - if(rdindex>=pcm_data[i].len) - rdindex=rdindex-pcm_data[i].len; -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_16(pcm_start_addr+i*16+8, &temp, 1); -#else - meiDMARead_16(pcm_start_addr+i*16+8, &temp, 1); -#endif - temp= (temp & 0xffff0000) + rdindex; -#ifdef PCM_ACCESS_DEBUG - meiDebugWrite_16(pcm_start_addr+i*16+8, &temp, 1); // update rdindex -#else - meiDMAWrite_16(pcm_start_addr+i*16+8, &temp, 1); // update rdindex -#endif - - bytes_to_wr = num_rd; - - // if(bytes_to_wr>0){ - // printk(" %d", num_rd); - // printk(" %d", rdindex); -// printk("\n\nrdindex = %d", rdindex); - //} - } - else{ //tx channel - // if((bytes_to_wr + num_rd) < pcm_data[i].len){ - for(j=0;j=pcm_data[i].len) - temp16=(wrindex+j*4) - pcm_data[i].len; - else - temp16=wrindex + j*4; -/* -#ifdef PCM_ACCESS_DEBUG - meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i+1].buff+j*4), 1); -#else - meiDMAWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i+1].buff+j*4), 1); -#endif*/ - -#ifdef PCM_ACCESS_DEBUG - meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i].buff+pcm_data[i].point), 1); - // meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i].buff), 1); -#else - meiDMAWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i].buff+pcm_data[i].point), 1); -#endif - pcm_data[i].point+=4; - if(pcm_data[i].point==PCM_BUFF_SIZE){ - // pcm_data[i].finish=1; - // printk("\nchannel[%d] finished", i); - pcm_data[i].point=0; - } - } - } - wrindex+=bytes_to_wr; - if(wrindex>=pcm_data[i].len) - wrindex=wrindex-pcm_data[i].len; -#ifdef PCM_ACCESS_DEBUG - meiDebugRead_16(pcm_start_addr+i*16+12, &temp, 1); -#else - meiDMARead_16(pcm_start_addr+i*16+12, &temp, 1); -#endif - temp=(temp&0xffff) + (wrindex<<16); -#ifdef PCM_ACCESS_DEBUG - meiDebugWrite_16(pcm_start_addr+i*16+12, &temp, 1); // update wrindex -#else - meiDMAWrite_16(pcm_start_addr+i*16+12, &temp, 1); // update wrindex -#endif - - //if(bytes_to_wr>0){ - // printk(" %d", bytes_to_wr); - // printk(" %d", wrindex); -// printk("\n\nwrindex = %d", wrindex); - //} - // } - } - } - return; -} -//000002:fchang Start -static int meiResetArc(void) -{ - u32 auxreg0; - u32 auxreg5; - int flshcnt=0; - int flshcnt1=0; - int flshcnt2=0; - - meiLongwordWrite(MEI_CONTROL, 1); - meiLongwordWrite(MEI_DEBUG_DEC, 3); - meiLongwordWrite(MEI_DEBUG_WAD, 0x3c); - meiLongwordWrite(MEI_DEBUG_DATA, 0x10); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_DEC, 0x0); - meiLongwordWrite(MEI_DEBUG_WAD, 0x2); - meiLongwordWrite(MEI_DEBUG_DATA, 0x0); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_WAD, 0x3); - meiLongwordWrite(MEI_DEBUG_DATA, 0x0); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_DEC, 0x0); - meiLongwordWrite(MEI_DEBUG_RAD, 0x0); - meiPollForDbgDone(); - meiLongwordRead(MEI_DEBUG_DATA, &auxreg0); - auxreg0 = auxreg0 & 0x03ffffff; - meiLongwordWrite(MEI_DEBUG_WAD, 0x0); - meiLongwordWrite(MEI_DEBUG_DATA, auxreg0); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_WAD, 0x10a); - meiLongwordWrite(MEI_DEBUG_DATA, 0x0); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_DEC, 0x2); - meiLongwordWrite(MEI_DEBUG_WAD, 0xfffc); - meiLongwordWrite(MEI_DEBUG_DATA, 0x1fffffff); - meiPollForDbgDone(); - while(flshcnt<3){ - meiLongwordWrite(MEI_DEBUG_DEC, 0x0); - meiLongwordWrite(MEI_DEBUG_RAD, 0x0); - meiPollForDbgDone(); - meiLongwordRead(MEI_DEBUG_DATA, &auxreg0); - auxreg0 = auxreg0 & 0xff000000; - auxreg0 = auxreg0 | 0x3fff; - meiLongwordWrite(MEI_DEBUG_WAD, 0x0); - meiLongwordWrite(MEI_DEBUG_DATA, auxreg0); - meiPollForDbgDone(); - - meiLongwordWrite(MEI_DEBUG_DEC, 0x0); - meiLongwordWrite(MEI_DEBUG_RAD, 0x5); - meiPollForDbgDone(); - meiLongwordRead(MEI_DEBUG_DATA, &auxreg5); - auxreg5 = auxreg5 | 0x801; - meiLongwordWrite(MEI_DEBUG_WAD, 0x5); - meiLongwordWrite(MEI_DEBUG_DATA, auxreg5); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_RAD, 0x0); - meiPollForDbgDone(); - meiLongwordRead(MEI_DEBUG_DATA, &auxreg0); - auxreg0 = auxreg0 & 0x00ffffff; - if(auxreg0 == 0x4000) - flshcnt = flshcnt+1; - else{ - if(flshcnt == 0) - flshcnt1 = flshcnt1 +1; - else - flshcnt2 = flshcnt2 +1; - } - } - - return 1; -} - -static int meiResetCore(void) -{ - meiLongwordWrite(MEI_CONTROL, 0x1); - meiLongwordWrite(MEI_DEBUG_DEC, 0x2); - meiLongwordWrite(MEI_DEBUG_WAD, 0x31f10); - meiLongwordWrite(MEI_DEBUG_DATA, 0xf); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_WAD, 0x31f10); - meiLongwordWrite(MEI_DEBUG_DATA, 0x0); - meiPollForDbgDone(); - meiLongwordWrite(MEI_DEBUG_WAD, 0x31f00); - meiLongwordWrite(MEI_DEBUG_DATA, 0x55); - meiPollForDbgDone(); - return 1; -} - -static int meiEnalbeMailboxInt(void) -{ - u32 arc2meiintmsk; - meiLongwordRead(ARC_TO_MEI_INT_MASK, &arc2meiintmsk); - arc2meiintmsk = arc2meiintmsk | 0x1; - meiLongwordWrite(ARC_TO_MEI_INT_MASK, arc2meiintmsk); - meiLongwordWrite(MEI_CONTROL, 0x0); - return 1; -} - - - -//000002:fchang End - -static int mei_ioctl(struct inode * ino, struct file * fil, unsigned int command, unsigned long lon) -{ - int i,k; - u32 boot_loop; - u32 page_size; - u32 dest_addr; - u32 j; - u32 temp; - u32 temp2; - u16 trapsflag=0; - amazon_clreoc_pkt * current_clreoc; - struct timeval time_now; - struct timeval time_fini; - struct list_head * ptr; - amazon_mei_mib * mib_ptr; -// u16 buff[MSG_LENGTH]__attribute__ ((aligned(4))); - structpts pts; - int meierr=MEI_SUCCESS; - u16 data[12]; //used in makeCMV, to pass in payload when CMV set, ignored when CMV read. - meireg regrdwr; - meidebug debugrdwr; - amazon_mei_mib * temp_intvl; - struct sk_buff * eoc_skb; -// 603221:tc.chen start - u16 hdlc_cmd[2]; - u16 hdlc_rx_buffer[32]; - int hdlc_rx_len=0; -// 603221:tc.chen end - - int from_kernel = 0;//joelin - if (ino == (struct inode *)0) from_kernel = 1;//joelin - -// printk("\n switch.command = %i\n", command); - switch(command){ - case GET_ADSL_LINE_CODE: - pts.adslLineTableEntry_pt = (adslLineTableEntry *)kmalloc(sizeof(adslLineTableEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineTableEntry_pt, (char *)lon, sizeof(adslLineTableEntry)); - if(IS_FLAG_SET((&(pts.adslLineTableEntry_pt->flags)), LINE_CODE_FLAG)){ - pts.adslLineTableEntry_pt->adslLineCode = 2; - } - copy_to_user((char *)lon, (char *)pts.adslLineTableEntry_pt, sizeof(adslLineTableEntry)); - kfree(pts.adslLineTableEntry_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ATUC_LINE_EXT: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - pts.adslLineExtTableEntry_pt = (adslLineExtTableEntry *)kmalloc(sizeof(adslLineExtTableEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineExtTableEntry_pt, (char *)lon, sizeof(adslLineExtTableEntry)); - if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CAP_FLAG)){ - ATUC_LINE_TRANS_CAP_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 67 Index 0"); -#endif - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CAP_FLAG); - } - else{ - memcpy((&(pts.adslLineExtTableEntry_pt->adslLineTransAtucCap)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG)){ - ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 67 Index 0"); -#endif - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG); - } - else{ - memcpy((&(pts.adslLineExtTableEntry_pt->adslLineTransAtucConfig)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_ACTUAL_FLAG)){ - ATUC_LINE_TRANS_ACTUAL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 2 Address 1 Index 0"); -#endif - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_ACTUAL_FLAG); - } - else{ - memcpy((&(pts.adslLineExtTableEntry_pt->adslLineTransAtucActual)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG)){ // not supported currently -/* - LINE_GLITE_POWER_STATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 2 Address 0 Index 0"); -#endif - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG); - } - else{ - memcpy((&(pts.adslLineExtTableEntry_pt->adslLineGlitePowerState)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } -*/ - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG); - } - copy_to_user((char *)lon, (char *)pts.adslLineExtTableEntry_pt, sizeof(adslLineExtTableEntry)); - kfree(pts.adslLineTableEntry_pt); - up(&mei_sema); - break; -#endif - -#ifdef AMAZON_MEI_MIB_RFC3440 - case SET_ADSL_ATUC_LINE_EXT: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - pts.adslLineExtTableEntry_pt = (adslLineExtTableEntry *)kmalloc(sizeof(adslLineExtTableEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineExtTableEntry_pt, (char *)lon, sizeof(adslLineExtTableEntry)); - - //only adslLineTransAtucConfig can be set. - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CAP_FLAG); - if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG)){ - memcpy(data,(&(pts.adslLineExtTableEntry_pt->adslLineTransAtucConfig)), 2); - ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV_WR; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 67 Index 0"); -#endif - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG); - } - } - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_ACTUAL_FLAG); - CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG); - - copy_to_user((char *)lon, (char *)pts.adslLineExtTableEntry_pt, sizeof(adslLineExtTableEntry)); - kfree(pts.adslLineTableEntry_pt); - up(&mei_sema); - break; -#endif - - case GET_ADSL_ATUC_PHY: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslAtucPhysEntry_pt = (adslAtucPhysEntry *)kmalloc(sizeof(adslAtucPhysEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslAtucPhysEntry_pt, (char *)lon, sizeof(adslAtucPhysEntry)); - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_SER_NUM_FLAG)){ - ATUC_PHY_SER_NUM_FLAG_MAKECMV1; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 57 Index 0"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_SER_NUM_FLAG); - } - else{ - memcpy(pts.adslAtucPhysEntry_pt->serial_no, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - ATUC_PHY_SER_NUM_FLAG_MAKECMV2; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 57 Index 12"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_SER_NUM_FLAG); - } - else{ - memcpy((pts.adslAtucPhysEntry_pt->serial_no+24), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VENDOR_ID_FLAG)){ - ATUC_PHY_VENDOR_ID_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 64 Index 0"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VENDOR_ID_FLAG); - } - else{ - memcpy(pts.adslAtucPhysEntry_pt->vendor_id.vendor_id, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VER_NUM_FLAG)){ - ATUC_PHY_VER_NUM_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 58 Index 0"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VER_NUM_FLAG); - } - else{ - memcpy(pts.adslAtucPhysEntry_pt->version_no, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_STAT_FLAG)){ - pts.adslAtucPhysEntry_pt->status = CurrStatus.adslAtucCurrStatus; - } - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_OUT_PWR_FLAG)){ - ATUC_CURR_OUT_PWR_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 68 Index 5"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_OUT_PWR_FLAG); - } - else{ - memcpy((&(pts.adslAtucPhysEntry_pt->outputPwr)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_ATTR_FLAG)){ - ATUC_CURR_ATTR_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 69 Index 0"); -#endif - CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_ATTR_FLAG); - } - else{ - memcpy((&(pts.adslAtucPhysEntry_pt->attainableRate)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - copy_to_user((char *)lon, (char *)pts.adslAtucPhysEntry_pt, sizeof(adslAtucPhysEntry)); - kfree(pts.adslAtucPhysEntry_pt); - - up(&mei_sema); - break; - case GET_ADSL_ATUR_PHY: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslAturPhysEntry_pt = (adslAturPhysEntry *)kmalloc(sizeof(adslAturPhysEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslAturPhysEntry_pt, (char *)lon, sizeof(adslAturPhysEntry)); - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_SER_NUM_FLAG)){ - ATUR_PHY_SER_NUM_FLAG_MAKECMV1; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 62 Index 0"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_SER_NUM_FLAG); - } - else{ - memcpy(pts.adslAturPhysEntry_pt->serial_no, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - ATUR_PHY_SER_NUM_FLAG_MAKECMV2; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 62 Index 12"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_SER_NUM_FLAG); - } - else{ - memcpy((pts.adslAturPhysEntry_pt->serial_no+24), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VENDOR_ID_FLAG)){ - ATUR_PHY_VENDOR_ID_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 65 Index 0"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VENDOR_ID_FLAG); - } - else{ - memcpy(pts.adslAturPhysEntry_pt->vendor_id.vendor_id, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VER_NUM_FLAG)){ - ATUR_PHY_VER_NUM_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 61 Index 0"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VER_NUM_FLAG); - } - else{ - memcpy(pts.adslAturPhysEntry_pt->version_no, RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_SNRMGN_FLAG)){ - ATUR_SNRMGN_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 68 Index 4"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_SNRMGN_FLAG); - } - else{ - memcpy((&(pts.adslAturPhysEntry_pt->SnrMgn)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_ATTN_FLAG)){ - ATUR_ATTN_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 68 Index 2"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_ATTN_FLAG); - } - else{ - memcpy((&(pts.adslAturPhysEntry_pt->Attn)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_STAT_FLAG)){ - pts.adslAturPhysEntry_pt->status = CurrStatus.adslAturCurrStatus; - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_OUT_PWR_FLAG)){ - ATUR_CURR_OUT_PWR_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 69 Index 5"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_OUT_PWR_FLAG); - } - else{ - memcpy((&(pts.adslAturPhysEntry_pt->outputPwr)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_ATTR_FLAG)){ - ATUR_CURR_ATTR_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 68 Index 0"); -#endif - CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_ATTR_FLAG); - } - else{ - memcpy((&(pts.adslAturPhysEntry_pt->attainableRate)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - copy_to_user((char *)lon, (char *)pts.adslAturPhysEntry_pt, sizeof(adslAturPhysEntry)); - kfree(pts.adslAturPhysEntry_pt); - - up(&mei_sema); - break; - case GET_ADSL_ATUC_CHAN_INFO: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslAtucChanInfo_pt = (adslAtucChanInfo *)kmalloc(sizeof(adslAtucChanInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAtucChanInfo_pt, (char *)lon, sizeof(adslAtucChanInfo)); - if(IS_FLAG_SET((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_INTLV_DELAY_FLAG)){ - if((chantype.interleave!=1) || (chantype.fast==1)){ - CLR_FLAG((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_INTLV_DELAY_FLAG); - } - else{ - ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 3 Index 1"); -#endif - CLR_FLAG((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_INTLV_DELAY_FLAG); - } - else{ - memcpy((&(pts.adslAtucChanInfo_pt->interleaveDelay)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - } - if(IS_FLAG_SET((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_CURR_TX_RATE_FLAG)){ - ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 1 Index 0"); -#endif - CLR_FLAG((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_CURR_TX_RATE_FLAG); - } - else{ - pts.adslAtucChanInfo_pt->currTxRate = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - if(IS_FLAG_SET((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_PREV_TX_RATE_FLAG)){ - pts.adslAtucChanInfo_pt->prevTxRate = PrevTxRate.adslAtucChanPrevTxRate; - } - copy_to_user((char *)lon, (char *)pts.adslAtucChanInfo_pt, sizeof(adslAtucChanInfo)); - kfree(pts.adslAtucChanInfo_pt); - - up(&mei_sema); - break; - case GET_ADSL_ATUR_CHAN_INFO: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslAturChanInfo_pt = (adslAturChanInfo *)kmalloc(sizeof(adslAturChanInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAturChanInfo_pt, (char *)lon, sizeof(adslAturChanInfo)); - if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_INTLV_DELAY_FLAG)){ - if((chantype.interleave!=1) || (chantype.fast==1)){ - CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_INTLV_DELAY_FLAG); - } - else{ - ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 2 Index 1"); -#endif - CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_INTLV_DELAY_FLAG); - } - else{ - memcpy((&(pts.adslAturChanInfo_pt->interleaveDelay)), RxMessage+4, ((RxMessage[0]&0xf)*2)); - } - } - } - if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CURR_TX_RATE_FLAG)){ - ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 0 Index 0"); -#endif - CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CURR_TX_RATE_FLAG); - } - else{ - pts.adslAturChanInfo_pt->currTxRate = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_PREV_TX_RATE_FLAG)){ - pts.adslAturChanInfo_pt->prevTxRate = PrevTxRate.adslAturChanPrevTxRate; - } - if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CRC_BLK_LEN_FLAG)){ - // ? no CMV to update this - CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CRC_BLK_LEN_FLAG); - } - copy_to_user((char *)lon, (char *)pts.adslAturChanInfo_pt, sizeof(adslAturChanInfo)); - kfree(pts.adslAturChanInfo_pt); - - up(&mei_sema); - break; - case GET_ADSL_ATUC_PERF_DATA: - pts.atucPerfDataEntry_pt = (atucPerfDataEntry *)kmalloc(sizeof(atucPerfDataEntry), GFP_KERNEL); - copy_from_user((char *)pts.atucPerfDataEntry_pt, (char *)lon, sizeof(atucPerfDataEntry)); - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_LOFS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfLofs=ATUC_PERF_LOFS; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_LOSS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfLoss=ATUC_PERF_LOSS; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_ESS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfESs=ATUC_PERF_ESS; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_INITS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfInits=ATUC_PERF_INITS; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_VALID_INTVLS_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==96) - break; - } - pts.atucPerfDataEntry_pt->adslAtucPerfValidIntervals=i; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_INVALID_INTVLS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfInvalidIntervals=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_TIME_ELAPSED_FLAG)){ - do_gettimeofday(&time_now); - pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinTimeElapsed=time_now.tv_sec - (current_intvl->start_time).tv_sec; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_LOFS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinLofs=current_intvl->AtucPerfLof; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_LOSS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinLoss=current_intvl->AtucPerfLos; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_ESS_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinESs=current_intvl->AtucPerfEs; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_INIT_FLAG)){ - pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinInits=current_intvl->AtucPerfInit; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_TIME_ELAPSED_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i+=900; - } - do_gettimeofday(&time_now); - i+=time_now.tv_sec - (current_intvl->start_time).tv_sec; - if(i>=86400) - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayTimeElapsed=i-86400; - else - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayTimeElapsed=i; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_LOFS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfLof; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfLof; - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayLofs=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_LOSS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfLos; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfLos; - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayLoss=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_ESS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfEs; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfEs; - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayESs=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_INIT_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfInit; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfInit; - pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayInits=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_MON_SEC_FLAG)){ - i=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - i++; - } - if(i>=96) - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayMoniSecs=86400; - else - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayMoniSecs=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_LOFS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfLof; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLofs=j; - else - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLofs=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_LOSS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfLos; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLoss=j; - else - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLoss=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_ESS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfEs; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayESs=j; - else - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayESs=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_INITS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfInit; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayInits=j; - else - pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayInits=0; - } - - copy_to_user((char *)lon, (char *)pts.atucPerfDataEntry_pt, sizeof(atucPerfDataEntry)); - kfree(pts.atucPerfDataEntry_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ATUC_PERF_DATA_EXT: //??? CMV mapping not available - pts.atucPerfDataExtEntry_pt = (atucPerfDataExtEntry *)kmalloc(sizeof(atucPerfDataExtEntry), GFP_KERNEL); - copy_from_user((char *)pts.atucPerfDataExtEntry_pt, (char *)lon, sizeof(atucPerfDataExtEntry)); - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_FASTR_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfStatFastR=ATUC_PERF_STAT_FASTR; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_FAILED_FASTR_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfStatFailedFastR=ATUC_PERF_STAT_FAILED_FASTR; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_SESL_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfStatSesL=ATUC_PERF_STAT_SESL; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_UASL_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfStatUasL=ATUC_PERF_STAT_UASL; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_FASTR_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinFastR=current_intvl->AtucPerfStatFastR; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_FAILED_FASTR_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinFailedFastR=current_intvl->AtucPerfStatFailedFastR; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_SESL_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinSesL=current_intvl->AtucPerfStatSesL; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_UASL_FLAG)){ - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinUasL=current_intvl->AtucPerfStatUasL; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_FASTR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatFastR; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfStatFastR; - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DayFastR=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_FAILED_FASTR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatFailedFastR; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfStatFailedFastR; - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DayFailedFastR=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_SESL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatSesL; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfStatSesL; - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DaySesL=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_UASL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatUasL; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AtucPerfStatUasL; - pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DayUasL=j; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_FASTR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatFastR; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFastR=j; - else - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFastR=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_FAILED_FASTR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatFailedFastR; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFailedFastR=j; - else - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFailedFastR=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_SESL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatSesL; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DaySesL=j; - else - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DaySesL=0; - } - if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_UASL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AtucPerfStatUasL; - i++; - if(i==96) - break; - } - if(i==96) - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayUasL=j; - else - pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayUasL=0; - } - copy_to_user((char *)lon, (char *)pts.atucPerfDataExtEntry_pt, sizeof(atucPerfDataExtEntry)); - kfree(pts.atucPerfDataExtEntry_pt); - break; -#endif - case GET_ADSL_ATUR_PERF_DATA: - pts.aturPerfDataEntry_pt = (aturPerfDataEntry *)kmalloc(sizeof(aturPerfDataEntry), GFP_KERNEL); - copy_from_user((char *)pts.aturPerfDataEntry_pt, (char *)lon, sizeof(aturPerfDataEntry)); - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_LOFS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfLofs=ATUR_PERF_LOFS; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_LOSS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfLoss=ATUR_PERF_LOSS; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_LPR_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfLprs=ATUR_PERF_LPR; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_ESS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfESs=ATUR_PERF_ESS; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_VALID_INTVLS_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==96) - break; - } - pts.aturPerfDataEntry_pt->adslAturPerfValidIntervals=i; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_INVALID_INTVLS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfInvalidIntervals=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_TIME_ELAPSED_FLAG)){ - do_gettimeofday(&time_now); - pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinTimeElapsed=time_now.tv_sec - (current_intvl->start_time).tv_sec; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_LOFS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinLofs=current_intvl->AturPerfLof; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_LOSS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinLoss=current_intvl->AturPerfLos; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_LPR_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinLprs=current_intvl->AturPerfLpr; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_ESS_FLAG)){ - pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinESs=current_intvl->AturPerfEs; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_TIME_ELAPSED_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i+=900; - } - do_gettimeofday(&time_now); - i+=time_now.tv_sec - (current_intvl->start_time).tv_sec; - if(i>=86400) - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayTimeElapsed=i-86400; - else - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayTimeElapsed=i; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_LOFS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLof; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfLof; - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayLofs=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_LOSS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLos; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfLos; - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayLoss=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_LPR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLpr; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfLpr; - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayLprs=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_ESS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfEs; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfEs; - pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayESs=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_MON_SEC_FLAG)){ - i=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - i++; - } - if(i>=96) - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayMoniSecs=86400; - else - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayMoniSecs=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_LOFS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLof; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLofs=j; - else - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLofs=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_LOSS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLos; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLoss=j; - else - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLoss=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_LPR_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfLpr; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLprs=j; - else - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLprs=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_ESS_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfEs; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayESs=j; - else - pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayESs=0; - } - - copy_to_user((char *)lon, (char *)pts.aturPerfDataEntry_pt, sizeof(aturPerfDataEntry)); - kfree(pts.aturPerfDataEntry_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ATUR_PERF_DATA_EXT: - pts.aturPerfDataExtEntry_pt = (aturPerfDataExtEntry *)kmalloc(sizeof(aturPerfDataExtEntry), GFP_KERNEL); - copy_from_user((char *)pts.aturPerfDataExtEntry_pt, (char *)lon, sizeof(aturPerfDataExtEntry)); - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_STAT_SESL_FLAG)){ - pts.aturPerfDataExtEntry_pt->adslAturPerfStatSesL=ATUR_PERF_STAT_SESL; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_STAT_UASL_FLAG)){ - pts.aturPerfDataExtEntry_pt->adslAturPerfStatUasL=ATUR_PERF_STAT_UASL; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_15MIN_SESL_FLAG)){ - pts.aturPerfDataExtEntry_pt->adslAturPerfCurr15MinSesL=current_intvl->AturPerfStatSesL; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_15MIN_UASL_FLAG)){ - pts.aturPerfDataExtEntry_pt->adslAturPerfCurr15MinUasL=current_intvl->AturPerfStatUasL; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_1DAY_SESL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfStatSesL; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfStatSesL; - pts.aturPerfDataExtEntry_pt->adslAturPerfCurr1DaySesL=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_1DAY_UASL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfStatUasL; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturPerfStatUasL; - pts.aturPerfDataExtEntry_pt->adslAturPerfCurr1DayUasL=j; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_PREV_1DAY_SESL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfStatSesL; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DaySesL=j; - else - pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DaySesL=0; - } - if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_PREV_1DAY_UASL_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturPerfStatUasL; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DayUasL=j; - else - pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DayUasL=0; - } - copy_to_user((char *)lon, (char *)pts.aturPerfDataExtEntry_pt, sizeof(aturPerfDataExtEntry)); - kfree(pts.aturPerfDataExtEntry_pt); - break; -#endif - case GET_ADSL_ATUC_INTVL_INFO: - pts.adslAtucIntvlInfo_pt = (adslAtucIntvlInfo *)kmalloc(sizeof(adslAtucIntvlInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAtucIntvlInfo_pt, (char *)lon, sizeof(adslAtucIntvlInfo)); - - if(pts.adslAtucIntvlInfo_pt->IntervalNumber <1){ - pts.adslAtucIntvlInfo_pt->intervalLOF = ATUC_PERF_LOFS; - pts.adslAtucIntvlInfo_pt->intervalLOS = ATUC_PERF_LOSS; - pts.adslAtucIntvlInfo_pt->intervalES = ATUC_PERF_ESS; - pts.adslAtucIntvlInfo_pt->intervalInits = ATUC_PERF_INITS; - pts.adslAtucIntvlInfo_pt->intervalValidData = 1; - } - else{ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==pts.adslAtucIntvlInfo_pt->IntervalNumber){ - temp_intvl = list_entry(ptr, amazon_mei_mib, list); - pts.adslAtucIntvlInfo_pt->intervalLOF = temp_intvl->AtucPerfLof; - pts.adslAtucIntvlInfo_pt->intervalLOS = temp_intvl->AtucPerfLos; - pts.adslAtucIntvlInfo_pt->intervalES = temp_intvl->AtucPerfEs; - pts.adslAtucIntvlInfo_pt->intervalInits = temp_intvl->AtucPerfInit; - pts.adslAtucIntvlInfo_pt->intervalValidData = 1; - break; - } - } - if(ptr==&interval_list){ - pts.adslAtucIntvlInfo_pt->intervalValidData = 0; - pts.adslAtucIntvlInfo_pt->flags = 0; - pts.adslAtucIntvlInfo_pt->intervalLOF = 0; - pts.adslAtucIntvlInfo_pt->intervalLOS = 0; - pts.adslAtucIntvlInfo_pt->intervalES = 0; - pts.adslAtucIntvlInfo_pt->intervalInits = 0; - } - } - - copy_to_user((char *)lon, (char *)pts.adslAtucIntvlInfo_pt, sizeof(adslAtucIntvlInfo)); - kfree(pts.adslAtucIntvlInfo_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ATUC_INTVL_EXT_INFO: - pts.adslAtucInvtlExtInfo_pt = (adslAtucInvtlExtInfo *)kmalloc(sizeof(adslAtucInvtlExtInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAtucInvtlExtInfo_pt, (char *)lon, sizeof(adslAtucInvtlExtInfo)); - if(pts.adslAtucInvtlExtInfo_pt->IntervalNumber <1){ - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFastR = ATUC_PERF_STAT_FASTR; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFailedFastR = ATUC_PERF_STAT_FAILED_FASTR; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalSesL = ATUC_PERF_STAT_SESL; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalUasL = ATUC_PERF_STAT_UASL; -// pts.adslAtucInvtlExtInfo_pt->intervalValidData = 1; - } - else{ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==pts.adslAtucInvtlExtInfo_pt->IntervalNumber){ - temp_intvl = list_entry(ptr, amazon_mei_mib, list); - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFastR = temp_intvl->AtucPerfStatFastR; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFailedFastR = temp_intvl->AtucPerfStatFailedFastR; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalSesL = temp_intvl->AtucPerfStatSesL; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalUasL = temp_intvl->AtucPerfStatUasL; -// pts.adslAtucInvtlExtInfo_pt->intervalValidData = 1; - break; - } - } - if(ptr==&interval_list){ -// pts.adslAtucInvtlExtInfo_pt->intervalValidData = 0; - pts.adslAtucInvtlExtInfo_pt->flags = 0; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFastR = 0; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFailedFastR = 0; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalSesL = 0; - pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalUasL = 0; - } - } - copy_to_user((char *)lon, (char *)pts.adslAtucInvtlExtInfo_pt, sizeof(adslAtucInvtlExtInfo)); - kfree(pts.adslAtucInvtlExtInfo_pt); - break; -#endif - case GET_ADSL_ATUR_INTVL_INFO: - pts.adslAturIntvlInfo_pt = (adslAturIntvlInfo *)kmalloc(sizeof(adslAturIntvlInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAturIntvlInfo_pt, (char *)lon, sizeof(adslAturIntvlInfo)); - - if(pts.adslAturIntvlInfo_pt->IntervalNumber <1){ - pts.adslAturIntvlInfo_pt->intervalLOF = ATUR_PERF_LOFS; - pts.adslAturIntvlInfo_pt->intervalLOS = ATUR_PERF_LOSS; - pts.adslAturIntvlInfo_pt->intervalES = ATUR_PERF_ESS; - pts.adslAturIntvlInfo_pt->intervalLPR = ATUR_PERF_LPR; - pts.adslAturIntvlInfo_pt->intervalValidData = 1; - } - else{ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==pts.adslAturIntvlInfo_pt->IntervalNumber){ - temp_intvl = list_entry(ptr, amazon_mei_mib, list); - pts.adslAturIntvlInfo_pt->intervalLOF = temp_intvl->AturPerfLof; - pts.adslAturIntvlInfo_pt->intervalLOS = temp_intvl->AturPerfLos; - pts.adslAturIntvlInfo_pt->intervalES = temp_intvl->AturPerfEs; - pts.adslAturIntvlInfo_pt->intervalLPR = temp_intvl->AturPerfLpr; - pts.adslAturIntvlInfo_pt->intervalValidData = 1; - break; - } - } - if(ptr==&interval_list){ - pts.adslAturIntvlInfo_pt->intervalValidData = 0; - pts.adslAturIntvlInfo_pt->flags = 0; - pts.adslAturIntvlInfo_pt->intervalLOF = 0; - pts.adslAturIntvlInfo_pt->intervalLOS = 0; - pts.adslAturIntvlInfo_pt->intervalES = 0; - pts.adslAturIntvlInfo_pt->intervalLPR = 0; - } - } - - copy_to_user((char *)lon, (char *)pts.adslAturIntvlInfo_pt, sizeof(adslAturIntvlInfo)); - kfree(pts.adslAturIntvlInfo_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ATUR_INTVL_EXT_INFO: - pts.adslAturInvtlExtInfo_pt = (adslAturInvtlExtInfo *)kmalloc(sizeof(adslAturInvtlExtInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAturInvtlExtInfo_pt, (char *)lon, sizeof(adslAturInvtlExtInfo)); - - if(pts.adslAturInvtlExtInfo_pt->IntervalNumber <1){ - pts.adslAturInvtlExtInfo_pt->adslAturIntervalSesL = ATUR_PERF_STAT_SESL; - pts.adslAturInvtlExtInfo_pt->adslAturIntervalUasL = ATUR_PERF_STAT_UASL; -// pts.adslAturInvtlExtInfo_pt->intervalValidData = 1; - } - else{ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==pts.adslAturInvtlExtInfo_pt->IntervalNumber){ - temp_intvl = list_entry(ptr, amazon_mei_mib, list); - pts.adslAturInvtlExtInfo_pt->adslAturIntervalSesL = temp_intvl->AturPerfStatSesL; - pts.adslAturInvtlExtInfo_pt->adslAturIntervalUasL = temp_intvl->AturPerfStatUasL; -// pts.adslAturInvtlExtInfo_pt->intervalValidData = 1; - break; - } - } - if(ptr==&interval_list){ -// pts.adslAturInvtlExtInfo_pt->intervalValidData = 0; - pts.adslAturInvtlExtInfo_pt->flags = 0; - pts.adslAturInvtlExtInfo_pt->adslAturIntervalSesL = 0; - pts.adslAturInvtlExtInfo_pt->adslAturIntervalUasL = 0; - } - } - - copy_to_user((char *)lon, (char *)pts.adslAturInvtlExtInfo_pt, sizeof(adslAturInvtlExtInfo)); - kfree(pts.adslAturInvtlExtInfo_pt); - break; -#endif - case GET_ADSL_ATUC_CHAN_PERF_DATA: - pts.atucChannelPerfDataEntry_pt = (atucChannelPerfDataEntry *)kmalloc(sizeof(atucChannelPerfDataEntry), GFP_KERNEL); - copy_from_user((char *)pts.atucChannelPerfDataEntry_pt, (char *)lon, sizeof(atucChannelPerfDataEntry)); - - pts.atucChannelPerfDataEntry_pt->flags = 0; - - copy_to_user((char *)lon, (char *)pts.atucChannelPerfDataEntry_pt, sizeof(atucChannelPerfDataEntry)); - kfree(pts.atucChannelPerfDataEntry_pt); - break; - case GET_ADSL_ATUR_CHAN_PERF_DATA: - pts.aturChannelPerfDataEntry_pt = (aturChannelPerfDataEntry *)kmalloc(sizeof(aturChannelPerfDataEntry), GFP_KERNEL); - copy_from_user((char *)pts.aturChannelPerfDataEntry_pt, (char *)lon, sizeof(aturChannelPerfDataEntry)); - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_RECV_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanReceivedBlks=ATUR_CHAN_RECV_BLK; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_TX_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanTransmittedBlks=ATUR_CHAN_TX_BLK; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_CORR_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanCorrectedBlks=ATUR_CHAN_CORR_BLK; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_UNCORR_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanUncorrectBlks=ATUR_CHAN_UNCORR_BLK; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_VALID_INTVL_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==96) - break; - } - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfValidIntervals=i; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_INVALID_INTVL_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfInvalidIntervals=0; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG)){ - do_gettimeofday(&time_now); - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinTimeElapsed=time_now.tv_sec - (current_intvl->start_time).tv_sec; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinReceivedBlks=current_intvl->AturChanPerfRxBlk; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinTransmittedBlks=current_intvl->AturChanPerfTxBlk; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinCorrectedBlks=current_intvl->AturChanPerfCorrBlk; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG)){ - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinUncorrectBlks=current_intvl->AturChanPerfUncorrBlk; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG)){ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i+=900; - } - do_gettimeofday(&time_now); - i+=time_now.tv_sec - (current_intvl->start_time).tv_sec; - if(i>=86400) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayTimeElapsed=i-86400; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayTimeElapsed=i; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfRxBlk; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturChanPerfRxBlk; - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayReceivedBlks=j; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfTxBlk; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturChanPerfTxBlk; - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayTransmittedBlks=j; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfCorrBlk; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturChanPerfCorrBlk; - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayCorrectedBlks=j; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfUncorrBlk; - i++; - if(i==96) - j=0; - } - j+=current_intvl->AturChanPerfUncorrBlk; - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayUncorrectBlks=j; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG)){ - i=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - i++; - } - if(i>=96) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayMoniSecs=86400; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayMoniSecs=0; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfRxBlk; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayReceivedBlks=j; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayReceivedBlks=0; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_TRANS_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfTxBlk; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayTransmittedBlks=j; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayTransmittedBlks=0; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfCorrBlk; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayCorrectedBlks=j; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayCorrectedBlks=0; - } - if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG)){ - i=0; - j=0; - for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){ - mib_ptr = list_entry(ptr, amazon_mei_mib, list); - j+=mib_ptr->AturChanPerfUncorrBlk; - i++; - if(i==96) - break; - } - if(i==96) - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayUncorrectBlks=j; - else - pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayUncorrectBlks=0; - } - - copy_to_user((char *)lon, (char *)pts.aturChannelPerfDataEntry_pt, sizeof(aturChannelPerfDataEntry)); - kfree(pts.aturChannelPerfDataEntry_pt); - break; - case GET_ADSL_ATUC_CHAN_INTVL_INFO: - pts.adslAtucChanIntvlInfo_pt = (adslAtucChanIntvlInfo *)kmalloc(sizeof(adslAtucChanIntvlInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAtucChanIntvlInfo_pt, (char *)lon, sizeof(adslAtucChanIntvlInfo)); - - pts.adslAtucChanIntvlInfo_pt->flags = 0; - - copy_to_user((char *)lon, (char *)pts.adslAtucChanIntvlInfo_pt, sizeof(adslAtucChanIntvlInfo)); - kfree(pts.adslAtucChanIntvlInfo_pt); - break; - case GET_ADSL_ATUR_CHAN_INTVL_INFO: - pts.adslAturChanIntvlInfo_pt = (adslAturChanIntvlInfo *)kmalloc(sizeof(adslAturChanIntvlInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslAturChanIntvlInfo_pt, (char *)lon, sizeof(adslAturChanIntvlInfo)); - - if(pts.adslAturChanIntvlInfo_pt->IntervalNumber <1){ - pts.adslAturChanIntvlInfo_pt->chanIntervalRecvdBlks = ATUR_CHAN_RECV_BLK; - pts.adslAturChanIntvlInfo_pt->chanIntervalXmitBlks = ATUR_CHAN_TX_BLK; - pts.adslAturChanIntvlInfo_pt->chanIntervalCorrectedBlks = ATUR_CHAN_CORR_BLK; - pts.adslAturChanIntvlInfo_pt->chanIntervalUncorrectBlks = ATUR_CHAN_UNCORR_BLK; - pts.adslAturChanIntvlInfo_pt->intervalValidData = 1; - } - else{ - i=0; - for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){ - i++; - if(i==pts.adslAturChanIntvlInfo_pt->IntervalNumber){ - temp_intvl = list_entry(ptr, amazon_mei_mib, list); - pts.adslAturChanIntvlInfo_pt->chanIntervalRecvdBlks = temp_intvl->AturChanPerfRxBlk; - pts.adslAturChanIntvlInfo_pt->chanIntervalXmitBlks = temp_intvl->AturChanPerfTxBlk; - pts.adslAturChanIntvlInfo_pt->chanIntervalCorrectedBlks = temp_intvl->AturChanPerfCorrBlk; - pts.adslAturChanIntvlInfo_pt->chanIntervalUncorrectBlks = temp_intvl->AturChanPerfUncorrBlk; - pts.adslAturChanIntvlInfo_pt->intervalValidData = 1; - break; - } - } - if(ptr==&interval_list){ - pts.adslAturChanIntvlInfo_pt->intervalValidData = 0; - pts.adslAturChanIntvlInfo_pt->flags = 0; - } - } - - copy_to_user((char *)lon, (char *)pts.adslAturChanIntvlInfo_pt, sizeof(adslAturChanIntvlInfo)); - kfree(pts.adslAturChanIntvlInfo_pt); - break; - case GET_ADSL_ALRM_CONF_PROF: - pts.adslLineAlarmConfProfileEntry_pt = (adslLineAlarmConfProfileEntry *)kmalloc(sizeof(adslLineAlarmConfProfileEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineAlarmConfProfileEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileEntry)); - - strncpy(pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileName, AlarmConfProfile.adslLineAlarmConfProfileName, 32); - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOFS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLofs=AlarmConfProfile.adslAtucThresh15MinLofs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOSS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLoss=AlarmConfProfile.adslAtucThresh15MinLoss; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_ESS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinESs=AlarmConfProfile.adslAtucThresh15MinESs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEUP_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateUp=AlarmConfProfile.adslAtucThreshFastRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEUP_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateUp=AlarmConfProfile.adslAtucThreshInterleaveRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEDOWN_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateDown=AlarmConfProfile.adslAtucThreshFastRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateDown=AlarmConfProfile.adslAtucThreshInterleaveRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAtucInitFailureTrapEnable=AlarmConfProfile.adslAtucInitFailureTrapEnable; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOFS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLofs=AlarmConfProfile.adslAturThresh15MinLofs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOSS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLoss=AlarmConfProfile.adslAturThresh15MinLoss; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LPRS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLprs=AlarmConfProfile.adslAturThresh15MinLprs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_ESS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinESs=AlarmConfProfile.adslAturThresh15MinESs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEUP_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateUp=AlarmConfProfile.adslAturThreshFastRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEUP_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateUp=AlarmConfProfile.adslAturThreshInterleaveRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEDOWN_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateDown=AlarmConfProfile.adslAturThreshFastRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateDown=AlarmConfProfile.adslAturThreshInterleaveRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG)){ - pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileRowStatus=AlarmConfProfile.adslLineAlarmConfProfileRowStatus; - } - copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileEntry_pt, sizeof(adslLineAlarmConfProfileEntry)); - kfree(pts.adslLineAlarmConfProfileEntry_pt); - break; -#ifdef AMAZON_MEI_MIB_RFC3440 - case GET_ADSL_ALRM_CONF_PROF_EXT: - pts.adslLineAlarmConfProfileExtEntry_pt = (adslLineAlarmConfProfileExtEntry *)kmalloc(sizeof(adslLineAlarmConfProfileExtEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineAlarmConfProfileExtEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileExtEntry)); - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_FAILED_FASTR_FLAG)){ - pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinFailedFastR=AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_SESL_FLAG)){ - pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinSesL=AlarmConfProfileExt.adslAtucThreshold15MinSesL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_UASL_FLAG)){ - pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinUasL=AlarmConfProfileExt.adslAtucThreshold15MinUasL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_SESL_FLAG)){ - pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinSesL=AlarmConfProfileExt.adslAturThreshold15MinSesL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_UASL_FLAG)){ - pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinUasL=AlarmConfProfileExt.adslAturThreshold15MinUasL; - } - copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileExtEntry_pt, sizeof(adslLineAlarmConfProfileExtEntry)); - kfree(pts.adslLineAlarmConfProfileExtEntry_pt); - break; -#endif - case SET_ADSL_ALRM_CONF_PROF: - pts.adslLineAlarmConfProfileEntry_pt = (adslLineAlarmConfProfileEntry *)kmalloc(sizeof(adslLineAlarmConfProfileEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineAlarmConfProfileEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileEntry)); - - strncpy(AlarmConfProfile.adslLineAlarmConfProfileName, pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileName, 32); - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOFS_FLAG)){ - AlarmConfProfile.adslAtucThresh15MinLofs=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLofs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOSS_FLAG)){ - AlarmConfProfile.adslAtucThresh15MinLoss=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLoss; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_ESS_FLAG)){ - AlarmConfProfile.adslAtucThresh15MinESs=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinESs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEUP_FLAG)){ - AlarmConfProfile.adslAtucThreshFastRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEUP_FLAG)){ - AlarmConfProfile.adslAtucThreshInterleaveRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEDOWN_FLAG)){ - AlarmConfProfile.adslAtucThreshFastRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG)){ - AlarmConfProfile.adslAtucThreshInterleaveRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG)){ - AlarmConfProfile.adslAtucInitFailureTrapEnable=pts.adslLineAlarmConfProfileEntry_pt->adslAtucInitFailureTrapEnable; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOFS_FLAG)){ - AlarmConfProfile.adslAturThresh15MinLofs=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLofs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOSS_FLAG)){ - AlarmConfProfile.adslAturThresh15MinLoss=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLoss; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LPRS_FLAG)){ - AlarmConfProfile.adslAturThresh15MinLprs=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLprs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_ESS_FLAG)){ - AlarmConfProfile.adslAturThresh15MinESs=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinESs; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEUP_FLAG)){ - AlarmConfProfile.adslAturThreshFastRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEUP_FLAG)){ - AlarmConfProfile.adslAturThreshInterleaveRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateUp; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEDOWN_FLAG)){ - AlarmConfProfile.adslAturThreshFastRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG)){ - AlarmConfProfile.adslAturThreshInterleaveRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateDown; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG)){ - AlarmConfProfile.adslLineAlarmConfProfileRowStatus=pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileRowStatus; - } - copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileEntry_pt, sizeof(adslLineAlarmConfProfileEntry)); - kfree(pts.adslLineAlarmConfProfileEntry_pt); - break; - -#ifdef AMAZON_MEI_MIB_RFC3440 - case SET_ADSL_ALRM_CONF_PROF_EXT: - pts.adslLineAlarmConfProfileExtEntry_pt = (adslLineAlarmConfProfileExtEntry *)kmalloc(sizeof(adslLineAlarmConfProfileExtEntry), GFP_KERNEL); - copy_from_user((char *)pts.adslLineAlarmConfProfileExtEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileExtEntry)); - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_FAILED_FASTR_FLAG)){ - AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR=pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinFailedFastR; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_SESL_FLAG)){ - AlarmConfProfileExt.adslAtucThreshold15MinSesL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinSesL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_UASL_FLAG)){ - AlarmConfProfileExt.adslAtucThreshold15MinUasL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinUasL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_SESL_FLAG)){ - AlarmConfProfileExt.adslAturThreshold15MinSesL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinSesL; - } - if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_UASL_FLAG)){ - AlarmConfProfileExt.adslAturThreshold15MinUasL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinUasL; - } - copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileExtEntry_pt, sizeof(adslLineAlarmConfProfileExtEntry)); - kfree(pts.adslLineAlarmConfProfileExtEntry_pt); - break; -#endif - - case ADSL_ATUR_TRAPS: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - trapsflag=0; - if(AlarmConfProfile.adslAtucThresh15MinLofs!=0 && current_intvl->AtucPerfLof>=AlarmConfProfile.adslAtucThresh15MinLofs) - trapsflag|=ATUC_PERF_LOFS_THRESH_FLAG; - if(AlarmConfProfile.adslAtucThresh15MinLoss!=0 && current_intvl->AtucPerfLos>=AlarmConfProfile.adslAtucThresh15MinLoss) - trapsflag|=ATUC_PERF_LOSS_THRESH_FLAG; - if(AlarmConfProfile.adslAtucThresh15MinESs!=0 && current_intvl->AtucPerfEs>=AlarmConfProfile.adslAtucThresh15MinESs) - trapsflag|=ATUC_PERF_ESS_THRESH_FLAG; - if(chantype.fast==1){ - if(AlarmConfProfile.adslAtucThreshFastRateUp!=0 || AlarmConfProfile.adslAtucThreshFastRateDown!=0){ - ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 1 Index 0"); -#endif - } - else{ - temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - if((AlarmConfProfile.adslAtucThreshFastRateUp!=0) && (temp>=PrevTxRate.adslAtucChanPrevTxRate+AlarmConfProfile.adslAtucThreshFastRateUp)){ - trapsflag|=ATUC_RATE_CHANGE_FLAG; - PrevTxRate.adslAtucChanPrevTxRate = temp; - } - if((AlarmConfProfile.adslAtucThreshFastRateDown!=0) && (temp<=PrevTxRate.adslAtucChanPrevTxRate-AlarmConfProfile.adslAtucThreshFastRateDown)){ - trapsflag|=ATUC_RATE_CHANGE_FLAG; - PrevTxRate.adslAtucChanPrevTxRate = temp; - } - } - } - } - if(chantype.interleave==1){ - if(AlarmConfProfile.adslAtucThreshInterleaveRateUp!=0 || AlarmConfProfile.adslAtucThreshInterleaveRateDown!=0){ - ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 1 Index 0"); -#endif - } - else{ - temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - if((AlarmConfProfile.adslAtucThreshInterleaveRateUp!=0) && (temp>=PrevTxRate.adslAtucChanPrevTxRate+AlarmConfProfile.adslAtucThreshInterleaveRateUp)){ - trapsflag|=ATUC_RATE_CHANGE_FLAG; - PrevTxRate.adslAtucChanPrevTxRate = temp; - } - if((AlarmConfProfile.adslAtucThreshInterleaveRateDown!=0) && (temp<=PrevTxRate.adslAtucChanPrevTxRate-AlarmConfProfile.adslAtucThreshInterleaveRateDown)){ - trapsflag|=ATUC_RATE_CHANGE_FLAG; - PrevTxRate.adslAtucChanPrevTxRate = temp; - } - } - } - } - if(AlarmConfProfile.adslAturThresh15MinLofs!=0 && current_intvl->AturPerfLof>=AlarmConfProfile.adslAturThresh15MinLofs) - trapsflag|=ATUR_PERF_LOFS_THRESH_FLAG; - if(AlarmConfProfile.adslAturThresh15MinLoss!=0 && current_intvl->AturPerfLos>=AlarmConfProfile.adslAturThresh15MinLoss) - trapsflag|=ATUR_PERF_LOSS_THRESH_FLAG; - if(AlarmConfProfile.adslAturThresh15MinLprs!=0 && current_intvl->AturPerfLpr>=AlarmConfProfile.adslAturThresh15MinLprs) - trapsflag|=ATUR_PERF_LPRS_THRESH_FLAG; - if(AlarmConfProfile.adslAturThresh15MinESs!=0 && current_intvl->AturPerfEs>=AlarmConfProfile.adslAturThresh15MinESs) - trapsflag|=ATUR_PERF_ESS_THRESH_FLAG; - if(chantype.fast==1){ - if(AlarmConfProfile.adslAturThreshFastRateUp!=0 || AlarmConfProfile.adslAturThreshFastRateDown!=0){ - ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 0 Index 0"); -#endif - } - else{ - temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - if((AlarmConfProfile.adslAturThreshFastRateUp!=0) && (temp>=PrevTxRate.adslAturChanPrevTxRate+AlarmConfProfile.adslAturThreshFastRateUp)){ - trapsflag|=ATUR_RATE_CHANGE_FLAG; - PrevTxRate.adslAturChanPrevTxRate = temp; - } - if((AlarmConfProfile.adslAturThreshFastRateDown!=0) && (temp<=PrevTxRate.adslAturChanPrevTxRate-AlarmConfProfile.adslAturThreshFastRateDown)){ - trapsflag|=ATUR_RATE_CHANGE_FLAG; - PrevTxRate.adslAturChanPrevTxRate = temp; - } - } - } - } - if(chantype.interleave==1){ - if(AlarmConfProfile.adslAturThreshInterleaveRateUp!=0 || AlarmConfProfile.adslAturThreshInterleaveRateDown!=0){ - ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 6 Address 0 Index 0"); -#endif - } - else{ - temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - if((AlarmConfProfile.adslAturThreshInterleaveRateUp!=0) && (temp>=PrevTxRate.adslAturChanPrevTxRate+AlarmConfProfile.adslAturThreshInterleaveRateUp)){ - trapsflag|=ATUR_RATE_CHANGE_FLAG; - PrevTxRate.adslAturChanPrevTxRate = temp; - } - if((AlarmConfProfile.adslAturThreshInterleaveRateDown!=0) && (temp<=PrevTxRate.adslAturChanPrevTxRate-AlarmConfProfile.adslAturThreshInterleaveRateDown)){ - trapsflag|=ATUR_RATE_CHANGE_FLAG; - PrevTxRate.adslAturChanPrevTxRate = temp; - } - } - } - } - copy_to_user((char *)lon, (char *)(&trapsflag), 2); - - up(&mei_sema); - break; - -#ifdef AMAZON_MEI_MIB_RFC3440 - case ADSL_ATUR_EXT_TRAPS: - trapsflag=0; - if(AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR!=0 && current_intvl->AtucPerfStatFailedFastR>=AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR) - trapsflag|=ATUC_15MIN_FAILED_FASTR_TRAP_FLAG; - if(AlarmConfProfileExt.adslAtucThreshold15MinSesL!=0 && current_intvl->AtucPerfStatSesL>=AlarmConfProfileExt.adslAtucThreshold15MinSesL) - trapsflag|=ATUC_15MIN_SESL_TRAP_FLAG; - if(AlarmConfProfileExt.adslAtucThreshold15MinUasL!=0 && current_intvl->AtucPerfStatUasL>=AlarmConfProfileExt.adslAtucThreshold15MinUasL) - trapsflag|=ATUC_15MIN_UASL_TRAP_FLAG; - if(AlarmConfProfileExt.adslAturThreshold15MinSesL!=0 && current_intvl->AturPerfStatSesL>=AlarmConfProfileExt.adslAturThreshold15MinSesL) - trapsflag|=ATUR_15MIN_SESL_TRAP_FLAG; - if(AlarmConfProfileExt.adslAturThreshold15MinUasL!=0 && current_intvl->AturPerfStatUasL>=AlarmConfProfileExt.adslAturThreshold15MinUasL) - trapsflag|=ATUR_15MIN_UASL_TRAP_FLAG; - copy_to_user((char *)lon, (char *)(&trapsflag), 2); - break; -#endif - -// 603221:tc.chen start - case GET_ADSL_LINE_STATUS: - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslLineStatusInfo_pt = (adslLineStatusInfo *)kmalloc(sizeof(adslLineStatusInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslLineStatusInfo_pt, (char *)lon, sizeof(adslLineStatusInfo)); - - if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_MODEM_STATUS_FLAG)){ - LINE_STAT_MODEM_STATUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group STAT Address 0 Index 0"); -#endif - pts.adslLineStatusInfo_pt->adslModemStatus = 0; - } - else{ - pts.adslLineStatusInfo_pt->adslModemStatus = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_MODE_SEL_FLAG)){ - LINE_STAT_MODE_SEL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group STAT Address 1 Index 0"); -#endif - pts.adslLineStatusInfo_pt->adslModeSelected = 0; - } - else{ - pts.adslLineStatusInfo_pt->adslModeSelected = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_TRELLCOD_ENABLE_FLAG)){ - LINE_STAT_TRELLCOD_ENABLE_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group OPTN Address 2 Index 0"); -#endif - pts.adslLineStatusInfo_pt->adslTrellisCodeEnable = 0; - } - else{ - - pts.adslLineStatusInfo_pt->adslTrellisCodeEnable = (RxMessage[4]>>13)&0x1==0x1?0:1; - } - } - - if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_LATENCY_FLAG)){ - LINE_STAT_LATENCY_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group STAT Address 12 Index 0"); -#endif - pts.adslLineStatusInfo_pt->adslLatency = 0; - } - else{ - pts.adslLineStatusInfo_pt->adslLatency = RxMessage[4]; - } - } - - copy_to_user((char *)lon, (char *)pts.adslLineStatusInfo_pt, sizeof(adslLineStatusInfo)); - kfree(pts.adslLineStatusInfo_pt); - - up(&mei_sema); - break; - - - case GET_ADSL_LINE_RATE: - if (showtime!=1) - return -ERESTARTSYS; - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslLineRateInfo_pt = (adslLineRateInfo *)kmalloc(sizeof(adslLineRateInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslLineRateInfo_pt, (char *)lon, sizeof(adslLineRateInfo)); - - if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_DATA_RATEDS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - if (chantype.interleave) - LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP0_MAKECMV; - else - LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP1_MAKECMV; - - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group RATE Address 1 Index 0"); -#endif - pts.adslLineRateInfo_pt->adslDataRateds = 0; - } - else{ - pts.adslLineRateInfo_pt->adslDataRateds = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - }else // adsl 2/2+ - { - unsigned long Mp,Lp,Tp,Rp,Kp,Bpn,DataRate,DataRate_remain; - Mp=Lp=Tp=Rp=Kp=Bpn=DataRate=DataRate_remain=0; - //// up stream data rate - - if (chantype.interleave) - { - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 25 Index 0"); -#endif - Lp = 0; - }else - Lp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 23 Index 0"); -#endif - Rp = 0; - }else - Rp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 24 Index 0"); -#endif - Mp = 0; - }else - Mp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 26 Index 0"); -#endif - Tp = 0; - }else - Tp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 28 Index 0"); -#endif - Kp = 0; - }else - { - Kp=RxMessage[4]+ RxMessage[5]+1; - Bpn=RxMessage[4]+ RxMessage[5]; - } - }else - { - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 25 Index 1"); -#endif - Lp = 0; - }else - Lp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 23 Index 1"); -#endif - Rp = 0; - }else - Rp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 24 Index 1"); -#endif - Mp = 0; - }else - Mp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 26 Index 1"); -#endif - Tp = 0; - }else - Tp=RxMessage[4]; - - LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 28 Index 2"); -#endif - Kp = 0; - }else - { - Kp=RxMessage[4]+ RxMessage[5]+1; - Bpn=RxMessage[4]+ RxMessage[5]; - } - } - DataRate=((Tp*(Bpn+1)-1)*Mp*Lp*4)/(Tp*(Kp*Mp+Rp)); - //DataRate_remain=((((Tp*(Bpn+1)-1)*Mp*Lp*4)%(Tp*(Kp*Mp+Rp)))*1000)/(Tp*(Kp*Mp+Rp)); - //pts.adslLineRateInfo_pt->adslDataRateds = DataRate * 1000 + DataRate_remain; - pts.adslLineRateInfo_pt->adslDataRateds = DataRate; - } - } - - if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_DATA_RATEUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - if (chantype.interleave) - LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP0_MAKECMV; - else - LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP1_MAKECMV; - - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ - #ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group RATE Address 0 Index 0"); - #endif - pts.adslLineRateInfo_pt->adslDataRateus = 0; - } - else{ - pts.adslLineRateInfo_pt->adslDataRateus = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - }else // adsl 2/2+ - { - unsigned long Mp,Lp,Tp,Rp,Kp,Bpn,DataRate,DataRate_remain; - Mp=Lp=Tp=Rp=Kp=Bpn=DataRate=DataRate_remain=0; - //// down stream data rate - - if (chantype.interleave) - { - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 14 Index 0"); -#endif - Lp = 0; - }else - Lp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 12 Index 0"); -#endif - Rp = 0; - }else - Rp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 13 Index 0"); -#endif - Mp = 0; - }else - Mp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 15 Index 0"); -#endif - Tp = 0; - }else - Tp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP0_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 17 Index 0"); -#endif - Kp = 0; - }else - { - Kp=RxMessage[4]+ RxMessage[5]+1; - Bpn=RxMessage[4]+ RxMessage[5]; - } - }else - { - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 14 Index 1"); -#endif - Lp = 0; - }else - Lp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 12 Index 1"); -#endif - Rp = 0; - }else - Rp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 13 Index 1"); -#endif - Mp = 0; - }else - Mp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 15 Index 1"); -#endif - Tp = 0; - }else - Tp=RxMessage[4]; - - LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 17 Index 2"); -#endif - Kp = 0; - }else - { - Kp=RxMessage[4]+ RxMessage[5]+1; - Bpn=RxMessage[4]+ RxMessage[5]; - } - } - DataRate=((Tp*(Bpn+1)-1)*Mp*Lp*4)/(Tp*(Kp*Mp+Rp)); - //DataRate_remain=((((Tp*(Bpn+1)-1)*Mp*Lp*4)%(Tp*(Kp*Mp+Rp)))*1000)/(Tp*(Kp*Mp+Rp)); - //pts.adslLineRateInfo_pt->adslDataRateus = DataRate * 1000 + DataRate_remain; - pts.adslLineRateInfo_pt->adslDataRateus = DataRate; - } - } - - if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_ATTNDRDS_FLAG)){ - LINE_RATE_ATTNDRDS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 68 Index 4"); -#endif - pts.adslLineRateInfo_pt->adslATTNDRds = 0; - } - else{ - pts.adslLineRateInfo_pt->adslATTNDRds = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - - if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_ATTNDRUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - LINE_RATE_ATTNDRUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ - #ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 69 Index 4"); - #endif - pts.adslLineRateInfo_pt->adslATTNDRus = 0; - } - else{ - pts.adslLineRateInfo_pt->adslATTNDRus = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x24; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_RATE_END; - } - pts.adslLineRateInfo_pt->adslATTNDRus = (u32)le16_to_cpu(hdlc_rx_buffer[1])<<16 | (u32)le16_to_cpu(hdlc_rx_buffer[2]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_RATE_END; - } - } - } - copy_to_user((char *)lon, (char *)pts.adslLineRateInfo_pt, sizeof(adslLineRateInfo)); - up(&mei_sema); - -GET_ADSL_LINE_RATE_END: - kfree(pts.adslLineRateInfo_pt); - break; - - case GET_ADSL_LINE_INFO: - if (showtime!=1) - return -ERESTARTSYS; - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslLineInfo_pt = (adslLineInfo *)kmalloc(sizeof(adslLineInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslLineInfo_pt, (char *)lon, sizeof(adslLineInfo)); - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_INTLV_DEPTHDS_FLAG)){ - if (chantype.interleave) - LINE_INFO_INTLV_DEPTHDS_FLAG_LP0_MAKECMV; - else - LINE_INFO_INTLV_DEPTHDS_FLAG_LP1_MAKECMV; - - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 27 Index 0"); -#endif - pts.adslLineInfo_pt->adslInterleaveDepthds = 0; - } - else{ - pts.adslLineInfo_pt->adslInterleaveDepthds = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_INTLV_DEPTHUS_FLAG)){ - if (chantype.interleave) - LINE_INFO_INTLV_DEPTHUS_FLAG_LP0_MAKECMV; - else - LINE_INFO_INTLV_DEPTHUS_FLAG_LP1_MAKECMV; - - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group CNFG Address 16 Index 0"); -#endif - pts.adslLineInfo_pt->adslInterleaveDepthus = 0; - } - else{ - pts.adslLineInfo_pt->adslInterleaveDepthus = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_LATNDS_FLAG)){ - LINE_INFO_LATNDS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 68 Index 1"); -#endif - pts.adslLineInfo_pt->adslLATNds = 0; - } - else{ - pts.adslLineInfo_pt->adslLATNds = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_LATNUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - LINE_INFO_LATNUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 69 Index 1"); -#endif - pts.adslLineInfo_pt->adslLATNus = 0; - } - else{ - pts.adslLineInfo_pt->adslLATNus = RxMessage[4]; - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x21; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - pts.adslLineInfo_pt->adslLATNus = le16_to_cpu(hdlc_rx_buffer[1]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SATNDS_FLAG)){ - LINE_INFO_SATNDS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 68 Index 2"); -#endif - pts.adslLineInfo_pt->adslSATNds = 0; - } - else{ - pts.adslLineInfo_pt->adslSATNds = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SATNUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - LINE_INFO_SATNUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 69 Index 2"); -#endif - pts.adslLineInfo_pt->adslSATNus = 0; - } - else{ - pts.adslLineInfo_pt->adslSATNus = RxMessage[4]; - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x22; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - pts.adslLineInfo_pt->adslSATNus = le16_to_cpu(hdlc_rx_buffer[1]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SNRMNDS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode - { - LINE_INFO_SNRMNDS_FLAG_ADSL1_MAKECMV; - } - else if ((adsl_mode == 0x4000) || (adsl_mode == 0x8000) || adsl_mode_extend > 0) - { - LINE_INFO_SNRMNDS_FLAG_ADSL2PLUS_MAKECMV; - } - else - { - LINE_INFO_SNRMNDS_FLAG_ADSL2_MAKECMV; - } - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 68 Index 3"); -#endif - pts.adslLineInfo_pt->adslSNRMds = 0; - } - else{ - if (adsl_mode>8 || adsl_mode_extend>0) - { - int SNRMds,SNRMds_remain; - SNRMds=RxMessage[4]; - SNRMds_remain=((SNRMds&0xff)*1000)/256; - SNRMds=(SNRMds>>8)&0xff; - if ((SNRMds_remain%100)>=50) SNRMds_remain=(SNRMds_remain/100)+1; - else SNRMds_remain=(SNRMds_remain/100); - pts.adslLineInfo_pt->adslSNRMds = SNRMds*10 + SNRMds_remain; - }else - { - pts.adslLineInfo_pt->adslSNRMds = RxMessage[4]; - } - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SNRMNUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend == 0) - { - LINE_INFO_SNRMNUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 69 Index 3"); -#endif - pts.adslLineInfo_pt->adslSNRMus = 0; - } - else{ - pts.adslLineInfo_pt->adslSNRMus = RxMessage[4]; - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x23; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - pts.adslLineInfo_pt->adslSNRMus = le16_to_cpu(hdlc_rx_buffer[1]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_ACATPDS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend == 0) - { - LINE_INFO_ACATPDS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ - #ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 68 Index 6"); - #endif - pts.adslLineInfo_pt->adslACATPds = 0; - } - else{ - pts.adslLineInfo_pt->adslACATPds = RxMessage[4]; - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x25; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - pts.adslLineInfo_pt->adslACATPds = le16_to_cpu(hdlc_rx_buffer[1]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - } - } - - if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_ACATPUS_FLAG)){ - if (adsl_mode <=8 && adsl_mode_extend == 0) - { - LINE_INFO_ACATPUS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 69 Index 6"); -#endif - pts.adslLineInfo_pt->adslACATPus = 0; - } - else{ - pts.adslLineInfo_pt->adslACATPus = RxMessage[4]; - } - }else - { - hdlc_cmd[0]=0x0181; - hdlc_cmd[1]=0x26; - up(&mei_sema); - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - pts.adslLineInfo_pt->adslACATPus = le16_to_cpu(hdlc_rx_buffer[1]); - } - if(down_interruptible(&mei_sema)) - { - meierr = -ERESTARTSYS; - goto GET_ADSL_LINE_INFO_END; - } - } - } - - copy_to_user((char *)lon, (char *)pts.adslLineInfo_pt, sizeof(adslLineInfo)); - up(&mei_sema); - -GET_ADSL_LINE_INFO_END: - kfree(pts.adslLineInfo_pt); - break; - - case GET_ADSL_NEAREND_STATS: - if (showtime!=1) - return -ERESTARTSYS; - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslNearEndPerfStats_pt = (adslNearEndPerfStats *)kmalloc(sizeof(adslNearEndPerfStats), GFP_KERNEL); - copy_from_user((char *)pts.adslNearEndPerfStats_pt, (char *)lon, sizeof(adslNearEndPerfStats)); - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_SUPERFRAME_FLAG)){ - NEAREND_PERF_SUPERFRAME_FLAG_LSW_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 20 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslSuperFrames = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslSuperFrames = (u32)(RxMessage[4]); - } - NEAREND_PERF_SUPERFRAME_FLAG_MSW_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 21 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslSuperFrames = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslSuperFrames += (((u32)(RxMessage[4]))<<16); - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOS_FLAG) || - IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOF_FLAG) || - IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LPR_FLAG) || - IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_NCD_FLAG) || - IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LCD_FLAG) ){ - NEAREND_PERF_LOS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 0 Index 0"); -#endif - RxMessage[4] = 0; - } - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOS_FLAG)){ - if( (RxMessage[4]&0x1) == 0x1) - pts.adslNearEndPerfStats_pt->adslneLOS = 1; - else - pts.adslNearEndPerfStats_pt->adslneLOS = 0; - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOF_FLAG)){ - if( (RxMessage[4]&0x2) == 0x2) - pts.adslNearEndPerfStats_pt->adslneLOF = 1; - else - pts.adslNearEndPerfStats_pt->adslneLOF = 0; - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LPR_FLAG)){ - if( (RxMessage[4]&0x4) == 0x4) - pts.adslNearEndPerfStats_pt->adslneLPR = 1; - else - pts.adslNearEndPerfStats_pt->adslneLPR = 0; - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_NCD_FLAG)){ - pts.adslNearEndPerfStats_pt->adslneNCD = (RxMessage[4]>>4)&0x3; - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LCD_FLAG)){ - pts.adslNearEndPerfStats_pt->adslneLCD = (RxMessage[4]>>6)&0x3; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_CRC_FLAG)){ - if (chantype.interleave) - NEAREND_PERF_CRC_FLAG_LP0_MAKECMV; - else - NEAREND_PERF_CRC_FLAG_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 2 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneCRC = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneCRC = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_RSCORR_FLAG)){ - if (chantype.interleave) - NEAREND_PERF_RSCORR_FLAG_LP0_MAKECMV; - else - NEAREND_PERF_RSCORR_FLAG_LP1_MAKECMV; - - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 3 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneRSCorr = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneRSCorr = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_FECS_FLAG)){ - NEAREND_PERF_FECS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 6 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneFECS = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneFECS = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_ES_FLAG)){ - NEAREND_PERF_ES_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 7 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneES = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneES = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_SES_FLAG)){ - NEAREND_PERF_SES_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 8 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneSES = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneSES = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOSS_FLAG)){ - NEAREND_PERF_LOSS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 9 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneLOSS = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneLOSS = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_UAS_FLAG)){ - NEAREND_PERF_UAS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 10 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneUAS = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneUAS = RxMessage[4]; - } - } - - if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_HECERR_FLAG)){ - if (chantype.bearchannel0) - { - NEAREND_PERF_HECERR_FLAG_BC0_MAKECMV; - }else if (chantype.bearchannel1) - { - NEAREND_PERF_HECERR_FLAG_BC1_MAKECMV; - } - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 11 Index 0"); -#endif - pts.adslNearEndPerfStats_pt->adslneHECErrors = 0; - } - else{ - pts.adslNearEndPerfStats_pt->adslneHECErrors = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - - copy_to_user((char *)lon, (char *)pts.adslNearEndPerfStats_pt, sizeof(adslNearEndPerfStats)); - kfree(pts.adslNearEndPerfStats_pt); - - up(&mei_sema); - break; - - case GET_ADSL_FAREND_STATS: - - if (showtime!=1) - return -ERESTARTSYS; - - if (adsl_mode>8 || adsl_mode_extend > 0) - { - do_gettimeofday(&time_now); - if( FarendData_acquire_time.tv_sec==0 || time_now.tv_sec - FarendData_acquire_time.tv_sec>=1) - { - hdlc_cmd[0]=0x105; - - if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],2)!= -EBUSY) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); - hdlc_rx_len=0; - hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2); - if (hdlc_rx_len <=0) - { - return -ERESTARTSYS; - } - FarendStatsData.adslfeRSCorr = ((u32)le16_to_cpu(hdlc_rx_buffer[1]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[2]); - FarendStatsData.adslfeCRC = ((u32)le16_to_cpu(hdlc_rx_buffer[3]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[4]); - FarendStatsData.adslfeFECS = ((u32)le16_to_cpu(hdlc_rx_buffer[5]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[6]); - FarendStatsData.adslfeES = ((u32)le16_to_cpu(hdlc_rx_buffer[7]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[8]); - FarendStatsData.adslfeSES = ((u32)le16_to_cpu(hdlc_rx_buffer[9]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[10]); - FarendStatsData.adslfeLOSS = ((u32)le16_to_cpu(hdlc_rx_buffer[11]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[12]); - FarendStatsData.adslfeUAS = ((u32)le16_to_cpu(hdlc_rx_buffer[13]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[14]); - do_gettimeofday(&FarendData_acquire_time); - } - - } - } - - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - pts.adslFarEndPerfStats_pt = (adslFarEndPerfStats *)kmalloc(sizeof(adslFarEndPerfStats), GFP_KERNEL); - copy_from_user((char *)pts.adslFarEndPerfStats_pt, (char *)lon, sizeof(adslFarEndPerfStats)); - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOS_FLAG) || - IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOF_FLAG) || - IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LPR_FLAG) || - IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_NCD_FLAG) || - IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LCD_FLAG) ){ - FAREND_PERF_LOS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 1 Index 0"); -#endif - RxMessage[4] = 0; - } - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOS_FLAG)){ - if((RxMessage[4]&0x1) == 0x1) - pts.adslFarEndPerfStats_pt->adslfeLOS = 1; - else - pts.adslFarEndPerfStats_pt->adslfeLOS = 0; - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOF_FLAG)){ - if((RxMessage[4]&0x2) == 0x2) - pts.adslFarEndPerfStats_pt->adslfeLOF = 1; - else - pts.adslFarEndPerfStats_pt->adslfeLOF = 0; - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LPR_FLAG)){ - if((RxMessage[4]&0x4) == 0x4) - pts.adslFarEndPerfStats_pt->adslfeLPR = 1; - else - pts.adslFarEndPerfStats_pt->adslfeLPR = 0; - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_NCD_FLAG)){ - pts.adslFarEndPerfStats_pt->adslfeNCD = (RxMessage[4]>>4)&0x3; - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LCD_FLAG)){ - pts.adslFarEndPerfStats_pt->adslfeLCD = (RxMessage[4]>>6)&0x3; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_CRC_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - if (chantype.interleave) - { - FAREND_PERF_CRC_FLAG_LP0_MAKECMV; - } - else - { - FAREND_PERF_CRC_FLAG_LP1_MAKECMV; - } - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 24 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeCRC = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeCRC = RxMessage[4]; - } - }else - { - pts.adslFarEndPerfStats_pt->adslfeCRC = FarendStatsData.adslfeCRC; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_RSCORR_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - if (chantype.interleave) - FAREND_PERF_RSCORR_FLAG_LP0_MAKECMV; - else - FAREND_PERF_RSCORR_FLAG_LP1_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 28 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeRSCorr = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeRSCorr = RxMessage[4]; - - } - } - else - { - pts.adslFarEndPerfStats_pt->adslfeRSCorr = FarendStatsData.adslfeRSCorr; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_FECS_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - FAREND_PERF_FECS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 32 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeFECS = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeFECS = RxMessage[4]; - } - }else { - pts.adslFarEndPerfStats_pt->adslfeFECS = FarendStatsData.adslfeFECS; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_ES_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - FAREND_PERF_ES_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 33 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeES = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeES = RxMessage[4]; - } - }else - { - pts.adslFarEndPerfStats_pt->adslfeES = FarendStatsData.adslfeES; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_SES_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - FAREND_PERF_SES_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 34 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeSES = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeSES = RxMessage[4]; - - } - }else - { - pts.adslFarEndPerfStats_pt->adslfeSES = FarendStatsData.adslfeSES; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOSS_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - FAREND_PERF_LOSS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeLOSS = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeLOSS = RxMessage[4]; - - } - }else - { - pts.adslFarEndPerfStats_pt->adslfeLOSS = FarendStatsData.adslfeLOSS; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_UAS_FLAG)){ - if (adsl_mode<=8 && adsl_mode_extend == 0) - { - FAREND_PERF_UAS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 36 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeUAS = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeUAS = RxMessage[4]; - - } - }else - { - pts.adslFarEndPerfStats_pt->adslfeUAS = FarendStatsData.adslfeUAS; - } - } - - if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_HECERR_FLAG)){ - if (chantype.bearchannel0) - { - FAREND_PERF_HECERR_FLAG_BC0_MAKECMV; - }else if (chantype.bearchannel1) - { - FAREND_PERF_HECERR_FLAG_BC1_MAKECMV; - } - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 37 Index 0"); -#endif - pts.adslFarEndPerfStats_pt->adslfeHECErrors = 0; - } - else{ - pts.adslFarEndPerfStats_pt->adslfeHECErrors = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16); - } - } - - copy_to_user((char *)lon, (char *)pts.adslFarEndPerfStats_pt, sizeof(adslFarEndPerfStats)); - kfree(pts.adslFarEndPerfStats_pt); - - up(&mei_sema); - - break; -// 603221:tc.chen end - case GET_ADSL_LOOP_DIAGNOSTICS_MODE: - //lon = loop_diagnostics_mode; - copy_to_user((char *)lon, (char *)&loop_diagnostics_mode, sizeof(int)); - break; -//>> SHC - case IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE: - copy_to_user((char *)lon, (char *)&loop_diagnostics_completed, sizeof(int)); - break; - -//<< end SHC - case LOOP_DIAGNOSTIC_MODE_COMPLETE: - loop_diagnostics_completed = 1; - // read adsl mode - makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group STAT Address 1 Index 0"); -#endif - } - adsl_mode = RxMessage[4]; - - makeCMV(H2D_CMV_READ, STAT, 17, 0, 1, data); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group STAT Address 1 Index 0"); -#endif - } - adsl_mode_extend = RxMessage[4]; - wake_up_interruptible(&wait_queue_loop_diagnostic); - break; - case SET_ADSL_LOOP_DIAGNOSTICS_MODE: - if (lon != loop_diagnostics_mode) - { - loop_diagnostics_completed = 0; - loop_diagnostics_mode = lon; - - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_REBOOT, NULL); - - } - break; - case GET_ADSL_ATUR_SUBCARRIER_STATS: - if (loop_diagnostics_completed == 0) - { - interruptible_sleep_on_timeout(&wait_queue_loop_diagnostic,300*HZ); - if (loop_diagnostics_completed==0) - { - return -ERESTARTSYS; - } - } - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - pts.adslATURSubcarrierInfo_pt = (adslATURSubcarrierInfo *)kmalloc(sizeof(adslATURSubcarrierInfo), GFP_KERNEL); - copy_from_user((char *)pts.adslATURSubcarrierInfo_pt, (char *)lon, sizeof(adslATURSubcarrierInfo)); - - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_HLINSC)){ - FAREND_HLINSC_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - pts.adslATURSubcarrierInfo_pt->HLINSCds = 0; - } - else{ - pts.adslATURSubcarrierInfo_pt->HLINSCds = RxMessage[4]; - - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_HLINPS)){ - int index=0,size=12; - //printk("FAREND_HLINPS\n"); - for (index=0;index<1024;index+=size) - { - if (index+size>=1024) - size = 1024-index; - FAREND_HLINPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - memcpy(&pts.adslATURSubcarrierInfo_pt->HLINpsds[index],&RxMessage[4],size*2); -#if 0 - int msg_idx; - for(msg_idx=0;msg_idxflags)), FAREND_HLOGMT)){ - FAREND_HLOGMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - pts.adslATURSubcarrierInfo_pt->HLOGMTds = 0; - } - else{ - pts.adslATURSubcarrierInfo_pt->HLOGMTds = RxMessage[4]; - - } - } - - ///////////////////////////////////////////////////////////////////////// - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_HLOGPS)){ - //printk("FAREND_HLOGPS\n"); - int index=0,size=12; - for (index=0;index<256;index+=size) - { - if (index+size>=256) - size = 256-index; - - FAREND_HLOGPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - if (adsl_mode < 0x4000 && adsl_mode_extend==0)//adsl2 mode - { - memcpy(&pts.adslATURSubcarrierInfo_pt->HLOGpsds[index],&RxMessage[4],size*2); - }else - { - int msg_idx=0; - for (msg_idx=0;msg_idxHLOGpsds[(index+msg_idx)*2+1] = RxMessage[4+msg_idx]; - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - } - } - } - if (adsl_mode >= 0x4000 || adsl_mode_extend >0)//adsl2+ mode - { - pts.adslATURSubcarrierInfo_pt->HLOGpsds[0] = pts.adslATURSubcarrierInfo_pt->HLOGpsds[1]; - for (index=1;index<256;index++) - { - pts.adslATURSubcarrierInfo_pt->HLOGpsds[index*2] = (pts.adslATURSubcarrierInfo_pt->HLOGpsds[(index)*2-1] + pts.adslATURSubcarrierInfo_pt->HLOGpsds[(index)*2+1] +1) >>1; - } - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_QLNMT)){ - FAREND_QLNMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - pts.adslATURSubcarrierInfo_pt->QLNMTds = 0; - } - else{ - pts.adslATURSubcarrierInfo_pt->QLNMTds = RxMessage[4]; - } - } - - ///////////////////////////////////////////////////////////////////////// - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_QLNPS)){ - int index=0,size=12; - //printk("FAREND_QLNPS\n"); - for (index=0;index<128;index+=size) - { - if (index+size>=128) - size = 128-index; - FAREND_QLNPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - int msg_idx=0; - for (msg_idx=0;msg_idxQLNpsds[index],&RxMessage[4],size*2); - if (adsl_mode < 0x4000 && adsl_mode_extend==0)//adsl2 mode - { - pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - }else - { - pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*4+1] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*4+3] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - } - - - } - } - if (adsl_mode >= 0x4000 || adsl_mode_extend >0)//adsl2+ mode - { - pts.adslATURSubcarrierInfo_pt->QLNpsds[0] = pts.adslATURSubcarrierInfo_pt->QLNpsds[1]; - for (index=1;index<256;index++) - { - pts.adslATURSubcarrierInfo_pt->QLNpsds[index*2] = (pts.adslATURSubcarrierInfo_pt->QLNpsds[(index)*2-1] + pts.adslATURSubcarrierInfo_pt->QLNpsds[(index)*2+1]) >>1; - } - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_SNRMT)){ - FAREND_SNRMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - pts.adslATURSubcarrierInfo_pt->SNRMTds = 0; - } - else{ - pts.adslATURSubcarrierInfo_pt->SNRMTds = RxMessage[4]; - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_SNRPS)){ - int index=0,size=12; - //printk("FAREND_SNRPS\n"); - for (index=0;index<512;index+=size) - { - if (index+size>=512) - size = 512-index; - FAREND_SNRPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - //memcpy(&pts.adslATURSubcarrierInfo_pt->SNRpsds[index],&RxMessage[4],size*2); - int msg_idx=0; - for (msg_idx=0;msg_idxSNRpsds[index+msg_idx] = (u16)(RxMessage[4+msg_idx]&0xFF); - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - - } - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_BITPS)){ - int index=0,size=12; - //printk("FAREND_BITPS\n"); - for (index=0;index<256;index+=size) - { - if (index+size>=256) - size = 256-index; - FAREND_BITPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - int msg_idx=0; - for (msg_idx=0;msg_idxBITpsds[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATURSubcarrierInfo_pt->BITpsds[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - //printk("index:%d ,cmv_result: %04X, %d\n",index+msg_idx,RxMessage[4+msg_idx],RxMessage[4+msg_idx]); - - } - - } - } - } - if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_GAINPS)){ - int index=0,size=12; - //printk("FAREND_GAINPS\n"); - for (index=0;index<512;index+=size) - { - FAREND_GAINPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - } - else{ - /* - int msg_idx=0; - for (msg_idx=0;msg_idxGAINpsds[(index+msg_idx)*2] = RxMessage[4+msg_idx]&0xFF; - pts.adslATURSubcarrierInfo_pt->GAINpsds[(index+msg_idx)*2+1] = (RxMessage[4+msg_idx]>>8)&0xFF; - - } - */ - memcpy(&pts.adslATURSubcarrierInfo_pt->GAINpsds[index],&RxMessage[4],size*2); -#if 0 - int msg_idx=0; - for (msg_idx=0;msg_idxflags)), NEAREND_HLINSC)){ - NEAREND_HLINSC_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 71 Index 2"); -#endif - pts.adslATUCSubcarrierInfo_pt->HLINSCus = 0; - } - else{ - pts.adslATUCSubcarrierInfo_pt->HLINSCus = RxMessage[4]; - - } - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_HLINPS)){ - int index=0,size=12; - //printk("NEAREND_HLINPS\n"); - for (index=0;index<128;index+=size) - { - if (index+size>=128) - size = 128-index; - NEAREND_HLINPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 73 Index 0"); -#endif - } - else{ - memcpy(&pts.adslATUCSubcarrierInfo_pt->HLINpsus[index],&RxMessage[4],size*2); -#if 0 - int msg_idx; - for (msg_idx=0;msg_idxflags)), NEAREND_HLOGMT)){ - NEAREND_HLOGMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 80 Index 0"); -#endif - pts.adslATUCSubcarrierInfo_pt->HLOGMTus = 0; - } - else{ - pts.adslATUCSubcarrierInfo_pt->HLOGMTus = RxMessage[4]; - - } - } - - ///////////////////////////////////////////////////////////////////////// - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_HLOGPS)){ - int index=0,size=12; - //printk("NEAREND_HLOGPS\n"); - for (index=0;index<64;index+=size) - { - if (index+size>=64) - size = 64-index; - NEAREND_HLOGPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 75 Index 0"); -#endif - } - else{ -#if 0 - if (adsl_mode <0x4000)//adsl /adsl2 mode - { -#endif - memcpy(&pts.adslATUCSubcarrierInfo_pt->HLOGpsus[index],&RxMessage[4],size*2); -#if 0 - }else - { - int msg_idx=0; - for (msg_idx=0;msg_idxHLOGpsus[(index+msg_idx)*2+1] = RxMessage[4+msg_idx]; - pts.adslATUCSubcarrierInfo_pt->HLOGpsus[(index+msg_idx)] = RxMessage[4+msg_idx]; - } - } -#endif - } - } -#if 0 - if (adsl_mode >= 0x4000)//adsl2 mode - { - pts.adslATUCSubcarrierInfo_pt->HLOGpsus[0] = pts.adslATUCSubcarrierInfo_pt->HLOGpsus[1]; - for (index=1;index<64;index++) - { - pts.adslATUCSubcarrierInfo_pt->HLOGpsus[index*2] = (pts.adslATUCSubcarrierInfo_pt->HLOGpsus[(index)*2-1] + pts.adslATUCSubcarrierInfo_pt->HLOGpsus[(index)*2+1]) >>1; - } - } -#endif - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_QLNMT)){ - NEAREND_QLNMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 80 Index 1"); -#endif - pts.adslATUCSubcarrierInfo_pt->QLNMTus = 0; - } - else{ - pts.adslATUCSubcarrierInfo_pt->QLNMTus = RxMessage[4]; - } - } - - ///////////////////////////////////////////////////////////////////////// - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_QLNPS)){ - int index=0,size=12; - //printk("NEAREND_QLNPS\n"); - for (index=0;index<32;index+=size) - { - if (index+size>=32) - size = 32-index; - NEAREND_QLNPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 77 Index 0"); -#endif - } - else{ - int msg_idx=0; - for (msg_idx=0;msg_idxQLNpsds[index],&RxMessage[4],size*2); - if (adsl_mode == 0x200 || adsl_mode == 0x800 || adsl_mode ==0x2000 || adsl_mode ==0x4000 || (adsl_mode == 0 && (adsl_mode_extend == 0x4 || adsl_mode_extend == 0x2))//ADSL 2 Annex B(0x200)/J(0x800)/M(0x2000) //ADSL 2+ B,J,M - if (adsl_mode < 0x4000 && adsl_mode_extend==0)//adsl2 mode - { - pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*4+1] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*4+3] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - }else -#endif - { - pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - } - - - } - } -#if 0 - //if (adsl_mode <0x4000)//Annex I/J/L/M - if (adsl_mode == 0x200 || adsl_mode == 0x800 || adsl_mode ==0x2000 || adsl_mode ==0x4000 || (adsl_mode == 0 && (adsl_mode_extend == 0x4 || adsl_mode_extend == 0x2))//ADSL 2 Annex B(0x200)/J(0x800)/M(0x2000) //ADSL 2+ B,J,M - { - pts.adslATUCSubcarrierInfo_pt->QLNpsus[0] = pts.adslATUCSubcarrierInfo_pt->QLNpsus[1]; - for (index=1;index<64;index++) - { - pts.adslATUCSubcarrierInfo_pt->QLNpsus[index*2] = (pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index)*2-1] + pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index)*2+1]) >>1; - } - } -#endif - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_SNRMT)){ - NEAREND_SNRMT_MAKECMV(H2D_CMV_READ); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 80 Index 2"); -#endif - pts.adslATUCSubcarrierInfo_pt->SNRMTus = 0; - } - else{ - pts.adslATUCSubcarrierInfo_pt->SNRMTus = RxMessage[4]; - } - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_SNRPS)){ - int index=0,size=12; - //printk("NEAREND_SNRPS\n"); - for (index=0;index<64;index+=size) - { - if (index+size>=64) - size = 64-index; - NEAREND_SNRPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 78 Index 0"); -#endif - } - else{ - //memcpy(&pts.adslATUCSubcarrierInfo_pt->SNRpsus[index],&RxMessage[4],size*2); - int msg_idx=0; - for (msg_idx=0;msg_idxSNRpsus[index+msg_idx] = (u16)(RxMessage[4+msg_idx]&0xFF); - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - - } - } - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_BITPS)){ - int index=0,size=12; - //printk("NEAREND_BITPS\n"); - for (index=0;index<32;index+=size) - { - if (index+size>=32) - size = 32-index; - NEAREND_BITPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 22 Index 0"); -#endif - } - else{ - int msg_idx=0; - for (msg_idx=0;msg_idxBITpsus[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF); - pts.adslATUCSubcarrierInfo_pt->BITpsus[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF); - //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]); - } - - } - } - } - if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_GAINPS)){ - int index=0,size=12; - //printk("NEAREND_GAINPS\n"); - for (index=0;index<64;index+=size) - { - if (index+size>=64) - size = 64-index; - NEAREND_GAINPS_MAKECMV(H2D_CMV_READ,index,size); - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group INFO Address 24 Index 0"); -#endif - } - else{ - /* - int msg_idx=0; - for (msg_idx=0;msg_idxGAINpsds[(index+msg_idx)*2] = RxMessage[4+msg_idx]&0xFF; - pts.adslATUCSubcarrierInfo_pt->GAINpsds[(index+msg_idx)*2+1] = (RxMessage[4+msg_idx]>>8)&0xFF; - - } - */ - memcpy(&pts.adslATUCSubcarrierInfo_pt->GAINpsus[index],&RxMessage[4],size*2); -#if 0 - int msg_idx; - for (msg_idx=0;msg_idxACTPSDus = ((int )(j*256 - temp*10*256 + k*10)) /256; - } - // DS - i=0; - j=temp=temp2=0; - NOMPSD_DS_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - i=-1; - } - else{ - j=RxMessage[4]; - } - PCB_DS_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - i=-1; - } - else{ - temp=RxMessage[4]; - } - RMSGI_DS_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group PLAM Address 35 Index 0"); -#endif - i=-1; - } - else{ - //temp2=RxMessage[4]; - k=(int16_t)RxMessage[4]; - } - if (i==0) - { - pts.adslPowerSpectralDensity_pt->ACTPSDds = ((int )(j*256 - temp*10*256 + k*10)) /256; - } - copy_to_user((char *)lon, (char *)pts.adslPowerSpectralDensity_pt, sizeof(adslPowerSpectralDensity)); - kfree(pts.adslPowerSpectralDensity_pt); - up(&mei_sema); - break; - case AMAZON_MEI_START: - showtime=0; - loop_diagnostics_completed = 0; -#ifdef ARC_READY_ACK -#ifdef LOCK_RETRY - i=0; -lock_retry: - if(down_trylock(&mei_sema)!=0) - { - reboot_lock = 1; - printk("lock fail\n"); - i++; - if (i <=5) - { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(10); - goto lock_retry; - }else - { - printk("Force to Reboot ADSL!\n"); - up(&mei_sema); - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1000); - sema_init(&mei_sema, 1); // semaphore initialization, mutex - } - }else - { - reboot_lock = 1; - } -#else - if(down_interruptible(&mei_sema)) //disable CMV access until ARC ready - { - return -ERESTARTSYS; - } -#endif -#endif - //CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON - if(chantype.interleave==1){ - kfree(interleave_mei_net.priv); - unregister_netdev(&interleave_mei_net); - } - else if(chantype.fast==1){ - kfree(fast_mei_net.priv); - unregister_netdev(&fast_mei_net); - } - chantype.interleave=0; - chantype.fast=0; - meiMailboxInterruptsDisable(); //disable all MEI interrupts - if(mei_arc_swap_buff == NULL){ - mei_arc_swap_buff = (u32 *)kmalloc(MAXSWAPSIZE*4, GFP_KERNEL); - if(mei_arc_swap_buff==NULL){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n malloc fail for codeswap buff"); -#endif - meierr=MEI_FAILURE; - } - } - if(meiForceRebootAdslModem() != MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n meiForceRebootAdslModem() error..."); -#endif - meierr=MEI_FAILURE; - } - interruptible_sleep_on(&wait_queue_codeswap); - // reset is called - break; - case AMAZON_MEI_MIB_DAEMON: -#ifdef IFX_SMALL_FOOTPRINT /* [ */ - return -1; -#else /* ][ !IFX_SMALL_FOOTPRINT */ - i=0; - while(1){ - if(istart_time.tv_sec>=900){ - if(current_intvl->list.next!=&interval_list){ - current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list); - do_gettimeofday(&(current_intvl->start_time)); - } - else{ - mib_ptr = list_entry(interval_list.next, amazon_mei_mib, list); - list_del(interval_list.next); - memset(mib_ptr, 0, sizeof(amazon_mei_mib)); - list_add_tail(&(mib_ptr->list), &interval_list); - if(current_intvl->list.next==&interval_list) -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nlink list error"); -#endif - current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list); - do_gettimeofday(&(current_intvl->start_time)); - } - } - - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; -/* - ATUC_PERF_LO_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 0 Index 0"); -#endif - } - else{ - if(RxMessage[4]&PLAM_LOS_FailureBit){ - current_intvl->AtucPerfLos++; - ATUC_PERF_LOSS++; - CurrStatus.adslAtucCurrStatus = 2; - } - if(RxMessage[4]&PLAM_LOF_FailureBit){ - current_intvl->AtucPerfLof++; - ATUC_PERF_LOFS++; - CurrStatus.adslAtucCurrStatus = 1; - } - if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit))) - CurrStatus.adslAtucCurrStatus = 0; - } -*/ - ATUC_PERF_ESS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 7 Index 0"); -#endif - } - else{ - temp = RxMessage[4]-mib_pread.ATUC_PERF_ESS; - if(temp>=0){ - current_intvl->AtucPerfEs+=temp; - ATUC_PERF_ESS+=temp; - mib_pread.ATUC_PERF_ESS = RxMessage[4]; - } - else{ - current_intvl->AtucPerfEs+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4]; - ATUC_PERF_ESS+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4]; - mib_pread.ATUC_PERF_ESS = RxMessage[4]; - } - } -/* - ATUR_PERF_LO_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 1 Index 0"); -#endif - } - else{ - if(RxMessage[4]&PLAM_LOS_FailureBit){ - current_intvl->AturPerfLos++; - ATUR_PERF_LOSS++; - CurrStatus.adslAturCurrStatus = 2; - } - if(RxMessage[4]&PLAM_LOF_FailureBit){ - current_intvl->AturPerfLof++; - ATUR_PERF_LOFS++; - CurrStatus.adslAturCurrStatus = 1; - } - if(RxMessage[4]&PLAM_LPR_FailureBit){ - current_intvl->AturPerfLpr++; - ATUR_PERF_LPR++; - CurrStatus.adslAturCurrStatus = 3; - } - if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit|PLAM_LPR_FailureBit))) - CurrStatus.adslAturCurrStatus = 0; - } -*/ - ATUR_PERF_ESS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 33 Index 0"); -#endif - } - else{ - temp = RxMessage[4]-mib_pread.ATUR_PERF_ESS; - if(temp>=0){ - current_intvl->AturPerfEs+=temp; - ATUR_PERF_ESS+=temp; - mib_pread.ATUR_PERF_ESS = RxMessage[4]; - } - else{ - current_intvl->AturPerfEs+=0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4]; - ATUR_PERF_ESS+= 0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4]; - mib_pread.ATUR_PERF_ESS=RxMessage[4]; - } - } - // to update rx/tx blocks - ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 20 Index 0"); -#endif - } - else{ - temp = RxMessage[4]; - } - ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 21 Index 0"); -#endif - } - else{ - temp2 = RxMessage[4]; - } - if((temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK)>=0){ - current_intvl->AturChanPerfRxBlk+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK; - ATUR_CHAN_RECV_BLK+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK; - mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16); - } - else{ - current_intvl->AturChanPerfRxBlk+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16)); - ATUR_CHAN_RECV_BLK+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16)); - mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16); - } - current_intvl->AturChanPerfTxBlk = current_intvl->AturChanPerfRxBlk; - ATUR_CHAN_TX_BLK = ATUR_CHAN_RECV_BLK; -/* - ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS) - printk("\n\nCMV fail, Group 7 Address 20 Index 0"); - else{ - if(RxMessage[4]){ - current_intvl->AturChanPerfTxBlk+=RxMessage[4]; - ATUR_CHAN_TX_BLK+=RxMessage[4]; - } - } - ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS) - printk("\n\nCMV fail, Group 7 Address 21 Index 0"); - else{ - if(RxMessage[4]){ - current_intvl->AturChanPerfTxBlk+=(int)((RxMessage[4])<<16); - ATUR_CHAN_TX_BLK+=(int)((RxMessage[4])<<16); - } - } -*/ - if(chantype.interleave == 1){ - ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 3 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_INTL; - if(temp>=0){ - current_intvl->AturChanPerfCorrBlk+=temp; - ATUR_CHAN_CORR_BLK+=temp; - mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4]; - ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4]; - mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4]; - } - } - } - else if(chantype.fast == 1){ - ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 3 Index 1"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_FAST; - if(temp>=0){ - current_intvl->AturChanPerfCorrBlk+=temp; - ATUR_CHAN_CORR_BLK+=temp; - mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4]; - ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4]; - mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4]; - } - } - } - - if(chantype.interleave == 1){ - ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 2 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL; - if(temp>=0){ - current_intvl->AturChanPerfUncorrBlk+=temp; - ATUR_CHAN_UNCORR_BLK+=temp; - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4]; - ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4]; - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4]; - } - } - } - else if(chantype.fast == 1){ - ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 2 Index 1"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST; - if(temp>=0){ - current_intvl->AturChanPerfUncorrBlk+=temp; - ATUR_CHAN_UNCORR_BLK+=temp; - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4]; - ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4]; - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4]; - } - } - } - - //RFC-3440 - -#ifdef AMAZON_MEI_MIB_RFC3440 - ATUC_PERF_STAT_FASTR_FLAG_MAKECMV; //??? - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 0 Address 0 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FASTR; - if(temp>=0){ - current_intvl->AtucPerfStatFastR+=temp; - ATUC_PERF_STAT_FASTR+=temp; - mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4]; - ATUC_PERF_STAT_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4]; - } - } - ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV; //??? - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 0 Address 0 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FAILED_FASTR; - if(temp>=0){ - current_intvl->AtucPerfStatFailedFastR+=temp; - ATUC_PERF_STAT_FAILED_FASTR+=temp; - mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatFailedFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4]; - ATUC_PERF_STAT_FAILED_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4]; - } - } - ATUC_PERF_STAT_SESL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 8 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_SESL; - if(temp>=0){ - current_intvl->AtucPerfStatSesL+=temp; - ATUC_PERF_STAT_SESL+=temp; - mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatSesL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4]; - ATUC_PERF_STAT_SESL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4]; - } - } - ATUC_PERF_STAT_UASL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 10 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_UASL; - if(temp>=0){ - current_intvl->AtucPerfStatUasL+=temp; - ATUC_PERF_STAT_UASL+=temp; - mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4]; - ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4]; - } - } - ATUR_PERF_STAT_SESL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 34 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_PERF_STAT_SESL; - if(temp>=0){ - current_intvl->AtucPerfStatUasL+=temp; - ATUC_PERF_STAT_UASL+=temp; - mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4]; - ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4]; - mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4]; - } - } - -#endif - up(&mei_sema); - - do_gettimeofday(&time_fini); - i = ((int)((time_fini.tv_sec-time_now.tv_sec)*1000)) + ((int)((time_fini.tv_usec-time_now.tv_usec)/1000)) ; //msec - }//showtime==1 - } - break; -#endif /* ] !IFX_SMALL_FOOTPRINT */ - case AMAZON_MEI_RESET: - case AMAZON_MEI_REBOOT: - case AMAZON_MEI_SHOWTIME: -/* if(mei_arc_swap_buff !=NULL){ - kfree(mei_arc_swap_buff); - mei_arc_swap_buff=NULL; - } - if(image_buffer !=NULL){ -// kfree(image_buffer); - vfree(image_buffer); - image_buffer =NULL; - } -*/ - if(clreoc_command_pkt !=NULL){ - kfree(clreoc_command_pkt); - clreoc_command_pkt =NULL; - } - for(i=0;istart_time)); - ATUC_PERF_LOFS=0; - ATUC_PERF_LOSS=0; - ATUC_PERF_ESS=0; - ATUC_PERF_INITS=0; - ATUR_PERF_LOFS=0; - ATUR_PERF_LOSS=0; - ATUR_PERF_LPR=0; - ATUR_PERF_ESS=0; - ATUR_CHAN_RECV_BLK=0; - ATUR_CHAN_TX_BLK=0; - ATUR_CHAN_CORR_BLK=0; - ATUR_CHAN_UNCORR_BLK=0; - memset((((u8 *)&AlarmConfProfile)+32), 0, 16*4); - AlarmConfProfile.adslLineAlarmConfProfileRowStatus=1; -*/ - PrevTxRate.adslAtucChanPrevTxRate=0; - PrevTxRate.adslAturChanPrevTxRate=0; - CurrStatus.adslAtucCurrStatus=0; - CurrStatus.adslAturCurrStatus=0; - - if((command==AMAZON_MEI_RESET) || (command==AMAZON_MEI_REBOOT)){ -#ifdef AMAZON_CHECK_LINK - if (adsl_link_notify){ - (*adsl_link_notify)(0); - } -#endif - showtime=0; - //CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON - // disconnect net_dev - if(chantype.interleave==1){ - kfree(interleave_mei_net.priv); - unregister_netdev(&interleave_mei_net); -// if(unregister_netdev(&interleave_mei_net)!=0) -// printk("\n unregister interleave fail"); - } - else if(chantype.fast==1){ - kfree(fast_mei_net.priv); - unregister_netdev(&fast_mei_net); -// if(unregister_netdev(&fast_mei_net)!=0) -// printk("\n unregister fast fail"); - } - chantype.interleave=0; - chantype.fast=0; -// 603221:tc.chen start - chantype.bearchannel0 = 0; - chantype.bearchannel1 = 0; - adsl_mode = 0; -// 603221:tc.chen end - - while(1){ - - makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, NULL); //maximum allowed tx message length, in bytes - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ - //printk("AdslInitStatsData.FullInitializationCount++\n"); - AdslInitStatsData.FullInitializationCount++; - //printk("AdslInitStatsData.FailedFullInitializationCount++\n"); - AdslInitStatsData.FailedFullInitializationCount++; - //printk("AdslInitStatsData.LINIT_Errors++\n"); - AdslInitStatsData.LINIT_Errors++; - }else - { - //printk("RxMessage=%X\n",RxMessage[4]); - if ( RxMessage[4]!=0x1) - { - //printk("AdslInitStatsData.FullInitializationCount++\n"); - AdslInitStatsData.FullInitializationCount++; - if ( RxMessage[4] != 0x7) - { - //printk("AdslInitStatsData.LINIT_Errors++\n"); - AdslInitStatsData.LINIT_Errors++; - //printk("AdslInitStatsData.FailedFullInitializationCount++\n"); - AdslInitStatsData.FailedFullInitializationCount++; - - } - } - } - - reboot_flag=0; - wake_up_interruptible(&wait_queue_codeswap); //wake up codeswap daemon - - interruptible_sleep_on_timeout(&wait_queue_reboot, 1*HZ); // sleep until arc ready -#ifdef ARC_READY_ACK - if(reboot_flag!=0) - break; - else - { - up(&mei_sema); - printk("\n reboot retry"); - } -#else - break; -#endif - } - } - else{ //AMAZON_MEI_SHOWTIME - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; - - // clreoc stuff - makeCMV(H2D_CMV_READ, INFO, 83, 0, 1, data); //maximum allowed tx message length, in bytes - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 3 Address 83 Index 0"); -#endif - } - else{ - clreoc_max_tx_len = (int)RxMessage[4]; - clreoc_command_pkt = kmalloc((clreoc_max_tx_len*CLREOC_BUFF_SIZE), GFP_KERNEL); - if(clreoc_command_pkt == NULL){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("kmalloc error for clreoc_command_pkt\n\n"); -#endif - up(&mei_sema); - return -1; - } - for(i=0;ilen)>0){ - copy_to_user((char *)lon, (char*)(&(current_clreoc->len)), 4); - break; - } - else//wait for eoc data from higher layer - interruptible_sleep_on(&wait_queue_clreoc); - } - break; - case AMAZON_MEI_GET_EOC_DATA: - current_clreoc = list_entry(clreoc_list.next, amazon_clreoc_pkt, list); - if((current_clreoc->len)>0){ - copy_to_user((char*)lon, (char*)(current_clreoc->command), current_clreoc->len); - meierr=1; - list_del(clreoc_list.next); //remove and add to end of list - current_clreoc->len = 0; - list_add_tail(&(current_clreoc->list), &clreoc_list); - } - else - meierr=-1; - break; - case AMAZON_MEI_EOC_SEND: - copy_from_user((char *)(&debugrdwr), (char *)lon, sizeof(debugrdwr)); - eoc_skb = dev_alloc_skb(debugrdwr.iCount*4); - if(eoc_skb==NULL){ - printk("\n\nskb alloc fail"); - break; - } - - eoc_skb->len=debugrdwr.iCount*4; - memcpy(skb_put(eoc_skb, debugrdwr.iCount*4), (char *)debugrdwr.buffer, debugrdwr.iCount*4); - - ifx_push_eoc(eoc_skb); //pass data to higher layer - break; -#endif //#ifdef AMAZON_CLEAR_EOC - case AMAZON_MIB_LO_ATUC: - do_gettimeofday(&time_now); - if(lon&0x1){ - if((time_now.tv_sec-(mib_pflagtime.ATUC_PERF_LOSS_PTIME).tv_sec)>2){ - current_intvl->AtucPerfLos++; - ATUC_PERF_LOSS++; - CurrStatus.adslAtucCurrStatus = 2; - } - (mib_pflagtime.ATUC_PERF_LOSS_PTIME).tv_sec = time_now.tv_sec; - } - if(lon&0x2){ - if((time_now.tv_sec-(mib_pflagtime.ATUC_PERF_LOFS_PTIME).tv_sec)>2){ - current_intvl->AtucPerfLof++; - ATUC_PERF_LOFS++; - CurrStatus.adslAtucCurrStatus = 1; - } - (mib_pflagtime.ATUC_PERF_LOFS_PTIME).tv_sec = time_now.tv_sec; - } - if(!(lon&0x3)) - CurrStatus.adslAtucCurrStatus = 0; - break; - case AMAZON_MIB_LO_ATUR: - do_gettimeofday(&time_now); - if(lon&0x1){ - if((time_now.tv_sec-(mib_pflagtime.ATUR_PERF_LOSS_PTIME).tv_sec)>2){ - current_intvl->AturPerfLos++; - ATUR_PERF_LOSS++; - CurrStatus.adslAturCurrStatus = 2; - } - (mib_pflagtime.ATUR_PERF_LOSS_PTIME).tv_sec = time_now.tv_sec; - } - if(lon&0x2){ - if((time_now.tv_sec-(mib_pflagtime.ATUR_PERF_LOFS_PTIME).tv_sec)>2){ - current_intvl->AturPerfLof++; - ATUR_PERF_LOFS++; - CurrStatus.adslAturCurrStatus = 1; - } - (mib_pflagtime.ATUR_PERF_LOFS_PTIME).tv_sec = time_now.tv_sec; - } - if(lon&0x4){ - if((time_now.tv_sec-(mib_pflagtime.ATUR_PERF_LPR_PTIME).tv_sec)>2){ - current_intvl->AturPerfLpr++; - ATUR_PERF_LPR++; - CurrStatus.adslAturCurrStatus = 3; - } - (mib_pflagtime.ATUR_PERF_LPR_PTIME).tv_sec = time_now.tv_sec; - } - if(!(lon&0x7)) - CurrStatus.adslAturCurrStatus = 0; - break; - case AMAZON_MEI_DOWNLOAD: - // DMA the boot code page(s) -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n start download pages"); -#endif - for( boot_loop = 0; boot_loop < img_hdr->count; boot_loop++){ - if( img_hdr->page[boot_loop].p_size & BOOT_FLAG){ - page_size = meiGetPage( boot_loop, GET_PROG, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( page_size > 0){ - meiDMAWrite(dest_addr, mei_arc_swap_buff, page_size); - } - } - if( img_hdr->page[boot_loop].d_size & BOOT_FLAG){ - page_size = meiGetPage( boot_loop, GET_DATA, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( page_size > 0){ - meiDMAWrite( dest_addr, mei_arc_swap_buff, page_size); - } - } - } -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n pages downloaded"); -#endif - break; - //509221:tc.chen start - case AMAZON_MEI_DEBUG_MODE: - mei_debug_mode = lon; - break; - //509221:tc.chen end - } - return meierr; -} - - -////////////////////// Interrupt handler ///////////////////////////////////////////////////// -static void mei_interrupt_arcmsgav(int,void *,struct pt_regs *); -static void mei_interrupt_arcmsgav(int int1, void * void0, struct pt_regs * regs) -{ - u32 scratch; - u32 fetchpage; - u32 size; - u32 dest_addr; - u32 temp; - int i; - - meiDebugRead(ARC_MEI_MAILBOXR, &scratch, 1); - if(scratch & OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK) - { - if(showtime==1){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n Code Swap Request After ShowTime !!!"); -#endif - } - else{ -#ifdef AMAZON_MEI_DEBUG_ON -// printk("\n\n Code Swap Request"); -#endif - fetchpage = scratch & ~OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK; - size = meiGetPage( fetchpage, GET_PROG, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( size > 0) - { -#ifdef AMAZON_MEI_DEBUG_ON -// printk(" : prom page num %d",fetchpage); -#endif - meiDMAWrite( dest_addr, mei_arc_swap_buff, size); - } - - size = meiGetPage( fetchpage, GET_DATA, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr); - if( size > 0) - { -#ifdef AMAZON_MEI_DEBUG_ON -// printk(" : data page num %d",fetchpage); -#endif - meiDMAWrite( dest_addr, mei_arc_swap_buff, size); - } - } - // Notify arc that mailbox read complete - meiLongwordWrite(ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV); - - // Tell ARC Codeswap is done - meiLongwordWrite(MEI_TO_ARC_INT, MEI_TO_ARC_CS_DONE); - asm("SYNC"); - i=0; - while(i>4)==D2H_AUTONOMOUS_MODEM_READY_MSG){ //check ARC ready message - -#ifdef LOCK_RETRY - if (reboot_lock) - { - reboot_lock = 0; - up(&mei_sema); // allow cmv access - } -#else - up(&mei_sema); // allow cmv access -#endif - reboot_flag=1; -//#ifdef ADSL_LED_SUPPORT -#if 0 - led_support_check=1;//adsl led for 1.1.2.7.1.1 - adsl_led_flash();//adsl led for 1.1.2.7.1.1 -#endif - wake_up_interruptible(&wait_queue_reboot); // wait up ioctl reboot - } -#endif - } - } -// meiLongwordWrite(ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV); - mask_and_ack_amazon_irq(AMAZON_MEI_INT); - return; -} - -// 603221:tc.chen start -////////////////////////hdlc //////////////// - -// get hdlc status -static unsigned int ifx_me_hdlc_status(void) -{ - u16 CMVMSG[MSG_LENGTH]; - int ret; - - if (showtime!=1) - return -ENETRESET; - - makeCMV_local(H2D_CMV_READ, STAT, 14, 0, 1, NULL,CMVMSG); //Get HDLC status - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - return CMVMSG[4]&0x0F; -} - -int ifx_me_is_resloved(int status) -{ - u16 CMVMSG[MSG_LENGTH]; - int ret; - - if (status == ME_HDLC_MSG_QUEUED || status == ME_HDLC_MSG_SENT) - return ME_HDLC_UNRESOLVED; - if (status == ME_HDLC_IDLE) - { - makeCMV_local(H2D_CMV_READ, CNTL, 2, 0, 1, NULL,CMVMSG); //Get ME-HDLC Control - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return IFX_POP_EOC_FAIL; - } - if (CMVMSG[4]&(1<<0)) - { - return ME_HDLC_UNRESOLVED; - } - - } - return ME_HDLC_RESOLVED; -} - -int _ifx_me_hdlc_send(unsigned char *hdlc_pkt,int len,int max_length) -{ - int ret; - u16 CMVMSG[MSG_LENGTH]; - u16 data=0; - u16 pkt_len=len; - if (pkt_len > max_length) - { - printk("Exceed maximum eoc message length\n"); - return -ENOBUFS; - } - //while(pkt_len > 0) - { - makeCMV_local(H2D_CMV_WRITE, INFO, 81, 0, (pkt_len+1)/2,(u16 *)hdlc_pkt,CMVMSG); //Write clear eoc message to ARC - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - - makeCMV_local(H2D_CMV_WRITE, INFO, 83, 2, 1,&pkt_len,CMVMSG); //Update tx message length - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - - data = (1<<0); - makeCMV_local(H2D_CMV_WRITE, CNTL, 2, 0, 1,&data,CMVMSG); //Start to send - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - return 0; - } -} - -static int ifx_me_hdlc_send(unsigned char *hdlc_pkt,int hdlc_pkt_len) -{ - int hdlc_status=0; - u16 CMVMSG[MSG_LENGTH]; - int max_hdlc_tx_length=0,ret=0,retry=0; - - while(retry<10) - { - hdlc_status = ifx_me_hdlc_status(); - if (ifx_me_is_resloved(hdlc_status)==ME_HDLC_RESOLVED) // arc ready to send HDLC message - { - makeCMV_local(H2D_CMV_READ, INFO, 83, 0, 1, NULL,CMVMSG); //Get Maximum Allowed HDLC Tx Message Length - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - max_hdlc_tx_length = CMVMSG[4]; - ret = _ifx_me_hdlc_send(hdlc_pkt,hdlc_pkt_len,max_hdlc_tx_length); - return ret; - } - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(10); - } - return -EBUSY; -} - -int ifx_mei_hdlc_read(char *hdlc_pkt,int max_hdlc_pkt_len) -{ - u16 CMVMSG[MSG_LENGTH]; - int msg_read_len,ret=0,pkt_len=0,retry = 0; - - while(retry<10) - { - ret = ifx_me_hdlc_status(); - if (ret == ME_HDLC_RESP_RCVD) - { - int current_size=0; - makeCMV_local(H2D_CMV_READ, INFO, 83, 3, 1, NULL,CMVMSG); //Get EoC packet length - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - return -EIO; - } - - pkt_len = CMVMSG[4]; - if (pkt_len > max_hdlc_pkt_len) - { - ret = -ENOMEM; - goto error; - } - while( current_size < pkt_len) - { - if (pkt_len - current_size >(MSG_LENGTH*2-8)) - msg_read_len = (MSG_LENGTH*2-8); - else - msg_read_len = pkt_len - (current_size); - makeCMV_local(H2D_CMV_READ, INFO, 82, 0 + (current_size/2), (msg_read_len+1)/2, NULL,CMVMSG); //Get hdlc packet - ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - if (ret != 0) - { - goto error; - } - memcpy(hdlc_pkt+current_size,&CMVMSG[4],msg_read_len); - current_size +=msg_read_len; - } - ret = current_size; - break; - }else - { - ret = -ENODATA; - } - - retry++; - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(10); - - } - return ret; -error: - - return ret; -} - -////////////////////////hdlc //////////////// -// 603221:tc.chen end - -/////////////////////// clearEoC, int ifx_pop_eoc(sk_buff * pkt) ////////// -int ifx_pop_eoc(struct sk_buff * pkt); -int ifx_pop_eoc(struct sk_buff * pkt) -{ - amazon_clreoc_pkt * current; - if(showtime!=1){ - dev_kfree_skb(pkt); - return IFX_POP_EOC_FAIL; - } - if((pkt->len)>clreoc_max_tx_len){ - dev_kfree_skb(pkt); - return IFX_POP_EOC_FAIL; - } - current = list_entry(clreoc_list.next, amazon_clreoc_pkt, list); - while(1){ - if(current->len==0){ - memcpy(current->command, pkt->data, pkt->len); - current->len=pkt->len; - break; - } - else{ - if((current->list).next==&clreoc_list){ - dev_kfree_skb(pkt); - return IFX_POP_EOC_FAIL; //buffer full - } - current = list_entry((current->list).next,amazon_clreoc_pkt, list); - } - } - wake_up_interruptible(&wait_queue_clreoc); - - dev_kfree_skb(pkt); - return IFX_POP_EOC_DONE; -} -/* this is used in circular fifo mode */ -/* -int ifx_pop_eoc(sk_buff * pkt); -int ifx_pop_eoc(sk_buff * pkt) -{ - int buff_space,i; - if(showtime!=1) - return IFX_POP_EOC_FAIL; - - if(clreoc_wr>=clreoc_rd) - buff_space = (MEI_CLREOC_BUFF_SIZE-1)-(clreoc_wr - clreoc_rd); - else - buff_space = clreoc_rd - clreoc_wr - 1; - if((pkt->len)>buff_space) - return IFX_POP_EOC_FAIL; - - if((clreoc_wr+pkt->len)>MEI_CLREOC_BUFF_SIZE){ - memcpy((clreoc+clreoc_wr), pkt->data, ((clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE+1)); - memcpy(clreoc, (pkt->data)+((clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE+1), (pkt->len)-((clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE+1)); - clreoc_wr=(clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE; - } - else{ - memcpy((clreoc+clreoc_wr), pkt->data, pkt->len); - if((clreoc_wr+pkt->len)=MEI_CLREOC_BUFF_SIZE) - clreoc_wr=0; - else - clreoc_wr+=pkt->len; - } - wake_up_interruptible(&wait_queue_clreoc); - return IFX_POP_EOC_DONE; -} -*/ - - -//////////////////////////////////////////////////////////////////////////// -//int amazon_mei_init_module (void); -//void amazon_mei_cleanup_module (void); -//int __init init_module (void); -//void __exit cleanup_module (void); - -int __init amazon_mei_init_module(void) -//int __init init_module(void) -{ - struct proc_dir_entry *entry; - int i; - -//dying gasp-start -#ifdef IFX_DYING_GASP - -//000003:fchang Start -#ifdef CONFIG_CPU_AMAZON_E - //GPIO31 :dying gasp event indication - // (1) logic high: dying gasp event is false (default) - // (2) logic low: dying gasp event is true - CLEAR_BIT((*((volatile u32 *)0xB0100B18)), 0x4); - CLEAR_BIT((*((volatile u32 *)0xB0100B1c)), 0x4); - CLEAR_BIT((*((volatile u32 *)0xB0100B20)), 0x4); - SET_BIT((*((volatile u32 *)0xB0100B24)), 0x4); - asm("SYNC"); -#else //000003:fchang End - - //GPIO31 :dying gasp event indication - // (1) logic high: dying gasp event is false (default) - // (2) logic low: dying gasp event is true - CLEAR_BIT((*((volatile u32 *)0xB0100B48)), 0x8000); - CLEAR_BIT((*((volatile u32 *)0xB0100B4C)), 0x8000); - CLEAR_BIT((*((volatile u32 *)0xB0100B50)), 0x8000); - SET_BIT((*((volatile u32 *)0xB0100B54)), 0x8000); -#if 0 -//warning-led-start -//GPIO 22 - SET_BIT ((*((volatile u32 *)0xB0100B48)), 0x40); - CLEAR_BIT((*((volatile u32 *)0xB0100B4C)), 0x40); - CLEAR_BIT((*((volatile u32 *)0xB0100B50)), 0x40); - SET_BIT((*((volatile u32 *)0xB0100B54)), 0x40); - CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //GPIO ON - printk("LED ON ON ON ON ON ON....."); -//warning-led-end -#endif - asm("SYNC"); -#endif //000003:fchang - -#endif //IFX_DYING_GASP -//dying gasp -end - - - reg_entry_t regs_temp[PROC_ITEMS] = // Items being debugged - { - /* { flag, name, description } */ - { &arcmsgav, "arcmsgav", "arc to mei message ", 0 }, - { &cmv_reply, "cmv_reply", "cmv needs reply", 0}, - { &cmv_waiting, "cmv_waiting", "waiting for cmv reply from arc", 0}, - { &indicator_count, "indicator_count", "ARC to MEI indicator count", 0}, - { &cmv_count, "cmv_count", "MEI to ARC CMVs", 0}, - { &reply_count, "reply_count", "ARC to MEI Reply", 0}, - { (int *)Recent_indicator, "Recent_indicator", "most recent indicator", 0}, - { (int *)8, "version", "version of firmware", 0}, - }; - memcpy((char *)regs, (char *)regs_temp, sizeof(regs_temp)); - - - //sema_init(&mei_sema, 0); // semaphore initialization, mutex - sema_init(&mei_sema, 1); // semaphore initialization, mutex - - init_waitqueue_head(&wait_queue_arcmsgav); // for ARCMSGAV - init_waitqueue_head(&wait_queue_codeswap); // for codeswap daemon - init_waitqueue_head(&wait_queue_mibdaemon); // for mib daemon - init_waitqueue_head(&wait_queue_reboot); // for ioctl reboot - init_waitqueue_head(&wait_queue_clreoc); // for clreoc_wr function - init_waitqueue_head(&wait_queue_loop_diagnostic); // for loop diagnostic function -#ifdef ADSL_LED_SUPPORT - init_waitqueue_head(&wait_queue_led); // adsl led for led function - init_waitqueue_head(&wait_queue_led_polling); // adsl led for led function - led_task.routine = adsl_led_flash_task; // adsl led for led function - led_poll_init(); // adsl led for led function -#endif //ADSL_LED_SUPPORT -#ifdef IFX_DYING_GASP - init_waitqueue_head(&wait_queue_dying_gasp); // IFX_DYING_GASP - lop_poll_init(); // IFX_DYING_GASP -#endif //IFX_DYING_GASP - - init_waitqueue_head(&wait_queue_uas_poll);//joelin 04/16/2005 - unavailable_seconds_poll_init();//joelin 04/16/2005 - memset(&mib_pflagtime, 0, (sizeof(mib_flags_pretime))); - - // initialize link list for intervals - mei_mib = (amazon_mei_mib *)kmalloc((sizeof(amazon_mei_mib)*INTERVAL_NUM), GFP_KERNEL); - if(mei_mib == NULL){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("kmalloc error for amazon_mei_mib\n\n"); -#endif - return -1; - } - memset(mei_mib, 0, (sizeof(amazon_mei_mib)*INTERVAL_NUM)); - INIT_LIST_HEAD(&interval_list); - for(i=0;istart_time)); - // initialize clreoc list - clreoc_pkt = (amazon_clreoc_pkt *)kmalloc((sizeof(amazon_clreoc_pkt)*CLREOC_BUFF_SIZE), GFP_KERNEL); - if(clreoc_pkt == NULL){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("kmalloc error for clreoc_pkt\n\n"); -#endif - return -1; - } - memset(clreoc_pkt, 0, (sizeof(amazon_clreoc_pkt)*CLREOC_BUFF_SIZE)); - INIT_LIST_HEAD(&clreoc_list); - for(i=0;ilow_ino; - entry->proc_fops = &proc_operations; - } else { -#ifdef AMAZON_MEI_DEBUG_ON - printk( KERN_ERR - ": can't create /proc/" MEI_DIRNAME - "/%s\n\n", regs[i].name); -#endif - return(-ENOMEM); - } - } - ///////////////////////////////// register net device //////////////////////////// - if(register_netdev(&phy_mei_net)!=0){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\n Register phy Device Failed."); -#endif - return -1; - } -/* - if(register_netdev(&interleave_mei_net)!=0){ - printk("\n\n Register interleave Device Failed."); - return -1; - } - if(register_netdev(&fast_mei_net)!=0){ - printk("\n\n Register fast Device Failed."); - return -1; - } -*/ -#ifdef DFE_LOOPBACK - mei_arc_swap_buff = (u32 *)kmalloc(MAXSWAPSIZE*4, GFP_KERNEL); - if (mei_arc_swap_buff){ -#ifdef ARC_READY_ACK - if(down_interruptible(&mei_sema)) //disable CMV access until ARC ready - { - return -ERESTARTSYS; - } -#ifdef LOCK_RETRY - reboot_lock = 1; -#endif -#endif - meiForceRebootAdslModem(); - kfree(mei_arc_swap_buff); - }else{ -#ifdef AMAZON_MEI_DEBUG_ON - printk("cannot load image: no memory\n\n"); -#endif - } -#endif -#ifdef IFX_SMALL_FOOTPRINT - mib_poll_init(); -#endif - return 0; -} - -void __exit amazon_mei_cleanup_module(void) -//void __exit cleanup_module(void) -{ - int i; -#ifdef ADSL_LED_SUPPORT - stop_led_module=1; //wake up and clean led module - led_support_check=0;//joelin , clear task - showtime=0;//joelin,clear task - //CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON - firmware_support_led=0;//joelin ,clear task - wake_up_interruptible(&wait_queue_led); //wake up and clean led module - wake_up_interruptible(&wait_queue_led_polling); //wake up and clean led module -#endif - for(i=0;icomm, "kmibpoll"); - sigfillset(&tsk->blocked); - - printk("Inside mib poll loop ...\n"); - i=0; - while(1){ - if(istart_time.tv_sec>=900){ - if(current_intvl->list.next!=&interval_list){ - current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list); - do_gettimeofday(&(current_intvl->start_time)); - } - else{ - mib_ptr = list_entry(interval_list.next, amazon_mei_mib, list); - list_del(interval_list.next); - memset(mib_ptr, 0, sizeof(amazon_mei_mib)); - list_add_tail(&(mib_ptr->list), &interval_list); - if(current_intvl->list.next==&interval_list) -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nlink list error"); -#endif - current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list); - do_gettimeofday(&(current_intvl->start_time)); - } - } - - if(down_interruptible(&mei_sema)) - return -ERESTARTSYS; -/* - ATUC_PERF_LO_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 0 Index 0"); -#endif - } - else{ - if(RxMessage[4]&PLAM_LOS_FailureBit){ - current_intvl->AtucPerfLos++; - ATUC_PERF_LOSS++; - CurrStatus.adslAtucCurrStatus = 2; - } - if(RxMessage[4]&PLAM_LOF_FailureBit){ - current_intvl->AtucPerfLof++; - ATUC_PERF_LOFS++; - CurrStatus.adslAtucCurrStatus = 1; - } - if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit))) - CurrStatus.adslAtucCurrStatus = 0; - } -*/ - - if(showtime!=1) - goto mib_poll_end; - ATUC_PERF_ESS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 7 Index 0"); -#endif - } - else{ - temp = RxMessage[4]-mib_pread.ATUC_PERF_ESS; - if(temp>=0){ - current_intvl->AtucPerfEs+=temp; - ATUC_PERF_ESS+=temp; - mib_pread.ATUC_PERF_ESS = RxMessage[4]; - } - else{ - current_intvl->AtucPerfEs+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4]; - ATUC_PERF_ESS+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4]; - mib_pread.ATUC_PERF_ESS = RxMessage[4]; - } - } -/* - ATUR_PERF_LO_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 1 Index 0"); -#endif - } - else{ - if(RxMessage[4]&PLAM_LOS_FailureBit){ - current_intvl->AturPerfLos++; - ATUR_PERF_LOSS++; - CurrStatus.adslAturCurrStatus = 2; - } - if(RxMessage[4]&PLAM_LOF_FailureBit){ - current_intvl->AturPerfLof++; - ATUR_PERF_LOFS++; - CurrStatus.adslAturCurrStatus = 1; - } - if(RxMessage[4]&PLAM_LPR_FailureBit){ - current_intvl->AturPerfLpr++; - ATUR_PERF_LPR++; - CurrStatus.adslAturCurrStatus = 3; - } - if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit|PLAM_LPR_FailureBit))) - CurrStatus.adslAturCurrStatus = 0; - } -*/ - if(showtime!=1) - goto mib_poll_end; - ATUR_PERF_ESS_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 33 Index 0"); -#endif - } - else{ - temp = RxMessage[4]-mib_pread.ATUR_PERF_ESS; - if(temp>=0){ - current_intvl->AturPerfEs+=temp; - ATUR_PERF_ESS+=temp; - mib_pread.ATUR_PERF_ESS = RxMessage[4]; - } - else{ - current_intvl->AturPerfEs+=0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4]; - ATUR_PERF_ESS+= 0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4]; - mib_pread.ATUR_PERF_ESS=RxMessage[4]; - } - } - if(showtime!=1) - goto mib_poll_end; - // to update rx/tx blocks - ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 20 Index 0"); -#endif - } - else{ - temp = RxMessage[4]; - } - if(showtime!=1) - goto mib_poll_end; - ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 21 Index 0"); -#endif - } - else{ - temp2 = RxMessage[4]; - } - if((temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK)>=0){ - current_intvl->AturChanPerfRxBlk+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK; - ATUR_CHAN_RECV_BLK+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK; - mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16); - } - else{ - current_intvl->AturChanPerfRxBlk+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16)); - ATUR_CHAN_RECV_BLK+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16)); - mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16); - } - current_intvl->AturChanPerfTxBlk = current_intvl->AturChanPerfRxBlk; - ATUR_CHAN_TX_BLK = ATUR_CHAN_RECV_BLK; -/* - ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS) - printk("\n\nCMV fail, Group 7 Address 20 Index 0"); - else{ - if(RxMessage[4]){ - current_intvl->AturChanPerfTxBlk+=RxMessage[4]; - ATUR_CHAN_TX_BLK+=RxMessage[4]; - } - } - ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS) - printk("\n\nCMV fail, Group 7 Address 21 Index 0"); - else{ - if(RxMessage[4]){ - current_intvl->AturChanPerfTxBlk+=(int)((RxMessage[4])<<16); - ATUR_CHAN_TX_BLK+=(int)((RxMessage[4])<<16); - } - } -*/ - if(chantype.interleave == 1){ - if(showtime!=1) - goto mib_poll_end; - ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 3 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_INTL; - if(temp>=0){ - current_intvl->AturChanPerfCorrBlk+=temp; - ATUR_CHAN_CORR_BLK+=temp; - mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4]; - ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4]; - mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4]; - } - } - } - else if(chantype.fast == 1){ - if(showtime!=1) - goto mib_poll_end; - ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 3 Index 1"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_FAST; - if(temp>=0){ - current_intvl->AturChanPerfCorrBlk+=temp; - ATUR_CHAN_CORR_BLK+=temp; - mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4]; - ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4]; - mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4]; - } - } - } - - if(chantype.interleave == 1){ - if(showtime!=1) - goto mib_poll_end; - ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 2 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL; - if(temp>=0){ - current_intvl->AturChanPerfUncorrBlk+=temp; - ATUR_CHAN_UNCORR_BLK+=temp; - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4]; - ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4]; - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4]; - } - } - } - else if(chantype.fast == 1){ - if(showtime!=1) - goto mib_poll_end; - ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 2 Index 1"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST; - if(temp>=0){ - current_intvl->AturChanPerfUncorrBlk+=temp; - ATUR_CHAN_UNCORR_BLK+=temp; - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4]; - } - else{ - current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4]; - ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4]; - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4]; - } - } - } - - //RFC-3440 - -#ifdef AMAZON_MEI_MIB_RFC3440 - if(showtime!=1) - goto mib_poll_end; - ATUC_PERF_STAT_FASTR_FLAG_MAKECMV; //??? - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 0 Address 0 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FASTR; - if(temp>=0){ - current_intvl->AtucPerfStatFastR+=temp; - ATUC_PERF_STAT_FASTR+=temp; - mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4]; - ATUC_PERF_STAT_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4]; - } - } - if(showtime!=1) - goto mib_poll_end; - ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV; //??? - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 0 Address 0 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FAILED_FASTR; - if(temp>=0){ - current_intvl->AtucPerfStatFailedFastR+=temp; - ATUC_PERF_STAT_FAILED_FASTR+=temp; - mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatFailedFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4]; - ATUC_PERF_STAT_FAILED_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4]; - } - } - if(showtime!=1) - goto mib_poll_end; - ATUC_PERF_STAT_SESL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 8 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_SESL; - if(temp>=0){ - current_intvl->AtucPerfStatSesL+=temp; - ATUC_PERF_STAT_SESL+=temp; - mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatSesL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4]; - ATUC_PERF_STAT_SESL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4]; - } - } - if(showtime!=1) - goto mib_poll_end; - ATUC_PERF_STAT_UASL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 10 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_UASL; - if(temp>=0){ - current_intvl->AtucPerfStatUasL+=temp; - ATUC_PERF_STAT_UASL+=temp; - mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4]; - ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4]; - mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4]; - } - } - if(showtime!=1) - goto mib_poll_end; - ATUR_PERF_STAT_SESL_FLAG_MAKECMV; - if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){ -#ifdef AMAZON_MEI_DEBUG_ON - printk("\n\nCMV fail, Group 7 Address 34 Index 0"); -#endif - } - else{ - temp = RxMessage[4] - mib_pread.ATUR_PERF_STAT_SESL; - if(temp>=0){ - current_intvl->AtucPerfStatUasL+=temp; - ATUC_PERF_STAT_UASL+=temp; - mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4]; - } - else{ - current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4]; - ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4]; - mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4]; - } - } - -#endif -mib_poll_end: - up(&mei_sema); - - do_gettimeofday(&time_fini); - i = ((int)((time_fini.tv_sec-time_now.tv_sec)*1000)) + ((int)((time_fini.tv_usec-time_now.tv_usec)/1000)) ; //msec - }//showtime==1 - } - -} -int mib_poll_init(void) -{ - printk("Starting mib_poll...\n"); - - kernel_thread(adsl_mib_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL); - return 0; -} -#endif //IFX_SMALL_FOOTPRINT -//EXPORT_NO_SYMBOLS; - -#ifdef ADSL_LED_SUPPORT -// adsl led -start -int led_status_on=0,led_need_to_flash=0; -int led_current_flashing=0; -unsigned long led_delay=0; -static int led_poll(void *unused) -{ - stop_led_module=0; //begin polling ... - while(!stop_led_module){ - if ((!led_status_on)&&(!led_need_to_flash)) interruptible_sleep_on_timeout (&wait_queue_led_polling,1000); //10 seconds timeout for waiting wakeup -// else printk("direct running task, no waiting"); - run_task_queue(&tq_ifx_led);//joelin task -// printk("led and LOP polling...\n"); - } - return 0; -} -static int led_poll_init(void) -{ -// printk("Starting adsl led polling...\n"); - -//warning-led-start -// CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON -//warning-led-end - - kernel_thread(led_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL); - return 0; -} - -int adsl_led_flash(void) -{ - int i; - if (!firmware_support_led) return 0; //joelin version check - - if (led_status_on == 0 && led_need_to_flash == 0) - { - queue_task(&led_task, &tq_ifx_led);//joelin task - wake_up_interruptible(&wait_queue_led_polling); //wake up and clean led module -// printk("queue Task 1...\n"); //joelin test - } - led_need_to_flash=1;//asking to flash led - - return 0; -} - -int adsl_led_flash_task(void *ptr) -{ - - u16 one=1; - u16 zero=0; - u16 data=0x0600; - int kernel_use=1; - u16 CMVMSG[MSG_LENGTH]; -//adsl-led-start for >v1.1.2.7.1.1 -// printk("Task Running...\n"); //joelin test - if ((firmware_support_led==2)&&(led_support_check)) - { - led_support_check=0; - data=0x0600; - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 0, 1, &data,CMVMSG); //configure GPIO9 GPIO10 as outputs - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 2, 1, &data,CMVMSG); //enable writing to bit 9 and bit10 - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - - data=0x0a01; - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 4, 1, &data,CMVMSG); //use GPIO10 for TR68 .Enable and don't invert. - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - -#ifdef DATA_LED_ON_MODE - data=0x0903;//tecom //use GPIO9 for TR68 data led .turn on. -#else - data=0x0900; -#endif - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 5, 1, &data,CMVMSG); //use GPIO9 for TR68 data led .turn off. - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG); - - } - if (!showtime) {led_need_to_flash=0; return 0;} -//adsl-led-end for >v1.1.2.7.1.1 - - if (led_status_on == 0 || led_need_to_flash == 1) - { - - if (led_current_flashing==0) - { - if (firmware_support_led==1){//>1.1.2.3.1.1 - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 0, 1, &one,CMVMSG); //flash - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG); - } - else if (firmware_support_led==2){//>1.1.2.7.1.1 - data=0x0901;//flash - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 5, 1, &data,CMVMSG); //use GPIO9 for TR68 data led .flash. - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG); - - }//(firmware_support_led==2) - led_current_flashing = 1;//turn on led - } - led_status_on=1; - - do{//do nothing , waiting untill no data traffic - led_need_to_flash=0; - interruptible_sleep_on_timeout(&wait_queue_led, 25); //the time for LED Off , if no data traffic - }while(led_need_to_flash==1); - - }else if (led_status_on == 1 && led_need_to_flash==0) - { - if (led_current_flashing==1) - {//turn off led - if (firmware_support_led==1){//>1.1.2.3.1.1 - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 0, 1, &zero,CMVMSG);//off - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG); - } //>1.1.2.3.1.1 - else if (firmware_support_led==2){//>1.1.2.7.1.1 -#ifdef DATA_LED_ON_MODE - data=0x0903;//tecom //use GPIO9 for TR68 data led .turn on. -#else - data=0x0900;//off -#endif - makeCMV_local(H2D_CMV_WRITE, INFO, 91, 5, 1, &data,CMVMSG); //use GPIO9 for TR68 data led .off. - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG); - - }//(firmware_support_led==2) - led_status_on=0; - led_current_flashing = 0; - } - } - - if (led_status_on == 1 || led_need_to_flash) - {//led flash job on going or led need to flash - queue_task(&led_task, &tq_ifx_led); //joelin task -// printk("queue Task 2...\n"); //joelin test - } - return 0; -} -//joelin adsl led-end -#else -int adsl_led_flash(void) -{ - return 0; -} -#endif //ADSL_LED_SUPPORT -#ifdef IFX_DYING_GASP -static int lop_poll(void *unused) -{ - - while(1) - { - interruptible_sleep_on_timeout(&wait_queue_dying_gasp, 1); -#ifdef CONFIG_CPU_AMAZON_E //000003:fchang - if(showtime&&((*((volatile u32 *)0xB0100B14))&0x4)==0x0) {//000003:fchang -#else //000003:fchang - if(showtime&&((*((volatile u32 *)0xB0100B44))&0x8000)==0x0) { -#endif //CONFIG_CPU_AMAZON_E - mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_WRITEDEBUG, &lop_debugwr); - printk("send dying gasp..\n");} - - } - return 0; - } -static int lop_poll_init(void) -{ -// printk("Starting LOP polling...\n"); - kernel_thread(lop_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL); - return 0; -} - -#endif //IFX_DYING_GASP - -//joelin 04/16/2005-satrt -static int unavailable_seconds_poll(void *unused) -{ - while(1){ - interruptible_sleep_on_timeout (&wait_queue_uas_poll,100); //1 second timeout for waiting wakeup - if (!showtime) unavailable_seconds++; - } - return 0; -} -static int unavailable_seconds_poll_init(void) -{ - - kernel_thread(unavailable_seconds_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL); - return 0; -} - - -//joelin 04/16/2005-end -EXPORT_SYMBOL(meiDebugWrite); -EXPORT_SYMBOL(ifx_pop_eoc); - -MODULE_LICENSE("GPL"); - -module_init(amazon_mei_init_module); -module_exit(amazon_mei_cleanup_module); - diff --git a/target/linux/amazon/files/drivers/char/ifx_ssc.c b/target/linux/amazon/files/drivers/char/ifx_ssc.c deleted file mode 100644 index ea01659a9..000000000 --- a/target/linux/amazon/files/drivers/char/ifx_ssc.c +++ /dev/null @@ -1,2121 +0,0 @@ -/************************************************** - * - * drivers/ifx/serial/ifx_ssc.c - * - * Driver for IFX_SSC serial ports - * - * Copyright (C) 2004 Infineon Technologies AG - * Author Michael Schoenenborn (IFX COM TI BT) - * - */ -#define IFX_SSC_DRV_VERSION "0.2.1" -/* - ************************************************** - * - * This driver was originally based on the INCA-IP driver, but due to - * fundamental conceptual drawbacks there has been changed a lot. - * - * Based on INCA-IP driver Copyright (c) 2003 Gary Jennejohn - * Based on the VxWorks drivers Copyright (c) 2002, Infineon Technologies. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -// ### TO DO: general issues: -// - power management -// - interrupt handling (direct/indirect) -// - pin/mux-handling (just overall concept due to project dependency) -// - multiple instances capability -// - slave functionality - -/* - * Include section - */ -#ifndef EXPORT_SYMTAB -#define EXPORT_SYMTAB -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -//#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#ifdef SSC_FRAME_INT_ENABLE -#undef SSC_FRAME_INT_ENABLE -#endif - -#define not_yet - -#define SPI_VINETIC - -/* - * Deal with CONFIG_MODVERSIONS - */ -#if CONFIG_MODVERSIONS==1 -# include -#endif - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Michael Schoenenborn"); -MODULE_DESCRIPTION("IFX SSC driver"); -MODULE_SUPPORTED_DEVICE("ifx_ssc"); -MODULE_PARM(maj, "i"); -MODULE_PARM_DESC(maj, "Major device number"); - -/* allow the user to set the major device number */ -static int maj = 0; - - -/* - * This is the per-channel data structure containing pointers, flags - * and variables for the port. This driver supports a maximum of PORT_CNT. - * isp is allocated in ifx_ssc_init() based on the chip version. - */ -static struct ifx_ssc_port *isp; - -/* prototypes for fops */ -static ssize_t ifx_ssc_read(struct file *, char *, size_t, loff_t *); -static ssize_t ifx_ssc_write(struct file *, const char *, size_t, loff_t *); -//static unsigned int ifx_ssc_poll(struct file *, struct poll_table_struct *); -int ifx_ssc_ioctl(struct inode *, struct file *, unsigned int, unsigned long); -int ifx_ssc_open(struct inode *, struct file *); -int ifx_ssc_close(struct inode *, struct file *); - -/* other forward declarations */ -static unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info); -static void ifx_ssc_rx_int(int, void *, struct pt_regs *); -static void ifx_ssc_tx_int(int, void *, struct pt_regs *); -static void ifx_ssc_err_int(int, void *, struct pt_regs *); -#ifdef SSC_FRAME_INT_ENABLE -static void ifx_ssc_frm_int(int, void *, struct pt_regs *); -#endif -static void tx_int(struct ifx_ssc_port *); -static int ifx_ssc1_read_proc(char *, char **, off_t, int, int *, void *); -static void ifx_gpio_init(void); -/************************************************************************ - * Function declaration - ************************************************************************/ -//interrupt.c -extern unsigned int amazon_get_fpi_hz(void); -extern void disable_amazon_irq(unsigned int irq_nr); -extern void enable_amazon_irq(unsigned int irq_nr); -extern void mask_and_ack_amazon_irq(unsigned int irq_nr); - - -/*****************************************************************/ -typedef struct { - int (*request)(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, - const char * devname, - void *dev_id); - void (*free)(unsigned int irq, void *dev_id); - void (*enable)(unsigned int irq); - void (*disable)(unsigned int irq); - void (*clear)(unsigned int irq); -} ifx_int_wrapper_t; - -static ifx_int_wrapper_t ifx_int_wrapper = { - request: request_irq, // IM action: enable int - free: free_irq, // IM action: disable int - enable: enable_amazon_irq, - disable: disable_amazon_irq, - clear: mask_and_ack_amazon_irq, - //end: -}; - -/* Fops-struct */ -static struct file_operations ifx_ssc_fops = { - owner: THIS_MODULE, - read: ifx_ssc_read, /* read */ - write: ifx_ssc_write, /* write */ -// poll: ifx_ssc_poll, /* poll */ - ioctl: ifx_ssc_ioctl, /* ioctl */ - open: ifx_ssc_open, /* open */ - release: ifx_ssc_close, /* release */ -}; - - -static inline unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info) -{ // ATTENTION: This function assumes that the CLC register is set with the - // appropriate value for RMC. - unsigned int rmc; - - rmc = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_CLC) & - IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET; - if (rmc == 0){ - printk("ifx_ssc_get_kernel_clk rmc==0 \n"); - return (0); - } - return (amazon_get_fpi_hz() / rmc); -} - -#ifndef not_yet -#ifdef IFX_SSC_INT_USE_BH -/* - * This routine is used by the interrupt handler to schedule - * processing in the software interrupt portion of the driver - * (also known as the "bottom half"). This can be called any - * number of times for any channel without harm. - */ -static inline void -ifx_ssc_sched_event(struct ifx_ssc_port *info, int event) -{ - info->event |= 1 << event; /* remember what kind of event and who */ - queue_task(&info->tqueue, &tq_cyclades); /* it belongs to */ - mark_bh(CYCLADES_BH); /* then trigger event */ -} /* ifx_ssc_sched_event */ - - -/* - * This routine is used to handle the "bottom half" processing for the - * serial driver, known also the "software interrupt" processing. - * This processing is done at the kernel interrupt level, after the - * cy#/_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This - * is where time-consuming activities which can not be done in the - * interrupt driver proper are done; the interrupt driver schedules - * them using ifx_ssc_sched_event(), and they get done here. - * - * This is done through one level of indirection--the task queue. - * When a hardware interrupt service routine wants service by the - * driver's bottom half, it enqueues the appropriate tq_struct (one - * per port) to the tq_cyclades work queue and sets a request flag - * via mark_bh for processing that queue. When the time is right, - * do_ifx_ssc_bh is called (because of the mark_bh) and it requests - * that the work queue be processed. - * - * Although this may seem unwieldy, it gives the system a way to - * pass an argument (in this case the pointer to the ifx_ssc_port - * structure) to the bottom half of the driver. Previous kernels - * had to poll every port to see if that port needed servicing. - */ -static void -do_ifx_ssc_bh(void) -{ - run_task_queue(&tq_cyclades); -} /* do_ifx_ssc_bh */ - -static void -do_softint(void *private_) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *) private_; - - if (test_and_clear_bit(Cy_EVENT_HANGUP, &info->event)) { - wake_up_interruptible(&info->open_wait); - info->flags &= ~(ASYNC_NORMAL_ACTIVE| - ASYNC_CALLOUT_ACTIVE); - } - if (test_and_clear_bit(Cy_EVENT_OPEN_WAKEUP, &info->event)) { - wake_up_interruptible(&info->open_wait); - } - if (test_and_clear_bit(Cy_EVENT_DELTA_WAKEUP, &info->event)) { - wake_up_interruptible(&info->delta_msr_wait); - } - if (test_and_clear_bit(Cy_EVENT_WRITE_WAKEUP, &info->event)) { - wake_up_interruptible(&tty->write_wait); - } -#ifdef Z_WAKE - if (test_and_clear_bit(Cy_EVENT_SHUTDOWN_WAKEUP, &info->event)) { - wake_up_interruptible(&info->shutdown_wait); - } -#endif -} /* do_softint */ -#endif /* IFX_SSC_INT_USE_BH */ -#endif // not_yet - -inline static void -rx_int(struct ifx_ssc_port *info) -{ - int fifo_fill_lev, bytes_in_buf, i; - unsigned long tmp_val; - unsigned long *tmp_ptr; - unsigned int rx_valid_cnt; - /* number of words waiting in the RX FIFO */ - fifo_fill_lev = (READ_PERIPHERAL_REGISTER(info->mapbase + - IFX_SSC_FSTAT) & - IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> - IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET; - // Note: There are always 32 bits in a fifo-entry except for the last - // word of a contigous transfer block and except for not in rx-only - // mode and CON.ENBV set. But for this case it should be a convention - // in software which helps: - // In tx or rx/tx mode all transfers from the buffer to the FIFO are - // 32-bit wide, except for the last three bytes, which could be a - // combination of 16- and 8-bit access. - // => The whole block is received as 32-bit words as a contigous stream, - // even if there was a gap in tx which has the fifo run out of data! - // Just the last fifo entry *may* be partially filled (0, 1, 2 or 3 bytes)! - - /* free space in the RX buffer */ - bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr; - // transfer with 32 bits per entry - while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) { - tmp_ptr = (unsigned long *)info->rxbuf_ptr; - *tmp_ptr = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RB); - info->rxbuf_ptr += 4; - info->stats.rxBytes += 4; - fifo_fill_lev --; - bytes_in_buf -= 4; - } // while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) - // now do the rest as mentioned in STATE.RXBV - while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) { - rx_valid_cnt = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & - IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> - IFX_SSC_STATE_RX_BYTE_VALID_OFFSET; - if (rx_valid_cnt == 0) break; - if (rx_valid_cnt > bytes_in_buf) { - // ### TO DO: warning message: not block aligned data, other data - // in this entry will be lost - rx_valid_cnt = bytes_in_buf; - } - tmp_val = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RB); - - for (i=0; irxbuf_ptr = (tmp_val >> ( 8 * (rx_valid_cnt - i-1))) & 0xff; -/* - *info->rxbuf_ptr = tmp_val & 0xff; - tmp_val >>= 8; -*/ - bytes_in_buf--; - - - info->rxbuf_ptr++; - } - info->stats.rxBytes += rx_valid_cnt; - } // while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) - - // check if transfer is complete - if (info->rxbuf_ptr >= info->rxbuf_end) { - ifx_int_wrapper.disable(info->rxirq); - /* wakeup any processes waiting in read() */ - wake_up_interruptible(&info->rwait); - /* and in poll() */ - //wake_up_interruptible(&info->pwait); - } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && - (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) == 0)) { - // if buffer not filled completely and rx request done initiate new transfer -/* - if (info->rxbuf_end - info->rxbuf_ptr < 65536) -*/ - if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE) - WRITE_PERIPHERAL_REGISTER((info->rxbuf_end - info->rxbuf_ptr) << - IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - else - WRITE_PERIPHERAL_REGISTER(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - } -} // rx_int - -inline static void -tx_int(struct ifx_ssc_port *info) -{ - - int fifo_space, fill, i; - fifo_space = ((READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_ID) & - IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) - - ((READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_FSTAT) & - IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> - IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET); - - if (fifo_space == 0) - return; - - fill = info->txbuf_end - info->txbuf_ptr; - - if (fill > fifo_space * 4) - fill = fifo_space * 4; - - for (i = 0; i < fill / 4; i++) { - // at first 32 bit access - WRITE_PERIPHERAL_REGISTER(*(UINT32 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB); - info->txbuf_ptr += 4; - } - - fifo_space -= fill / 4; - info->stats.txBytes += fill & ~0x3; - fill &= 0x3; - if ((fifo_space > 0) & (fill > 1)) { - // trailing 16 bit access - WRITE_PERIPHERAL_REGISTER_16(*(UINT16 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB); - info->txbuf_ptr += 2; - info->stats.txBytes += 2; - fifo_space --; -/* added by bingtao */ - fill -=2; - } - if ((fifo_space > 0) & (fill > 0)) { - // trailing 8 bit access - WRITE_PERIPHERAL_REGISTER_8(*(UINT8 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB); - info->txbuf_ptr ++; - info->stats.txBytes ++; -/* - fifo_space --; -*/ - } - - // check if transmission complete - if (info->txbuf_ptr >= info->txbuf_end) { - ifx_int_wrapper.disable(info->txirq); - kfree(info->txbuf); - info->txbuf = NULL; - /* wake up any process waiting in poll() */ - //wake_up_interruptible(&info->pwait); - } - -} // tx_int - -static void -ifx_ssc_rx_int(int irq, void *dev_id, struct pt_regs *regs) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id; - //WRITE_PERIPHERAL_REGISTER(IFX_SSC_R_BIT, info->mapbase + IFX_SSC_IRN_CR); - rx_int(info); -} - -static void -ifx_ssc_tx_int(int irq, void *dev_id, struct pt_regs *regs) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id; - //WRITE_PERIPHERAL_REGISTER(IFX_SSC_T_BIT, info->mapbase + IFX_SSC_IRN_CR); - tx_int(info); -} - -static void -ifx_ssc_err_int(int irq, void *dev_id, struct pt_regs *regs) -{ - struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id; - unsigned int state; - unsigned int write_back = 0; - unsigned long flags; - - - local_irq_save(flags); - state = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE); - - if ((state & IFX_SSC_STATE_RX_UFL) != 0) { - info->stats.rxUnErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR; - } - if ((state & IFX_SSC_STATE_RX_OFL) != 0) { - info->stats.rxOvErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR; - } - if ((state & IFX_SSC_STATE_TX_OFL) != 0) { - info->stats.txOvErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR; - } - if ((state & IFX_SSC_STATE_TX_UFL) != 0) { - info->stats.txUnErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR; - } -// if ((state & IFX_SSC_STATE_ABORT_ERR) != 0) { -// info->stats.abortErr++; -// write_back |= IFX_SSC_WHBSTATE_CLR_ABORT_ERROR; -// } - if ((state & IFX_SSC_STATE_MODE_ERR) != 0) { - info->stats.modeErr++; - write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR; - } - - if (write_back) - WRITE_PERIPHERAL_REGISTER(write_back, - info->mapbase + IFX_SSC_WHBSTATE); - - local_irq_restore(flags); -} - -#ifdef SSC_FRAME_INT_ENABLE -static void -ifx_ssc_frm_int(int irq, void *dev_id, struct pt_regs *regs) -{ - // ### TO DO: wake up framing wait-queue in conjunction with batch execution -} -#endif - -static void -ifx_ssc_abort(struct ifx_ssc_port *info) -{ - unsigned long flags; - bool enabled; - - local_irq_save(flags); - - // disable all int's - ifx_int_wrapper.disable(info->rxirq); - ifx_int_wrapper.disable(info->txirq); - ifx_int_wrapper.disable(info->errirq); -/* - ifx_int_wrapper.disable(info->frmirq); -*/ - local_irq_restore(flags); - - // disable SSC (also aborts a receive request!) - // ### TO DO: Perhaps it's better to abort after the receiption of a - // complete word. The disable cuts the transmission immediatly and - // releases the chip selects. This could result in unpredictable - // behavior of connected external devices! - enabled = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) - & IFX_SSC_STATE_IS_ENABLED) != 0; - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - - // flush fifos - WRITE_PERIPHERAL_REGISTER(IFX_SSC_XFCON_FIFO_FLUSH, - info->mapbase + IFX_SSC_TXFCON); - WRITE_PERIPHERAL_REGISTER(IFX_SSC_XFCON_FIFO_FLUSH, - info->mapbase + IFX_SSC_RXFCON); - - // free txbuf - if (info->txbuf != NULL) { - kfree(info->txbuf); - info->txbuf = NULL; - } - - // wakeup read process - if (info->rxbuf != NULL) - wake_up_interruptible(&info->rwait); - - // clear pending int's - ifx_int_wrapper.clear(info->rxirq); - ifx_int_wrapper.clear(info->txirq); - ifx_int_wrapper.clear(info->errirq); -/* - ifx_int_wrapper.clear(info->frmirq); -*/ - - // clear error flags - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, - info->mapbase + IFX_SSC_WHBSTATE); - - //printk("IFX SSC%d: Transmission aborted\n", info->port_nr); - // enable SSC - if (enabled) - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - -} // ifx_ssc_abort - - -/* - * This routine is called whenever a port is opened. It enforces - * exclusive opening of a port and enables interrupts, etc. - */ -int -ifx_ssc_open(struct inode *inode, struct file * filp) -{ - struct ifx_ssc_port *info; - int line; - int from_kernel = 0; - - if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) { - from_kernel = 1; - line = (int)inode; - } - else { - line = MINOR(filp->f_dentry->d_inode->i_rdev); - filp->f_op = &ifx_ssc_fops; - } - - /* don't open more minor devices than we can support */ - if (line < 0 || line >= PORT_CNT) - return -ENXIO; - - info = &isp[line]; - - /* exclusive open */ - if (info->port_is_open != 0) - return -EBUSY; - info->port_is_open++; - - ifx_int_wrapper.disable(info->rxirq); - ifx_int_wrapper.disable(info->txirq); - ifx_int_wrapper.disable(info->errirq); -/* - ifx_int_wrapper.disable(info->frmirq); -*/ - - /* Flush and enable TX/RX FIFO */ - WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_TXFIFO_FL << - IFX_SSC_XFCON_ITL_OFFSET) | - IFX_SSC_XFCON_FIFO_FLUSH | - IFX_SSC_XFCON_FIFO_ENABLE, - info->mapbase + IFX_SSC_TXFCON); - WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_RXFIFO_FL << - IFX_SSC_XFCON_ITL_OFFSET) | - IFX_SSC_XFCON_FIFO_FLUSH | - IFX_SSC_XFCON_FIFO_ENABLE, - info->mapbase + IFX_SSC_RXFCON); - - - /* logically flush the software FIFOs */ - info->rxbuf_ptr = 0; - info->txbuf_ptr = 0; - - /* clear all error bits */ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, - info->mapbase + IFX_SSC_WHBSTATE); - - // clear pending interrupts - ifx_int_wrapper.clear(info->rxirq); - ifx_int_wrapper.clear(info->txirq); - ifx_int_wrapper.clear(info->errirq); -/* - ifx_int_wrapper.clear(info->frmirq); -*/ - - // enable SSC - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - MOD_INC_USE_COUNT; - - return 0; -} /* ifx_ssc_open */ -EXPORT_SYMBOL(ifx_ssc_open); - -/* - * This routine is called when a particular device is closed. - */ -int -ifx_ssc_close(struct inode *inode, struct file *filp) -{ - struct ifx_ssc_port *info; - int idx; - - if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) - idx = (int)inode; - else - idx = MINOR(filp->f_dentry->d_inode->i_rdev); - - if (idx < 0 || idx >= PORT_CNT) - return -ENXIO; - - info = &isp[idx]; - if (!info) - return -ENXIO; - - // disable SSC - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - // call abort function to disable int's, flush fifos... - ifx_ssc_abort(info); - - info->port_is_open --; - MOD_DEC_USE_COUNT; - - return 0; -} /* ifx_ssc_close */ -EXPORT_SYMBOL(ifx_ssc_close); - -/* added by bingtao */ -/* helper routine to handle reads from the kernel or user-space */ -/* info->rxbuf : never kfree and contains valid data */ -/* should be points to NULL after copying data !!! */ -static ssize_t -ifx_ssc_read_helper_poll(struct ifx_ssc_port *info, char *buf, size_t len, - int from_kernel) -{ - ssize_t ret_val; - unsigned long flags; - - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) - return -EFAULT; - local_irq_save(flags); - info->rxbuf_ptr = info->rxbuf; - info->rxbuf_end = info->rxbuf + len; - local_irq_restore(flags); -/* Vinetic driver always works in IFX_SSC_MODE_RXTX */ -/* TXRX in poll mode */ - while (info->rxbuf_ptr < info->rxbuf_end){ -/* This is the key point, if you don't check this condition - kfree (NULL) will happen - because tx only need write into FIFO, it's much fast than rx - So when rx still waiting , tx already finish and release buf -*/ - if (info->txbuf_ptr < info->txbuf_end) { - tx_int(info); - } - - rx_int(info); - }; - - ret_val = info->rxbuf_ptr - info->rxbuf; - return (ret_val); -} // ifx_ssc_read_helper_poll - -/* helper routine to handle reads from the kernel or user-space */ -/* info->rx_buf : never kfree and contains valid data */ -/* should be points to NULL after copying data !!! */ -static ssize_t -ifx_ssc_read_helper(struct ifx_ssc_port *info, char *buf, size_t len, - int from_kernel) -{ - ssize_t ret_val; - unsigned long flags; - DECLARE_WAITQUEUE(wait, current); - - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) - return -EFAULT; - local_irq_save(flags); - info->rxbuf_ptr = info->rxbuf; - info->rxbuf_end = info->rxbuf + len; - if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) { - if ((info->txbuf == NULL) || - (info->txbuf != info->txbuf_ptr) || - (info->txbuf_end != len + info->txbuf)) { - local_irq_restore(flags); - printk("IFX SSC - %s: write must be called before calling " - "read in combined RX/TX!\n", __FUNCTION__); - return -EFAULT; - } - local_irq_restore(flags); - /* should enable tx, right?*/ - tx_int(info); - if (info->txbuf_ptr < info->txbuf_end){ - ifx_int_wrapper.enable(info->txirq); - } - - ifx_int_wrapper.enable(info->rxirq); - } else { // rx mode - local_irq_restore(flags); - if (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) & - IFX_SSC_RXCNT_TODO_MASK) - return -EBUSY; - ifx_int_wrapper.enable(info->rxirq); - // rx request limited to ' bytes -/* - if (len < 65536) -*/ - if (len < IFX_SSC_RXREQ_BLOCK_SIZE) - WRITE_PERIPHERAL_REGISTER(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - else - WRITE_PERIPHERAL_REGISTER(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - } - - __add_wait_queue(&info->rwait, &wait); - set_current_state(TASK_INTERRUPTIBLE); - // wakeup done in rx_int - - do { - local_irq_save(flags); - if (info->rxbuf_ptr >= info->rxbuf_end) - break; - local_irq_restore(flags); - -// if (filp->f_flags & O_NONBLOCK) -// { -// N = -EAGAIN; -// goto out; -// } - if (signal_pending(current)) { - ret_val = -ERESTARTSYS; - goto out; - } - schedule(); - } while (1); - - ret_val = info->rxbuf_ptr - info->rxbuf; // should be equal to len - local_irq_restore(flags); - - out: - current->state = TASK_RUNNING; - __remove_wait_queue(&info->rwait, &wait); - return (ret_val); -} // ifx_ssc_read_helper - - -#if 0 -/* helper routine to handle reads from the kernel or user-space */ -/* appropriate in interrupt context */ -static ssize_t -ifx_ssc_read_helper(struct ifx_ssc_port *info, char *buf, size_t len, - int from_kernel) -{ - ssize_t ret_val; - unsigned long flags; - DECLARE_WAITQUEUE(wait, current); - - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) - return -EFAULT; - local_irq_save(flags); - info->rxbuf_ptr = info->rxbuf; - info->rxbuf_end = info->rxbuf + len; - if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) { - if ((info->txbuf == NULL) || - (info->txbuf != info->txbuf_ptr) || - (info->txbuf_end != len + info->txbuf)) { - local_irq_restore(flags); - printk("IFX SSC - %s: write must be called before calling " - "read in combined RX/TX!\n", __FUNCTION__); - return -EFAULT; - } - local_irq_restore(flags); - /* should enable tx, right?*/ - tx_int(info); - if (!in_irq()){ - if (info->txbuf_ptr < info->txbuf_end){ - ifx_int_wrapper.enable(info->txirq); - } - ifx_int_wrapper.enable(info->rxirq); - } - } else { // rx mode - local_irq_restore(flags); - if (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) & - IFX_SSC_RXCNT_TODO_MASK) - return -EBUSY; - if (!in_irq()){ - ifx_int_wrapper.enable(info->rxirq); - } - - if (len < IFX_SSC_RXREQ_BLOCK_SIZE) - WRITE_PERIPHERAL_REGISTER(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - else - WRITE_PERIPHERAL_REGISTER(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, - info->mapbase + IFX_SSC_RXREQ); - } - if (in_irq()){ - do { - rx_int(info); - if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) { - tx_int(info); - } - - if (info->rxbuf_ptr >= info->rxbuf_end) - break; - } while (1); - ret_val = info->rxbuf_ptr - info->rxbuf; - }else{ - __add_wait_queue(&info->rwait, &wait); - set_current_state(TASK_INTERRUPTIBLE); - // wakeup done in rx_int - - do { - local_irq_save(flags); - if (info->rxbuf_ptr >= info->rxbuf_end) - break; - local_irq_restore(flags); - - if (signal_pending(current)) { - ret_val = -ERESTARTSYS; - goto out; - } - schedule(); - } while (1); - - ret_val = info->rxbuf_ptr - info->rxbuf; // should be equal to len - local_irq_restore(flags); - - out: - current->state = TASK_RUNNING; - __remove_wait_queue(&info->rwait, &wait); - } - return (ret_val); -} // ifx_ssc_read_helper -#endif - -/* helper routine to handle writes to the kernel or user-space */ -/* info->txbuf has two cases: - * 1) return value < 0 (-EFAULT), not touched at all - * 2) kfree and points to NULL in interrupt routine (but maybe later ) - */ -static ssize_t -ifx_ssc_write_helper(struct ifx_ssc_port *info, const char *buf, - size_t len, int from_kernel) -{ - // check if in tx or tx/rx mode - if (info->opts.modeRxTx == IFX_SSC_MODE_RX) - return -EFAULT; - - info->txbuf_ptr = info->txbuf; - info->txbuf_end = len + info->txbuf; - /* start the transmission (not in rx/tx, see read helper) */ - if (info->opts.modeRxTx == IFX_SSC_MODE_TX) { - tx_int(info); - if (info->txbuf_ptr < info->txbuf_end){ - ifx_int_wrapper.enable(info->txirq); - } - } - //local_irq_restore(flags); - return len; -} - -/* - * kernel interfaces for read and write. - * The caller must set port to: n for SSC with n=m-1 (e.g. n=0 for SSC1) - */ -ssize_t -ifx_ssc_kread(int port, char *kbuf, size_t len) -{ - struct ifx_ssc_port *info; - ssize_t ret_val; - - if (port < 0 || port >= PORT_CNT) - return -ENXIO; - - if (len == 0) - return 0; - - info = &isp[port]; - - // check if reception in progress - if (info->rxbuf != NULL){ - printk("SSC device busy\n"); - return -EBUSY; - } - - info->rxbuf = kbuf; - if (info->rxbuf == NULL){ - printk("SSC device error\n"); - return -EINVAL; - } - -/* changed by bingtao */ - /* change by TaiCheng */ - //if (!in_irq()){ - if (0){ - ret_val = ifx_ssc_read_helper(info, kbuf, len, 1); - }else{ - ret_val = ifx_ssc_read_helper_poll(info, kbuf, len, 1); - }; - info->rxbuf = NULL; - - // ### TO DO: perhaps warn if ret_val != len - ifx_int_wrapper.disable(info->rxirq); - - return (ret_val); -} // ifx_ssc_kread -EXPORT_SYMBOL(ifx_ssc_kread); - -ssize_t -ifx_ssc_kwrite(int port, const char *kbuf, size_t len) -{ - struct ifx_ssc_port *info; - ssize_t ret_val; - - if (port < 0 || port >= PORT_CNT) - return -ENXIO; - - if (len == 0) - return 0; - - info = &isp[port]; - - // check if transmission in progress - if (info->txbuf != NULL) - return -EBUSY; - info->txbuf = (char *)kbuf; - - ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 1); - if (ret_val < 0){ - info->txbuf = NULL; - } - return ret_val; -} -EXPORT_SYMBOL(ifx_ssc_kwrite); - - -/* - * user interfaces to read and write - */ -static ssize_t -ifx_ssc_read(struct file *filp, char *ubuf, size_t len, loff_t *off) -{ - ssize_t ret_val; - int idx; - struct ifx_ssc_port *info; - -/* - if (len == 0) - return (0); -*/ - idx = MINOR(filp->f_dentry->d_inode->i_rdev); - info = &isp[idx]; - - // check if reception in progress - if (info->rxbuf != NULL) - return -EBUSY; - - info->rxbuf = kmalloc(len+ 3, GFP_KERNEL); - if (info->rxbuf == NULL) - return -ENOMEM; - - ret_val = ifx_ssc_read_helper(info, info->rxbuf, len, 0); - // ### TO DO: perhaps warn if ret_val != len - if (copy_to_user((void*)ubuf, info->rxbuf, ret_val) != 0) - ret_val = -EFAULT; - - ifx_int_wrapper.disable(info->rxirq); - - kfree(info->rxbuf); - info->rxbuf = NULL; - return (ret_val); -} // ifx_ssc_read - -/* - * As many bytes as we have free space for are copied from the user - * into txbuf and the actual byte count is returned. The transmission is - * always kicked off by calling the appropriate TX routine. - */ -static ssize_t -ifx_ssc_write(struct file *filp, const char *ubuf, size_t len, loff_t *off) -{ - int idx; - struct ifx_ssc_port *info; - int ret_val; - - if (len == 0) - return (0); - - idx = MINOR(filp->f_dentry->d_inode->i_rdev); - info = &isp[idx]; - - // check if transmission in progress - if (info->txbuf != NULL) - return -EBUSY; - - info->txbuf = kmalloc(len+ 3, GFP_KERNEL); - if (info->txbuf == NULL) - return -ENOMEM; - - ret_val = copy_from_user(info->txbuf, ubuf, len); - if (ret_val == 0) - ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 0); - else - ret_val = -EFAULT; - if (ret_val < 0) { - kfree(info->txbuf); // otherwise will be done in ISR - info->txbuf = NULL; - } - return (ret_val); -} /* ifx_ssc_write */ - - -/* - * ------------------------------------------------------------ - * ifx_ssc_ioctl() and friends - * ------------------------------------------------------------ - */ - -/*----------------------------------------------------------------------------- - FUNC-NAME : ifx_ssc_frm_status_get - LONG-NAME : framing status get - PURPOSE : Get the actual status of the framing. - - PARAMETER : *info pointer to the port-specific structure ifx_ssc_port. - - RESULT : pointer to a structure ifx_ssc_frm_status which holds busy and - count values. - - REMARKS : Returns a register value independent of framing is enabled or - not! Changes structure inside of info, so the return value isn't - needed at all, but could be used for simple access. ------------------------------------------------------------------------------*/ -static struct ifx_ssc_frm_status * -ifx_ssc_frm_status_get(struct ifx_ssc_port *info) -{ - unsigned long tmp; - - tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFSTAT); - info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0; - info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0; - info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) - >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET; - info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) - >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET; - tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFCON); - info->frm_status.EnIntAfterData = - (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0; - info->frm_status.EnIntAfterPause = - (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0; - return (&info->frm_status); -} // ifx_ssc_frm_status_get - - -/*----------------------------------------------------------------------------- - FUNC-NAME : ifx_ssc_frm_control_get - LONG-NAME : framing control get - PURPOSE : Get the actual control values of the framing. - - PARAMETER : *info pointer to the port-specific structure ifx_ssc_port. - - RESULT : pointer to a structure ifx_ssc_frm_opts which holds control bits - and count reload values. - - REMARKS : Changes structure inside of info, so the return value isn't - needed at all, but could be used for simple access. ------------------------------------------------------------------------------*/ -static struct ifx_ssc_frm_opts * -ifx_ssc_frm_control_get(struct ifx_ssc_port *info) -{ - unsigned long tmp; - - tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFCON); - info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0; - info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) - >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET; - info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) - >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET; - info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) - >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET; - info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) - >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET; - info->frm_opts.StopAfterPause = - (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0; - return (&info->frm_opts); -} // ifx_ssc_frm_control_get - - -/*----------------------------------------------------------------------------- - FUNC-NAME : ifx_ssc_frm_control_set - LONG-NAME : framing control set - PURPOSE : Set the actual control values of the framing. - - PARAMETER : *info pointer to the port-specific structure ifx_ssc_port. - - RESULT : pointer to a structure ifx_ssc_frm_opts which holds control bits - and count reload values. - - REMARKS : ------------------------------------------------------------------------------*/ -static int -ifx_ssc_frm_control_set(struct ifx_ssc_port *info) -{ - unsigned long tmp; - - // check parameters - if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX) || - (info->frm_opts.DataLength < 1) || - (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX) || - (info->frm_opts.PauseLength < 1) || - ((info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> - IFX_SSC_SFCON_PAUSE_DATA_OFFSET)) != 0 ) || - ((info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> - IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)) != 0 )) - return -EINVAL; - - // read interrupt bits (they're not changed here) - tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFCON) & - (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | - IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE); - - // set all values with respect to it's bit position (for data and pause - // length set N-1) - tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET; - tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET; - tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET; - tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET; - tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE; - tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE; - - WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_SFCON); - - return 0; -} // ifx_ssc_frm_control_set - - -/*----------------------------------------------------------------------------- - FUNC-NAME : ifx_ssc_rxtx_mode_set - LONG-NAME : rxtx mode set - PURPOSE : Set the transmission mode. - - PARAMETER : *info pointer to the port-specific structure ifx_ssc_port. - - RESULT : Returns error code - - REMARKS : Assumes that SSC not used (SSC disabled, device not opened yet - or just closed) ------------------------------------------------------------------------------*/ -static int -ifx_ssc_rxtx_mode_set(struct ifx_ssc_port *info, unsigned int val) -{ - unsigned long tmp; - - // check parameters - if (!(info) || (val & ~(IFX_SSC_MODE_MASK))) - return -EINVAL; - /*check BUSY and RXCNT*/ - if ( READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_BUSY - ||READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK) - return -EBUSY; - // modify - tmp = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_CON) & - ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val); - WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_CON); - info->opts.modeRxTx = val; -/* - printk(KERN_DEBUG "IFX SSC%d: Setting mode to %s%s\n", - info->port_nr, - ((val & IFX_SSC_CON_RX_OFF) == 0) ? "rx ":"", - ((val & IFX_SSC_CON_TX_OFF) == 0) ? "tx":""); -*/ - return 0; -} // ifx_ssc_rxtx_mode_set - -void ifx_gpio_init(void) -{ - u32 temp; -/* set gpio pin p0.10(SPI_DIN) p0.11(SPI_DOUT) p0.12(SPI_CLK) p0.13(SPI_CS2) direction */ - temp = *(AMAZON_GPIO_P0_DIR) ; - temp &= 0xFFFFFBFF; - temp |= 0x3800; - *(AMAZON_GPIO_P0_DIR) = temp; -/* set port 0 alternate select register 0 */ - temp = *(AMAZON_GPIO_P0_ALTSEL0) ; - temp &= 0xFFFFC3FF; - temp |= 0x00001c00; - *(AMAZON_GPIO_P0_ALTSEL0) = temp; - -/* set port 0 alternate select register 1 */ - temp = *(AMAZON_GPIO_P0_ALTSEL1) ; - temp &= 0xFFFFC3FF; - temp |= 0x00002000; - *(AMAZON_GPIO_P0_ALTSEL1) = temp; - -/* set port 0 open drain mode register */ - temp = *(AMAZON_GPIO_P0_OD); - temp |= 0x00003800; /* set output pin normal mode */ - *(AMAZON_GPIO_P0_OD)= temp; -} - -/* - * This routine intializes the SSC appropriately depending - * on slave/master and full-/half-duplex mode. - * It assumes that the SSC is disabled and the fifo's and buffers - * are flushes later on. - */ -static int -ifx_ssc_sethwopts(struct ifx_ssc_port *info) -{ - unsigned long flags, bits; - struct ifx_ssc_hwopts *opts = &info->opts; - - /* sanity checks */ - if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH) || - (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH)) { - printk("%s: sanity check failed\n", __FUNCTION__); - return -EINVAL; - } - bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET; - bits |= IFX_SSC_CON_ENABLE_BYTE_VALID; -// if (opts->abortErrDetect) -// bits |= IFX_SSC_CON_ABORT_ERR_CHECK; - if (opts->rxOvErrDetect) - bits |= IFX_SSC_CON_RX_OFL_CHECK; - if (opts->rxUndErrDetect) - bits |= IFX_SSC_CON_RX_UFL_CHECK; - if (opts->txOvErrDetect) - bits |= IFX_SSC_CON_TX_OFL_CHECK; - if (opts->txUndErrDetect) - bits |= IFX_SSC_CON_TX_UFL_CHECK; - if (opts->loopBack) - bits |= IFX_SSC_CON_LOOPBACK_MODE; - if (opts->echoMode) - bits |= IFX_SSC_CON_ECHO_MODE_ON; - if (opts->headingControl) - bits |= IFX_SSC_CON_MSB_FIRST; - if (opts->clockPhase) - bits |= IFX_SSC_CON_LATCH_THEN_SHIFT; - if (opts->clockPolarity) - bits |= IFX_SSC_CON_CLOCK_FALL; - switch (opts->modeRxTx) { - case IFX_SSC_MODE_TX: - bits |= IFX_SSC_CON_RX_OFF; - break; - case IFX_SSC_MODE_RX: - bits |= IFX_SSC_CON_TX_OFF; - break; - } // switch (opts->modeRxT) - local_irq_save(flags); - WRITE_PERIPHERAL_REGISTER(bits, info->mapbase + IFX_SSC_CON); - WRITE_PERIPHERAL_REGISTER((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) | - (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), - info->mapbase + IFX_SSC_GPOCON); - //master mode - if (opts->masterSelect){ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_MASTER_SELECT,info->mapbase + IFX_SSC_WHBSTATE); - }else{ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT,info->mapbase + IFX_SSC_WHBSTATE); - } - // init serial framing - WRITE_PERIPHERAL_REGISTER(0, info->mapbase + IFX_SSC_SFCON); - /* set up the port pins */ - //check for general requirements to switch (external) pad/pin characteristics - ifx_gpio_init(); - local_irq_restore(flags); - - return 0; -} // ifx_ssc_sethwopts - -static int -ifx_ssc_set_baud(struct ifx_ssc_port *info, unsigned int baud) -{ - unsigned int ifx_ssc_clock; - unsigned int br; - unsigned long flags; - bool enabled; - - ifx_ssc_clock = ifx_ssc_get_kernel_clk(info); - if (ifx_ssc_clock ==0) - return -EINVAL; - - local_irq_save(flags); - /* have to disable the SSC to set the baudrate */ - enabled = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) - & IFX_SSC_STATE_IS_ENABLED) != 0; - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - // compute divider - br = ((ifx_ssc_clock >> 1)/baud) - 1; - asm("SYNC"); - if (br > 0xffff || - ((br == 0) && - ((READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & - IFX_SSC_STATE_IS_MASTER) == 0))){ - local_irq_restore(flags); - printk("%s: illegal baudrate %u\n", __FUNCTION__, baud); - return -EINVAL; - } - WRITE_PERIPHERAL_REGISTER(br, info->mapbase + IFX_SSC_BR); - if (enabled) - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - local_irq_restore(flags); - return 0; -} // ifx_ssc_set_baud - -static int -ifx_ssc_hwinit(struct ifx_ssc_port *info) -{ - unsigned long flags; - bool enabled; - - /* have to disable the SSC */ - enabled = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) - & IFX_SSC_STATE_IS_ENABLED) != 0; - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - - if (ifx_ssc_sethwopts(info) < 0) - { - printk("%s: setting the hardware options failed\n", - __FUNCTION__); - return -EINVAL; - } - - if (ifx_ssc_set_baud(info, info->baud) < 0) { - printk("%s: setting the baud rate failed\n", __FUNCTION__); - return -EINVAL; - } - local_irq_save(flags); - /* TX FIFO */ - WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_TXFIFO_FL << - IFX_SSC_XFCON_ITL_OFFSET) | - IFX_SSC_XFCON_FIFO_ENABLE, - info->mapbase + IFX_SSC_TXFCON); - /* RX FIFO */ - WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_RXFIFO_FL << - IFX_SSC_XFCON_ITL_OFFSET) | - IFX_SSC_XFCON_FIFO_ENABLE, - info->mapbase + IFX_SSC_RXFCON); - local_irq_restore(flags); - if (enabled) - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE, - info->mapbase + IFX_SSC_WHBSTATE); - return 0; -} // ifx_ssc_hwinit - -/*----------------------------------------------------------------------------- - FUNC-NAME : ifx_ssc_batch_exec - LONG-NAME : - PURPOSE : - - PARAMETER : *info pointer to the port-specific structure ifx_ssc_port. - - RESULT : Returns error code - - REMARKS : ------------------------------------------------------------------------------*/ -static int -ifx_ssc_batch_exec(struct ifx_ssc_port *info, struct ifx_ssc_batch_list *batch_anchor) -{ - // ### TO DO: implement user space batch execution - // first, copy the whole linked list from user to kernel space - // save some hardware options - // execute list - // restore hardware options if selected - return -EFAULT; -} // ifx_ssc_batch_exec - - -/* - * This routine allows the driver to implement device- - * specific ioctl's. If the ioctl number passed in cmd is - * not recognized by the driver, it should return ENOIOCTLCMD. - */ -int -ifx_ssc_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long data) -{ - struct ifx_ssc_port *info; - int line, ret_val = 0; - unsigned long flags; - unsigned long tmp; - int from_kernel = 0; - - if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) - { - from_kernel = 1; - line = (int)inode; - } - else - line = MINOR(filp->f_dentry->d_inode->i_rdev); - - /* don't use more minor devices than we can support */ - if (line < 0 || line >= PORT_CNT) - return -ENXIO; - - info = &isp[line]; - - switch (cmd) { - case IFX_SSC_STATS_READ: - /* data must be a pointer to a struct ifx_ssc_statistics */ - if (from_kernel) - memcpy((void *)data, (void *)&info->stats, - sizeof(struct ifx_ssc_statistics)); - else - if (copy_to_user((void *)data, - (void *)&info->stats, - sizeof(struct ifx_ssc_statistics))) - ret_val = -EFAULT; - break; - case IFX_SSC_STATS_RESET: - /* just resets the statistics counters */ - memset((void *)&info->stats, 0, sizeof(struct ifx_ssc_statistics)); - break; - case IFX_SSC_BAUD_SET: - /* if the buffers are not empty then the port is */ - /* busy and we shouldn't change things on-the-fly! */ - if (!info->txbuf || !info->rxbuf || - (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) - & IFX_SSC_STATE_BUSY)) { - ret_val = -EBUSY; - break; - } - /* misuse flags */ - if (from_kernel) - flags = *((unsigned long *)data); - else - if (copy_from_user((void *)&flags, - (void *)data, sizeof(flags))) - { - ret_val = -EFAULT; - break; - } - if (flags == 0) - { - ret_val = -EINVAL; - break; - } - if (ifx_ssc_set_baud(info, flags) < 0) - { - ret_val = -EINVAL; - break; - } - info->baud = flags; - break; - case IFX_SSC_BAUD_GET: - if (from_kernel) - *((unsigned int *)data) = info->baud; - else - if (copy_to_user((void *)data, - (void *)&info->baud, - sizeof(unsigned long))) - ret_val = -EFAULT; - break; - case IFX_SSC_RXTX_MODE_SET: - if (from_kernel) - tmp = *((unsigned long *)data); - else - if (copy_from_user((void *)&tmp, - (void *)data, sizeof(tmp))) { - ret_val = -EFAULT; - break; - } - ret_val = ifx_ssc_rxtx_mode_set(info, tmp); - break; - case IFX_SSC_RXTX_MODE_GET: - tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_CON) & - (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)); - if (from_kernel) - *((unsigned int *)data) = tmp; - else - if (copy_to_user((void *)data, - (void *)&tmp, - sizeof(tmp))) - ret_val = -EFAULT; - break; - - case IFX_SSC_ABORT: - ifx_ssc_abort(info); - break; - - case IFX_SSC_GPO_OUT_SET: - if (from_kernel) - tmp = *((unsigned long *)data); - else - if (copy_from_user((void *)&tmp, - (void *)data, sizeof(tmp))) { - ret_val = -EFAULT; - break; - } - if (tmp > IFX_SSC_MAX_GPO_OUT) - ret_val = -EINVAL; - else - WRITE_PERIPHERAL_REGISTER - (1<<(tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS), - info->mapbase + IFX_SSC_WHBGPOSTAT); - break; - case IFX_SSC_GPO_OUT_CLR: - if (from_kernel) - tmp = *((unsigned long *)data); - else - if (copy_from_user((void *)&tmp, - (void *)data, sizeof(tmp))) { - ret_val = -EFAULT; - break; - } - if (tmp > IFX_SSC_MAX_GPO_OUT) - ret_val = -EINVAL; - else { - WRITE_PERIPHERAL_REGISTER - (1<<(tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS), - info->mapbase + IFX_SSC_WHBGPOSTAT); - } - break; - case IFX_SSC_GPO_OUT_GET: - tmp = READ_PERIPHERAL_REGISTER - (info->mapbase + IFX_SSC_GPOSTAT); - if (from_kernel) - *((unsigned int *)data) = tmp; - else - if (copy_to_user((void *)data, - (void *)&tmp, - sizeof(tmp))) - ret_val = -EFAULT; - break; - case IFX_SSC_FRM_STATUS_GET: - ifx_ssc_frm_status_get(info); - if (from_kernel) - memcpy((void *)data, (void *)&info->frm_status, - sizeof(struct ifx_ssc_frm_status)); - else - if (copy_to_user((void *)data, - (void *)&info->frm_status, - sizeof(struct ifx_ssc_frm_status))) - ret_val = -EFAULT; - break; - case IFX_SSC_FRM_CONTROL_GET: - ifx_ssc_frm_control_get(info); - if (from_kernel) - memcpy((void *)data, (void *)&info->frm_opts, - sizeof(struct ifx_ssc_frm_opts)); - else - if (copy_to_user((void *)data, - (void *)&info->frm_opts, - sizeof(struct ifx_ssc_frm_opts))) - ret_val = -EFAULT; - break; - case IFX_SSC_FRM_CONTROL_SET: - if (from_kernel) - memcpy((void *)&info->frm_opts, (void *)data, - sizeof(struct ifx_ssc_frm_opts)); - else - if (copy_to_user((void *)&info->frm_opts, - (void *)data, - sizeof(struct ifx_ssc_frm_opts))){ - ret_val = -EFAULT; - break; - } - ret_val = ifx_ssc_frm_control_set(info); - break; - case IFX_SSC_HWOPTS_SET: - /* data must be a pointer to a struct ifx_ssc_hwopts */ - /* if the buffers are not empty then the port is */ - /* busy and we shouldn't change things on-the-fly! */ - if (!info->txbuf || !info->rxbuf || - (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) - & IFX_SSC_STATE_BUSY)) { - ret_val = -EBUSY; - break; - } - if (from_kernel) - memcpy((void *)&info->opts, (void *)data, - sizeof(struct ifx_ssc_hwopts)); - else - if (copy_from_user((void *)&info->opts, - (void *)data, - sizeof(struct ifx_ssc_hwopts))) - { - ret_val = -EFAULT; - break; - } - if (ifx_ssc_hwinit(info) < 0) - { - ret_val = -EIO; - } - break; - case IFX_SSC_HWOPTS_GET: - /* data must be a pointer to a struct ifx_ssc_hwopts */ - if (from_kernel) - memcpy((void *)data, (void *)&info->opts, - sizeof(struct ifx_ssc_hwopts)); - else - if (copy_to_user((void *)data, - (void *)&info->opts, - sizeof(struct ifx_ssc_hwopts))) - ret_val = -EFAULT; - break; - default: - ret_val = -ENOIOCTLCMD; - } - - return ret_val; -} /* ifx_ssc_ioctl */ -EXPORT_SYMBOL(ifx_ssc_ioctl); - -///* the poll routine */ -//static unsigned int -//ifx_ssc_poll(struct file *filp, struct poll_table_struct *pts) -//{ -// int unit = MINOR(filp->f_dentry->d_inode->i_rdev); -// struct ifx_ssc_port *info; -// unsigned int mask = 0; -// int spc; -// -// info = &isp[unit]; -// -// /* add event to the wait queues */ -// /* DO NOT FORGET TO DO A WAKEUP ON THESE !!!! */ -// poll_wait(filp, &info->pwait, pts); -// -// /* are there bytes in the RX SW-FIFO? */ -// if (info->rxrp != info->rxwp) -// mask |= POLLIN | POLLRDNORM; -// -// /* free space in the TX SW-FIFO */ -// spc = info->txrp - info->txwp - 1; -// if (spc < 0) -// spc += TX_BUFSIZE; -//#ifdef IFX_SSC_USEDMA -// /* writing always works, except in the DMA case when all descriptors */ -// /* are used up */ -// if (unit == 1 && info->dma_freecnt == 0) -// spc = 0; -//#endif -// if (spc > 0) -// mask |= POLLOUT | POLLWRNORM; -// -// return (mask); -//} - -static int -ifx_ssc1_read_proc(char *page, char **start, off_t offset, int count, int *eof, void *data) -{ - int off = 0; - unsigned long flags; - - /* don't want any interrupts here */ - save_flags(flags); - cli(); - - - /* print statistics */ - off += sprintf(page+off, "Statistics for Infineon Synchronous Serial Controller SSC1\n"); - off += sprintf(page+off, "RX overflow errors %d\n", isp[0].stats.rxOvErr); - off += sprintf(page+off, "RX underflow errors %d\n", isp[0].stats.rxUnErr); - off += sprintf(page+off, "TX overflow errors %d\n", isp[0].stats.txOvErr); - off += sprintf(page+off, "TX underflow errors %d\n", isp[0].stats.txUnErr); - off += sprintf(page+off, "Abort errors %d\n", isp[0].stats.abortErr); - off += sprintf(page+off, "Mode errors %d\n", isp[0].stats.modeErr); - off += sprintf(page+off, "RX Bytes %d\n", isp[0].stats.rxBytes); - off += sprintf(page+off, "TX Bytes %d\n", isp[0].stats.txBytes); - - restore_flags (flags); /* XXXXX */ - *eof = 1; - return (off); -} - - -/* - * This routine prints out the appropriate serial driver version number - */ -static inline void -show_version(void) -{ -#if 0 - printk("Infineon Technologies Synchronous Serial Controller (SSC) driver\n" - " version %s - built %s %s\n", IFX_SSC_DRV_VERSION, __DATE__, __TIME__); -#endif -} /* show_version */ - - -/* - * Due to the fact that a port can be dynamically switched between slave - * and master mode using an IOCTL the hardware is not initialized here, - * but in ifx_ssc_hwinit() as a result of an IOCTL. - */ -int __init -ifx_ssc_init(void) -{ - struct ifx_ssc_port *info; - int i, nbytes; - unsigned long flags; - int ret_val; - - // ### TO DO: dynamic port count evaluation due to pin multiplexing - - ret_val = -ENOMEM; - nbytes = PORT_CNT * sizeof(struct ifx_ssc_port); - isp = (struct ifx_ssc_port *)kmalloc(nbytes, GFP_KERNEL); - if (isp == NULL) - { - printk("%s: no memory for isp\n", __FUNCTION__); - return (ret_val); - } - memset(isp, 0, nbytes); - - show_version(); - - /* register the device */ - ret_val = -ENXIO; -/* - i = maj; -*/ - if ((i = register_chrdev(maj, "ssc", &ifx_ssc_fops)) < 0) - { - printk("Unable to register major %d for the Infineon SSC\n", maj); - if (maj == 0){ - goto errout; - } - else{ - maj = 0; - if ((i = register_chrdev(maj, "ssc", &ifx_ssc_fops)) < 0) - { - printk("Unable to register major %d for the Infineon SSC\n", maj); - goto errout; - } - } - } - if (maj == 0) maj = i; - //printk("registered major %d for Infineon SSC\n", maj); - - /* set default values in ifx_ssc_port */ - for (i = 0; i < PORT_CNT; i++) { - info = &isp[i]; - info->port_nr = i; - /* default values for the HwOpts */ - info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT; - info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT; - info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT; - info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT; - info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT; - info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK; - info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE; - info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA; - info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY; - info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE; - info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL; - info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH; - info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX; - info->opts.gpoCs = IFX_SSC_DEF_GPO_CS; - info->opts.gpoInv = IFX_SSC_DEF_GPO_INV; - info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE; - info->baud = IFX_SSC_DEF_BAUDRATE; - info->rxbuf = NULL; - info->txbuf = NULL; - /* values specific to SSC1 */ - if (i == 0) { - info->mapbase = AMAZON_SSC_BASE_ADD_0; - // ### TO DO: power management - - // setting interrupt vectors - info->txirq = IFX_SSC_TIR; - info->rxirq = IFX_SSC_RIR; - info->errirq = IFX_SSC_EIR; -/* - info->frmirq = IFX_SSC_FIR; -*/ - } - /* activate SSC */ - /* CLC.DISS = 0 */ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC); - -// ### TO DO: multiple instances - - init_waitqueue_head(&info->rwait); - //init_waitqueue_head(&info->pwait); - - local_irq_save(flags); - - // init serial framing register - WRITE_PERIPHERAL_REGISTER(IFX_SSC_DEF_SFCON, info->mapbase + IFX_SSC_SFCON); - - /* try to get the interrupts */ - // ### TO DO: interrupt handling with multiple instances - ret_val = ifx_int_wrapper.request(info->txirq, ifx_ssc_tx_int, - 0, "ifx_ssc_tx", info); - if (ret_val){ - printk("%s: unable to get irq %d\n", __FUNCTION__, - info->txirq); - local_irq_restore(flags); - goto errout; - } - ret_val = ifx_int_wrapper.request(info->rxirq, ifx_ssc_rx_int, - 0, "ifx_ssc_rx", info); - if (ret_val){ - printk("%s: unable to get irq %d\n", __FUNCTION__, - info->rxirq); - local_irq_restore(flags); - goto irqerr; - } - ret_val = ifx_int_wrapper.request(info->errirq, ifx_ssc_err_int, - 0, "ifx_ssc_err", info); - if (ret_val){ - printk("%s: unable to get irq %d\n", __FUNCTION__, - info->errirq); - local_irq_restore(flags); - goto irqerr; - } -/* - ret_val = ifx_int_wrapper.request(info->frmirq, ifx_ssc_frm_int, - 0, "ifx_ssc_frm", info); - if (ret_val){ - printk("%s: unable to get irq %d\n", __FUNCTION__, - info->frmirq); - local_irq_restore(flags); - goto irqerr; - } - -*/ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_DEF_IRNEN, info->mapbase + IFX_SSC_IRN_EN); - - local_irq_restore(flags); - } // for (i = 0; i < PORT_CNT; i++) - - /* init the SSCs with default values */ - for (i = 0; i < PORT_CNT; i++) - { - info = &isp[i]; - if (ifx_ssc_hwinit(info) < 0) - { - printk("%s: hardware init failed for port %d\n", - __FUNCTION__, i); - goto irqerr; - } - } - - /* register /proc read handler */ - // ### TO DO: multiple instances - /* for SSC1, which is always present */ - create_proc_read_entry("driver/ssc1", 0, NULL, ifx_ssc1_read_proc, NULL); - return 0; - -irqerr: - // ### TO DO: multiple instances - ifx_int_wrapper.free(isp[0].txirq,&isp[0]); - ifx_int_wrapper.free(isp[0].rxirq,&isp[0]); - ifx_int_wrapper.free(isp[0].errirq,&isp[0]); -/* - ifx_int_wrapper.free(isp[0].frmirq, &isp[0]); -*/ -errout: - /* free up any allocated memory in the error case */ - kfree(isp); - return (ret_val); -} /* ifx_ssc_init */ - - -void -ifx_ssc_cleanup_module(void) -{ - int i; - - /* free up any allocated memory */ - for (i = 0; i < PORT_CNT; i++) - { - /* disable the SSC */ - WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE,isp[i].mapbase + IFX_SSC_WHBSTATE); - /* free the interrupts */ - ifx_int_wrapper.free(isp[i].txirq, &isp[i]); - ifx_int_wrapper.free(isp[i].rxirq, &isp[i]); - ifx_int_wrapper.free(isp[i].errirq, &isp[i]); -/* - ifx_int_wrapper.free(isp[i].frmirq, &isp[i]); - - if (isp[i].rxbuf != NULL) - kfree(isp[i].rxbuf); - if (isp[i].txbuf != NULL) - kfree(isp[i].txbuf); -*/ - } - kfree(isp); - /* unregister the device */ - if (unregister_chrdev(maj, "ssc")) - { - printk("Unable to unregister major %d for the SSC\n", maj); - } - /* delete /proc read handler */ - remove_proc_entry("driver/ssc1", NULL); - remove_proc_entry("driver/ssc2", NULL); -} /* ifx_ssc_cleanup_module */ - -module_exit(ifx_ssc_cleanup_module); - -/* Module entry-points */ -module_init(ifx_ssc_init); - -#ifndef MODULE -static int __init -ifx_ssc_set_maj(char *str) -{ - maj = simple_strtol(str, NULL, 0); - return 1; -} -__setup("ssc_maj=", ifx_ssc_set_maj); -#endif /* !MODULE */ - -#define AMAZON_SSC_EMSG(fmt,arg...) printk("%s: "fmt,__FUNCTION__, ##arg) -/* Brief: chip select enable - */ -inline int amazon_ssc_cs_low(u32 pin) -{ - int ret=0; - if ((ret=ifx_ssc_ioctl((struct inode *)0, NULL,IFX_SSC_GPO_OUT_CLR, (unsigned long)&pin))){ - AMAZON_SSC_EMSG("clear CS %d fails\n",pin); - } - wmb(); - return ret; -} -EXPORT_SYMBOL(amazon_ssc_cs_low); -/* Brief: chip select disable - */ -inline int amazon_ssc_cs_high(u32 pin) -{ - int ret=0; - if ((ret=ifx_ssc_ioctl((struct inode *)0, NULL,IFX_SSC_GPO_OUT_SET, (unsigned long)&pin))){ - AMAZON_SSC_EMSG("set CS %d fails\n", pin); - } - wmb(); - return ret; -} -EXPORT_SYMBOL(amazon_ssc_cs_high); -/* Brief: one SSC session - * Parameter: - * tx_buf - * tx_len - * rx_buf - * rx_len - * session_mode: IFX_SSC_MODE_RXTX or IFX_SSC_MODE_TX - * Return: >=0 number of bytes received (if rx_buf != 0) or transmitted - * <0 error code - * Description: - * 0. copy data to internal buffer - * 1. Write command - * 2a. If SSC_SESSION_MODE_TXONLY, read tx_len data - * 2b. If not Read back (tx_len + rx_len) data - * 3. copy internal buffer to rx buf if necessary - */ -static int ssc_session(char * tx_buf, u32 tx_len, char * rx_buf, u32 rx_len) -{ - int ret=0; - - char * ssc_tx_buf=NULL; - char * ssc_rx_buf=NULL; - -// volatile char ssc_tx_buf[128]={0}; -// volatile char ssc_rx_buf[128]={0}; - - int eff_size=0; - u8 mode=0; - - if (tx_buf == NULL && tx_len ==0 && rx_buf == NULL && rx_len == 0){ - AMAZON_SSC_EMSG("invalid parameters\n"); - ret=-EINVAL; - goto ssc_session_exit; - }else if (tx_buf == NULL || tx_len == 0){ - if (rx_buf != NULL && rx_len != 0){ - mode = IFX_SSC_MODE_RX; - }else{ - AMAZON_SSC_EMSG("invalid parameters\n"); - ret=-EINVAL; - goto ssc_session_exit; - } - }else if (rx_buf == NULL || rx_len ==0){ - if (tx_buf != NULL && tx_len != 0){ - mode = IFX_SSC_MODE_TX; - }else{ - AMAZON_SSC_EMSG("invalid parameters\n"); - ret=-EINVAL; - goto ssc_session_exit; - } - }else{ - mode = IFX_SSC_MODE_RXTX; - } - - if (mode == IFX_SSC_MODE_RXTX){ - eff_size = tx_len + rx_len; - }else if (mode == IFX_SSC_MODE_RX){ - eff_size = rx_len; - }else{ - eff_size = tx_len; - } - - //4 bytes alignment, required by driver - /* change by TaiCheng */ - //if (in_irq()){ - if (1){ - ssc_tx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_ATOMIC); - ssc_rx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_ATOMIC); - }else{ - ssc_tx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_KERNEL); - ssc_rx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_KERNEL); - } - if (ssc_tx_buf == NULL || ssc_rx_buf == NULL){ - AMAZON_SSC_EMSG("no memory for size of %d\n", eff_size); - ret = -ENOMEM; - goto ssc_session_exit; - } - memset((void*)ssc_tx_buf, 0, eff_size); - memset((void*)ssc_rx_buf, 0, eff_size); - - if (tx_len>0){ - memcpy(ssc_tx_buf, tx_buf, tx_len); - } - - ret=ifx_ssc_kwrite(0, ssc_tx_buf, eff_size); - - if (ret > 0) { - ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite - } - - if ( ret != eff_size ){ - AMAZON_SSC_EMSG("ifx_ssc_write return %d\n",ret); - goto ssc_session_exit; - } - ret=ifx_ssc_kread(0, ssc_rx_buf,eff_size); - if ( ret != eff_size ){ - AMAZON_SSC_EMSG("ifx_ssc_read return %d\n",ret); - goto ssc_session_exit; - } - - memcpy(rx_buf, ssc_rx_buf+tx_len, rx_len); - - if (mode == IFX_SSC_MODE_TX) { - ret = tx_len; - }else{ - ret = rx_len; - } -ssc_session_exit: - - if (ssc_tx_buf != NULL) kfree(ssc_tx_buf); - if (ssc_rx_buf != NULL) kfree(ssc_rx_buf); - - if (ret<0) { - printk("ssc session fails\n"); - } - return ret; -} -/* Brief: TX-RX session - * Parameter: - * tx_buf - * tx_len - * rx_buf - * rx_len - * Return: >=0 number of bytes received - * <0 error code - * Description: - * 1. TX session - * 2. RX session - */ -int amazon_ssc_txrx(char * tx_buf, u32 tx_len, char * rx_buf, u32 rx_len) -{ - return ssc_session(tx_buf,tx_len,rx_buf,rx_len); -} -EXPORT_SYMBOL(amazon_ssc_txrx); -/* Brief: TX only session - * Parameter: - * tx_buf - * tx_len - * Return: >=0 number of bytes transmitted - * <0 error code - */ -int amazon_ssc_tx(char * tx_buf, u32 tx_len) -{ - return ssc_session(tx_buf,tx_len,NULL,0); -} -EXPORT_SYMBOL(amazon_ssc_tx); -/* Brief: RX only session - * Parameter: - * rx_buf - * rx_len - * Return: >=0 number of bytes received - * <0 error code - */ -int amazon_ssc_rx(char * rx_buf, u32 rx_len) -{ - return ssc_session(NULL,0,rx_buf,rx_len); -} -EXPORT_SYMBOL(amazon_ssc_rx); - diff --git a/target/linux/amazon/files/drivers/mtd/maps/amazon.c b/target/linux/amazon/files/drivers/mtd/maps/amazon.c deleted file mode 100644 index 55bfe3237..000000000 --- a/target/linux/amazon/files/drivers/mtd/maps/amazon.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Handle mapping of the flash memory access routines - * on Amazon based devices. - * - * Copyright(C) 2004 peng.liu@infineon.com - * - * This code is GPLed - * - */ -// 000005:fchang 2005/6/2 Modified by Bingtao to double check if the EBU is enabled/disabled -// 506231:tc.chen 2005/06/23 increase firmware partition size form 192KB to 256KB -// 050701:linmars 2005/07/01 fix flash size wrong alignment after increase firmware partition -// 165001:henryhsu 2005/8/18 Remove the support for Intel flash because of 2.1 not enough rootfs partition size -// 165001:henryhsu 2005/9/7 Rolback to support INtel flash -// 509071:tc.chen 2005/09/07 Reduced flash writing time -// 511046:linmars 2005/11/04 change bootloader size from 128 into 64 -// 511241:linmars 2005/11/24 merge TaiChen's IRM patch - -// copyright 2005 infineon - -// copyright 2007 john crispin -// copyright 2007 felix fietkau -// copyright 2009 hauke mehrtens - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#define AMAZON_PCI_ARB_CTL_ALT 0xb100205c -#define AMAZON_MTD_REG32( addr ) (*(volatile u32 *)(addr)) - - -static struct map_info amazon_map = { - .name = "AMAZON_FLASH", - .bankwidth = 2, -}; - -static map_word amazon_read16(struct map_info * map, unsigned long ofs) -{ - map_word temp; - ofs ^= 2; - temp.x[0] = *((__u16 *) (map->virt + ofs)); - return temp; -} - -static void amazon_write16(struct map_info *map, map_word d, unsigned long adr) -{ - adr ^= 2; - *((__u16 *) (map->virt + adr)) = d.x[0]; -} - -void amazon_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) -{ - u8 *p; - u8 *to_8; - from = (unsigned long) (from + map->virt); - p = (u8 *) from; - to_8 = (u8 *) to; - while(len--){ - *to_8++ = *p++; - } -} - -void amazon_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) -{ - u8 *p = (u8*) from; - u8 *to_8; - to += (unsigned long) map->virt; - to_8 = (u8*)to; - while(len--){ - *p++ = *to_8++; - } -} - -#define UBOOT_SIZE 0x40000 - -static struct mtd_partition amazon_partitions[3] = { - { - name:"U-Boot", /* U-Boot firmware */ - offset:0x00000000, - size:UBOOT_SIZE , /* 128k */ - }, - { - name:"kernel", /* firmware */ - offset:UBOOT_SIZE, - size:0x00100000, /* 192K */ - }, - { - name:"rootfs", /* default partition */ - offset:0x00200000, - size:0x00200000, - }, -}; - -unsigned long uImage_size = 0x10000d; - -int find_uImage_size(unsigned long start_offset) -{ - unsigned long magic; - unsigned long temp; - amazon_copy_from(&amazon_map, &magic, start_offset, 4); - if (!(ntohl(magic) == 0x27051956)) { - printk(KERN_INFO "amazon_mtd: invalid magic (0x%08X) of kernel at 0x%08lx \n", ntohl(magic), start_offset); - return 0; - } - amazon_copy_from(&amazon_map, &temp, start_offset + 12, 4); - printk(KERN_INFO "amazon_mtd: kernel size is %ld \n", temp + 0x40); - return temp + 0x40; -} - -static int __init amazon_mtd_probe(struct platform_device *dev) -{ - unsigned long uimage_size; - struct mtd_info *mymtd = NULL; - struct mtd_partition *parts = NULL; - - *AMAZON_EBU_BUSCON0 = 0x1d7ff; - - amazon_map.read = amazon_read16; - amazon_map.write = amazon_write16; - amazon_map.copy_from = amazon_copy_from; - amazon_map.copy_to = amazon_copy_to; - - amazon_map.phys = dev->resource->start; - amazon_map.size = dev->resource->end - amazon_map.phys + 1; - amazon_map.virt = ioremap_nocache(amazon_map.phys, amazon_map.size); - - if (!amazon_map.virt) { - printk(KERN_WARNING "amazon_mtd: Failed to ioremap!\n"); - return -EIO; - } - - mymtd = (struct mtd_info *) do_map_probe("cfi_probe", &amazon_map); - if (!mymtd) { - iounmap(amazon_map.virt); - printk(KERN_WARNING "amazon_mtd: probing failed\n"); - return -ENXIO; - } - - mymtd->owner = THIS_MODULE; - parts = &amazon_partitions[0]; - - /* Some Samsung devices are containing a 16 MB flash chip with a bigger U-Boot partition. */ - if(mymtd->size == 0x01000000 && mymtd->erasesize == 0x00020000) { - printk(KERN_INFO "amazon_mtd: Found big flash chip!\n"); - amazon_partitions[0].size = 0x60000; - amazon_partitions[1].offset = 0x60000; - uimage_size = find_uImage_size(amazon_partitions[1].offset); - amazon_partitions[1].size = uimage_size; - amazon_partitions[2].offset = 0x60000 + uimage_size; - amazon_partitions[2].size = mymtd->size - amazon_partitions[2].offset - mymtd->erasesize; - } else { - printk(KERN_INFO "amazon_mtd: Found small flash chip!\n"); - uimage_size = find_uImage_size(amazon_partitions[1].offset); - amazon_partitions[1].size = uimage_size; - amazon_partitions[2].offset = UBOOT_SIZE + uimage_size; - amazon_partitions[2].size = mymtd->size - amazon_partitions[2].offset - (2 * mymtd->erasesize); - } - - add_mtd_partitions(mymtd, parts, 3); - - printk(KERN_INFO "amazon_mtd: added %s flash with %dMB\n", - amazon_map.name, ((int)mymtd->size) >> 20); - return 0; -} - -static struct platform_driver amazon_mtd_driver = { - .probe = amazon_mtd_probe, - .driver = { - .name = "amazon_mtd", - .owner = THIS_MODULE, - }, -}; - -static int __init amazon_mtd_init(void) -{ - int ret = platform_driver_register(&amazon_mtd_driver); - if (ret) - printk(KERN_WARNING "amazon_mtd: error registering platfom driver!\n"); - return ret; -} - -static void __exit amazon_mtd_cleanup(void) -{ - platform_driver_unregister(&amazon_mtd_driver); -} - -module_init(amazon_mtd_init); -module_exit(amazon_mtd_cleanup); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("john crispin blogic@openwrt.org"); -MODULE_DESCRIPTION("MTD map driver for AMAZON boards"); - diff --git a/target/linux/amazon/files/drivers/net/admmod.c b/target/linux/amazon/files/drivers/net/admmod.c deleted file mode 100644 index 70ba1496a..000000000 --- a/target/linux/amazon/files/drivers/net/admmod.c +++ /dev/null @@ -1,1484 +0,0 @@ -/****************************************************************************** - Copyright (c) 2004, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. - ****************************************************************************** - Module : admmod.c - Date : 2004-09-01 - Description : JoeLin - Remarks: - - Revision: - MarsLin, add to support VLAN - - *****************************************************************************/ -//000001.joelin 2005/06/02 add"ADM6996_MDC_MDIO_MODE" define, -// if define ADM6996_MDC_MDIO_MODE==> ADM6996LC and ADM6996I will be in MDIO/MDC(SMI)(16 bit) mode, -// amazon should contrl ADM6996 by MDC/MDIO pin -// if undef ADM6996_MDC_MDIO_MODE==> ADM6996 will be in EEProm(32 bit) mode, -// amazon should contrl ADM6996 by GPIO15,16,17,18 pin -/* 507281:linmars 2005/07/28 support MDIO/EEPROM config mode */ -/* 509201:linmars remove driver testing codes */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -//#include - - -unsigned int ifx_sw_conf[ADM_SW_MAX_PORT_NUM+1] = \ - {ADM_SW_PORT0_CONF, ADM_SW_PORT1_CONF, ADM_SW_PORT2_CONF, \ - ADM_SW_PORT3_CONF, ADM_SW_PORT4_CONF, ADM_SW_PORT5_CONF}; -unsigned int ifx_sw_bits[8] = \ - {0x1, 0x3, 0x7, 0xf, 0x1f, 0x3f, 0x7f, 0xff}; -unsigned int ifx_sw_vlan_port[6] = {0, 2, 4, 6, 7, 8}; -//050613:fchang -/* 507281:linmars start */ -#ifdef CONFIG_SWITCH_ADM6996_MDIO -#define ADM6996_MDC_MDIO_MODE 1 //000001.joelin -#else -#undef ADM6996_MDC_MDIO_MODE -#endif -/* 507281:linmars end */ -#define adm6996i 0 -#define adm6996lc 1 -#define adm6996l 2 -unsigned int adm6996_mode=adm6996i; -/* - initialize GPIO pins. - output mode, low -*/ -void ifx_gpio_init(void) -{ - //GPIO16,17,18 direction:output - //GPIO16,17,18 output 0 - - AMAZON_SW_REG(AMAZON_GPIO_P1_DIR) |= (GPIO_MDIO|GPIO_MDCS|GPIO_MDC); - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT) =AMAZON_SW_REG(AMAZON_GPIO_P1_IN)& ~(GPIO_MDIO|GPIO_MDCS|GPIO_MDC); - -} - -/* read one bit from mdio port */ -int ifx_sw_mdio_readbit(void) -{ - //int val; - - //val = (AMAZON_SW_REG(GPIO_conf0_REG) & GPIO0_INPUT_MASK) >> 8; - //return val; - //GPIO16 - return AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&1; -} - -/* - MDIO mode selection - 1 -> output - 0 -> input - - switch input/output mode of GPIO 0 -*/ -void ifx_mdio_mode(int mode) -{ -// AMAZON_SW_REG(GPIO_conf0_REG) = mode ? GPIO_ENABLEBITS : -// ((GPIO_ENABLEBITS | MDIO_INPUT) & ~MDIO_OUTPUT_EN); - mode?(AMAZON_SW_REG(AMAZON_GPIO_P1_DIR)|=GPIO_MDIO): - (AMAZON_SW_REG(AMAZON_GPIO_P1_DIR)&=~GPIO_MDIO); - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_DIR); - mode?(r|=GPIO_MDIO):(r&=~GPIO_MDIO); - AMAZON_SW_REG(AMAZON_GPIO_P1_DIR)=r;*/ -} - -void ifx_mdc_hi(void) -{ - //GPIO_SET_HI(GPIO_MDC); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)|=GPIO_MDC; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r|=GPIO_MDC; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)|GPIO_MDC; -} - -void ifx_mdio_hi(void) -{ - //GPIO_SET_HI(GPIO_MDIO); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)|=GPIO_MDIO; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r|=GPIO_MDIO; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)|GPIO_MDIO; -} - -void ifx_mdcs_hi(void) -{ - //GPIO_SET_HI(GPIO_MDCS); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)|=GPIO_MDCS; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r|=GPIO_MDCS; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)|GPIO_MDCS; -} - -void ifx_mdc_lo(void) -{ - //GPIO_SET_LOW(GPIO_MDC); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)&=~GPIO_MDC; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r&=~GPIO_MDC; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&(~GPIO_MDC); -} - -void ifx_mdio_lo(void) -{ - //GPIO_SET_LOW(GPIO_MDIO); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)&=~GPIO_MDIO; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r&=~GPIO_MDIO; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&(~GPIO_MDIO); -} - -void ifx_mdcs_lo(void) -{ - //GPIO_SET_LOW(GPIO_MDCS); - //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)&=~GPIO_MDCS; - /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT); - r&=~GPIO_MDCS; - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/ - - AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&(~GPIO_MDCS); -} - -/* - mdc pulse - 0 -> 1 -> 0 -*/ -static void ifx_sw_mdc_pulse(void) -{ - ifx_mdc_lo(); - udelay(ADM_SW_MDC_DOWN_DELAY); - ifx_mdc_hi(); - udelay(ADM_SW_MDC_UP_DELAY); - ifx_mdc_lo(); -} - -/* - mdc toggle - 1 -> 0 -*/ -static void ifx_sw_mdc_toggle(void) -{ - ifx_mdc_hi(); - udelay(ADM_SW_MDC_UP_DELAY); - ifx_mdc_lo(); - udelay(ADM_SW_MDC_DOWN_DELAY); -} - -/* - enable eeprom write - For ATC 93C66 type EEPROM; accessing ADM6996 internal EEPROM type registers -*/ -static void ifx_sw_eeprom_write_enable(void) -{ - unsigned int op; - - ifx_mdcs_lo(); - ifx_mdc_lo(); - ifx_mdio_hi(); - udelay(ADM_SW_CS_DELAY); - /* enable chip select */ - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - /* start bit */ - ifx_mdio_hi(); - ifx_sw_mdc_pulse(); - - /* eeprom write enable */ - op = ADM_SW_BIT_MASK_4; - while (op) - { - if (op & ADM_SW_EEPROM_WRITE_ENABLE) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 3); - while (op) - { - ifx_mdio_lo(); - ifx_sw_mdc_pulse(); - op >>= 1; - } - /* disable chip select */ - ifx_mdcs_lo(); - udelay(ADM_SW_CS_DELAY); - ifx_sw_mdc_pulse(); -} - -/* - disable eeprom write -*/ -static void ifx_sw_eeprom_write_disable(void) -{ - unsigned int op; - - ifx_mdcs_lo(); - ifx_mdc_lo(); - ifx_mdio_hi(); - udelay(ADM_SW_CS_DELAY); - /* enable chip select */ - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - - /* start bit */ - ifx_mdio_hi(); - ifx_sw_mdc_pulse(); - /* eeprom write disable */ - op = ADM_SW_BIT_MASK_4; - while (op) - { - if (op & ADM_SW_EEPROM_WRITE_DISABLE) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 3); - while (op) - { - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - /* disable chip select */ - ifx_mdcs_lo(); - udelay(ADM_SW_CS_DELAY); - ifx_sw_mdc_pulse(); -} - -/* - read registers from ADM6996 - serial registers start at 0x200 (addr bit 9 = 1b) - EEPROM registers -> 16bits; Serial registers -> 32bits -*/ -#ifdef ADM6996_MDC_MDIO_MODE //smi mode//000001.joelin -static int ifx_sw_read_adm6996i_smi(unsigned int addr, unsigned int *dat) -{ - addr=(addr<<16)&0x3ff0000; - AMAZON_SW_REG(AMAZON_SW_MDIO_ACC) =(0xC0000000|addr); - while ((AMAZON_SW_REG(AMAZON_SW_MDIO_ACC))&0x80000000){}; - *dat=((AMAZON_SW_REG(AMAZON_SW_MDIO_ACC))&0x0FFFF); - return 0; -} -#endif - -static int ifx_sw_read_adm6996i(unsigned int addr, unsigned int *dat) -{ - unsigned int op; - - ifx_gpio_init(); - - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - - ifx_mdcs_lo(); - ifx_mdc_lo(); - ifx_mdio_lo(); - - udelay(ADM_SW_CS_DELAY); - - /* preamble, 32 bit 1 */ - ifx_mdio_hi(); - op = ADM_SW_BIT_MASK_32; - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* command start (01b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_START) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* read command (10b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_READ) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* send address A9 ~ A0 */ - op = ADM_SW_BIT_MASK_10; - while (op) - { - if (op & addr) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* turnaround bits */ - op = ADM_SW_BIT_MASK_2; - ifx_mdio_hi(); - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - udelay(ADM_SW_MDC_DOWN_DELAY); - - /* set MDIO pin to input mode */ - ifx_mdio_mode(ADM_SW_MDIO_INPUT); - - /* start read data */ - *dat = 0; -//adm6996i op = ADM_SW_BIT_MASK_32; - op = ADM_SW_BIT_MASK_16;//adm6996i - while (op) - { - *dat <<= 1; - if (ifx_sw_mdio_readbit()) *dat |= 1; - ifx_sw_mdc_toggle(); - - op >>= 1; - } - - /* set MDIO to output mode */ - ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); - - /* dummy clock */ - op = ADM_SW_BIT_MASK_4; - ifx_mdio_lo(); - while(op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - ifx_mdc_lo(); - ifx_mdio_lo(); - ifx_mdcs_hi(); - - /* EEPROM registers */ -//adm6996i if (!(addr & 0x200)) -//adm6996i { -//adm6996i if (addr % 2) -//adm6996i *dat >>= 16; -//adm6996i else -//adm6996i *dat &= 0xffff; -//adm6996i } - - return 0; -} -//adm6996 -static int ifx_sw_read_adm6996l(unsigned int addr, unsigned int *dat) -{ - unsigned int op; - - ifx_gpio_init(); - - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - - ifx_mdcs_lo(); - ifx_mdc_lo(); - ifx_mdio_lo(); - - udelay(ADM_SW_CS_DELAY); - - /* preamble, 32 bit 1 */ - ifx_mdio_hi(); - op = ADM_SW_BIT_MASK_32; - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* command start (01b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_START) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* read command (10b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_READ) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* send address A9 ~ A0 */ - op = ADM_SW_BIT_MASK_10; - while (op) - { - if (op & addr) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* turnaround bits */ - op = ADM_SW_BIT_MASK_2; - ifx_mdio_hi(); - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - udelay(ADM_SW_MDC_DOWN_DELAY); - - /* set MDIO pin to input mode */ - ifx_mdio_mode(ADM_SW_MDIO_INPUT); - - /* start read data */ - *dat = 0; - op = ADM_SW_BIT_MASK_32; - while (op) - { - *dat <<= 1; - if (ifx_sw_mdio_readbit()) *dat |= 1; - ifx_sw_mdc_toggle(); - - op >>= 1; - } - - /* set MDIO to output mode */ - ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); - - /* dummy clock */ - op = ADM_SW_BIT_MASK_4; - ifx_mdio_lo(); - while(op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - ifx_mdc_lo(); - ifx_mdio_lo(); - ifx_mdcs_hi(); - - /* EEPROM registers */ - if (!(addr & 0x200)) - { - if (addr % 2) - *dat >>= 16; - else - *dat &= 0xffff; - } - - return 0; -} - -static int ifx_sw_read(unsigned int addr, unsigned int *dat) -{ -#ifdef ADM6996_MDC_MDIO_MODE //smi mode ////000001.joelin - ifx_sw_read_adm6996i_smi(addr,dat); -#else - if (adm6996_mode==adm6996i) ifx_sw_read_adm6996i(addr,dat); - else ifx_sw_read_adm6996l(addr,dat); -#endif - return 0; - -} - -/* - write register to ADM6996 eeprom registers -*/ -//for adm6996i -start -#ifdef ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin -static int ifx_sw_write_adm6996i_smi(unsigned int addr, unsigned int dat) -{ - - AMAZON_SW_REG(AMAZON_SW_MDIO_ACC) = ((addr<<16)&0x3ff0000)|dat|0x80000000; - while ((AMAZON_SW_REG(AMAZON_SW_MDIO_ACC))&0x80000000){}; - - return 0; - -} -#endif //ADM6996_MDC_MDIO_MODE //000001.joelin - -static int ifx_sw_write_adm6996i(unsigned int addr, unsigned int dat) -{ - unsigned int op; - - ifx_gpio_init(); - - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - - ifx_mdcs_lo(); - ifx_mdc_lo(); - ifx_mdio_lo(); - - udelay(ADM_SW_CS_DELAY); - - /* preamble, 32 bit 1 */ - ifx_mdio_hi(); - op = ADM_SW_BIT_MASK_32; - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* command start (01b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_START) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* write command (01b) */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_SMI_WRITE) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* send address A9 ~ A0 */ - op = ADM_SW_BIT_MASK_10; - while (op) - { - if (op & addr) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* turnaround bits */ - op = ADM_SW_BIT_MASK_2; - ifx_mdio_hi(); - while (op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - udelay(ADM_SW_MDC_DOWN_DELAY); - - /* set MDIO pin to output mode */ - ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); - - - /* start write data */ - op = ADM_SW_BIT_MASK_16; - while (op) - { - if (op & dat) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_toggle(); - op >>= 1; - } - - // /* set MDIO to output mode */ - // ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); - - /* dummy clock */ - op = ADM_SW_BIT_MASK_4; - ifx_mdio_lo(); - while(op) - { - ifx_sw_mdc_pulse(); - op >>= 1; - } - - ifx_mdc_lo(); - ifx_mdio_lo(); - ifx_mdcs_hi(); - - /* EEPROM registers */ -//adm6996i if (!(addr & 0x200)) -//adm6996i { -//adm6996i if (addr % 2) -//adm6996i *dat >>= 16; -//adm6996i else -//adm6996i *dat &= 0xffff; -//adm6996i } - - return 0; -} -//for adm6996i-end -static int ifx_sw_write_adm6996l(unsigned int addr, unsigned int dat) -{ - unsigned int op; - - ifx_gpio_init(); - - /* enable write */ - ifx_sw_eeprom_write_enable(); - - /* chip select */ - ifx_mdcs_hi(); - udelay(ADM_SW_CS_DELAY); - - /* issue write command */ - /* start bit */ - ifx_mdio_hi(); - ifx_sw_mdc_pulse(); - - /* EEPROM write command */ - op = ADM_SW_BIT_MASK_2; - while (op) - { - if (op & ADM_SW_EEPROM_WRITE) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_pulse(); - op >>= 1; - } - - /* send address A7 ~ A0 */ - op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 1); - - while (op) - { - if (op & addr) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_toggle(); - op >>= 1; - } - - /* start write data */ - op = ADM_SW_BIT_MASK_16; - while (op) - { - if (op & dat) - ifx_mdio_hi(); - else - ifx_mdio_lo(); - - ifx_sw_mdc_toggle(); - op >>= 1; - } - - /* disable cs & wait 1 clock */ - ifx_mdcs_lo(); - udelay(ADM_SW_CS_DELAY); - ifx_sw_mdc_toggle(); - - ifx_sw_eeprom_write_disable(); - - return 0; -} - -static int ifx_sw_write(unsigned int addr, unsigned int dat) -{ -#ifdef ADM6996_MDC_MDIO_MODE //smi mode ////000001.joelin - ifx_sw_write_adm6996i_smi(addr,dat); -#else //000001.joelin - if (adm6996_mode==adm6996i) ifx_sw_write_adm6996i(addr,dat); - else ifx_sw_write_adm6996l(addr,dat); -#endif //000001.joelin - return 0; -} - -/* - do switch PHY reset -*/ -int ifx_sw_reset(void) -{ - /* reset PHY */ - ifx_sw_write(ADM_SW_PHY_RESET, 0); - - return 0; -} - -/* 509201:linmars start */ -#if 0 -/* - check port status -*/ -int ifx_check_port_status(int port) -{ - unsigned int val; - - if ((port < 0) || (port > ADM_SW_MAX_PORT_NUM)) - { - ifx_printf(("error on port number (%d)!!\n", port)); - return -1; - } - - ifx_sw_read(ifx_sw_conf[port], &val); - if (ifx_sw_conf[port]%2) val >>= 16; - /* only 16bits are effective */ - val &= 0xFFFF; - - ifx_printf(("Port %d status (%.8x): \n", port, val)); - - if (val & ADM_SW_PORT_FLOWCTL) - ifx_printf(("\t802.3x flow control supported!\n")); - else - ifx_printf(("\t802.3x flow control not supported!\n")); - - if (val & ADM_SW_PORT_AN) - ifx_printf(("\tAuto negotiation ON!\n")); - else - ifx_printf(("\tAuto negotiation OFF!\n")); - - if (val & ADM_SW_PORT_100M) - ifx_printf(("\tLink at 100M!\n")); - else - ifx_printf(("\tLink at 10M!\n")); - - if (val & ADM_SW_PORT_FULL) - ifx_printf(("\tFull duplex!\n")); - else - ifx_printf(("\tHalf duplex!\n")); - - if (val & ADM_SW_PORT_DISABLE) - ifx_printf(("\tPort disabled!\n")); - else - ifx_printf(("\tPort enabled!\n")); - - if (val & ADM_SW_PORT_TOS) - ifx_printf(("\tTOS enabled!\n")); - else - ifx_printf(("\tTOS disabled!\n")); - - if (val & ADM_SW_PORT_PPRI) - ifx_printf(("\tPort priority first!\n")); - else - ifx_printf(("\tVLAN or TOS priority first!\n")); - - if (val & ADM_SW_PORT_MDIX) - ifx_printf(("\tAuto MDIX!\n")); - else - ifx_printf(("\tNo auto MDIX\n")); - - ifx_printf(("\tPVID: %d\n", \ - ((val >> ADM_SW_PORT_PVID_SHIFT)&ifx_sw_bits[ADM_SW_PORT_PVID_BITS]))); - - return 0; -} -/* - initialize a VLAN - clear all VLAN bits -*/ -int ifx_sw_vlan_init(int vlanid) -{ - ifx_sw_write(ADM_SW_VLAN0_CONF + vlanid, 0); - - return 0; -} - -/* - add a port to certain vlan -*/ -int ifx_sw_vlan_add(int port, int vlanid) -{ - int reg = 0; - - if ((port < 0) || (port > ADM_SW_MAX_PORT_NUM) || (vlanid < 0) || - (vlanid > ADM_SW_MAX_VLAN_NUM)) - { - ifx_printf(("Port number or VLAN number ERROR!!\n")); - return -1; - } - ifx_sw_read(ADM_SW_VLAN0_CONF + vlanid, ®); - reg |= (1 << ifx_sw_vlan_port[port]); - ifx_sw_write(ADM_SW_VLAN0_CONF + vlanid, reg); - - return 0; -} - -/* - delete a given port from certain vlan -*/ -int ifx_sw_vlan_del(int port, int vlanid) -{ - unsigned int reg = 0; - - if ((port < 0) || (port > ADM_SW_MAX_PORT_NUM) || (vlanid < 0) || (vlanid > ADM_SW_MAX_VLAN_NUM)) - { - ifx_printf(("Port number or VLAN number ERROR!!\n")); - return -1; - } - ifx_sw_read(ADM_SW_VLAN0_CONF + vlanid, ®); - reg &= ~(1 << ifx_sw_vlan_port[port]); - ifx_sw_write(ADM_SW_VLAN0_CONF + vlanid, reg); - - return 0; -} - -/* - default VLAN setting - - port 0~3 as untag port and PVID = 1 - VLAN1: port 0~3 and port 5 (MII) -*/ -static int ifx_sw_init(void) -{ - ifx_printf(("Setting default ADM6996 registers... \n")); - - /* MAC clone, 802.1q based VLAN */ - ifx_sw_write(ADM_SW_VLAN_MODE, 0xff30); - /* auto MDIX, PVID=1, untag */ - ifx_sw_write(ADM_SW_PORT0_CONF, 0x840f); - ifx_sw_write(ADM_SW_PORT1_CONF, 0x840f); - ifx_sw_write(ADM_SW_PORT2_CONF, 0x840f); - ifx_sw_write(ADM_SW_PORT3_CONF, 0x840f); - /* auto MDIX, PVID=2, untag */ - ifx_sw_write(ADM_SW_PORT5_CONF, 0x880f); - /* port 0~3 & 5 as VLAN1 */ - ifx_sw_write(ADM_SW_VLAN0_CONF+1, 0x0155); - - return 0; -} -#endif -/* 509201:linmars end */ - -int adm_open(struct inode *node, struct file *filp) -{ - return 0; -} - -ssize_t adm_read(struct file *filep, char *buf, size_t count, loff_t *ppos) -{ - return count; -} - -ssize_t adm_write(struct file *filep, const char *buf, size_t count, loff_t *ppos) -{ - return count; -} - -/* close */ -int adm_release(struct inode *inode, struct file *filp) -{ - return 0; -} - -/* IOCTL function */ -int adm_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long args) -{ - PREGRW uREGRW; - unsigned int rtval; - unsigned int val; //6996i - unsigned int control[6] ; //6996i - unsigned int status[6] ; //6996i - - PMACENTRY mMACENTRY;//adm6996i - PPROTOCOLFILTER uPROTOCOLFILTER ;///adm6996i - - if (_IOC_TYPE(cmd) != ADM_MAGIC) - { - printk("adm_ioctl: IOC_TYPE(%x) != ADM_MAGIC(%x)! \n", _IOC_TYPE(cmd), ADM_MAGIC); - return (-EINVAL); - } - - if(_IOC_NR(cmd) >= KEY_IOCTL_MAX_KEY) - { - printk(KERN_WARNING "adm_ioctl: IOC_NR(%x) invalid! \n", _IOC_NR(cmd)); - return (-EINVAL); - } - - switch (cmd) - { - case ADM_IOCTL_REGRW: - { - uREGRW = (PREGRW)kmalloc(sizeof(REGRW), GFP_KERNEL); - rtval = copy_from_user(uREGRW, (PREGRW)args, sizeof(REGRW)); - if (rtval != 0) - { - printk("ADM_IOCTL_REGRW: copy from user FAILED!! \n"); - return (-EFAULT); - } - - switch(uREGRW->mode) - { - case REG_READ: - uREGRW->value = 0x12345678;//inl(uREGRW->addr); - copy_to_user((PREGRW)args, uREGRW, sizeof(REGRW)); - break; - case REG_WRITE: - //outl(uREGRW->value, uREGRW->addr); - break; - - default: - printk("No such Register Read/Write function!! \n"); - return (-EFAULT); - } - kfree(uREGRW); - break; - } - - case ADM_SW_IOCTL_REGRW: - { - unsigned int val = 0xff; - - uREGRW = (PREGRW)kmalloc(sizeof(REGRW), GFP_KERNEL); - rtval = copy_from_user(uREGRW, (PREGRW)args, sizeof(REGRW)); - if (rtval != 0) - { - printk("ADM_IOCTL_REGRW: copy from user FAILED!! \n"); - return (-EFAULT); - } - - switch(uREGRW->mode) - { - case REG_READ: - ifx_sw_read(uREGRW->addr, &val); - uREGRW->value = val; - copy_to_user((PREGRW)args, uREGRW, sizeof(REGRW)); - break; - - case REG_WRITE: - ifx_sw_write(uREGRW->addr, uREGRW->value); - break; - default: - printk("No such Register Read/Write function!! \n"); - return (-EFAULT); - } - kfree(uREGRW); - break; - } -/* 509201:linmars start */ -#if 0 - case ADM_SW_IOCTL_PORTSTS: - for (rtval = 0; rtval < ADM_SW_MAX_PORT_NUM+1; rtval++) - ifx_check_port_status(rtval); - break; - case ADM_SW_IOCTL_INIT: - ifx_sw_init(); - break; -#endif -/* 509201:linmars end */ -//adm6996i - case ADM_SW_IOCTL_MACENTRY_ADD: - case ADM_SW_IOCTL_MACENTRY_DEL: - case ADM_SW_IOCTL_MACENTRY_GET_INIT: - case ADM_SW_IOCTL_MACENTRY_GET_MORE: - - - mMACENTRY = (PMACENTRY)kmalloc(sizeof(MACENTRY), GFP_KERNEL); - rtval = copy_from_user(mMACENTRY, (PMACENTRY)args, sizeof(MACENTRY)); - if (rtval != 0) - { - printk("ADM_SW_IOCTL_MACENTRY: copy from user FAILED!! \n"); - return (-EFAULT); - } - control[0]=(mMACENTRY->mac_addr[1]<<8)+mMACENTRY->mac_addr[0] ; - control[1]=(mMACENTRY->mac_addr[3]<<8)+mMACENTRY->mac_addr[2] ; - control[2]=(mMACENTRY->mac_addr[5]<<8)+mMACENTRY->mac_addr[4] ; - control[3]=(mMACENTRY->fid&0xf)+((mMACENTRY->portmap&0x3f)<<4); - if (((mMACENTRY->info_type)&0x01)) control[4]=(mMACENTRY->ctrl.info_ctrl)+0x1000; //static ,info control - else control[4]=((mMACENTRY->ctrl.age_timer)&0xff);//not static ,agetimer - if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT) { - //initial the pointer to the first address - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - control[5]=0x030;//initial the first address - ifx_sw_write(0x11f,control[5]); - - - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - - } //if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT) - if (cmd==ADM_SW_IOCTL_MACENTRY_ADD) control[5]=0x07;//create a new address - else if (cmd==ADM_SW_IOCTL_MACENTRY_DEL) control[5]=0x01f;//erased an existed address - else if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) - control[5]=0x02c;//search by the mac address field - - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - ifx_sw_write(0x11a,control[0]); - ifx_sw_write(0x11b,control[1]); - ifx_sw_write(0x11c,control[2]); - ifx_sw_write(0x11d,control[3]); - ifx_sw_write(0x11e,control[4]); - ifx_sw_write(0x11f,control[5]); - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - val=((val&0x7000)>>12);//result ,status5[14:12] - mMACENTRY->result=val; - - if (!val) { - printk(" Command OK!! \n"); - if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) { - ifx_sw_read(0x120,&(status[0])); - ifx_sw_read(0x121,&(status[1])); - ifx_sw_read(0x122,&(status[2])); - ifx_sw_read(0x123,&(status[3])); - ifx_sw_read(0x124,&(status[4])); - ifx_sw_read(0x125,&(status[5])); - - - mMACENTRY->mac_addr[0]=(status[0]&0x00ff) ; - mMACENTRY->mac_addr[1]=(status[0]&0xff00)>>8 ; - mMACENTRY->mac_addr[2]=(status[1]&0x00ff) ; - mMACENTRY->mac_addr[3]=(status[1]&0xff00)>>8 ; - mMACENTRY->mac_addr[4]=(status[2]&0x00ff) ; - mMACENTRY->mac_addr[5]=(status[2]&0xff00)>>8 ; - mMACENTRY->fid=(status[3]&0xf); - mMACENTRY->portmap=((status[3]>>4)&0x3f); - if (status[5]&0x2) {//static info_ctrl //status5[1]???? - mMACENTRY->ctrl.info_ctrl=(status[4]&0x00ff); - mMACENTRY->info_type=1; - } - else {//not static age_timer - mMACENTRY->ctrl.age_timer=(status[4]&0x00ff); - mMACENTRY->info_type=0; - } -//status5[13]???? mMACENTRY->occupy=(status[5]&0x02)>>1;//status5[1] - mMACENTRY->occupy=(status[5]&0x02000)>>13;//status5[13] ??? - mMACENTRY->bad=(status[5]&0x04)>>2;//status5[2] - }//if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) - - } - else if (val==0x001) - printk(" All Entry Used!! \n"); - else if (val==0x002) - printk(" Entry Not Found!! \n"); - else if (val==0x003) - printk(" Try Next Entry!! \n"); - else if (val==0x005) - printk(" Command Error!! \n"); - else - printk(" UnKnown Error!! \n"); - - copy_to_user((PMACENTRY)args, mMACENTRY,sizeof(MACENTRY)); - - break; - - case ADM_SW_IOCTL_FILTER_ADD: - case ADM_SW_IOCTL_FILTER_DEL: - case ADM_SW_IOCTL_FILTER_GET: - - uPROTOCOLFILTER = (PPROTOCOLFILTER)kmalloc(sizeof(PROTOCOLFILTER), GFP_KERNEL); - rtval = copy_from_user(uPROTOCOLFILTER, (PPROTOCOLFILTER)args, sizeof(PROTOCOLFILTER)); - if (rtval != 0) - { - printk("ADM_SW_IOCTL_FILTER_ADD: copy from user FAILED!! \n"); - return (-EFAULT); - } - - if(cmd==ADM_SW_IOCTL_FILTER_DEL) { //delete filter - uPROTOCOLFILTER->ip_p=00; //delet filter - uPROTOCOLFILTER->action=00; //delete filter - } //delete filter - - ifx_sw_read(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), &val);//rx68~rx6b,protocol filter0~7 - - if (((uPROTOCOLFILTER->protocol_filter_num)%2)==00){ - if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= val&0x00ff;//get filter ip_p - else val=(val&0xff00)|(uPROTOCOLFILTER->ip_p);//set filter ip_p - } - else { - if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= (val>>8);//get filter ip_p - else val=(val&0x00ff)|((uPROTOCOLFILTER->ip_p)<<8);//set filter ip_p - } - if(cmd!=ADM_SW_IOCTL_FILTER_GET) ifx_sw_write(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), val);//write rx68~rx6b,protocol filter0~7 - - ifx_sw_read(0x95, &val); //protocol filter action - if(cmd==ADM_SW_IOCTL_FILTER_GET) { - uPROTOCOLFILTER->action= ((val>>(uPROTOCOLFILTER->protocol_filter_num*2))&0x3);//get filter action - copy_to_user((PPROTOCOLFILTER)args, uPROTOCOLFILTER, sizeof(PROTOCOLFILTER)); - - } - else { - val=(val&(~(0x03<<(uPROTOCOLFILTER->protocol_filter_num*2))))|(((uPROTOCOLFILTER->action)&0x03)<<(uPROTOCOLFILTER->protocol_filter_num*2)); - // printk("%d----\n",val); - ifx_sw_write(0x95, val); //write protocol filter action - } - - break; -//adm6996i - - /* others */ - default: - return -EFAULT; - } - /* end of switch */ - return 0; -} - -/* Santosh: handle IGMP protocol filter ADD/DEL/GET */ -int adm_process_protocol_filter_request (unsigned int cmd, PPROTOCOLFILTER uPROTOCOLFILTER) -{ - unsigned int val; //6996i - - if(cmd==ADM_SW_IOCTL_FILTER_DEL) { //delete filter - uPROTOCOLFILTER->ip_p=00; //delet filter - uPROTOCOLFILTER->action=00; //delete filter - } //delete filter - - ifx_sw_read(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), &val);//rx68~rx6b,protocol filter0~7 - - if (((uPROTOCOLFILTER->protocol_filter_num)%2)==00){ - if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= val&0x00ff;//get filter ip_p - else val=(val&0xff00)|(uPROTOCOLFILTER->ip_p);//set filter ip_p - } - else { - if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= (val>>8);//get filter ip_p - else val=(val&0x00ff)|((uPROTOCOLFILTER->ip_p)<<8);//set filter ip_p - } - if(cmd!=ADM_SW_IOCTL_FILTER_GET) ifx_sw_write(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), val);//write rx68~rx6b,protocol filter0~7 - - ifx_sw_read(0x95, &val); //protocol filter action - if(cmd==ADM_SW_IOCTL_FILTER_GET) { - uPROTOCOLFILTER->action= ((val>>(uPROTOCOLFILTER->protocol_filter_num*2))&0x3);//get filter action - } - else { - val=(val&(~(0x03<<(uPROTOCOLFILTER->protocol_filter_num*2))))|(((uPROTOCOLFILTER->action)&0x03)<<(uPROTOCOLFILTER->protocol_filter_num*2)); - ifx_sw_write(0x95, val); //write protocol filter action - } - - return 0; -} - - -/* Santosh: function for MAC ENTRY ADD/DEL/GET */ - -int adm_process_mac_table_request (unsigned int cmd, PMACENTRY mMACENTRY) -{ - unsigned int rtval; - unsigned int val; //6996i - unsigned int control[6] ; //6996i - unsigned int status[6] ; //6996i - - // printk ("adm_process_mac_table_request: enter\n"); - - control[0]=(mMACENTRY->mac_addr[1]<<8)+mMACENTRY->mac_addr[0] ; - control[1]=(mMACENTRY->mac_addr[3]<<8)+mMACENTRY->mac_addr[2] ; - control[2]=(mMACENTRY->mac_addr[5]<<8)+mMACENTRY->mac_addr[4] ; - control[3]=(mMACENTRY->fid&0xf)+((mMACENTRY->portmap&0x3f)<<4); - - if (((mMACENTRY->info_type)&0x01)) control[4]=(mMACENTRY->ctrl.info_ctrl)+0x1000; //static ,info control - else control[4]=((mMACENTRY->ctrl.age_timer)&0xff);//not static ,agetimer - if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT) { - //initial the pointer to the first address - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - control[5]=0x030;//initial the first address - ifx_sw_write(0x11f,control[5]); - - - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - - } //if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT) - if (cmd==ADM_SW_IOCTL_MACENTRY_ADD) control[5]=0x07;//create a new address - else if (cmd==ADM_SW_IOCTL_MACENTRY_DEL) control[5]=0x01f;//erased an existed address - else if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) - control[5]=0x02c;//search by the mac address field - - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - ifx_sw_write(0x11a,control[0]); - ifx_sw_write(0x11b,control[1]); - ifx_sw_write(0x11c,control[2]); - ifx_sw_write(0x11d,control[3]); - ifx_sw_write(0x11e,control[4]); - ifx_sw_write(0x11f,control[5]); - val=0x8000;//busy ,status5[15] - while(val&0x8000){ //check busy ? - ifx_sw_read(0x125, &val); - } - val=((val&0x7000)>>12);//result ,status5[14:12] - mMACENTRY->result=val; - - if (!val) { - printk(" Command OK!! \n"); - if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) { - ifx_sw_read(0x120,&(status[0])); - ifx_sw_read(0x121,&(status[1])); - ifx_sw_read(0x122,&(status[2])); - ifx_sw_read(0x123,&(status[3])); - ifx_sw_read(0x124,&(status[4])); - ifx_sw_read(0x125,&(status[5])); - - - mMACENTRY->mac_addr[0]=(status[0]&0x00ff) ; - mMACENTRY->mac_addr[1]=(status[0]&0xff00)>>8 ; - mMACENTRY->mac_addr[2]=(status[1]&0x00ff) ; - mMACENTRY->mac_addr[3]=(status[1]&0xff00)>>8 ; - mMACENTRY->mac_addr[4]=(status[2]&0x00ff) ; - mMACENTRY->mac_addr[5]=(status[2]&0xff00)>>8 ; - mMACENTRY->fid=(status[3]&0xf); - mMACENTRY->portmap=((status[3]>>4)&0x3f); - if (status[5]&0x2) {//static info_ctrl //status5[1]???? - mMACENTRY->ctrl.info_ctrl=(status[4]&0x00ff); - mMACENTRY->info_type=1; - } - else {//not static age_timer - mMACENTRY->ctrl.age_timer=(status[4]&0x00ff); - mMACENTRY->info_type=0; - } -//status5[13]???? mMACENTRY->occupy=(status[5]&0x02)>>1;//status5[1] - mMACENTRY->occupy=(status[5]&0x02000)>>13;//status5[13] ??? - mMACENTRY->bad=(status[5]&0x04)>>2;//status5[2] - }//if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) - - } - else if (val==0x001) - printk(" All Entry Used!! \n"); - else if (val==0x002) - printk(" Entry Not Found!! \n"); - else if (val==0x003) - printk(" Try Next Entry!! \n"); - else if (val==0x005) - printk(" Command Error!! \n"); - else - printk(" UnKnown Error!! \n"); - - // printk ("adm_process_mac_table_request: Exit\n"); - return 0; -} - -/* Santosh: End of function for MAC ENTRY ADD/DEL*/ -struct file_operations adm_ops = -{ - read: adm_read, - write: adm_write, - open: adm_open, - release: adm_release, - ioctl: adm_ioctl -}; - -int adm_proc(char *buf, char **start, off_t offset, int count, int *eof, void *data) -{ - int len = 0; - - len += sprintf(buf+len, " ************ Registers ************ \n"); - *eof = 1; - return len; -} - -int __init init_adm6996_module(void) -{ - unsigned int val = 000; - unsigned int val1 = 000; - - printk("Loading ADM6996 driver... \n"); - - /* if running on adm5120 */ - /* set GPIO 0~2 as adm6996 control pins */ - //outl(0x003f3f00, 0x12000028); - /* enable switch port 5 (MII) as RMII mode (5120MAC <-> 6996MAC) */ - //outl(0x18a, 0x12000030); - /* group adm5120 port 1 ~ 5 as VLAN0, port 5 & 6(CPU) as VLAN1 */ - //outl(0x417e, 0x12000040); - /* end adm5120 fixup */ -#ifdef ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin - register_chrdev(69, "adm6996", &adm_ops); - AMAZON_SW_REG(AMAZON_SW_MDIO_CFG) = 0x27be; - AMAZON_SW_REG(AMAZON_SW_EPHY) = 0xfc; - adm6996_mode=adm6996i; - ifx_sw_read(0xa0, &val); - ifx_sw_read(0xa1, &val1); - val=((val1&0x0f)<<16)|val; - printk ("\nADM6996 SMI Mode-"); - printk ("Chip ID:%5x \n ", val); -#else //000001.joelin - - AMAZON_SW_REG(AMAZON_SW_MDIO_CFG) = 0x2c50; - AMAZON_SW_REG(AMAZON_SW_EPHY) = 0xff; - - AMAZON_SW_REG(AMAZON_GPIO_P1_ALTSEL0) &= ~(GPIO_MDIO|GPIO_MDCS|GPIO_MDC); - AMAZON_SW_REG(AMAZON_GPIO_P1_ALTSEL1) &= ~(GPIO_MDIO|GPIO_MDCS|GPIO_MDC); - AMAZON_SW_REG(AMAZON_GPIO_P1_OD) |= (GPIO_MDIO|GPIO_MDCS|GPIO_MDC); - - ifx_gpio_init(); - register_chrdev(69, "adm6996", &adm_ops); - mdelay(100); - - /* create proc entries */ - // create_proc_read_entry("admide", 0, NULL, admide_proc, NULL); - -//joelin adm6996i support start - adm6996_mode=adm6996i; - ifx_sw_read(0xa0, &val); - adm6996_mode=adm6996l; - ifx_sw_read(0x200, &val1); -// printk ("\n %0x \n",val1); - if ((val&0xfff0)==0x1020) { - printk ("\n ADM6996I .. \n"); - adm6996_mode=adm6996i; - } - else if ((val1&0xffffff00)==0x71000) {//71010 or 71020 - printk ("\n ADM6996LC .. \n"); - adm6996_mode=adm6996lc; - } - else { - printk ("\n ADM6996L .. \n"); - adm6996_mode=adm6996l; - } -#endif //ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin - - if ((adm6996_mode==adm6996lc)||(adm6996_mode==adm6996i)){ -#if 0 /* removed by MarsLin */ - ifx_sw_write(0x29,0xc000); - ifx_sw_write(0x30,0x0985); -#else - ifx_sw_read(0xa0, &val); - if (val == 0x1021) // for both 6996LC and 6996I, only AB version need the patch - ifx_sw_write(0x29, 0x9000); - ifx_sw_write(0x30,0x0985); -#endif - } -//joelin adm6996i support end - return 0; -} - -void __exit cleanup_adm6996_module(void) -{ - printk("Free ADM device driver... \n"); - - unregister_chrdev(69, "adm6996"); - - /* remove proc entries */ - // remove_proc_entry("admide", NULL); -} - -/* MarsLin, add start */ -#if defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT) || defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT_MODULE) - #define SET_BIT(reg, mask) reg |= (mask) - #define CLEAR_BIT(reg, mask) reg &= (~mask) - static int ifx_hw_reset(void) - { - CLEAR_BIT((*AMAZON_GPIO_P0_ALTSEL0),0x2000); - CLEAR_BIT((*AMAZON_GPIO_P0_ALTSEL1),0x2000); - SET_BIT((*AMAZON_GPIO_P0_OD),0x2000); - SET_BIT((*AMAZON_GPIO_P0_DIR), 0x2000); - CLEAR_BIT((*AMAZON_GPIO_P0_OUT), 0x2000); - mdelay(500); - SET_BIT((*AMAZON_GPIO_P0_OUT), 0x2000); - cleanup_adm6996_module(); - return init_adm6996_module(); - } - int (*adm6996_hw_reset)(void) = ifx_hw_reset; - EXPORT_SYMBOL(adm6996_hw_reset); - EXPORT_SYMBOL(adm6996_mode); - int (*adm6996_sw_read)(unsigned int addr, unsigned int *data) = ifx_sw_read; - EXPORT_SYMBOL(adm6996_sw_read); - int (*adm6996_sw_write)(unsigned int addr, unsigned int data) = ifx_sw_write; - EXPORT_SYMBOL(adm6996_sw_write); -#endif -/* MarsLin, add end */ - -/* Santosh: for IGMP proxy/snooping, Begin */ -EXPORT_SYMBOL (adm_process_mac_table_request); -EXPORT_SYMBOL (adm_process_protocol_filter_request); -/* Santosh: for IGMP proxy/snooping, End */ - -MODULE_DESCRIPTION("ADMtek 6996 Driver"); -MODULE_AUTHOR("Joe Lin "); -MODULE_LICENSE("GPL"); - -module_init(init_adm6996_module); -module_exit(cleanup_adm6996_module); - diff --git a/target/linux/amazon/files/drivers/net/amazon_sw.c b/target/linux/amazon/files/drivers/net/amazon_sw.c deleted file mode 100644 index 54a70622e..000000000 --- a/target/linux/amazon/files/drivers/net/amazon_sw.c +++ /dev/null @@ -1,899 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - */ -//----------------------------------------------------------------------- -/* - * Description: - * Driver for Infineon Amazon 3 port switch - */ -//----------------------------------------------------------------------- -/* Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com] - * Created: 7-April-2004 - */ -//----------------------------------------------------------------------- -/* History - * Changed on: Jun 28, 2004 - * Changed by: peng.liu@infineon.com - * Reason: add hardware flow control (HFC) (CONFIG_NET_HW_FLOWCONTROL) - * - * Changed on: Apr 6, 2005 - * Changed by: mars.lin@infineon.com - * Reason : supoort port identification - */ - - -// copyright 2004-2005 infineon.com - -// copyright 2007 john crispin -// copyright 2007 felix fietkau -// copyright 2009 hauke mehrtens - - -// TODO -// port vlan code from bcrm target... the tawainese code was scrapped due to crappyness -// check all the mmi reg settings and possibly document them better -// verify the ethtool code -// remove the while(1) stuff -// further clean up and rework ... but it works for now -// check the mode[]=bridge stuff -// verify that the ethaddr can be set from u-boot - - -#ifndef __KERNEL__ -#define __KERNEL__ -#endif - - -#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -#define MODVERSIONS -#endif - -#if defined(MODVERSIONS) && !defined(__GENKSYMS__) -#include -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -// how many mii ports are there ? -#define AMAZON_SW_INT_NO 2 - -#define ETHERNET_PACKET_DMA_BUFFER_SIZE 1536 - -/***************************************** Module Parameters *************************************/ -char mode[] = "bridge"; -module_param_array(mode, charp, NULL, 0); - -static int timeout = 1 * HZ; -module_param(timeout, int, 0); - -int switch_init(struct net_device *dev); -void switch_tx_timeout(struct net_device *dev); - -static struct net_device *switch_devs[2]; - -int add_mac_table_entry(u64 entry_value) -{ - int i; - u32 data1, data2; - - AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) = ~7; - - for (i = 0; i < 32; i++) { - AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0x80000000 | 0x20 | i; - while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {}; - data1 = AMAZON_SW_REG32(AMAZON_SW_DATA1); - data2 = AMAZON_SW_REG32(AMAZON_SW_DATA2); - if ((data1 & (0x00700000)) != 0x00700000) - continue; - AMAZON_SW_REG32(AMAZON_SW_DATA1) = (u32) (entry_value >> 32); - AMAZON_SW_REG32(AMAZON_SW_DATA2) = (u32) entry_value & 0xffffffff; - AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0xc0000020 | i; - while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {}; - break; - } - AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) |= 7; - if (i >= 32) - return -1; - return OK; -} - -u64 read_mac_table_entry(int index) -{ - u32 data1, data2; - u64 value; - AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0x80000000 | 0x20 | index; - while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {}; - data1 = AMAZON_SW_REG32(AMAZON_SW_DATA1) & 0xffffff; - data2 = AMAZON_SW_REG32(AMAZON_SW_DATA2); - value = (u64) data1 << 32 | (u64) data2; - return value; -} - -int write_mac_table_entry(int index, u64 value) -{ - u32 data1, data2; - data1 = (u32) (value >> 32); - data2 = (u32) value & 0xffffffff; - AMAZON_SW_REG32(AMAZON_SW_DATA1) = data1; - AMAZON_SW_REG32(AMAZON_SW_DATA2) = data2; - AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0xc0000020 | index; - while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {}; - return OK; -} - -u32 get_mdio_reg(int phy_addr, int reg_num) -{ - u32 value; - AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = (3 << 30) | ((phy_addr & 0x1f) << 21) | ((reg_num & 0x1f) << 16); - while (AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & (1 << 31)) {}; - value = AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & 0xffff; - return value; -} - -int set_mdio_reg(int phy_addr, int reg_num, u32 value) -{ - AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = (2 << 30) | ((phy_addr & 0x1f) << 21) | ((reg_num & 0x1f) << 16) | (value & 0xffff); - while (AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & (1 << 31)) {}; - return OK; -} - -int auto_negotiate(int phy_addr) -{ - u32 value = 0; - value = get_mdio_reg(phy_addr, MDIO_BASE_CONTROL_REG); - set_mdio_reg(phy_addr, MDIO_BASE_CONTROL_REG, (value | RESTART_AUTO_NEGOTIATION | AUTO_NEGOTIATION_ENABLE | PHY_RESET)); - return OK; -} - -/* - In this version of switch driver, we split the dma channels for the switch. - 2 for port0 and 2 for port1. So that we can do internal bridging if necessary. - In switch mode, packets coming in from port0 or port1 is able to do Destination - address lookup. Packets coming from port0 with destination address of port1 should - not go to pmac again. The switch hardware should be able to do the switch in the hard - ware level. Packets coming from the pmac should not do the DA look up in that the - desination is already known for the kernel. It only needs to go to the correct NIC to - find its way out. - */ -int amazon_sw_chip_init(void) -{ - u32 tmp1; - int i = 0; - - /* Aging tick select: 5mins */ - tmp1 = 0xa0; - if (strcmp(mode, "bridge") == 0) { - // bridge mode, set militarised mode to 1, no learning! - tmp1 |= 0xC00; - } else { - // enable learning for P0 and P1, - tmp1 |= 3; - } - - /* unknown broadcast/multicast/unicast to all ports */ - AMAZON_SW_REG32(AMAZON_SW_UN_DEST) = 0x1ff; - - AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) = tmp1; - - /* OCS:1 set OCS bit, split the two NIC in rx direction EDL:1 (enable DA lookup) */ -#if defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT) || defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT_MODULE) - AMAZON_SW_REG32(AMAZON_SW_P2_PCTL) = 0x700; -#else - AMAZON_SW_REG32(AMAZON_SW_P2_PCTL) = 0x401; -#endif - - /* EPC: 1 split the two NIC in tx direction CRC is generated */ - AMAZON_SW_REG32(AMAZON_SW_P2_CTL) = 0x6; - - // for bi-directional - AMAZON_SW_REG32(AMAZON_SW_P0_WM) = 0x14141412; - AMAZON_SW_REG32(AMAZON_SW_P1_WM) = 0x14141412; - AMAZON_SW_REG32(AMAZON_SW_P2_WM) = 0x28282826; - AMAZON_SW_REG32(AMAZON_SW_GBL_WM) = 0x0; - - AMAZON_SW_REG32(AMAZON_CGU_PLL0SR) = (AMAZON_SW_REG32(AMAZON_CGU_PLL0SR)) | 0x58000000; - // clock for PHY - AMAZON_SW_REG32(AMAZON_CGU_IFCCR) = (AMAZON_SW_REG32(AMAZON_CGU_IFCCR)) | 0x80000004; - // enable power for PHY - AMAZON_SW_REG32(AMAZON_PMU_PWDCR) = (AMAZON_SW_REG32(AMAZON_PMU_PWDCR)) | AMAZON_PMU_PWDCR_EPHY; - // set reverse MII, enable MDIO statemachine - AMAZON_SW_REG32(AMAZON_SW_MDIO_CFG) = 0x800027bf; - while (1) - if (((AMAZON_SW_REG32(AMAZON_SW_MDIO_CFG)) & 0x80000000) == 0) - break; - AMAZON_SW_REG32(AMAZON_SW_EPHY) = 0xff; - - // auto negotiation - AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = 0x83e08000; - auto_negotiate(0x1f); - - /* enable all ports */ - AMAZON_SW_REG32(AMAZON_SW_PS_CTL) = 0x7; - for (i = 0; i < 32; i++) - write_mac_table_entry(i, 1 << 50); - return 0; -} - -static unsigned char my_ethaddr[MAX_ADDR_LEN]; -/* need to get the ether addr from u-boot */ -static int __init ethaddr_setup(char *line) -{ - char *ep; - int i; - - memset(my_ethaddr, 0, MAX_ADDR_LEN); - for (i = 0; i < 6; i++) { - my_ethaddr[i] = line ? simple_strtoul(line, &ep, 16) : 0; - if (line) - line = (*ep) ? ep + 1 : ep; - } - printk(KERN_INFO "amazon_mii0: mac address %2x-%2x-%2x-%2x-%2x-%2x \n", my_ethaddr[0], my_ethaddr[1], my_ethaddr[2], my_ethaddr[3], my_ethaddr[4], my_ethaddr[5]); - return 0; -} - -__setup("ethaddr=", ethaddr_setup); - -static void open_rx_dma(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - struct dma_device_info *dma_dev = priv->dma_device; - int i; - - for (i = 0; i < dma_dev->num_rx_chan; i++) - dma_dev->rx_chan[i].control = 1; - dma_device_update_rx(dma_dev); -} - -#ifdef CONFIG_NET_HW_FLOWCONTROL -static void close_rx_dma(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - struct dma_device_info *dma_dev = priv->dma_device; - int i; - - for (i = 0; i < dma_dev->num_rx_chan; i++) - dma_dev->rx_chan[i].control = 0; - dma_device_update_rx(dma_dev); -} - -void amazon_xon(struct net_device *dev) -{ - unsigned long flag; - local_irq_save(flag); - open_rx_dma(dev); - local_irq_restore(flag); -} -#endif - -int switch_open(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - if (!strcmp(dev->name, "eth1")) { - priv->mdio_phy_addr = PHY0_ADDR; - } - open_rx_dma(dev); - -#ifdef CONFIG_NET_HW_FLOWCONTROL - if ((priv->fc_bit = netdev_register_fc(dev, amazon_xon)) == 0) { - printk(KERN_WARNING "amazon_mii0: Hardware Flow Control register fails\n"); - } -#endif - - netif_start_queue(dev); - return OK; -} - -int switch_release(struct net_device *dev) -{ - int i; - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - struct dma_device_info *dma_dev = priv->dma_device; - - for (i = 0; i < dma_dev->num_tx_chan; i++) - dma_dev->tx_chan[i].control = 0; - for (i = 0; i < dma_dev->num_rx_chan; i++) - dma_dev->rx_chan[i].control = 0; - - dma_device_update(dma_dev); - -#ifdef CONFIG_NET_HW_FLOWCONTROL - if (priv->fc_bit) { - netdev_unregister_fc(priv->fc_bit); - } -#endif - netif_stop_queue(dev); - - return OK; -} - - -void switch_rx(struct net_device *dev, int len, struct sk_buff *skb) -{ - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); -#ifdef CONFIG_NET_HW_FLOWCONTROL - int mit_sel = 0; -#endif - skb->dev = dev; - skb->protocol = eth_type_trans(skb, dev); - -#ifdef CONFIG_NET_HW_FLOWCONTROL - mit_sel = netif_rx(skb); - switch (mit_sel) { - case NET_RX_SUCCESS: - case NET_RX_CN_LOW: - case NET_RX_CN_MOD: - break; - case NET_RX_CN_HIGH: - break; - case NET_RX_DROP: - if ((priv->fc_bit) - && (!test_and_set_bit(priv->fc_bit, &netdev_fc_xoff))) { - close_rx_dma(dev); - } - break; - } -#else - netif_rx(skb); -#endif - priv->stats.rx_packets++; - priv->stats.rx_bytes += len; - return; -} - -int asmlinkage switch_hw_tx(char *buf, int len, struct net_device *dev) -{ - struct switch_priv *priv = netdev_priv(dev); - struct dma_device_info *dma_dev = priv->dma_device; - - dma_dev->current_tx_chan = 0; - return dma_device_write(dma_dev, buf, len, priv->skb); -} - -int asmlinkage switch_tx(struct sk_buff *skb, struct net_device *dev) -{ - int len; - char *data; - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - - len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; - data = skb->data; - priv->skb = skb; - dev->trans_start = jiffies; - - if (switch_hw_tx(data, len, dev) != len) { - dev_kfree_skb_any(skb); - return OK; - } - - priv->stats.tx_packets++; - priv->stats.tx_bytes += len; - return OK; -} - -void switch_tx_timeout(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - priv->stats.tx_errors++; - netif_wake_queue(dev); - return; -} - -void negotiate(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - unsigned short data = get_mdio_reg(priv->mdio_phy_addr, MDIO_ADVERTISMENT_REG); - - data &= ~(MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD); - - switch (priv->current_speed_selection) { - case 10: - if (priv->current_duplex == full) - data |= MDIO_ADVERT_10_FD; - else if (priv->current_duplex == half) - data |= MDIO_ADVERT_10_HD; - else - data |= MDIO_ADVERT_10_HD | MDIO_ADVERT_10_FD; - break; - - case 100: - if (priv->current_duplex == full) - data |= MDIO_ADVERT_100_FD; - else if (priv->current_duplex == half) - data |= MDIO_ADVERT_100_HD; - else - data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD; - break; - - case 0: /* Auto */ - if (priv->current_duplex == full) - data |= MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD; - else if (priv->current_duplex == half) - data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_10_HD; - else - data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD; - break; - - default: /* assume autoneg speed and duplex */ - data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD; - } - - set_mdio_reg(priv->mdio_phy_addr, MDIO_ADVERTISMENT_REG, data); - - /* Renegotiate with link partner */ - - data = get_mdio_reg(priv->mdio_phy_addr, MDIO_BASE_CONTROL_REG); - data |= MDIO_BC_NEGOTIATE; - - set_mdio_reg(priv->mdio_phy_addr, MDIO_BASE_CONTROL_REG, data); - -} - - -void set_duplex(struct net_device *dev, enum duplex new_duplex) -{ - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - if (new_duplex != priv->current_duplex) { - priv->current_duplex = new_duplex; - negotiate(dev); - } -} - -void set_speed(struct net_device *dev, unsigned long speed) -{ - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - priv->current_speed_selection = speed; - negotiate(dev); -} - -static int switch_ethtool_ioctl(struct net_device *dev, struct ifreq *ifr) -{ - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - struct ethtool_cmd ecmd; - - if (copy_from_user(&ecmd, ifr->ifr_data, sizeof(ecmd))) - return -EFAULT; - - switch (ecmd.cmd) { - case ETHTOOL_GSET: - memset((void *) &ecmd, 0, sizeof(ecmd)); - ecmd.supported = SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | - SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full; - ecmd.port = PORT_TP; - ecmd.transceiver = XCVR_EXTERNAL; - ecmd.phy_address = priv->mdio_phy_addr; - - ecmd.speed = priv->current_speed; - - ecmd.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; - - ecmd.advertising = ADVERTISED_TP; - if (priv->current_duplex == autoneg && priv->current_speed_selection == 0) - ecmd.advertising |= ADVERTISED_Autoneg; - else { - ecmd.advertising |= ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | - ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; - if (priv->current_speed_selection == 10) - ecmd.advertising &= ~(ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full); - else if (priv->current_speed_selection == 100) - ecmd.advertising &= ~(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full); - if (priv->current_duplex == half) - ecmd.advertising &= ~(ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Full); - else if (priv->current_duplex == full) - ecmd.advertising &= ~(ADVERTISED_10baseT_Half | ADVERTISED_100baseT_Half); - } - ecmd.autoneg = AUTONEG_ENABLE; - if (copy_to_user(ifr->ifr_data, &ecmd, sizeof(ecmd))) - return -EFAULT; - break; - - case ETHTOOL_SSET: - if (!capable(CAP_NET_ADMIN)) { - return -EPERM; - } - if (ecmd.autoneg == AUTONEG_ENABLE) { - set_duplex(dev, autoneg); - set_speed(dev, 0); - } else { - set_duplex(dev, ecmd.duplex == DUPLEX_HALF ? half : full); - set_speed(dev, ecmd.speed == SPEED_10 ? 10 : 100); - } - break; - - case ETHTOOL_GDRVINFO: - { - struct ethtool_drvinfo info; - memset((void *) &info, 0, sizeof(info)); - strncpy(info.driver, "AMAZONE", sizeof(info.driver) - 1); - strncpy(info.fw_version, "N/A", sizeof(info.fw_version) - 1); - strncpy(info.bus_info, "N/A", sizeof(info.bus_info) - 1); - info.regdump_len = 0; - info.eedump_len = 0; - info.testinfo_len = 0; - if (copy_to_user(ifr->ifr_data, &info, sizeof(info))) - return -EFAULT; - } - break; - case ETHTOOL_NWAY_RST: - if (priv->current_duplex == autoneg && priv->current_speed_selection == 0) - negotiate(dev); - break; - default: - return -EOPNOTSUPP; - break; - } - return 0; -} - - - -int mac_table_tools_ioctl(struct net_device *dev, struct mac_table_req *req) -{ - int cmd; - int i; - cmd = req->cmd; - switch (cmd) { - case RESET_MAC_TABLE: - for (i = 0; i < 32; i++) { - write_mac_table_entry(i, 0); - } - break; - case READ_MAC_ENTRY: - req->entry_value = read_mac_table_entry(req->index); - break; - case WRITE_MAC_ENTRY: - write_mac_table_entry(req->index, req->entry_value); - break; - case ADD_MAC_ENTRY: - add_mac_table_entry(req->entry_value); - break; - default: - return -EINVAL; - } - - return 0; -} - - -/* - the ioctl for the switch driver is developed in the conventional way - the control type falls into some basic categories, among them, the - SIOCETHTOOL is the traditional eth interface. VLAN_TOOLS and - MAC_TABLE_TOOLS are designed specifically for amazon chip. User - should be aware of the data structures used in these interfaces. -*/ -int switch_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -{ - struct data_req *switch_data_req = (struct data_req *) ifr->ifr_data; - struct mac_table_req *switch_mac_table_req; - switch (cmd) { - case SIOCETHTOOL: - switch_ethtool_ioctl(dev, ifr); - break; - case SIOCGMIIPHY: /* Get PHY address */ - break; - case SIOCGMIIREG: /* Read MII register */ - break; - case SIOCSMIIREG: /* Write MII register */ - break; - case SET_ETH_SPEED_10: /* 10 Mbps */ - break; - case SET_ETH_SPEED_100: /* 100 Mbps */ - break; - case SET_ETH_SPEED_AUTO: /* Auto negotiate speed */ - break; - case SET_ETH_DUPLEX_HALF: /* Half duplex. */ - break; - case SET_ETH_DUPLEX_FULL: /* Full duplex. */ - break; - case SET_ETH_DUPLEX_AUTO: /* Autonegotiate duplex */ - break; - case SET_ETH_REG: - AMAZON_SW_REG32(switch_data_req->index) = switch_data_req->value; - break; - case MAC_TABLE_TOOLS: - switch_mac_table_req = (struct mac_table_req *) ifr->ifr_data; - mac_table_tools_ioctl(dev, switch_mac_table_req); - break; - default: - return -EINVAL; - } - - return 0; -} - -struct net_device_stats *switch_stats(struct net_device *dev) -{ - struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev); - return &priv->stats; -} - -int switch_change_mtu(struct net_device *dev, int new_mtu) -{ - if (new_mtu >= 1516) - new_mtu = 1516; - dev->mtu = new_mtu; - return 0; -} - -int switch_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev) -{ - u8 *buf = NULL; - int len = 0; - struct sk_buff *skb = NULL; - - len = dma_device_read(dma_dev, &buf, (void **) &skb); - - if (len >= 0x600) { - printk(KERN_WARNING "amazon_mii0: packet too large %d\n", len); - goto switch_hw_receive_err_exit; - } - - /* remove CRC */ - len -= 4; - if (skb == NULL) { - printk(KERN_WARNING "amazon_mii0: cannot restore pointer\n"); - goto switch_hw_receive_err_exit; - } - if (len > (skb->end - skb->tail)) { - printk(KERN_WARNING "amazon_mii0: BUG, len:%d end:%p tail:%p\n", (len + 4), skb->end, skb->tail); - goto switch_hw_receive_err_exit; - } - skb_put(skb, len); - skb->dev = dev; - switch_rx(dev, len, skb); - return OK; - - switch_hw_receive_err_exit: - if (skb) - dev_kfree_skb_any(skb); - return -EIO; -} - -int dma_intr_handler(struct dma_device_info *dma_dev, int status) -{ - struct net_device *dev; - - dev = dma_dev->priv; - switch (status) { - case RCV_INT: - switch_hw_receive(dev, dma_dev); - break; - case TX_BUF_FULL_INT: - netif_stop_queue(dev); - break; - case TRANSMIT_CPT_INT: - netif_wake_queue(dev); - break; - } - return OK; -} - -/* reserve 2 bytes in front of data pointer*/ -u8 *dma_buffer_alloc(int len, int *byte_offset, void **opt) -{ - u8 *buffer = NULL; - struct sk_buff *skb = NULL; - skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE); - if (skb == NULL) { - return NULL; - } - buffer = (u8 *) (skb->data); - skb_reserve(skb, 2); - *(int *) opt = (int) skb; - *byte_offset = 2; - return buffer; -} - -int dma_buffer_free(u8 * dataptr, void *opt) -{ - struct sk_buff *skb = NULL; - if (opt == NULL) { - kfree(dataptr); - } else { - skb = (struct sk_buff *) opt; - dev_kfree_skb_any(skb); - } - return OK; -} - -int init_dma_device(_dma_device_info * dma_dev, struct net_device *dev) -{ - int i; - int num_tx_chan, num_rx_chan; - if (strcmp(dma_dev->device_name, "switch1") == 0) { - num_tx_chan = 1; - num_rx_chan = 2; - } else { - num_tx_chan = 1; - num_rx_chan = 2; - } - dma_dev->priv = dev; - - dma_dev->weight = 1; - dma_dev->num_tx_chan = num_tx_chan; - dma_dev->num_rx_chan = num_rx_chan; - dma_dev->ack = 1; - dma_dev->tx_burst_len = 4; - dma_dev->rx_burst_len = 4; - for (i = 0; i < dma_dev->num_tx_chan; i++) { - dma_dev->tx_chan[i].weight = QOS_DEFAULT_WGT; - dma_dev->tx_chan[i].desc_num = 10; - dma_dev->tx_chan[i].packet_size = 0; - dma_dev->tx_chan[i].control = 0; - } - for (i = 0; i < num_rx_chan; i++) { - dma_dev->rx_chan[i].weight = QOS_DEFAULT_WGT; - dma_dev->rx_chan[i].desc_num = 10; - dma_dev->rx_chan[i].packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE; - dma_dev->rx_chan[i].control = 0; - } - dma_dev->intr_handler = dma_intr_handler; - dma_dev->buffer_alloc = dma_buffer_alloc; - dma_dev->buffer_free = dma_buffer_free; - return 0; -} - -int switch_set_mac_address(struct net_device *dev, void *p) -{ - struct sockaddr *addr = p; - memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); - return OK; -} - -static const struct net_device_ops amazon_mii_ops = { - .ndo_init = switch_init, - .ndo_open = switch_open, - .ndo_stop = switch_release, - .ndo_start_xmit = switch_tx, - .ndo_do_ioctl = switch_ioctl, - .ndo_get_stats = switch_stats, - .ndo_change_mtu = switch_change_mtu, - .ndo_set_mac_address = switch_set_mac_address, - .ndo_tx_timeout = switch_tx_timeout, -}; - -int switch_init(struct net_device *dev) -{ - u64 retval = 0; - int i; - int result; - struct switch_priv *priv; - ether_setup(dev); /* assign some of the fields */ - printk(KERN_INFO "amazon_mii0: %s up using ", dev->name); - dev->watchdog_timeo = timeout; - - priv = netdev_priv(dev); - priv->dma_device = (struct dma_device_info *) kmalloc(sizeof(struct dma_device_info), GFP_KERNEL); - if (priv->num == 0) { - sprintf(priv->dma_device->device_name, "switch1"); - } else if (priv->num == 1) { - sprintf(priv->dma_device->device_name, "switch2"); - } - printk("\"%s\"\n", priv->dma_device->device_name); - init_dma_device(priv->dma_device, dev); - result = dma_device_register(priv->dma_device); - - /* read the mac address from the mac table and put them into the mac table. */ - for (i = 0; i < 6; i++) { - retval += my_ethaddr[i]; - } - /* ethaddr not set in u-boot ? */ - if (retval == 0) { - dev->dev_addr[0] = 0x00; - dev->dev_addr[1] = 0x20; - dev->dev_addr[2] = 0xda; - dev->dev_addr[3] = 0x86; - dev->dev_addr[4] = 0x23; - dev->dev_addr[5] = 0x74 + (unsigned char) priv->num; - } else { - for (i = 0; i < 6; i++) { - dev->dev_addr[i] = my_ethaddr[i]; - } - dev->dev_addr[5] += +(unsigned char) priv->num; - } - return OK; -} - -static int amazon_mii_probe(struct platform_device *dev) -{ - int i = 0, result, device_present = 0; - struct switch_priv *priv; - - for (i = 0; i < AMAZON_SW_INT_NO; i++) { - switch_devs[i] = alloc_etherdev(sizeof(struct switch_priv)); - switch_devs[i]->netdev_ops = &amazon_mii_ops; - strcpy(switch_devs[i]->name, "eth%d"); - priv = (struct switch_priv *) netdev_priv(switch_devs[i]); - priv->num = i; - if ((result = register_netdev(switch_devs[i]))) - printk(KERN_WARNING "amazon_mii0: error %i registering device \"%s\"\n", result, switch_devs[i]->name); - else - device_present++; - } - amazon_sw_chip_init(); - return device_present ? 0 : -ENODEV; -} - -static int amazon_mii_remove(struct platform_device *dev) -{ - int i; - struct switch_priv *priv; - for (i = 0; i < AMAZON_SW_INT_NO; i++) { - priv = netdev_priv(switch_devs[i]); - if (priv->dma_device) { - dma_device_unregister(priv->dma_device); - kfree(priv->dma_device); - } - kfree(netdev_priv(switch_devs[i])); - unregister_netdev(switch_devs[i]); - } - return 0; -} - -static struct platform_driver amazon_mii_driver = { - .probe = amazon_mii_probe, - .remove = amazon_mii_remove, - .driver = { - .name = "amazon_mii0", - .owner = THIS_MODULE, - }, -}; - -static int __init amazon_mii_init(void) -{ - int ret = platform_driver_register(&amazon_mii_driver); - if (ret) - printk(KERN_WARNING "amazon_mii0: Error registering platfom driver!\n"); - return ret; -} - -static void __exit amazon_mii_cleanup(void) -{ - platform_driver_unregister(&amazon_mii_driver); -} - -module_init(amazon_mii_init); -module_exit(amazon_mii_cleanup); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Wu Qi Ming"); -MODULE_DESCRIPTION("ethernet driver for AMAZON boards"); - diff --git a/target/linux/amazon/files/drivers/serial/amazon_asc.c b/target/linux/amazon/files/drivers/serial/amazon_asc.c deleted file mode 100644 index 449208616..000000000 --- a/target/linux/amazon/files/drivers/serial/amazon_asc.c +++ /dev/null @@ -1,711 +0,0 @@ -/* - * Driver for AMAZONASC serial ports - * - * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. - * Based on drivers/serial/serial_s3c2400.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright (C) 2004 Infineon IFAP DC COM CPE - * Copyright (C) 2007 Felix Fietkau - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define PORT_AMAZONASC 111 - -#include - -#define UART_NR 1 - -#define UART_DUMMY_UER_RX 1 - -#define SERIAL_AMAZONASC_MAJOR TTY_MAJOR -#define CALLOUT_AMAZONASC_MAJOR TTYAUX_MAJOR -#define SERIAL_AMAZONASC_MINOR 64 -#define SERIAL_AMAZONASC_NR UART_NR - -static void amazonasc_tx_chars(struct uart_port *port); -static struct uart_port amazonasc_ports[UART_NR]; -static struct uart_driver amazonasc_reg; -static unsigned int uartclk = 0; - -static void amazonasc_stop_tx(struct uart_port *port) -{ - /* fifo underrun shuts up after firing once */ - return; -} - -static void amazonasc_start_tx(struct uart_port *port) -{ - unsigned long flags; - - local_irq_save(flags); - amazonasc_tx_chars(port); - local_irq_restore(flags); - - return; -} - -static void amazonasc_stop_rx(struct uart_port *port) -{ - /* clear the RX enable bit */ - amazon_writel(ASCWHBCON_CLRREN, AMAZON_ASC_WHBCON); -} - -static void amazonasc_enable_ms(struct uart_port *port) -{ - /* no modem signals */ - return; -} - -#include - -static void -amazonasc_rx_chars(struct uart_port *port) -{ -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)) - struct tty_struct *tty = port->state->port.tty; -#else - struct tty_struct *tty = port->info->port.tty; -#endif - unsigned int ch = 0, rsr = 0, fifocnt; - - fifocnt = amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; - while (fifocnt--) - { - u8 flag = TTY_NORMAL; - ch = amazon_readl(AMAZON_ASC_RBUF); - rsr = (amazon_readl(AMAZON_ASC_CON) & ASCCON_ANY) | UART_DUMMY_UER_RX; - tty_flip_buffer_push(tty); - port->icount.rx++; - - /* - * Note that the error handling code is - * out of the main execution path - */ - if (rsr & ASCCON_ANY) { - if (rsr & ASCCON_PE) { - port->icount.parity++; - amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLRPE, ASCWHBCON_CLRPE); - } else if (rsr & ASCCON_FE) { - port->icount.frame++; - amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLRFE, ASCWHBCON_CLRFE); - } - if (rsr & ASCCON_OE) { - port->icount.overrun++; - amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLROE, ASCWHBCON_CLROE); - } - - rsr &= port->read_status_mask; - - if (rsr & ASCCON_PE) - flag = TTY_PARITY; - else if (rsr & ASCCON_FE) - flag = TTY_FRAME; - } - - if ((rsr & port->ignore_status_mask) == 0) - tty_insert_flip_char(tty, ch, flag); - - if (rsr & ASCCON_OE) - /* - * Overrun is special, since it's reported - * immediately, and doesn't affect the current - * character - */ - tty_insert_flip_char(tty, 0, TTY_OVERRUN); - } - if (ch != 0) - tty_flip_buffer_push(tty); - - return; -} - - -static void amazonasc_tx_chars(struct uart_port *port) -{ -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)) - struct circ_buf *xmit = &port->state->xmit; -#else - struct circ_buf *xmit = &port->info->xmit; -#endif - - if (uart_tx_stopped(port)) { - amazonasc_stop_tx(port); - return; - } - - while (((amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) - >> ASCFSTAT_TXFFLOFF) != AMAZONASC_TXFIFO_FULL) - { - if (port->x_char) { - amazon_writel(port->x_char, AMAZON_ASC_TBUF); - port->icount.tx++; - port->x_char = 0; - continue; - } - - if (uart_circ_empty(xmit)) - break; - - amazon_writel(xmit->buf[xmit->tail], AMAZON_ASC_TBUF); - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); - port->icount.tx++; - } - - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) - uart_write_wakeup(port); -} - -static irqreturn_t amazonasc_tx_int(int irq, void *port) -{ - amazon_writel(ASC_IRNCR_TIR, AMAZON_ASC_IRNCR1); - amazonasc_start_tx(port); - - /* clear any pending interrupts */ - amazon_writel_masked(AMAZON_ASC_WHBCON, - (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE), - (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE)); - - return IRQ_HANDLED; -} - -static irqreturn_t amazonasc_er_int(int irq, void *port) -{ - /* clear any pending interrupts */ - amazon_writel_masked(AMAZON_ASC_WHBCON, - (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE), - (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE)); - - return IRQ_HANDLED; -} - -static irqreturn_t amazonasc_rx_int(int irq, void *port) -{ - amazon_writel(ASC_IRNCR_RIR, AMAZON_ASC_IRNCR1); - amazonasc_rx_chars((struct uart_port *) port); - return IRQ_HANDLED; -} - -static u_int amazonasc_tx_empty(struct uart_port *port) -{ - int status; - - /* - * FSTAT tells exactly how many bytes are in the FIFO. - * The question is whether we really need to wait for all - * 16 bytes to be transmitted before reporting that the - * transmitter is empty. - */ - status = amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; - return status ? 0 : TIOCSER_TEMT; -} - -static u_int amazonasc_get_mctrl(struct uart_port *port) -{ - /* no modem control signals - the readme says to pretend all are set */ - return TIOCM_CTS|TIOCM_CAR|TIOCM_DSR; -} - -static void amazonasc_set_mctrl(struct uart_port *port, u_int mctrl) -{ - /* no modem control - just return */ - return; -} - -static void amazonasc_break_ctl(struct uart_port *port, int break_state) -{ - /* no way to send a break */ - return; -} - -static int amazonasc_startup(struct uart_port *port) -{ - unsigned int con = 0; - unsigned long flags; - int retval; - - /* this assumes: CON.BRS = CON.FDE = 0 */ - if (uartclk == 0) - uartclk = amazon_get_fpi_hz(); - - amazonasc_ports[0].uartclk = uartclk; - - local_irq_save(flags); - - /* this setup was probably already done in u-boot */ - /* ASC and GPIO Port 1 bits 3 and 4 share the same pins - * P1.3 (RX) in, Alternate 10 - * P1.4 (TX) in, Alternate 10 - */ - amazon_writel_masked(AMAZON_GPIO_P1_DIR, 0x18, 0x10); //P1.4 output, P1.3 input - amazon_writel_masked(AMAZON_GPIO_P1_ALTSEL0, 0x18, 0x18); //ALTSETL0 11 - amazon_writel_masked(AMAZON_GPIO_P1_ALTSEL1, 0x18, 0); //ALTSETL1 00 - amazon_writel_masked(AMAZON_GPIO_P1_OD, 0x18, 0x10); - - /* set up the CLC */ - amazon_writel_masked(AMAZON_ASC_CLC, AMAZON_ASC_CLC_DISS, 0); - amazon_writel_masked(AMAZON_ASC_CLC, ASCCLC_RMCMASK, 1 << ASCCLC_RMCOFFSET); - - /* asynchronous mode */ - con = ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_OEN | ASCCON_PEN; - - /* choose the line - there's only one */ - amazon_writel(0, AMAZON_ASC_PISEL); - amazon_writel(((AMAZONASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, - AMAZON_ASC_TXFCON); - amazon_writel(((AMAZONASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, - AMAZON_ASC_RXFCON); - wmb(); - - amazon_writel_masked(AMAZON_ASC_CON, con, con); - - retval = request_irq(AMAZONASC_RIR, amazonasc_rx_int, 0, "asc_rx", port); - if (retval){ - printk("failed to request amazonasc_rx_int\n"); - return retval; - } - retval = request_irq(AMAZONASC_TIR, amazonasc_tx_int, 0, "asc_tx", port); - if (retval){ - printk("failed to request amazonasc_tx_int\n"); - goto err1; - } - - retval = request_irq(AMAZONASC_EIR, amazonasc_er_int, 0, "asc_er", port); - if (retval){ - printk("failed to request amazonasc_er_int\n"); - goto err2; - } - - local_irq_restore(flags); - return 0; - -err2: - free_irq(AMAZONASC_TIR, port); - -err1: - free_irq(AMAZONASC_RIR, port); - local_irq_restore(flags); - return retval; -} - -static void amazonasc_shutdown(struct uart_port *port) -{ - free_irq(AMAZONASC_RIR, port); - free_irq(AMAZONASC_TIR, port); - free_irq(AMAZONASC_EIR, port); - /* - * disable the baudrate generator to disable the ASC - */ - amazon_writel(0, AMAZON_ASC_CON); - - /* flush and then disable the fifos */ - amazon_writel_masked(AMAZON_ASC_RXFCON, ASCRXFCON_RXFFLU, ASCRXFCON_RXFFLU); - amazon_writel_masked(AMAZON_ASC_RXFCON, ASCRXFCON_RXFEN, 0); - amazon_writel_masked(AMAZON_ASC_TXFCON, ASCTXFCON_TXFFLU, ASCTXFCON_TXFFLU); - amazon_writel_masked(AMAZON_ASC_TXFCON, ASCTXFCON_TXFEN, 0); -} - -static void amazonasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old) -{ - unsigned int cflag; - unsigned int iflag; - unsigned int baud, quot; - unsigned int con = 0; - unsigned long flags; - - cflag = new->c_cflag; - iflag = new->c_iflag; - - /* byte size and parity */ - switch (cflag & CSIZE) { - /* 7 bits are always with parity */ - case CS7: con = ASCCON_M_7ASYNCPAR; break; - /* the ASC only suports 7 and 8 bits */ - case CS5: - case CS6: - default: - if (cflag & PARENB) - con = ASCCON_M_8ASYNCPAR; - else - con = ASCCON_M_8ASYNC; - break; - } - if (cflag & CSTOPB) - con |= ASCCON_STP; - if (cflag & PARENB) { - if (!(cflag & PARODD)) - con &= ~ASCCON_ODD; - else - con |= ASCCON_ODD; - } - - port->read_status_mask = ASCCON_OE; - if (iflag & INPCK) - port->read_status_mask |= ASCCON_FE | ASCCON_PE; - - port->ignore_status_mask = 0; - if (iflag & IGNPAR) - port->ignore_status_mask |= ASCCON_FE | ASCCON_PE; - - if (iflag & IGNBRK) { - /* - * If we're ignoring parity and break indicators, - * ignore overruns too (for real raw support). - */ - if (iflag & IGNPAR) - port->ignore_status_mask |= ASCCON_OE; - } - - /* - * Ignore all characters if CREAD is not set. - */ - if ((cflag & CREAD) == 0) - port->ignore_status_mask |= UART_DUMMY_UER_RX; - - /* set error signals - framing, parity and overrun */ - con |= ASCCON_FEN; - con |= ASCCON_OEN; - con |= ASCCON_PEN; - /* enable the receiver */ - con |= ASCCON_REN; - - /* block the IRQs */ - local_irq_save(flags); - - /* set up CON */ - amazon_writel(con, AMAZON_ASC_CON); - - /* Set baud rate - take a divider of 2 into account */ - baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16); - quot = uart_get_divisor(port, baud); - quot = quot/2 - 1; - - /* the next 3 probably already happened when we set CON above */ - /* disable the baudrate generator */ - amazon_writel_masked(AMAZON_ASC_CON, ASCCON_R, 0); - /* make sure the fractional divider is off */ - amazon_writel_masked(AMAZON_ASC_CON, ASCCON_FDE, 0); - /* set up to use divisor of 2 */ - amazon_writel_masked(AMAZON_ASC_CON, ASCCON_BRS, 0); - /* now we can write the new baudrate into the register */ - amazon_writel(quot, AMAZON_ASC_BTR); - /* turn the baudrate generator back on */ - amazon_writel_masked(AMAZON_ASC_CON, ASCCON_R, ASCCON_R); - - local_irq_restore(flags); -} - -static const char *amazonasc_type(struct uart_port *port) -{ - return port->type == PORT_AMAZONASC ? "AMAZONASC" : NULL; -} - -/* - * Release the memory region(s) being used by 'port' - */ -static void amazonasc_release_port(struct uart_port *port) -{ - return; -} - -/* - * Request the memory region(s) being used by 'port' - */ -static int amazonasc_request_port(struct uart_port *port) -{ - return 0; -} - -/* - * Configure/autoconfigure the port. - */ -static void amazonasc_config_port(struct uart_port *port, int flags) -{ - if (flags & UART_CONFIG_TYPE) { - port->type = PORT_AMAZONASC; - amazonasc_request_port(port); - } -} - -/* - * verify the new serial_struct (for TIOCSSERIAL). - */ -static int amazonasc_verify_port(struct uart_port *port, struct serial_struct *ser) -{ - int ret = 0; - if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMAZONASC) - ret = -EINVAL; - if (ser->irq < 0 || ser->irq >= NR_IRQS) - ret = -EINVAL; - if (ser->baud_base < 9600) - ret = -EINVAL; - return ret; -} - -static struct uart_ops amazonasc_pops = { - .tx_empty = amazonasc_tx_empty, - .set_mctrl = amazonasc_set_mctrl, - .get_mctrl = amazonasc_get_mctrl, - .stop_tx = amazonasc_stop_tx, - .start_tx = amazonasc_start_tx, - .stop_rx = amazonasc_stop_rx, - .enable_ms = amazonasc_enable_ms, - .break_ctl = amazonasc_break_ctl, - .startup = amazonasc_startup, - .shutdown = amazonasc_shutdown, - .set_termios = amazonasc_set_termios, - .type = amazonasc_type, - .release_port = amazonasc_release_port, - .request_port = amazonasc_request_port, - .config_port = amazonasc_config_port, - .verify_port = amazonasc_verify_port, -}; - -static struct uart_port amazonasc_ports[UART_NR] = { - { - membase: (void *)AMAZON_ASC, - mapbase: AMAZON_ASC, - iotype: SERIAL_IO_MEM, - irq: AMAZONASC_RIR, /* RIR */ - uartclk: 0, /* filled in dynamically */ - fifosize: 16, - unused: { AMAZONASC_TIR, AMAZONASC_EIR}, /* xmit/error/xmit-buffer-empty IRQ */ - type: PORT_AMAZONASC, - ops: &amazonasc_pops, - flags: ASYNC_BOOT_AUTOCONF, - }, -}; - -static void amazonasc_console_write(struct console *co, const char *s, u_int count) -{ - int i, fifocnt; - unsigned long flags; - local_irq_save(flags); - for (i = 0; i < count;) - { - /* wait until the FIFO is not full */ - do - { - fifocnt = (amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) - >> ASCFSTAT_TXFFLOFF; - } while (fifocnt == AMAZONASC_TXFIFO_FULL); - if (s[i] == '\0') - { - break; - } - if (s[i] == '\n') - { - amazon_writel('\r', AMAZON_ASC_TBUF); - do - { - fifocnt = (amazon_readl(AMAZON_ASC_FSTAT) & - ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF; - } while (fifocnt == AMAZONASC_TXFIFO_FULL); - } - amazon_writel(s[i], AMAZON_ASC_TBUF); - i++; - } - - local_irq_restore(flags); -} - -static void __init -amazonasc_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits) -{ - u_int lcr_h; - - lcr_h = amazon_readl(AMAZON_ASC_CON); - /* do this only if the ASC is turned on */ - if (lcr_h & ASCCON_R) { - u_int quot, div, fdiv, frac; - - *parity = 'n'; - if ((lcr_h & ASCCON_MODEMASK) == ASCCON_M_7ASYNCPAR || - (lcr_h & ASCCON_MODEMASK) == ASCCON_M_8ASYNCPAR) { - if (lcr_h & ASCCON_ODD) - *parity = 'o'; - else - *parity = 'e'; - } - - if ((lcr_h & ASCCON_MODEMASK) == ASCCON_M_7ASYNCPAR) - *bits = 7; - else - *bits = 8; - - quot = amazon_readl(AMAZON_ASC_BTR) + 1; - - /* this gets hairy if the fractional divider is used */ - if (lcr_h & ASCCON_FDE) - { - div = 1; - fdiv = amazon_readl(AMAZON_ASC_FDV); - if (fdiv == 0) - fdiv = 512; - frac = 512; - } - else - { - div = lcr_h & ASCCON_BRS ? 3 : 2; - fdiv = frac = 1; - } - /* - * This doesn't work exactly because we use integer - * math to calculate baud which results in rounding - * errors when we try to go from quot -> baud !! - * Try to make this work for both the fractional divider - * and the simple divider. Also try to avoid rounding - * errors using integer math. - */ - - *baud = frac * (port->uartclk / (div * 512 * 16 * quot)); - if (*baud > 1100 && *baud < 2400) - *baud = 1200; - if (*baud > 2300 && *baud < 4800) - *baud = 2400; - if (*baud > 4700 && *baud < 9600) - *baud = 4800; - if (*baud > 9500 && *baud < 19200) - *baud = 9600; - if (*baud > 19000 && *baud < 38400) - *baud = 19200; - if (*baud > 38400 && *baud < 57600) - *baud = 38400; - if (*baud > 57600 && *baud < 115200) - *baud = 57600; - if (*baud > 115200 && *baud < 230400) - *baud = 115200; - } -} - -static int __init amazonasc_console_setup(struct console *co, char *options) -{ - struct uart_port *port; - int baud = 115200; - int bits = 8; - int parity = 'n'; - int flow = 'n'; - - /* this assumes: CON.BRS = CON.FDE = 0 */ - if (uartclk == 0) - uartclk = amazon_get_fpi_hz(); - co->index = 0; - port = &amazonasc_ports[0]; - amazonasc_ports[0].uartclk = uartclk; - amazonasc_ports[0].type = PORT_AMAZONASC; - - if (options){ - uart_parse_options(options, &baud, &parity, &bits, &flow); - } - - return uart_set_options(port, co, baud, parity, bits, flow); -} - -static struct uart_driver amazonasc_reg; -static struct console amazonasc_console = { - name: "ttyS", - write: amazonasc_console_write, - device: uart_console_device, - setup: amazonasc_console_setup, - flags: CON_PRINTBUFFER, - index: -1, - data: &amazonasc_reg, -}; - -static struct uart_driver amazonasc_reg = { - .owner = THIS_MODULE, - .driver_name = "serial", - .dev_name = "ttyS", - .major = TTY_MAJOR, - .minor = 64, - .nr = UART_NR, - .cons = &amazonasc_console, -}; - -static int __init amazon_asc_probe(struct platform_device *dev) -{ - unsigned char res; - uart_register_driver(&amazonasc_reg); - res = uart_add_one_port(&amazonasc_reg, &amazonasc_ports[0]); - return res; -} - -static int amazon_asc_remove(struct platform_device *dev) -{ - uart_unregister_driver(&amazonasc_reg); - return 0; -} - -static struct platform_driver amazon_asc_driver = { - .probe = amazon_asc_probe, - .remove = amazon_asc_remove, - .driver = { - .name = "amazon_asc", - .owner = THIS_MODULE, - }, -}; - -static int __init amazon_asc_init(void) -{ - int ret = platform_driver_register(&amazon_asc_driver); - if (ret) - printk(KERN_WARNING "amazon_asc: error registering platfom driver!\n"); - return ret; -} - -static void __exit amazon_asc_cleanup(void) -{ - platform_driver_unregister(&amazon_asc_driver); -} - -module_init(amazon_asc_init); -module_exit(amazon_asc_cleanup); - -MODULE_AUTHOR("Gary Jennejohn, Felix Fietkau, John Crispin"); -MODULE_DESCRIPTION("MIPS AMAZONASC serial port driver"); -MODULE_LICENSE("GPL"); - diff --git a/target/linux/amazon/files/drivers/watchdog/amazon_wdt.c b/target/linux/amazon/files/drivers/watchdog/amazon_wdt.c deleted file mode 100644 index fcf1649d8..000000000 --- a/target/linux/amazon/files/drivers/watchdog/amazon_wdt.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Copyright 2004 Wu Qi Ming - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DRV_NAME "AMAZON WDT:" - -#undef AMAZON_WDT_DEBUG - -static int amazon_wdt_isopen = 0; - -#ifdef AMAZON_WDT_DEBUG -static struct proc_dir_entry* amazon_wdt_dir; -#endif - -int wdt_enable(int timeout) -{ - u32 hard_psw, ffpi; - int reload_value, divider = 1; - - ffpi = amazon_get_fpi_hz(); - - reload_value = 65536 - timeout * ffpi / 256; - - if (reload_value < 0) { - divider = 0; - reload_value = 65536 - timeout * ffpi / 16384; - } - - if (reload_value < 0){ - printk(KERN_INFO DRV_NAME "timeout too large %d\n", timeout); - return -EINVAL; - } - - printk(KERN_INFO DRV_NAME "timeout:%d reload_value: %8x\n", timeout, reload_value); - - hard_psw = (amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) + - (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0; - amazon_writel(hard_psw, AMAZON_WDT_CON0); - wmb(); - - amazon_writel((hard_psw & 0xff00) + (reload_value << 16) + 0xf2, AMAZON_WDT_CON0); - wmb(); - - amazon_writel(divider << 2, AMAZON_WDT_CON1); - wmb(); - - hard_psw = (amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) + - (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0; - amazon_writel(hard_psw, AMAZON_WDT_CON0); - wmb(); - - amazon_writel_masked(AMAZON_WDT_CON0, 0xff, 0xf3); - wmb(); - return 0; -} - -void wdt_disable(void) -{ - u32 hard_psw = 0; - - hard_psw = (amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) + - (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0; - amazon_writel(hard_psw, AMAZON_WDT_CON0); - wmb(); - - amazon_writel_masked(AMAZON_WDT_CON0, 0xff, 0xf2); - wmb(); - - amazon_writel_masked(AMAZON_WDT_CON1, 0x8, 0x8); - wmb(); - - hard_psw=(amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) + - (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0; - amazon_writel(hard_psw, AMAZON_WDT_CON0); - wmb(); - - amazon_writel_masked(AMAZON_WDT_CON0, 0xff, 0xf3); - wmb(); - - return; -} - -static int wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -{ - int result=0; - static int timeout=-1; - - switch(cmd){ - case AMAZON_WDT_IOC_START: - printk(KERN_INFO DRV_NAME "enable watch dog timer!\n"); - if (copy_from_user((void*)&timeout, (void*)arg, sizeof (int))) { - printk(KERN_INFO DRV_NAME "invalid argument\n"); - result=-EINVAL; - } else if ((result = wdt_enable(timeout)) < 0) { - timeout = -1; - } - break; - - case AMAZON_WDT_IOC_STOP: - printk(KERN_INFO DRV_NAME "disable watch dog timer\n"); - timeout = -1; - wdt_disable(); - break; - - case AMAZON_WDT_IOC_PING: - if (timeout < 0) { - result = -EIO; - } else { - result = wdt_enable(timeout); - } - break; - - default: - result=-EINVAL; - break; - } - return result; -} - -static ssize_t wdt_read(struct file *file, char *buf, size_t count, loff_t *offset) -{ - return 0; -} - -static ssize_t wdt_write(struct file *file, const char *buf, size_t count, loff_t *offset) -{ - return count; -} - -static int wdt_open(struct inode *inode, struct file *file) -{ - if (amazon_wdt_isopen == 1) - return -EBUSY; - - amazon_wdt_isopen = 1; - printk(KERN_INFO DRV_NAME "opened\n"); - return 0; -} - -static int wdt_release(struct inode *inode, struct file *file) -{ - amazon_wdt_isopen = 0; - printk(KERN_INFO DRV_NAME "closed\n"); - return 0; -} - -#ifdef AMAZON_WDT_DEBUG -int wdt_register_proc_read(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - int len=0; - len+=sprintf(buf+len,"NMISR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_NMISR)); - len+=sprintf(buf+len,"RST_REQ: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_RST_REQ)); - len+=sprintf(buf+len,"RST_SR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_RST_SR)); - len+=sprintf(buf+len,"WDT_CON0: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_CON0)); - len+=sprintf(buf+len,"WDT_CON1: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_CON1)); - len+=sprintf(buf+len,"WDT_SR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_SR)); - *eof = 1; - return len; -} -#endif - -static struct file_operations wdt_fops = { - read: wdt_read, - write: wdt_write, - ioctl: wdt_ioctl, - open: wdt_open, - release: wdt_release, -}; - -static int __init amazon_wdt_probe(struct platform_device *dev) -{ - int result = result = register_chrdev(0, "watchdog", &wdt_fops); - - if (result < 0) { - printk(KERN_INFO DRV_NAME "cannot register device\n"); - return result; - } - -#ifdef AMAZON_WDT_DEBUG - amazon_wdt_dir=proc_mkdir("amazon_wdt",NULL); - create_proc_read_entry("wdt_register", 0, amazon_wdt_dir, - wdt_register_proc_read, NULL); -#endif - - amazon_wdt_isopen=0; - printk(KERN_INFO DRV_NAME "driver loaded but inactive\n"); - return 0; -} - -static int amazon_wdt_remove(struct platform_device *dev) -{ - unregister_chrdev(0, "watchdog"); -#ifdef AMAZON_WDT_DEBUG - remove_proc_entry("wdt_register", amazon_wdt_dir); - remove_proc_entry("amazon_wdt", NULL); -#endif - printk(KERN_INFO DRV_NAME "unregistered\n"); - return 0; -} - -static struct platform_driver amazon_wdt_driver = { - .probe = amazon_wdt_probe, - .remove = amazon_wdt_remove, - .driver = { - .name = "amazon_wdt", - .owner = THIS_MODULE, - }, -}; - -static int __init amazon_wdt_init(void) -{ - int ret = platform_driver_register(&amazon_wdt_driver); - if (ret) - printk(KERN_WARNING "amazon_wdt: error registering platfom driver!\n"); - return ret; -} - -static void __exit amazon_wdt_exit(void) -{ - platform_driver_unregister(&amazon_wdt_driver); -} - -module_init(amazon_wdt_init); -module_exit(amazon_wdt_exit); - -MODULE_LICENSE ("GPL"); -MODULE_AUTHOR("Infineon / John Crispin "); -MODULE_DESCRIPTION("AMAZON WDT driver"); - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/adm6996.h b/target/linux/amazon/files/include/asm-mips/amazon/adm6996.h deleted file mode 100644 index 77cf4b131..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/adm6996.h +++ /dev/null @@ -1,232 +0,0 @@ -/****************************************************************************** - Copyright (c) 2004, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. - ****************************************************************************** - Module : ifx_swdrv.h - Date : 2004-09-01 - Description : JoeLin - Remarks: - - *****************************************************************************/ - -#ifndef _ADM_6996_MODULE_H_ -#define _ADM_6996_MODULE_H_ - -#include - -#define ifx_printf(x) printk x - -/* command codes */ -#define ADM_SW_SMI_READ 0x02 -#define ADM_SW_SMI_WRITE 0x01 -#define ADM_SW_SMI_START 0x01 - -#define ADM_SW_EEPROM_WRITE 0x01 -#define ADM_SW_EEPROM_WRITE_ENABLE 0x03 -#define ADM_SW_EEPROM_WRITE_DISABLE 0x00 -#define EEPROM_TYPE 8 /* for 93C66 */ - -/* bit masks */ -#define ADM_SW_BIT_MASK_1 0x00000001 -#define ADM_SW_BIT_MASK_2 0x00000002 -#define ADM_SW_BIT_MASK_4 0x00000008 -#define ADM_SW_BIT_MASK_10 0x00000200 -#define ADM_SW_BIT_MASK_16 0x00008000 -#define ADM_SW_BIT_MASK_32 0x80000000 - -/* delay timers */ -#define ADM_SW_MDC_DOWN_DELAY 5 -#define ADM_SW_MDC_UP_DELAY 5 -#define ADM_SW_CS_DELAY 5 - -/* MDIO modes */ -#define ADM_SW_MDIO_OUTPUT 1 -#define ADM_SW_MDIO_INPUT 0 - -#define ADM_SW_MAX_PORT_NUM 5 -#define ADM_SW_MAX_VLAN_NUM 15 - -/* registers */ -#define ADM_SW_PORT0_CONF 0x1 -#define ADM_SW_PORT1_CONF 0x3 -#define ADM_SW_PORT2_CONF 0x5 -#define ADM_SW_PORT3_CONF 0x7 -#define ADM_SW_PORT4_CONF 0x8 -#define ADM_SW_PORT5_CONF 0x9 -#define ADM_SW_VLAN_MODE 0x11 -#define ADM_SW_MAC_LOCK 0x12 -#define ADM_SW_VLAN0_CONF 0x13 -#define ADM_SW_PORT0_PVID 0x28 -#define ADM_SW_PORT1_PVID 0x29 -#define ADM_SW_PORT2_PVID 0x2a -#define ADM_SW_PORT34_PVID 0x2b -#define ADM_SW_PORT5_PVID 0x2c -#define ADM_SW_PHY_RESET 0x2f -#define ADM_SW_MISC_CONF 0x30 -#define ADM_SW_BNDWDH_CTL0 0x31 -#define ADM_SW_BNDWDH_CTL1 0x32 -#define ADM_SW_BNDWDH_CTL_ENA 0x33 - -/* port modes */ -#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */ -#define ADM_SW_PORT_AN 0x2 /* auto negotiation */ -#define ADM_SW_PORT_100M 0x4 /* 100M */ -#define ADM_SW_PORT_FULL 0x8 /* full duplex */ -#define ADM_SW_PORT_TAG 0x10 /* output tag on */ -#define ADM_SW_PORT_DISABLE 0x20 /* disable port */ -#define ADM_SW_PORT_TOS 0x40 /* TOS first */ -#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */ -#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */ -#define ADM_SW_PORT_PVID_SHIFT 10 -#define ADM_SW_PORT_PVID_BITS 4 - -/* VLAN */ -#define ADM_SW_VLAN_PORT0 0x1 -#define ADM_SW_VLAN_PORT1 0x2 -#define ADM_SW_VLAN_PORT2 0x10 -#define ADM_SW_VLAN_PORT3 0x40 -#define ADM_SW_VLAN_PORT4 0x80 -#define ADM_SW_VLAN_PORT5 0x100 - - -/* GPIO 012 enabled, output mode */ -#define GPIO_ENABLEBITS 0x000700f8 - -/* - define AMAZON GPIO port to ADM6996 EEPROM interface - MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction - MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only - MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only - EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */ - -#define GPIO_MDIO 1 //P1.0 -#define GPIO_MDC 2 //P1.1 -#define GPIO_MDCS 4 //P1.2 - -//joelin #define GPIO_MDIO 0 -//joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */ -//joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */ - - -#define MDIO_INPUT 0x00000001 -#define MDIO_OUTPUT_EN 0x00010000 - - -/* type definitions */ -typedef unsigned char U8; -typedef unsigned short U16; -typedef unsigned int U32; - -typedef struct _REGRW_ -{ - unsigned int addr; - unsigned int value; - unsigned int mode; -}REGRW, *PREGRW; - -//joelin adm6996i -typedef struct _MACENTRY_ -{ - unsigned char mac_addr[6]; - unsigned long fid:4; - unsigned long portmap:6; - union { - unsigned long age_timer:9; - unsigned long info_ctrl:9; - } ctrl; - unsigned long occupy:1; - unsigned long info_type:1; - unsigned long bad:1; - unsigned long result:3;//000:command ok ,001:all entry used,010:Entry Not found ,011:try next entry ,101:command error - - }MACENTRY, *PMACENTRY; -typedef struct _PROTOCOLFILTER_ -{ - int protocol_filter_num;//[0~7] - int ip_p; //Value Compared with Protocol in IP Heade[7:0] - char action:2;//Action for protocol Filter . -//00 = Protocol Portmap is Default Output Ports. -//01 = Protocol Portmap is 6'b0. -//10 = Protocol Portmap is the CPU port if the incoming port -//is not the CPU port. But if the incoming port is the CPU port, then Type Portmap contains Default Output Ports, excluding the CPU port. - }PROTOCOLFILTER, *PPROTOCOLFILTER; - -//joelin adm6996i - -/* Santosh: for IGMP proxy/snooping */ - -//050614:fchang int adm_process_mac_table_request (unsigned int cmd, struct _MACENTRY_ *mac); -//050614:fchang int adm_process_protocol_filter_request (unsigned int cmd, struct _PROTOCOLFILTER_ *filter); - - -/* IOCTL keys */ -#define KEY_IOCTL_ADM_REGRW 0x01 -#define KEY_IOCTL_ADM_SW_REGRW 0x02 -#define KEY_IOCTL_ADM_SW_PORTSTS 0x03 -#define KEY_IOCTL_ADM_SW_INIT 0x04 -//for adm6996i-start -#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD 0x05 -#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL 0x06 -#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT 0x07 -#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE 0x08 -#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD 0x09 -#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL 0x0a -#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET 0x0b - -//adm6996i #define KEY_IOCTL_MAX_KEY 0x05 -#define KEY_IOCTL_MAX_KEY 0x0c -//for adm6996i-end -/* IOCTL MAGIC */ -#define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k') - -/* IOCTL parameters */ -#define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW) -#define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW) -#define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL) -#define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL) - - -//6996i-stat -#define ADM_SW_IOCTL_MACENTRY_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD,MACENTRY) -#define ADM_SW_IOCTL_MACENTRY_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL,MACENTRY) -#define ADM_SW_IOCTL_MACENTRY_GET_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT,MACENTRY) -#define ADM_SW_IOCTL_MACENTRY_GET_MORE _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE,MACENTRY) -#define ADM_SW_IOCTL_FILTER_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD,PROTOCOLFILTER) -#define ADM_SW_IOCTL_FILTER_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL,PROTOCOLFILTER) -#define ADM_SW_IOCTL_FILTER_GET _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET,PROTOCOLFILTER) - -//6996i-end - - -#define REG_READ 0x0 -#define REG_WRITE 0x1 - -/* undefine symbol */ -#define AMAZON_SW_REG(reg) *((volatile U32*)(reg)) -//#define GPIO0_INPUT_MASK 0 -//#define GPIO_conf0_REG 0x12345678 -//#define GPIO_SET_HI -//#define GPIO_SET_LOW - -#endif -/* _ADM_6996_MODULE_H_ */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon.h deleted file mode 100644 index 28af7f59d..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon.h +++ /dev/null @@ -1,1447 +0,0 @@ -#ifndef AMAZON_H -#define AMAZON_H -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - -#define amazon_readl(a) __raw_readl(((u32*)(a))) -#define amazon_writel(a,b) __raw_writel(a, ((u32*)(b))) -#define amazon_writel_masked(a,b,c) __raw_writel((__raw_readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a))) - -unsigned int amazon_get_fpi_hz(void); - -#define IOPORT_RESOURCE_START 0x10000000 -#define IOPORT_RESOURCE_END 0xffffffff -#define IOMEM_RESOURCE_START 0x10000000 -#define IOMEM_RESOURCE_END 0xffffffff - -/* check ADSL link status */ -#define AMAZON_CHECK_LINK - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ - -#define AMAZON_WDT (KSEG1+0x10100900) -/***********************************************************************/ - -/***Reset Request Register***/ -#define AMAZON_RST_REQ ((volatile u32*)(AMAZON_WDT+ 0x0010)) -#define AMAZON_RST_REQ_PLL (1 << 31) -#define AMAZON_RST_REQ_PCI_CORE (1 << 13) -#define AMAZON_RST_REQ_TPE (1 << 12) -#define AMAZON_RST_REQ_AFE (1 << 11) -#define AMAZON_RST_REQ_DMA (1 << 9) -#define AMAZON_RST_REQ_SWITCH (1 << 8) -#define AMAZON_RST_REQ_DFE (1 << 7) -#define AMAZON_RST_REQ_PHY (1 << 5) -#define AMAZON_RST_REQ_PCI (1 << 4) -#define AMAZON_RST_REQ_FPI (1 << 2) -#define AMAZON_RST_REQ_CPU (1 << 1) -#define AMAZON_RST_REQ_HRST (1 << 0) -#define AMAZON_RST_ALL (AMAZON_RST_REQ_PLL \ - |AMAZON_RST_REQ_PCI_CORE \ - |AMAZON_RST_REQ_TPE \ - |AMAZON_RST_REQ_AFE \ - |AMAZON_RST_REQ_DMA \ - |AMAZON_RST_REQ_SWITCH \ - |AMAZON_RST_REQ_DFE \ - |AMAZON_RST_REQ_PHY \ - |AMAZON_RST_REQ_PCI \ - |AMAZON_RST_REQ_FPI \ - |AMAZON_RST_REQ_CPU \ - |AMAZON_RST_REQ_HRST) - -/***Reset Status Register Power On***/ -#define AMAZON_RST_SR ((volatile u32*)(AMAZON_WDT+ 0x0014)) - -/***Watchdog Timer Control Register 0***/ -#define AMAZON_WDT_CON0 ((volatile u32*)(AMAZON_WDT+ 0x0020)) - -/***Watchdog Timer Control Register 1***/ -#define AMAZON_WDT_CON1 ((volatile u32*)(AMAZON_WDT+ 0x0024)) -#define AMAZON_WDT_CON1_WDTDR (1 << 3) -#define AMAZON_WDT_CON1_WDTIR (1 << 2) - -/***Watchdog Timer Status Register***/ -#define AMAZON_WDT_SR ((volatile u32*)(AMAZON_WDT+ 0x0028)) -#define AMAZON_WDT_SR_WDTTIM(value) (((( 1 << 16) - 1) & (value)) << 16) -#define AMAZON_WDT_SR_WDTPR (1 << 5) -#define AMAZON_WDT_SR_WDTTO (1 << 4) -#define AMAZON_WDT_SR_WDTDS (1 << 3) -#define AMAZON_WDT_SR_WDTIS (1 << 2) -#define AMAZON_WDT_SR_WDTOE (1 << 1) -#define AMAZON_WDT_SR_WDTAE (1 << 0) - -/***NMI Status Register***/ -#define AMAZON_WDT_NMISR ((volatile u32*)(AMAZON_WDT+ 0x002C)) -#define AMAZON_WDT_NMISR_NMIWDT (1 << 2) -#define AMAZON_WDT_NMISR_NMIPLL (1 << 1) -#define AMAZON_WDT_NMISR_NMIEXT (1 << 0) - -#define AMAZON_WDT_RST_MON ((volatile u32*)(AMAZON_WDT+ 0x0030)) - -/***********************************************************************/ -/* Module : MCD register address and bits */ -/***********************************************************************/ -#define AMAZON_MCD (KSEG1+0x1F106000) - -/***Manufacturer Identification Register***/ -#define AMAZON_MCD_MANID ((volatile u32*)(AMAZON_MCD+ 0x0024)) -#define AMAZON_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) - -/***Chip Identification Register***/ -#define AMAZON_MCD_CHIPID ((volatile u32*)(AMAZON_MCD+ 0x0028)) -#define AMAZON_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define AMAZON_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define AMAZON_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define AMAZON_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define AMAZON_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) -#define AMAZON_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) - -#define AMAZON_CHIPID_STANDARD 0x00EB -#define AMAZON_CHIPID_YANGTSE 0x00ED - -/***Redesign Tracing Identification Register***/ -#define AMAZON_MCD_RTID ((volatile u32*)(AMAZON_MCD+ 0x002C)) -#define AMAZON_MCD_RTID_LC (1 << 15) -#define AMAZON_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define AMAZON_CGU (KSEG1+0x1F103000) -/***********************************************************************/ - -/***CGU Clock Divider Select Register***/ -#define AMAZON_CGU_DIV (AMAZON_CGU + 0x0000) -/***CGU PLL0 Status Register***/ -#define AMAZON_CGU_PLL0SR (AMAZON_CGU + 0x0004) -/***CGU PLL1 Status Register***/ -#define AMAZON_CGU_PLL1SR (AMAZON_CGU + 0x0008) -/***CGU Interface Clock Control Register***/ -#define AMAZON_CGU_IFCCR (AMAZON_CGU + 0x000c) -/***CGU Oscillator Control Register***/ -#define AMAZON_CGU_OSCCR (AMAZON_CGU + 0x0010) -/***CGU Memory Clock Delay Register***/ -#define AMAZON_CGU_MCDEL (AMAZON_CGU + 0x0014) -/***CGU CPU Clock Reduction Register***/ -#define AMAZON_CGU_CPUCRD (AMAZON_CGU + 0x0018) -/***CGU Test Register**/ -#define AMAZON_CGU_TST (AMAZON_CGU + 0x003c) - -/***********************************************************************/ -/* Module : PMU register address and bits */ -/***********************************************************************/ - -#define AMAZON_PMU AMAZON_CGU -/***********************************************************************/ - - -/***PMU Power Down Control Register***/ -#define AMAZON_PMU_PWDCR ((volatile u32*)(AMAZON_PMU+ 0x001c)) -#define AMAZON_PMU_PWDCR_TPE (1 << 13) -#define AMAZON_PMU_PWDCR_PLL (1 << 12) -#define AMAZON_PMU_PWDCR_XTAL (1 << 11) -#define AMAZON_PMU_PWDCR_EBU (1 << 10) -#define AMAZON_PMU_PWDCR_DFE (1 << 9) -#define AMAZON_PMU_PWDCR_SPI (1 << 8) -#define AMAZON_PMU_PWDCR_UART (1 << 7) -#define AMAZON_PMU_PWDCR_GPT (1 << 6) -#define AMAZON_PMU_PWDCR_DMA (1 << 5) -#define AMAZON_PMU_PWDCR_PCI (1 << 4) -#define AMAZON_PMU_PWDCR_SW (1 << 3) -#define AMAZON_PMU_PWDCR_IOR (1 << 2) -#define AMAZON_PMU_PWDCR_FPI (1 << 1) -#define AMAZON_PMU_PWDCR_EPHY (1 << 0) - -/***PMU Status Register***/ -#define AMAZON_PMU_SR ((volatile u32*)(AMAZON_PMU+ 0x0020)) -#define AMAZON_PMU_SR_TPE (1 << 13) -#define AMAZON_PMU_SR_PLL (1 << 12) -#define AMAZON_PMU_SR_XTAL (1 << 11) -#define AMAZON_PMU_SR_EBU (1 << 10) -#define AMAZON_PMU_SR_DFE (1 << 9) -#define AMAZON_PMU_SR_SPI (1 << 8) -#define AMAZON_PMU_SR_UART (1 << 7) -#define AMAZON_PMU_SR_GPT (1 << 6) -#define AMAZON_PMU_SR_DMA (1 << 5) -#define AMAZON_PMU_SR_PCI (1 << 4) -#define AMAZON_PMU_SR_SW (1 << 3) -#define AMAZON_PMU_SR_IOR (1 << 2) -#define AMAZON_PMU_SR_FPI (1 << 1) -#define AMAZON_PMU_SR_EPHY (1 << 0) - -/***********************************************************************/ -/* Module : BCU register address and bits */ -/***********************************************************************/ - -#define AMAZON_BCU (KSEG1+0x10100000) -/***********************************************************************/ - - -/***BCU Control Register (0010H)***/ -#define AMAZON_BCU_CON ((volatile u32*)(AMAZON_BCU+ 0x0010)) -#define AMAZON_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) -#define AMAZON_BCU_CON_SPE (1 << 19) -#define AMAZON_BCU_CON_PSE (1 << 18) -#define AMAZON_BCU_CON_DBG (1 << 16) -#define AMAZON_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***BCU Error Control Capture Register (0020H)***/ -#define AMAZON_BCU_ECON ((volatile u32*)(AMAZON_BCU+ 0x0020)) -#define AMAZON_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) -#define AMAZON_BCU_ECON_RDN (1 << 23) -#define AMAZON_BCU_ECON_WRN (1 << 22) -#define AMAZON_BCU_ECON_SVM (1 << 21) -#define AMAZON_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) -#define AMAZON_BCU_ECON_ABT (1 << 18) -#define AMAZON_BCU_ECON_RDY (1 << 17) -#define AMAZON_BCU_ECON_TOUT (1 << 16) -#define AMAZON_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) -#define AMAZON_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) - -/***BCU Error Address Capture Register (0024 H)***/ -#define AMAZON_BCU_EADD ((volatile u32*)(AMAZON_BCU+ 0x0024)) -#define AMAZON_BCU_EADD_FPIADR - -/***BCU Error Data Capture Register (0028H)***/ -#define AMAZON_BCU_EDAT ((volatile u32*)(AMAZON_BCU+ 0x0028)) -#define AMAZON_BCU_EDAT_FPIDAT - -/***********************************************************************/ -/* Module : Switch register address and bits */ -/***********************************************************************/ - -#define AMAZON_SWITCH (KSEG1+0x10106000) -/***********************************************************************/ -#define AMAZON_SW_UN_DEST AMAZON_SWITCH+0x00 /*Unknown destination register*/ -#define AMAZON_SW_VLAN_CTRL AMAZON_SWITCH+0x04 /*VLAN control register*/ -#define AMAZON_SW_PS_CTL AMAZON_SWITCH+0x08 /*port status control register*/ -#define AMAZON_SW_COS_CTL AMAZON_SWITCH+0x0c /*Cos control register*/ -#define AMAZON_SW_VLAN_COS AMAZON_SWITCH+0x10 /*VLAN priority cos mapping register*/ -#define AMAZON_SW_DSCP_COS3 AMAZON_SWITCH+0x14 /*DSCP cos mapping register3*/ -#define AMAZON_SW_DSCP_COS2 AMAZON_SWITCH+0x18 /*DSCP cos mapping register2*/ -#define AMAZON_SW_DSCP_COS1 AMAZON_SWITCH+0x1c /*DSCP cos mapping register1*/ -#define AMAZON_SW_DSCP_COS0 AMAZON_SWITCH+0x20 /*DSCP cos mapping register*/ -#define AMAZON_SW_ARL_CTL AMAZON_SWITCH+0x24 /*ARL control register*/ -#define AMAZON_SW_PKT_LEN AMAZON_SWITCH+0x28 /*packet length register*/ -#define AMAZON_SW_CPU_ACTL AMAZON_SWITCH+0x2c /*CPU control register1*/ -#define AMAZON_SW_DATA1 AMAZON_SWITCH+0x30 /*CPU access control register1*/ -#define AMAZON_SW_DATA2 AMAZON_SWITCH+0x34 /*CPU access control register2*/ -#define AMAZON_SW_P2_PCTL AMAZON_SWITCH+0x38 /*Port2 control register*/ -#define AMAZON_SW_P0_TX_CTL AMAZON_SWITCH+0x3c /*port0 TX control register*/ -#define AMAZON_SW_P1_TX_CTL AMAZON_SWITCH+0x40 /*port 1 TX control register*/ -#define AMAZON_SW_P0_WM AMAZON_SWITCH+0x44 /*port 0 watermark control register*/ -#define AMAZON_SW_P1_WM AMAZON_SWITCH+0x48 /*port 1 watermark control register*/ -#define AMAZON_SW_P2_WM AMAZON_SWITCH+0x4c /*port 2 watermark control register*/ -#define AMAZON_SW_GBL_WM AMAZON_SWITCH+0x50 /*Global watermark register*/ -#define AMAZON_SW_PM_CTL AMAZON_SWITCH+0x54 /*PM control register*/ -#define AMAZON_SW_P2_CTL AMAZON_SWITCH+0x58 /*PMAC control register*/ -#define AMAZON_SW_P2_TX_IPG AMAZON_SWITCH+0x5c /*port2 TX IPG control register*/ -#define AMAZON_SW_P2_RX_IPG AMAZON_SWITCH+0x60 /*prot2 RX IPG control register*/ -#define AMAZON_SW_MDIO_ACC AMAZON_SWITCH+0x64 /*MDIO access register*/ -#define AMAZON_SW_EPHY AMAZON_SWITCH+0x68 /*Ethernet PHY register*/ -#define AMAZON_SW_MDIO_CFG AMAZON_SWITCH+0x6c /*MDIO configuration register*/ -#define AMAZON_SW_P0_RCV_DROP_CNT AMAZON_SWITCH+0x70 /*port0 receive drop counter */ -#define AMAZON_SW_P0_RCV_FRAME_ERR_CNT AMAZON_SWITCH+0x74 /*port0 receive frame error conter*/ -#define AMAZON_SW_P0_TX_COLL_CNT AMAZON_SWITCH+0x78 /*port0 transmit collision counter*/ -#define AMAZON_SW_P0_TX_DROP_CNT AMAZON_SWITCH+0x7c /*port1 transmit drop counter*/ -#define AMAZON_SW_P1_RCV_DROP_CNT AMAZON_SWITCH+0x80 /*port1 receive drop counter*/ -#define AMAZON_SW_P1_RCV_FRAME_ERR_CNT AMAZON_SWITCH+0x84 /*port1 receive error counter*/ -#define AMAZON_SW_P1_TX_COLL_CNT AMAZON_SWITCH+0x88 /*port1 transmit collision counter*/ -#define AMAZON_SW_P1_TX_DROP_CNT AMAZON_SWITCH+0x8c /*port1 transmit drop counter*/ - - - -/***********************************************************************/ -/* Module : SSC register address and bits */ -/***********************************************************************/ -#define AMAZON_SSC_BASE_ADD_0 (KSEG1+0x10100800) - -/*165001:henryhsu:20050603:Source add by Bing Tao*/ - -/*configuration/Status Registers in Bus Clock Domain*/ -#define AMAZON_SSC_CLC ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0000)) -#define AMAZON_SSC_ID ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0008)) -#define AMAZON_SSC_CON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0010)) -#define AMAZON_SSC_STATE ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0014)) -#define AMAZON_SSC_WHBSTATE ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0018)) -#define AMAZON_SSC_TB ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0020)) -#define AMAZON_SSC_RB ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0024)) -#define AMAZON_SSC_FSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0038)) - -/*Configuration/Status Registers in Kernel Clock Domain*/ -#define AMAZON_SSC_PISEL ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0004)) -#define AMAZON_SSC_RXFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0030)) -#define AMAZON_SSC_TXFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0034)) -#define AMAZON_SSC_BR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0040)) -#define AMAZON_SSC_BRSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0044)) -#define AMAZON_SSC_SFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0060)) -#define AMAZON_SSC_SFSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0064)) -#define AMAZON_SSC_GPOCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0070)) -#define AMAZON_SSC_GPOSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0074)) -#define AMAZON_SSC_WHBGPOSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0078)) -#define AMAZON_SSC_RXREQ ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0080)) -#define AMAZON_SSC_RXCNT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0084)) - -/*DMA Registers in Bus Clock Domain*/ -#define AMAZON_SSC_DMA_CON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00ec)) - -/*interrupt Node Registers in Bus Clock Domain*/ -#define AMAZON_SSC_IRNEN ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00F4)) -#define AMAZON_SSC_IRNICR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00FC)) -#define AMAZON_SSC_IRNCR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00F8)) - -/*165001*/ - -/***********************************************************************/ - - - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#define AMAZON_EBU (KSEG1+0x10105300) -/***********************************************************************/ - - -/***EBU Clock Control Register***/ -#define AMAZON_EBU_CLC ((volatile u32*)(AMAZON_EBU+ 0x0000)) -#define AMAZON_EBU_CLC_DISS (1 << 1) -#define AMAZON_EBU_CLC_DISR (1 << 0) - -/***EBU Global Control Register***/ -#define AMAZON_EBU_CON ((volatile u32*)(AMAZON_EBU+ 0x0010)) -#define AMAZON_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) -#define AMAZON_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) -#define AMAZON_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) -#define AMAZON_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) -#define AMAZON_EBU_CON_ARBSYNC (1 << 5) -#define AMAZON_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ -#define AMAZON_EBU_ADDSEL0 ((volatile u32*)(AMAZON_EBU+ 0x0020)) -#define AMAZON_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -#define AMAZON_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_EBU_ADDSEL0_MIRRORE (1 << 1) -#define AMAZON_EBU_ADDSEL0_REGEN (1 << 0) - -/***EBU Address Select Register 1***/ -#define AMAZON_EBU_ADDSEL1 ((volatile u32*)(AMAZON_EBU+ 0x0024)) -#define AMAZON_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -#define AMAZON_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_EBU_ADDSEL1_MIRRORE (1 << 1) -#define AMAZON_EBU_ADDSEL1_REGEN (1 << 0) - -/***EBU Address Select Register 2***/ -#define AMAZON_EBU_ADDSEL2 ((volatile u32*)(AMAZON_EBU+ 0x0028)) -#define AMAZON_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -#define AMAZON_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_EBU_ADDSEL2_MIRRORE (1 << 1) -#define AMAZON_EBU_ADDSEL2_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ -#define AMAZON_EBU_BUSCON0 ((volatile u32*)(AMAZON_EBU+ 0x0060)) -#define AMAZON_EBU_BUSCON0_WRDIS (1 << 31) -#define AMAZON_EBU_BUSCON0_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -#define AMAZON_EBU_BUSCON0_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -#define AMAZON_EBU_BUSCON0_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -#define AMAZON_EBU_BUSCON0_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -#define AMAZON_EBU_BUSCON0_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -#define AMAZON_EBU_BUSCON0_WAITINV (1 << 19) -#define AMAZON_EBU_BUSCON0_SETUP (1 << 18) -#define AMAZON_EBU_BUSCON0_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -#define AMAZON_EBU_BUSCON0_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -#define AMAZON_EBU_BUSCON0_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -#define AMAZON_EBU_BUSCON0_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -#define AMAZON_EBU_BUSCON0_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -#define AMAZON_EBU_BUSCON0_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ -#define AMAZON_EBU_BUSCON1 ((volatile u32*)(AMAZON_EBU+ 0x0064)) -#define AMAZON_EBU_BUSCON1_WRDIS (1 << 31) -#define AMAZON_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -#define AMAZON_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -#define AMAZON_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -#define AMAZON_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -#define AMAZON_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -#define AMAZON_EBU_BUSCON1_WAITINV (1 << 19) -#define AMAZON_EBU_BUSCON1_SETUP (1 << 18) -#define AMAZON_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -#define AMAZON_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -#define AMAZON_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -#define AMAZON_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -#define AMAZON_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -#define AMAZON_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define AMAZON_EBU_BUSCON2 ((volatile u32*)(AMAZON_EBU+ 0x0068)) -#define AMAZON_EBU_BUSCON2_WRDIS (1 << 31) -#define AMAZON_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -#define AMAZON_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -#define AMAZON_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -#define AMAZON_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -#define AMAZON_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -#define AMAZON_EBU_BUSCON2_WAITINV (1 << 19) -#define AMAZON_EBU_BUSCON2_SETUP (1 << 18) -#define AMAZON_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -#define AMAZON_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -#define AMAZON_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -#define AMAZON_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -#define AMAZON_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -#define AMAZON_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : SDRAM register address and bits */ -/***********************************************************************/ - -#define AMAZON_SDRAM (KSEG1+0x1F800000) -/***********************************************************************/ - - -/***MC Access Error Cause Register***/ -#define AMAZON_SDRAM_MC_ERRCAUSE ((volatile u32*)(AMAZON_SDRAM+ 0x0010)) -#define AMAZON_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -#define AMAZON_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) -#define AMAZON_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) -#define AMAZON_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***MC Access Error Address Register***/ -#define AMAZON_SDRAM_MC_ERRADDR ((volatile u32*)(AMAZON_SDRAM+ 0x0020)) -#define AMAZON_SDRAM_MC_ERRADDR_ADDR - -/***MC I/O General Purpose Register***/ -#define AMAZON_SDRAM_MC_IOGP ((volatile u32*)(AMAZON_SDRAM+ 0x0100)) -#define AMAZON_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) -#define AMAZON_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) -#define AMAZON_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) -#define AMAZON_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) -#define AMAZON_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) -#define AMAZON_SDRAM_MC_IOGP_CPS (1 << 11) -#define AMAZON_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) -#define AMAZON_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) - -/***MC Self Refresh Register***/ -#define AMAZON_SDRAM_MC_SELFRFSH ((volatile u32*)(AMAZON_SDRAM+ 0x01A0)) -#define AMAZON_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -#define AMAZON_SDRAM_MC_SELFRFSH_PWD (1 << 0) -#define AMAZON_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) - -/***MC Enable Register***/ -#define AMAZON_SDRAM_MC_CTRLENA ((volatile u32*)(AMAZON_SDRAM+ 0x0110)) -#define AMAZON_SDRAM_MC_CTRLENA_ENA (1 << 0) -#define AMAZON_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) - -/***MC Mode Register Setup Code***/ -#define AMAZON_SDRAM_MC_MRSCODE ((volatile u32*)(AMAZON_SDRAM+ 0x0120)) -#define AMAZON_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) -#define AMAZON_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) -#define AMAZON_SDRAM_MC_MRSCODE_WT (1 << 3) -#define AMAZON_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***MC Configuration Data-word Width Register***/ -#define AMAZON_SDRAM_MC_CFGDW ((volatile u32*)(AMAZON_SDRAM+ 0x0130)) -#define AMAZON_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) -#define AMAZON_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) - -/***MC Configuration Physical Bank 0 Register***/ -#define AMAZON_SDRAM_MC_CFGPB0 ((volatile u32*)(AMAZON_SDRAM+ 0x140)) -#define AMAZON_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) -#define AMAZON_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) -#define AMAZON_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) -#define AMAZON_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) - -/***MC Latency Register***/ -#define AMAZON_SDRAM_MC_LATENCY ((volatile u32*)(AMAZON_SDRAM+ 0x0180)) -#define AMAZON_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) -#define AMAZON_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) -#define AMAZON_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) -#define AMAZON_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) -#define AMAZON_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) -#define AMAZON_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) - -/***MC Refresh Cycle Time Register***/ -#define AMAZON_SDRAM_MC_TREFRESH ((volatile u32*)(AMAZON_SDRAM+ 0x0190)) -#define AMAZON_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) -#define AMAZON_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) - -/***********************************************************************/ -/* Module : GPTU register address and bits */ -/***********************************************************************/ - -#define AMAZON_GPTU (KSEG1+0x10100A00) -/***********************************************************************/ - - -/***GPT Clock Control Register***/ -#define AMAZON_GPTU_CLC ((volatile u32*)(AMAZON_GPTU+ 0x0000)) -#define AMAZON_GPTU_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -#define AMAZON_GPTU_CLC_DISS (1 << 1) -#define AMAZON_GPTU_CLC_DISR (1 << 0) - -/***GPT Timer 3 Control Register***/ -#define AMAZON_GPTU_T3CON ((volatile u32*)(AMAZON_GPTU+ 0x0014)) -#define AMAZON_GPTU_T3CON_T3RDIR (1 << 15) -#define AMAZON_GPTU_T3CON_T3CHDIR (1 << 14) -#define AMAZON_GPTU_T3CON_T3EDGE (1 << 13) -#define AMAZON_GPTU_T3CON_BPS1(value) (((( 1 << 2) - 1) & (value)) << 11) -#define AMAZON_GPTU_T3CON_T3OTL (1 << 10) -#define AMAZON_GPTU_T3CON_T3UD (1 << 7) -#define AMAZON_GPTU_T3CON_T3R (1 << 6) -#define AMAZON_GPTU_T3CON_T3M(value) (((( 1 << 3) - 1) & (value)) << 3) -#define AMAZON_GPTU_T3CON_T3I(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write Hardware Modified Timer 3 Control Register -If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define AMAZON_GPTU_WHBT3CON ((volatile u32*)(AMAZON_GPTU+ 0x004C)) -#define AMAZON_GPTU_WHBT3CON_SETT3CHDIR (1 << 15) -#define AMAZON_GPTU_WHBT3CON_CLRT3CHDIR (1 << 14) -#define AMAZON_GPTU_WHBT3CON_SETT3EDGE (1 << 13) -#define AMAZON_GPTU_WHBT3CON_CLRT3EDGE (1 << 12) -#define AMAZON_GPTU_WHBT3CON_SETT3OTL (1 << 11) -#define AMAZON_GPTU_WHBT3CON_CLRT3OTL (1 << 10) - -/***GPT Timer 2 Control Register***/ -#define AMAZON_GPTU_T2CON ((volatile u32*)(AMAZON_GPTU+ 0x0010)) -#define AMAZON_GPTU_T2CON_TxRDIR (1 << 15) -#define AMAZON_GPTU_T2CON_TxCHDIR (1 << 14) -#define AMAZON_GPTU_T2CON_TxEDGE (1 << 13) -#define AMAZON_GPTU_T2CON_TxIRDIS (1 << 12) -#define AMAZON_GPTU_T2CON_TxRC (1 << 9) -#define AMAZON_GPTU_T2CON_TxUD (1 << 7) -#define AMAZON_GPTU_T2CON_TxR (1 << 6) -#define AMAZON_GPTU_T2CON_TxM(value) (((( 1 << 3) - 1) & (value)) << 3) -#define AMAZON_GPTU_T2CON_TxI(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Timer 4 Control Register***/ -#define AMAZON_GPTU_T4CON ((volatile u32*)(AMAZON_GPTU+ 0x0018)) -#define AMAZON_GPTU_T4CON_TxRDIR (1 << 15) -#define AMAZON_GPTU_T4CON_TxCHDIR (1 << 14) -#define AMAZON_GPTU_T4CON_TxEDGE (1 << 13) -#define AMAZON_GPTU_T4CON_TxIRDIS (1 << 12) -#define AMAZON_GPTU_T4CON_TxRC (1 << 9) -#define AMAZON_GPTU_T4CON_TxUD (1 << 7) -#define AMAZON_GPTU_T4CON_TxR (1 << 6) -#define AMAZON_GPTU_T4CON_TxM(value) (((( 1 << 3) - 1) & (value)) << 3) -#define AMAZON_GPTU_T4CON_TxI(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 2 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define AMAZON_GPTU_WHBT2CON ((volatile u32*)(AMAZON_GPTU+ 0x0048)) -#define AMAZON_GPTU_WHBT2CON_SETTxCHDIR (1 << 15) -#define AMAZON_GPTU_WHBT2CON_CLRTxCHDIR (1 << 14) -#define AMAZON_GPTU_WHBT2CON_SETTxEDGE (1 << 13) -#define AMAZON_GPTU_WHBT2CON_CLRTxEDGE (1 << 12) - -/***GPT Write HW Modified Timer 4 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define AMAZON_GPTU_WHBT4CON ((volatile u32*)(AMAZON_GPTU+ 0x0050)) -#define AMAZON_GPTU_WHBT4CON_SETTxCHDIR (1 << 15) -#define AMAZON_GPTU_WHBT4CON_CLRTxCHDIR (1 << 14) -#define AMAZON_GPTU_WHBT4CON_SETTxEDGE (1 << 13) -#define AMAZON_GPTU_WHBT4CON_CLRTxEDGE (1 << 12) - -/***GPT Capture Reload Register***/ -#define AMAZON_GPTU_CAPREL ((volatile u32*)(AMAZON_GPTU+ 0x0030)) -#define AMAZON_GPTU_CAPREL_CAPREL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 2 Register***/ -#define AMAZON_GPTU_T2 ((volatile u32*)(AMAZON_GPTU+ 0x0034)) -#define AMAZON_GPTU_T2_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 3 Register***/ -#define AMAZON_GPTU_T3 ((volatile u32*)(AMAZON_GPTU+ 0x0038)) -#define AMAZON_GPTU_T3_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 4 Register***/ -#define AMAZON_GPTU_T4 ((volatile u32*)(AMAZON_GPTU+ 0x003C)) -#define AMAZON_GPTU_T4_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 5 Register***/ -#define AMAZON_GPTU_T5 ((volatile u32*)(AMAZON_GPTU+ 0x0040)) -#define AMAZON_GPTU_T5_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Register***/ -#define AMAZON_GPTU_T6 ((volatile u32*)(AMAZON_GPTU+ 0x0044)) -#define AMAZON_GPTU_T6_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Control Register***/ -#define AMAZON_GPTU_T6CON ((volatile u32*)(AMAZON_GPTU+ 0x0020)) -#define AMAZON_GPTU_T6CON_T6SR (1 << 15) -#define AMAZON_GPTU_T6CON_T6CLR (1 << 14) -#define AMAZON_GPTU_T6CON_BPS2(value) (((( 1 << 2) - 1) & (value)) << 11) -#define AMAZON_GPTU_T6CON_T6OTL (1 << 10) -#define AMAZON_GPTU_T6CON_T6UD (1 << 7) -#define AMAZON_GPTU_T6CON_T6R (1 << 6) -#define AMAZON_GPTU_T6CON_T6M(value) (((( 1 << 3) - 1) & (value)) << 3) -#define AMAZON_GPTU_T6CON_T6I(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 6 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define AMAZON_GPTU_WHBT6CON ((volatile u32*)(AMAZON_GPTU+ 0x0054)) -#define AMAZON_GPTU_WHBT6CON_SETT6OTL (1 << 11) -#define AMAZON_GPTU_WHBT6CON_CLRT6OTL (1 << 10) - -/***GPT Timer 5 Control Register***/ -#define AMAZON_GPTU_T5CON ((volatile u32*)(AMAZON_GPTU+ 0x001C)) -#define AMAZON_GPTU_T5CON_T5SC (1 << 15) -#define AMAZON_GPTU_T5CON_T5CLR (1 << 14) -#define AMAZON_GPTU_T5CON_CI(value) (((( 1 << 2) - 1) & (value)) << 12) -#define AMAZON_GPTU_T5CON_T5CC (1 << 11) -#define AMAZON_GPTU_T5CON_CT3 (1 << 10) -#define AMAZON_GPTU_T5CON_T5RC (1 << 9) -#define AMAZON_GPTU_T5CON_T5UDE (1 << 8) -#define AMAZON_GPTU_T5CON_T5UD (1 << 7) -#define AMAZON_GPTU_T5CON_T5R (1 << 6) -#define AMAZON_GPTU_T5CON_T5M(value) (((( 1 << 3) - 1) & (value)) << 3) -#define AMAZON_GPTU_T5CON_T5I(value) (((( 1 << 3) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : ASC register address and bits */ -/***********************************************************************/ - -#define AMAZON_ASC (KSEG1+0x10100400) -/***********************************************************************/ - - -/***ASC Port Input Select Register***/ -#define AMAZON_ASC_PISEL (AMAZON_ASC+ 0x0004) -#define AMAZON_ASC_PISEL_RIS (1 << 0) - -/***ASC Control Register***/ -#define AMAZON_ASC_CON (AMAZON_ASC+ 0x0010) -#define AMAZON_ASC_CON_R (1 << 15) -#define AMAZON_ASC_CON_LB (1 << 14) -#define AMAZON_ASC_CON_BRS (1 << 13) -#define AMAZON_ASC_CON_ODD (1 << 12) -#define AMAZON_ASC_CON_FDE (1 << 11) -#define AMAZON_ASC_CON_OE (1 << 10) -#define AMAZON_ASC_CON_FE (1 << 9) -#define AMAZON_ASC_CON_PE (1 << 8) -#define AMAZON_ASC_CON_OEN (1 << 7) -#define AMAZON_ASC_CON_FEN (1 << 6) -#define AMAZON_ASC_CON_PENRXDI (1 << 5) -#define AMAZON_ASC_CON_REN (1 << 4) -#define AMAZON_ASC_CON_STP (1 << 3) -#define AMAZON_ASC_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) - -/***ASC Write Hardware Modified Control Register***/ -#define AMAZON_ASC_WHBCON (AMAZON_ASC+ 0x0050) -#define AMAZON_ASC_WHBCON_SETOE (1 << 13) -#define AMAZON_ASC_WHBCON_SETFE (1 << 12) -#define AMAZON_ASC_WHBCON_SETPE (1 << 11) -#define AMAZON_ASC_WHBCON_CLROE (1 << 10) -#define AMAZON_ASC_WHBCON_CLRFE (1 << 9) -#define AMAZON_ASC_WHBCON_CLRPE (1 << 8) -#define AMAZON_ASC_WHBCON_SETREN (1 << 5) -#define AMAZON_ASC_WHBCON_CLRREN (1 << 4) - -/***ASC Baudrate Timer/Reload Register***/ -#define AMAZON_ASC_BTR (AMAZON_ASC+ 0x0014) -#define AMAZON_ASC_BTR_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) - -/***ASC Fractional Divider Register***/ -#define AMAZON_ASC_FDV (AMAZON_ASC+ 0x0018) -#define AMAZON_ASC_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC IrDA Pulse Mode/Width Register***/ -#define AMAZON_ASC_PMW (AMAZON_ASC+ 0x001C) -#define AMAZON_ASC_PMW_IRPW (1 << 8) -#define AMAZON_ASC_PMW_PW_VALUE(value) (((( 1 << 8) - 1) & (value)) << 0) - -/***ASC Transmit Buffer Register***/ -#define AMAZON_ASC_TBUF (AMAZON_ASC+ 0x0020) -#define AMAZON_ASC_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Receive Buffer Register***/ -#define AMAZON_ASC_RBUF (AMAZON_ASC+ 0x0024) -#define AMAZON_ASC_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Autobaud Control Register***/ -#define AMAZON_ASC_ABCON (AMAZON_ASC+ 0x0030) -#define AMAZON_ASC_ABCON_RXINV (1 << 11) -#define AMAZON_ASC_ABCON_TXINV (1 << 10) -#define AMAZON_ASC_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) -#define AMAZON_ASC_ABCON_FCDETEN (1 << 4) -#define AMAZON_ASC_ABCON_ABDETEN (1 << 3) -#define AMAZON_ASC_ABCON_ABSTEN (1 << 2) -#define AMAZON_ASC_ABCON_AUREN (1 << 1) -#define AMAZON_ASC_ABCON_ABEN (1 << 0) - -/***Receive FIFO Control Register***/ -#define AMAZON_ASC_RXFCON (AMAZON_ASC+ 0x0040) -#define AMAZON_ASC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define AMAZON_ASC_RXFCON_RXTMEN (1 << 2) -#define AMAZON_ASC_RXFCON_RXFFLU (1 << 1) -#define AMAZON_ASC_RXFCON_RXFEN (1 << 0) - -/***Transmit FIFO Control Register***/ -#define AMAZON_ASC_TXFCON (AMAZON_ASC+ 0x0044) -#define AMAZON_ASC_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define AMAZON_ASC_TXFCON_TXTMEN (1 << 2) -#define AMAZON_ASC_TXFCON_TXFFLU (1 << 1) -#define AMAZON_ASC_TXFCON_TXFEN (1 << 0) - -/***FIFO Status Register***/ -#define AMAZON_ASC_FSTAT (AMAZON_ASC+ 0x0048) -#define AMAZON_ASC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define AMAZON_ASC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) - -/***ASC Write HW Modified Autobaud Control Register***/ -#define AMAZON_ASC_WHBABCON (AMAZON_ASC+ 0x0054) -#define AMAZON_ASC_WHBABCON_SETABEN (1 << 1) -#define AMAZON_ASC_WHBABCON_CLRABEN (1 << 0) - -/***ASC Autobaud Status Register***/ -#define AMAZON_ASC_ABSTAT (AMAZON_ASC+ 0x0034) -#define AMAZON_ASC_ABSTAT_DETWAIT (1 << 4) -#define AMAZON_ASC_ABSTAT_SCCDET (1 << 3) -#define AMAZON_ASC_ABSTAT_SCSDET (1 << 2) -#define AMAZON_ASC_ABSTAT_FCCDET (1 << 1) -#define AMAZON_ASC_ABSTAT_FCSDET (1 << 0) - -/***ASC Write HW Modified Autobaud Status Register***/ -#define AMAZON_ASC_WHBABSTAT (AMAZON_ASC+ 0x0058) -#define AMAZON_ASC_WHBABSTAT_SETDETWAIT (1 << 9) -#define AMAZON_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) -#define AMAZON_ASC_WHBABSTAT_SETSCCDET (1 << 7) -#define AMAZON_ASC_WHBABSTAT_CLRSCCDET (1 << 6) -#define AMAZON_ASC_WHBABSTAT_SETSCSDET (1 << 5) -#define AMAZON_ASC_WHBABSTAT_CLRSCSDET (1 << 4) -#define AMAZON_ASC_WHBABSTAT_SETFCCDET (1 << 3) -#define AMAZON_ASC_WHBABSTAT_CLRFCCDET (1 << 2) -#define AMAZON_ASC_WHBABSTAT_SETFCSDET (1 << 1) -#define AMAZON_ASC_WHBABSTAT_CLRFCSDET (1 << 0) - -/***ASC Clock Control Register***/ -#define AMAZON_ASC_CLC (AMAZON_ASC+ 0x0000) -#define AMAZON_ASC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -#define AMAZON_ASC_CLC_DISS (1 << 1) -#define AMAZON_ASC_CLC_DISR (1 << 0) - -/***ASC IRNCR0 **/ -#define AMAZON_ASC_IRNCR0 (AMAZON_ASC+ 0x00FC) -/***ASC IRNCR1 **/ -#define AMAZON_ASC_IRNCR1 (AMAZON_ASC+ 0x00F8) -#define ASC_IRNCR_TIR 0x1 -#define ASC_IRNCR_RIR 0x2 -#define ASC_IRNCR_EIR 0x4 -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define AMAZON_DMA (KSEG1+0x10103000) -/***********************************************************************/ -#define AMAZON_DMA_CH_ON AMAZON_DMA+0x28 -#define AMAZON_DMA_CH_RST AMAZON_DMA+0x2c -#define AMAZON_DMA_CH0_ISR AMAZON_DMA+0x30 -#define AMAZON_DMA_CH1_ISR AMAZON_DMA+0x34 -#define AMAZON_DMA_CH2_ISR AMAZON_DMA+0x38 -#define AMAZON_DMA_CH3_ISR AMAZON_DMA+0x3c -#define AMAZON_DMA_CH4_ISR AMAZON_DMA+0x40 -#define AMAZON_DMA_CH5_ISR AMAZON_DMA+0x44 -#define AMAZON_DMA_CH6_ISR AMAZON_DMA+0x48 -#define AMAZON_DMA_CH7_ISR AMAZON_DMA+0x4c -#define AMAZON_DMA_CH8_ISR AMAZON_DMA+0x50 -#define AMAZON_DMA_CH9_ISR AMAZON_DMA+0x54 -#define AMAZON_DMA_CH10_ISR AMAZON_DMA+0x58 -#define AMAZON_DMA_CH11_ISR AMAZON_DMA+0x5c -#define AMAZON_DMA_CH0_MSK AMAZON_DMA+0x60 -#define AMAZON_DMA_CH1_MSK AMAZON_DMA+0x64 -#define AMAZON_DMA_CH2_MSK AMAZON_DMA+0x68 -#define AMAZON_DMA_CH3_MSK AMAZON_DMA+0x6c -#define AMAZON_DMA_CH4_MSK AMAZON_DMA+0x70 -#define AMAZON_DMA_CH5_MSK AMAZON_DMA+0x74 -#define AMAZON_DMA_CH6_MSK AMAZON_DMA+0x78 -#define AMAZON_DMA_CH7_MSK AMAZON_DMA+0x7c -#define AMAZON_DMA_CH8_MSK AMAZON_DMA+0x80 -#define AMAZON_DMA_CH9_MSK AMAZON_DMA+0x84 -#define AMAZON_DMA_CH10_MSK AMAZON_DMA+0x88 -#define AMAZON_DMA_CH11_MSK AMAZON_DMA+0x8c -#define AMAZON_DMA_Desc_BA AMAZON_DMA+0x90 -#define AMAZON_DMA_CH0_DES_LEN AMAZON_DMA+0x94 -#define AMAZON_DMA_CH1_DES_LEN AMAZON_DMA+0x98 -#define AMAZON_DMA_CH2_DES_LEN AMAZON_DMA+0x9c -#define AMAZON_DMA_CH3_DES_LEN AMAZON_DMA+0xa0 -#define AMAZON_DMA_CH4_DES_LEN AMAZON_DMA+0xa4 -#define AMAZON_DMA_CH5_DES_LEN AMAZON_DMA+0xa8 -#define AMAZON_DMA_CH6_DES_LEN AMAZON_DMA+0xac -#define AMAZON_DMA_CH7_DES_LEN AMAZON_DMA+0xb0 -#define AMAZON_DMA_CH8_DES_LEN AMAZON_DMA+0xb4 -#define AMAZON_DMA_CH9_DES_LEN AMAZON_DMA+0xb8 -#define AMAZON_DMA_CH10_DES_LEN AMAZON_DMA+0xbc -#define AMAZON_DMA_CH11_DES_LEN AMAZON_DMA+0xc0 -#define AMAZON_DMA_CH1_DES_OFST AMAZON_DMA+0xc4 -#define AMAZON_DMA_CH2_DES_OFST AMAZON_DMA+0xc8 -#define AMAZON_DMA_CH3_DES_OFST AMAZON_DMA+0xcc -#define AMAZON_DMA_CH4_DES_OFST AMAZON_DMA+0xd0 -#define AMAZON_DMA_CH5_DES_OFST AMAZON_DMA+0xd4 -#define AMAZON_DMA_CH6_DES_OFST AMAZON_DMA+0xd8 -#define AMAZON_DMA_CH7_DES_OFST AMAZON_DMA+0xdc -#define AMAZON_DMA_CH8_DES_OFST AMAZON_DMA+0xe0 -#define AMAZON_DMA_CH9_DES_OFST AMAZON_DMA+0xe4 -#define AMAZON_DMA_CH10_DES_OFST AMAZON_DMA+0xe8 -#define AMAZON_DMA_CH11_DES_OFST AMAZON_DMA+0xec -#define AMAZON_DMA_SW_BL AMAZON_DMA+0xf0 -#define AMAZON_DMA_TPE_BL AMAZON_DMA+0xf4 -#define AMAZON_DMA_DPlus2FPI_BL AMAZON_DMA+0xf8 -#define AMAZON_DMA_GRX_BUF_LEN AMAZON_DMA+0xfc -#define AMAZON_DMA_DMA_ECON_REG AMAZON_DMA+0x100 -#define AMAZON_DMA_POLLING_REG AMAZON_DMA+0x104 -#define AMAZON_DMA_CH_WGT AMAZON_DMA+0x108 -#define AMAZON_DMA_TX_WGT AMAZON_DMA+0x10c -#define AMAZON_DMA_DPLus2FPI_CLASS AMAZON_DMA+0x110 -#define AMAZON_DMA_COMB_ISR AMAZON_DMA+0x114 - -//channel reset -#define SWITCH1_RST_MASK 0x83 /* Switch1 channel mask */ -#define SWITCH2_RST_MASK 0x10C /* Switch1 channel mask */ -#define TPE_RST_MASK 0x630 /* TPE channel mask */ -#define DPlus2FPI_RST_MASK 0x840 /* DPlusFPI channel mask */ - -//ISR -#define DMA_ISR_RDERR 0x20 -#define DMA_ISR_CMDCPT 0x10 -#define DMA_ISR_CPT 0x8 -#define DMA_ISR_DURR 0x4 -#define DMA_ISR_EOP 0x2 -#define DMA_DESC_BYTEOFF_SHIFT 23 - -#define DMA_POLLING_ENABLE 0x80000000 -#define DMA_POLLING_CNT 0x50 /*minimum 0x10, max 0xfff0*/ - -/***********************************************************************/ -/* Module : Debug register address and bits */ -/***********************************************************************/ - -#define AMAZON_DEBUG (KSEG1+0x1F106000) -/***********************************************************************/ - - -/***MCD Break System Control Register***/ -#define AMAZON_DEBUG_MCD_BSCR ((volatile u32*)(AMAZON_DEBUG+ 0x0000)) - -/***PMC Performance Counter Control Register0***/ -#define AMAZON_DEBUG_PMC_PCCR0 ((volatile u32*)(AMAZON_DEBUG+ 0x0010)) - -/***PMC Performance Counter Control Register1***/ -#define AMAZON_DEBUG_PMC_PCCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x0014)) - -/***PMC Performance Counter Register0***/ -#define AMAZON_DEBUG_PMC_PCR0 ((volatile u32*)(AMAZON_DEBUG+ 0x0018)) - -/*165001:henryhsu:20050603:Source modified by Bing Tao*/ - -/***PMC Performance Counter Register1***/ -//#define AMAZON_DEBUG_PMC_PCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x0020)) -#define AMAZON_DEBUG_PMC_PCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x001c)) - -/*165001*/ - - - -/***MCD Suspend Mode Control Register***/ -#define AMAZON_DEBUG_MCD_SMCR ((volatile u32*)(AMAZON_DEBUG+ 0x0024)) - -/***********************************************************************/ -/* Module : GPIO register address and bits */ -/***********************************************************************/ - -#define AMAZON_GPIO (KSEG1+0x10100B00) -/***********************************************************************/ - - -/***Port 0 Data Output Register (0010H)***/ -#define AMAZON_GPIO_P0_OUT ((volatile u32*)(AMAZON_GPIO+ 0x0010)) - -/***Port 1 Data Output Register (0040H)***/ -#define AMAZON_GPIO_P1_OUT ((volatile u32*)(AMAZON_GPIO+ 0x0040)) - -/***Port 0 Data Input Register (0014H)***/ -#define AMAZON_GPIO_P0_IN ((volatile u32*)(AMAZON_GPIO+ 0x0014)) - -/***Port 1 Data Input Register (0044H)***/ -#define AMAZON_GPIO_P1_IN ((volatile u32*)(AMAZON_GPIO+ 0x0044)) - -/***Port 0 Direction Register (0018H)***/ -#define AMAZON_GPIO_P0_DIR ((volatile u32*)(AMAZON_GPIO+ 0x0018)) - -/***Port 1 Direction Register (0048H)***/ -#define AMAZON_GPIO_P1_DIR ((volatile u32*)(AMAZON_GPIO+ 0x0048)) - -/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -#define AMAZON_GPIO_P0_ALTSEL0 ((volatile u32*)(AMAZON_GPIO+ 0x001C)) - -/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -#define AMAZON_GPIO_P1_ALTSEL0 ((volatile u32*)(AMAZON_GPIO+ 0x004C)) - -/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -#define AMAZON_GPIO_P0_ALTSEL1 ((volatile u32*)(AMAZON_GPIO+ 0x0020)) - -/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -#define AMAZON_GPIO_P1_ALTSEL1 ((volatile u32*)(AMAZON_GPIO+ 0x0050)) - -/***Port 0 Open Drain Control Register (0024H)***/ -#define AMAZON_GPIO_P0_OD ((volatile u32*)(AMAZON_GPIO+ 0x0024)) - -/***Port 1 Open Drain Control Register (0054H)***/ -#define AMAZON_GPIO_P1_OD ((volatile u32*)(AMAZON_GPIO+ 0x0054)) - -/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -#define AMAZON_GPIO_P0_STOFF ((volatile u32*)(AMAZON_GPIO+ 0x0028)) - -/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -#define AMAZON_GPIO_P1_STOFF ((volatile u32*)(AMAZON_GPIO+ 0x0058)) - -/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -#define AMAZON_GPIO_P0_PUDSEL ((volatile u32*)(AMAZON_GPIO+ 0x002C)) - -/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -#define AMAZON_GPIO_P1_PUDSEL ((volatile u32*)(AMAZON_GPIO+ 0x005C)) - -/***Port 0 Pull Up Device Enable Register (0030 H)***/ -#define AMAZON_GPIO_P0_PUDEN ((volatile u32*)(AMAZON_GPIO+ 0x0030)) - -/***Port 1 Pull Up Device Enable Register (0060 H)***/ -#define AMAZON_GPIO_P1_PUDEN ((volatile u32*)(AMAZON_GPIO+ 0x0060)) - -/***********************************************************************/ -/* Module : BIU register address and bits */ -/***********************************************************************/ - -#define AMAZON_BIU (KSEG1+0x1FA80000) -/***********************************************************************/ - - -/***BIU Identification Register***/ -#define AMAZON_BIU_ID ((volatile u32*)(AMAZON_BIU+ 0x0000)) -#define AMAZON_BIU_ID_ARCH (1 << 16) -#define AMAZON_BIU_ID_ID(value) (((( 1 << 8) - 1) & (value)) << 8) -#define AMAZON_BIU_ID_REV(value) (((( 1 << 8) - 1) & (value)) << 0) - -/***BIU Access Error Cause Register***/ -#define AMAZON_BIU_ERRCAUSE ((volatile u32*)(AMAZON_BIU+ 0x0100)) -#define AMAZON_BIU_ERRCAUSE_ERR (1 << 31) -#define AMAZON_BIU_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) -#define AMAZON_BIU_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) - -/***BIU Access Error Address Register***/ -#define AMAZON_BIU_ERRADDR ((volatile u32*)(AMAZON_BIU+ 0x0108)) -#define AMAZON_BIU_ERRADDR_ADDR - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define AMAZON_ICU (KSEG1+0x1F101000) -/***********************************************************************/ - -/***IM0 Interrupt Status Register***/ -#define AMAZON_ICU_IM0_ISR (AMAZON_ICU + 0x0010) -#define AMAZON_ICU_IM1_ISR (AMAZON_ICU + 0x0020) -#define AMAZON_ICU_IM2_ISR (AMAZON_ICU + 0x0030) -#define AMAZON_ICU_IM3_ISR (AMAZON_ICU + 0x0040) -#define AMAZON_ICU_IM4_ISR (AMAZON_ICU + 0x0050) - -/***IM0 Interrupt Enable Register***/ -#define AMAZON_ICU_IM0_IER (AMAZON_ICU + 0x0014) -#define AMAZON_ICU_IM1_IER (AMAZON_ICU + 0x0024) -#define AMAZON_ICU_IM2_IER (AMAZON_ICU + 0x0034) -#define AMAZON_ICU_IM3_IER (AMAZON_ICU + 0x0044) -#define AMAZON_ICU_IM4_IER (AMAZON_ICU + 0x0054) - -/***IM0 Interrupt Output Status Register***/ -#define AMAZON_ICU_IM0_IOSR (AMAZON_ICU + 0x0018) -#define AMAZON_ICU_IM1_IOSR (AMAZON_ICU + 0x0028) -#define AMAZON_ICU_IM2_IOSR (AMAZON_ICU + 0x0038) -#define AMAZON_ICU_IM3_IOSR (AMAZON_ICU + 0x0048) -#define AMAZON_ICU_IM4_IOSR (AMAZON_ICU + 0x0058) - -/***IM0 Interrupt Request Set Register***/ -#define AMAZON_ICU_IM0_IRSR (AMAZON_ICU + 0x001c) -#define AMAZON_ICU_IM1_IRSR (AMAZON_ICU + 0x002c) -#define AMAZON_ICU_IM2_IRSR (AMAZON_ICU + 0x003c) -#define AMAZON_ICU_IM3_IRSR (AMAZON_ICU + 0x004c) -#define AMAZON_ICU_IM4_IRSR (AMAZON_ICU + 0x005c) - -/***Interrupt Vector Value Register***/ -#define AMAZON_ICU_IM_VEC (AMAZON_ICU + 0x0060) - -/***Interrupt Vector Value Mask***/ -#define AMAZON_ICU_IM0_VEC_MASK 0x0000001f -#define AMAZON_ICU_IM1_VEC_MASK 0x000003e0 -#define AMAZON_ICU_IM2_VEC_MASK 0x00007c00 -#define AMAZON_ICU_IM3_VEC_MASK 0x000f8000 -#define AMAZON_ICU_IM4_VEC_MASK 0x01f00000 - -/***DMA Interrupt Mask Value***/ -#define AMAZON_DMA_H_MASK 0x00000fff - -/***External Interrupt Control Register***/ -#define AMAZON_ICU_EXTINTCR ((volatile u32*)(AMAZON_ICU + 0x0000)) -#define AMAZON_ICU_IRNICR ((volatile u32*)(AMAZON_ICU + 0x0004)) -#define AMAZON_ICU_IRNCR ((volatile u32*)(AMAZON_ICU + 0x0008)) -#define AMAZON_ICU_IRNEN ((volatile u32*)(AMAZON_ICU + 0x000c)) - -/***********************************************************************/ -/* Module : PCI/Card-BUS/PC-Card register address and bits */ -/***********************************************************************/ - -#define AMAZON_PCI (KSEG1+0x10105400) -#define AMAZON_PCI_CFG_BASE (KSEG1+0x11000000) -#define AMAZON_PCI_MEM_BASE (KSEG1+0x12000000) - -#define CLOCK_CONTROL AMAZON_PCI + 0x00000000 -#define ARB_CTRL_bit 1 -#define IDENTIFICATION AMAZON_PCI + 0x00000004 -#define SOFTRESET AMAZON_PCI + 0x00000010 -#define PCI_FPI_ERROR_ADDRESS AMAZON_PCI + 0x00000014 -#define FPI_PCI_ERROR_ADDRESS AMAZON_PCI + 0x00000018 -#define FPI_ERROR_TAG AMAZON_PCI + 0x0000001c -#define IRR AMAZON_PCI + 0x00000020 -#define IRA_IR AMAZON_PCI + 0x00000024 -#define IRM AMAZON_PCI + 0x00000028 -#define DMA_COMPLETE_BIT 0 -#define PCI_POWER_CHANGE_BIT 16 -#define PCI_MASTER0_BROKEN_INT_BIT 24 -#define PCI_MASTER1_BROKEN_INT_BIT 25 -#define PCI_MASTER2_BROKEN_INT_BIT 26 -#define EOI AMAZON_PCI + 0x0000002c -#define PCI_MODE AMAZON_PCI + 0x00000030 -#define PCI_MODE_cfgok_bit 24 -#define DEVICE_VENDOR_ID AMAZON_PCI + 0x00000034 -#define SUBSYSTEM_VENDOR_ID AMAZON_PCI + 0x00000038 -#define POWER_MANAGEMENT AMAZON_PCI + 0x0000003c -#define CLASS_CODE1 AMAZON_PCI + 0x00000040 -#define BAR11_MASK AMAZON_PCI + 0x00000044 -#define BAR12_MASK AMAZON_PCI + 0x00000048 -#define BAR13_MASK AMAZON_PCI + 0x0000004c -#define BAR14_MASK AMAZON_PCI + 0x00000050 -#define BAR15_MASK AMAZON_PCI + 0x00000054 -#define BAR16_MASK AMAZON_PCI + 0x00000058 -#define CARDBUS_CIS_POINTER1 AMAZON_PCI + 0x0000005c -#define SUBSYSTEM_ID1 AMAZON_PCI + 0x00000060 -#define PCI_ADDRESS_MAP_11 AMAZON_PCI + 0x00000064 -#define PCI_ADDRESS_MAP_12 AMAZON_PCI + 0x00000068 -#define PCI_ADDRESS_MAP_13 AMAZON_PCI + 0x0000006c -#define PCI_ADDRESS_MAP_14 AMAZON_PCI + 0x00000070 -#define PCI_ADDRESS_MAP_15 AMAZON_PCI + 0x00000074 -#define PCI_ADDRESS_MAP_16 AMAZON_PCI + 0x00000078 -#define FPI_SEGMENT_ENABLE AMAZON_PCI + 0x0000007c -#define CLASS_CODE2 AMAZON_PCI + 0x00000080 -#define BAR21_MASK AMAZON_PCI + 0x00000084 -#define BAR22_MASK AMAZON_PCI + 0x00000088 -#define BAR23_MASK AMAZON_PCI + 0x0000008c -#define BAR24_MASK AMAZON_PCI + 0x00000090 -#define BAR25_MASK AMAZON_PCI + 0x00000094 -#define BAR26_MASK AMAZON_PCI + 0x00000098 -#define CARDBUS_CIS_POINTER2 AMAZON_PCI + 0x0000009c -#define SUBSYSTEM_ID2 AMAZON_PCI + 0x000000a0 -#define PCI_ADDRESS_MAP_21 AMAZON_PCI + 0x000000a4 -#define PCI_ADDRESS_MAP_22 AMAZON_PCI + 0x000000a8 -#define PCI_ADDRESS_MAP_23 AMAZON_PCI + 0x000000ac -#define PCI_ADDRESS_MAP_24 AMAZON_PCI + 0x000000b0 -#define PCI_ADDRESS_MAP_25 AMAZON_PCI + 0x000000b4 -#define PCI_ADDRESS_MAP_26 AMAZON_PCI + 0x000000b8 -#define FPI_ADDRESS_MASK11LOW AMAZON_PCI + 0x000000bc -#define FPI_ADDRESS_MAP_0 AMAZON_PCI + 0x000000c0 -#define FPI_ADDRESS_MAP_1 AMAZON_PCI + 0x000000c4 -#define FPI_ADDRESS_MAP_2 AMAZON_PCI + 0x000000c8 -#define FPI_ADDRESS_MAP_3 AMAZON_PCI + 0x000000cc -#define FPI_ADDRESS_MAP_4 AMAZON_PCI + 0x000000d0 -#define FPI_ADDRESS_MAP_5 AMAZON_PCI + 0x000000d4 -#define FPI_ADDRESS_MAP_6 AMAZON_PCI + 0x000000d8 -#define FPI_ADDRESS_MAP_7 AMAZON_PCI + 0x000000dc -#define FPI_ADDRESS_MAP_11LOW AMAZON_PCI + 0x000000e0 -#define FPI_ADDRESS_MAP_11HIGH AMAZON_PCI + 0x000000e4 -#define FPI_BURST_LENGTH AMAZON_PCI + 0x000000e8 -#define SET_PCI_SERR AMAZON_PCI + 0x000000ec -#define DMA_FPI_START_ADDR AMAZON_PCI + 0x000000f0 -#define DMA_PCI_START_ADDR AMAZON_PCI + 0x000000f4 -#define DMA_TRANSFER_COUNT AMAZON_PCI + 0x000000f8 -#define DMA_CONTROL_STATUS AMAZON_PCI + 0x000000fc - -#define EXT_PCI1_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x0800 -#define EXT_PCI2_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x1000 -#define EXT_PCI3_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x1800 -#define EXT_PCI4_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x2000 -#define EXT_PCI5_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x2800 -#define EXT_PCI6_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x3000 -#define EXT_PCI7_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x3800 -#define EXT_PCI8_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x4000 -#define EXT_PCI9_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x4800 -#define EXT_PCI10_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x5000 -#define EXT_PCI11_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x5800 -#define EXT_PCI12_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x6000 -#define EXT_PCI13_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x6800 -#define EXT_PCI14_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x7000 -#define EXT_PCI15_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x7800 -#define EXT_CARDBUS_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0XF000 -#define EXT_PCI_BAR1_ADDR 0x10 -#define EXT_PCI_BAR2_ADDR 0x14 -#define EXT_PCI_BAR3_ADDR 0x18 -#define EXT_PCI_BAR4_ADDR 0x1C -#define EXT_PCI_BAR5_ADDR 0x20 -#define EXT_PCI_BAR6_ADDR 0x24 - -#define DEVICE_ID_VECDOR_ID_ADDR AMAZON_PCI_CFG_BASE + 0x0 -#define STATUS_COMMAND_ADDR AMAZON_PCI_CFG_BASE + 0x4 -#define BUS_MASTER_ENABLE_BIT 2 -#define MEM_SPACE_ENABLE_BIT 1 -#define CLASS_CODE_REVISION_ADDR AMAZON_PCI_CFG_BASE + 0x8 -#define BIST_HEADER_TYPE_LATENCY_CAHCE_ADDR AMAZON_PCI_CFG_BASE + 0xC -#define BAR1_ADDR AMAZON_PCI_CFG_BASE + 0x10 -#define BAR2_ADDR AMAZON_PCI_CFG_BASE + 0x14 -#define BAR3_ADDR AMAZON_PCI_CFG_BASE + 0x18 -#define BAR4_ADDR AMAZON_PCI_CFG_BASE + 0x1C -#define BAR3_ADDR AMAZON_PCI_CFG_BASE + 0x18 -#define BAR4_ADDR AMAZON_PCI_CFG_BASE + 0x1C -#define BAR5_ADDR AMAZON_PCI_CFG_BASE + 0x20 -#define BAR6_ADDR AMAZON_PCI_CFG_BASE + 0x24 -#define CARDBUS_CIS_POINTER_ADDR AMAZON_PCI_CFG_BASE + 0x28 -#define SUBSYSTEM_ID_VENDOR_ID_ADDR AMAZON_PCI_CFG_BASE + 0x2C -#define EXPANSION_ROM_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x30 -#define CAPABILITIES_POINTER_ADDR AMAZON_PCI_CFG_BASE + 0x34 -#define RESERVED_0x38 AMAZON_PCI_CFG_BASE + 0x38 -#define MAX_LAT_MIN_GNT_INT_PIN_LINE_ADDR AMAZON_PCI_CFG_BASE + 0x3C -#define POWER_MNGT_NEXT_POINTER_CAP_ID_ADDR AMAZON_PCI_CFG_BASE + 0x40 -#define POWER_MANAGEMENT_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x44 -#define RESERVED_0x48 AMAZON_PCI_CFG_BASE + 0x48 -#define RESERVED_0x4C AMAZON_PCI_CFG_BASE + 0x4C -#define ERROR_ADDR_PCI_FPI_ADDR AMAZON_PCI_CFG_BASE + 0x50 -#define ERROR_ADdR_FPI_PCI_ADDR AMAZON_PCI_CFG_BASE + 0x54 -#define ERROR_TAG_FPI_PCI_ADDR AMAZON_PCI_CFG_BASE + 0x58 -#define PCI_ARB_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x5C -#define INTERNAL_ARB_ENABLE_BIT 0 -#define ARB_SCHEME_BIT 1 -#define PCI_MASTER0_PRIOR_2BITS 2 -#define PCI_MASTER1_PRIOR_2BITS 4 -#define PCI_MASTER2_PRIOR_2BITS 6 -#define PCI_MASTER0_REQ_MASK_2BITS 8 -#define PCI_MASTER1_REQ_MASK_2BITS 10 -#define PCI_MASTER2_REQ_MASK_2BITS 12 -#define PCI_MASTER0_GNT_MASK_2BITS 14 -#define PCI_MASTER1_GNT_MASK_2BITS 16 -#define PCI_MASTER2_GNT_MASK_2BITS 18 -#define FPI_PCI_INT_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x60 -#define FPI_PCI_INT_ACK_ADDR AMAZON_PCI_CFG_BASE + 0x64 -#define FPI_PCI_INT_MASK_ADDR AMAZON_PCI_CFG_BASE + 0x68 -#define CARDBUS_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x6C -#define CARDBUS_CFRAME_ENABLE 0 - -#define CLOCK_CONTROL_default 0x00000000 -#define CLOCK_CONTROL_mask 0x00000003 - -#define IDENTIFICATION_default 0x0011C002 -#define IDENTIFICATION_mask 0x00000000 - -#define SOFTRESET_default 0x00000000 -// SOFTRESET bit 0 is writable but will be reset to 0 after software reset is over -#define SOFTRESET_mask 0x00000000 - -#define PCI_FPI_ERROR_ADDRESS_default 0xFFFFFFFF -#define PCI_FPI_ERROR_ADDRESS_mask 0x00000000 - -#define FPI_PCI_ERROR_ADDRESS_default 0xFFFFFFFF -#define FPI_PCI_ERROR_ADDRESS_mask 0x00000000 - -#define FPI_ERROR_TAG_default 0x0000000F -#define FPI_ERROR_TAG_mask 0x00000000 - -#define IRR_default 0x00000000 -#define IRR_mask 0x07013b2F - -#define IRA_IR_default 0x00000000 -#define IRA_IR_mask 0x07013b2F - -#define IRM_default 0x00000000 -#define IRM_mask 0xFFFFFFFF - -#define EOI_default 0x00000000 -#define EOI_mask 0x00000000 - -#define PCI_MODE_default 0x01000103 -#define PCI_MODE_mask 0x1107070F - -#define DEVICE_VENDOR_ID_default 0x000C15D1 -#define DEVICE_VENDOR_ID_mask 0xFFFFFFFF - -#define SUBSYSTEM_VENDOR_ID_default 0x000015D1 -#define SUBSYSTEM_VENDOR_ID_mask 0x0000FFFF - -#define POWER_MANAGEMENT_default 0x0000001B -#define POWER_MANAGEMENT_mask 0x0000001F - -#define CLASS_CODE1_default 0x00028000 -#define CLASS_CODE1_mask 0x00FFFFFF - -#define BAR11_MASK_default 0x0FF00008 -#define BAR11_MASK_mask 0x8FF00008 - -#define BAR12_MASK_default 0x80001800 -#define BAR12_MASK_mask 0x80001F08 - -#define BAR13_MASK_default 0x8FF00008 -#define BAR13_MASK_mask 0x8FF00008 - -#define BAR14_MASK_default 0x8F000000 -#define BAR14_MASK_mask 0x8FFFFF08 - -#define BAR15_MASK_default 0x80000000 -#define BAR15_MASK_mask 0x8FFFFF08 - -#define BAR16_MASK_default 0x80000001 -// bit 0 and bit 3 is mutually exclusive -#define BAR16_MASK_mask 0x8FFFFFF9 - -#define CARDBUS_CIS_POINTER1_default 0x00000000 -#define CARDBUS_CIS_POINTER1_mask 0x03FFFFFF - -#define SUBSYSTEM_ID1_default 0x0000000C -#define SUBSYSTEM_ID1_mask 0x0000FFFF - -#define PCI_ADDRESS_MAP_11_default 0x18000000 -#define PCI_ADDRESS_MAP_11_mask 0x7FFFFFF1 - -#define PCI_ADDRESS_MAP_12_default 0x18100000 -#define PCI_ADDRESS_MAP_12_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_13_default 0x18200000 -#define PCI_ADDRESS_MAP_13_mask 0x7FF00001 - -#define PCI_ADDRESS_MAP_14_default 0x70000000 -#define PCI_ADDRESS_MAP_14_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_15_default 0x00000001 -#define PCI_ADDRESS_MAP_15_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_16_default 0x60000000 -#define PCI_ADDRESS_MAP_16_mask 0x7FF00001 - -#define FPI_SEGMENT_ENABLE_default 0x000003FF -#define FPI_SEGMENT_ENABLE_mask 0x000003FF - -#define CLASS_CODE2_default 0x00FF0000 -#define CLASS_CODE2_mask 0x00FFFFFF - -#define BAR21_MASK_default 0x80000008 -#define BAR21_MASK_mask 0x8FFFFFF8 - -#define BAR22_MASK_default 0x80000008 -#define BAR22_MASK_mask 0x80001F08 - -#define BAR23_MASK_default 0x80000008 -#define BAR23_MASK_mask 0x8FF00008 - -#define BAR24_MASK_default 0x8FE00000 -#define BAR24_MASK_mask 0x8FFFFF08 - -#define BAR25_MASK_default 0x8FFFF000 -#define BAR25_MASK_mask 0x8FFFFF08 - -#define BAR26_MASK_default 0x8FFFFFE1 -#define BAR26_MASK_mask 0x8FFFFFF1 - -#define CARDBUS_CIS_POINTER2_default 0x00000000 -#define CARDBUS_CIS_POINTER2_mask 0x03FFFFFF - -#define SUBSYSTEM_ID2_default 0x0000000C -#define SUBSYSTEM_ID2_mask 0x0000FFFF - -#define PCI_ADDRESS_MAP_21_default 0x3FE00000 -#define PCI_ADDRESS_MAP_21_mask 0x7FFFFFF1 - -#define PCI_ADDRESS_MAP_22_default 0x68000000 -#define PCI_ADDRESS_MAP_22_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_23_default 0x20000000 -#define PCI_ADDRESS_MAP_23_mask 0x7FF00001 - -#define PCI_ADDRESS_MAP_24_default 0x70000001 -#define PCI_ADDRESS_MAP_24_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_25_default 0x78000001 -#define PCI_ADDRESS_MAP_25_mask 0x7FFFFF01 - -#define PCI_ADDRESS_MAP_26_default 0x20000000 -#define PCI_ADDRESS_MAP_26_mask 0x7FF00001 - -#define FPI_ADDRESS_MASK11LOW_default 0x00000000 -#define FPI_ADDRESS_MASK11LOW_mask 0x00070000 - -#define FPI_ADDRESS_MAP_0_default 0x00000000 -#define FPI_ADDRESS_MAP_0_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_1_default 0x10000000 -#define FPI_ADDRESS_MAP_1_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_2_default 0x20000000 -#define FPI_ADDRESS_MAP_2_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_3_default 0x30000000 -#define FPI_ADDRESS_MAP_3_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_4_default 0x40000000 -#define FPI_ADDRESS_MAP_4_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_5_default 0x50000000 -#define FPI_ADDRESS_MAP_5_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_6_default 0x60000000 -#define FPI_ADDRESS_MAP_6_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_7_default 0x70000000 -#define FPI_ADDRESS_MAP_7_mask 0xFFF00000 - -#define FPI_ADDRESS_MAP_11LOW_default 0xB0000000 -#define FPI_ADDRESS_MAP_11LOW_mask 0xFFFF0000 - -#define FPI_ADDRESS_MAP_11HIGH_default 0xB8000000 -#define FPI_ADDRESS_MAP_11HIGH_mask 0xFFF80000 - -#define FPI_BURST_LENGTH_default 0x00000000 -#define FPI_BURST_LENGTH_mask 0x00000303 - -#define SET_PCI_SERR_default 0x00000000 -#define SET_PCI_SERR_mask 0x00000000 - -#define DMA_FPI_START_ADDRESS_default 0x00000000 -#define DMA_FPI_START_ADDRESS_mask 0xFFFFFFFF - -#define DMA_PCI_START_ADDRESS_default 0x00000000 -#define DMA_PCI_START_ADDRESS_mask 0xFFFFFFFF - -#define DMA_TRANSFER_COUNT_default 0x00000000 -#define DMA_TRANSFER_COUNT_mask 0x0000FFFF - -#define DMA_CONTROL_STATUS_default 0x00000000 -#define DMA_CONTROL_STATUS_mask 0x00000000 // bit 0,1 is writable - -/***********************************************************************/ -#undef IKOS_MINI_BOOT //don't run a full booting -#ifdef CONFIG_USE_IKOS -#define CONFIG_USE_VENUS //Faster, 10M CPU and 192k baudrate -#ifdef CONFIG_USE_VENUS -#define IKOS_CPU_SPEED 10000000 -#else -#define IKOS_CPU_SPEED 180000 //IKOS is slow -#endif -#endif //CONFIG_USE_IKOS - -/* 165001:henryhsu:20050603:Source Modify form Bing Tao */ - -#if defined(CONFIG_NET_WIRELESS_SPURS) || defined(CONFIG_NET_WIRELESS_SPURS_MODULE) -#define EBU_PCI_SOFTWARE_ARBITOR -#endif - -#define AMAZON_B11 -#ifdef AMAZON_B11 -#define SWITCH_BUF_FPI_ADDR (0x10110000) -#define SWITCH_BUF_ADDR (KSEG1+SWITCH_BUF_FPI_ADDR) -#define SWITCH_BUF_SIZE (0x2800) -#define AMAZON_B11_CBM_QD_ADDR (SWITCH_BUF_ADDR+0x0) -#define AMAZON_B11_BOND_CELL_ADDR (SWITCH_BUF_ADDR+0x000) -#endif -#define AMAZON_REFERENCE_BOARD -//for AMAZON ATM bonding application -#ifdef AMAZON_REFERENCE_BOARD -#define GPIO_DETECT_LOW -#else -#undef GPIO_DETECT_LOW -#endif - -/* 165001 */ - -#undef AMAZON_IKOS_DEBUG_MSG -#undef AMAZON_INT_DEBUG_MSG -#undef AMAZON_ATM_DEBUG_MSG -#undef AMAZON_DMA_DEBUG_MSG -#undef AMAZON_SW_DEBUG_MSG -#undef AMAZON_WDT_DEBUG_MSG -#undef AMAZON_MTD_DEBUG_MSG -#undef AMAZON_SSC_DEBUG_MSG -#undef AMAZON_MEI_DEBUG_MSG - -#ifdef AMAZON_IKOS_DEBUG_MSG -#define AMAZON_IKOS_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args) -#else -#define AMAZON_IKOS_DMSG(fmt,args...) -#endif - -#ifdef AMAZON_WDT_DEBUG_MSG -#define AMAZON_WDT_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) -#else -#define AMAZON_WDT_DMSG(fm,args...) -#endif - -#ifdef AMAZON_SSC_DEBUG_MSG -#define AMAZON_SSC_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) -#else -#define AMAZON_SSC_DMSG(fm,args...) -#endif - -#ifdef AMAZON_DMA_DEBUG_MSG -#define AMAZON_DMA_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) -#else -#define AMAZON_DMA_DMSG(fm,args...) -#endif - -#ifdef AMAZON_ATM_DEBUG_MSG -#define AMAZON_TPE_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) -#else //not AMAZON_ATM_DEBUG -#define AMAZON_TPE_DMSG(fmt, args...) -#endif //AMAZON_ATM_DEBUG - -#ifdef AMAZON_SW_DEBUG_MSG -#define AMAZON_SW_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) -#else -#define AMAZON_SW_DMSG(fmt,args...) -#endif - -#ifdef AMAZON_MTD_DEBUG_MSG -#define AMAZON_MTD_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) -#else -#define AMAZON_MTD_DMSG(fmt,args...) -#endif - -#ifdef AMAZON_INT_DEBUG_MSG -#define AMAZON_INT_DMSG(x...) printk(x) -#else -#define AMAZON_INT_DMSG(x...) -#endif - -#ifdef AMAZON_MEI_DEBUG_MSG -#define AMAZON_MEI_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args) -#else -#define AMAZON_MEI_DMSG(fmt,args...) -#endif - -#endif //AMAZON_H diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_dma.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_dma.h deleted file mode 100644 index 63ab5924e..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_dma.h +++ /dev/null @@ -1,148 +0,0 @@ -#ifndef AMAZON_DMA_H -#define AMAZON_DMA_H - -#define RCV_INT 1 -#define TX_BUF_FULL_INT 2 -#define TRANSMIT_CPT_INT 4 - -#define QOS_DEFAULT_WGT 0x7fffffffUL; - - -enum attr_t{ - TX=0, - RX=1, - RESERVED=2, - DEFAULT=3, - -}; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -typedef struct rx_desc{ - u32 data_length:16; - volatile u32 reserved:7; - volatile u32 byte_offset:2; - volatile u32 Burst_length_offset:3; - volatile u32 EoP:1; - volatile u32 Res:1; - volatile u32 C:1; - volatile u32 OWN:1; - volatile u32 Data_Pointer; - /*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/ -}_rx_desc; - - -typedef struct tx_desc{ - volatile u32 data_length:16; - volatile u32 reserved1:7; - volatile u32 byte_offset:5; - volatile u32 EoP:1; - volatile u32 SoP:1; - volatile u32 C:1; - volatile u32 OWN:1; - volatile u32 Data_Pointer;//fix me:should be 28 bits here -}_tx_desc; -#else //BIG -typedef struct rx_desc{ - union - { - struct - { - volatile u32 OWN :1; - volatile u32 C :1; - volatile u32 SoP :1; - volatile u32 EoP :1; - volatile u32 Burst_length_offset :3; - volatile u32 byte_offset :2; - volatile u32 reserve :7; - volatile u32 data_length :16; - }field; - - volatile u32 word; - }status; - - volatile u32 Data_Pointer; -}_rx_desc; - - -typedef struct tx_desc{ - union - { - struct - { - volatile u32 OWN :1; - volatile u32 C :1; - volatile u32 SoP :1; - volatile u32 EoP :1; - volatile u32 byte_offset :5; - volatile u32 reserved :7; - volatile u32 data_length :16; - }field; - - volatile u32 word; - }status; - - volatile u32 Data_Pointer; -}_tx_desc; - -#endif //ENDIAN - -struct dma_channel_info{ - /*filled by driver, optional*/ - enum attr_t attr;/*TX or RX*/ - int weight; - int desc_num; - int packet_size; - int control;/*on or off*/ - - int desc_base; - int status; -}; - -typedef struct dma_channel_info _dma_channel_info; - -struct dma_device_info{ - /*variables*/ - /*filled by driver, compulsary*/ - char device_name[15]; - enum attr_t attr;/*default or else*/ - int tx_burst_len; - int rx_burst_len; - - int logic_rx_chan_base; - int logic_tx_chan_base; - u8 on_ch_bit; - /*filled by driver, optional*/ - int weight; - int current_tx_chan; - int current_rx_chan; - int num_tx_chan; - int num_rx_chan; - struct dma_channel_info tx_chan[2]; - struct dma_channel_info rx_chan[4]; - - /*functions, optional*/ - u8* (*buffer_alloc)(int len,int* offset, void** opt); - int (*buffer_free)(u8* dataptr, void* opt); - int (*intr_handler)(struct dma_device_info* info, int status); - /*set by device, clear by dma*/ - int ack; - void * priv; /* used by peripheral driver only */ -}; -typedef struct dma_device_info _dma_device_info; - -int dma_device_register(struct dma_device_info* info); - -int dma_device_unregister(struct dma_device_info* info); - -int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt); - -int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt); - -int dma_device_update(struct dma_device_info* info); - -void dma_device_update_rx(struct dma_device_info* dma_dev); - -void dma_device_update_tx(struct dma_device_info* dma_dev); - -void register_handler_sim(int (*handler)(int)); -#endif /* AMAZON_DMA_H */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei.h deleted file mode 100644 index 6ac8ab310..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei.h +++ /dev/null @@ -1,220 +0,0 @@ -#ifndef _AMAZON_MEI_H -#define _AMAZON_MEI_H -///////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#include "amazon_mei_app.h" - -#define AMAZON_MEI_DEBUG_ON -#define AMAZON_MEI_CMV_EXTRA - -#define AMAZON_MEI_MAJOR 106 - -/* -** Define where in ME Processor's memory map the Stratify chip lives -*/ -#define MEI_SPACE_ACCESS 0xB0100C00 - -#define MAXSWAPSIZE 8 * 1024 //8k *(32bits) -//#define AMAZON_ADSL_IMAGESIZE 16*1024 // 16k * (32bits) - - -// Mailboxes -#define MSG_LENGTH 16 // x16 bits -#define YES_REPLY 1 -#define NO_REPLY 0 - -#define CMV_TIMEOUT 100 //jiffies -#define MIB_INTERVAL 10000 //msec - -/*** Bit definitions ***/ - -#define FALSE 0 -#define TRUE 1 -#define BIT0 1<<0 -#define BIT1 1<<1 -#define BIT2 1<<2 -#define BIT3 1<<3 -#define BIT4 1<<4 -#define BIT5 1<<5 -#define BIT6 1<<6 -#define BIT7 1<<7 -#define BIT8 1<<8 -#define BIT9 1<<9 -#define BIT10 1<<10 -#define BIT11 1<<11 -#define BIT12 1<<12 -#define BIT13 1<<13 -#define BIT14 1<<14 -#define BIT15 1<<15 -#define BIT16 1<<16 -#define BIT17 1<<17 -#define BIT18 1<<18 -#define BIT19 1<<19 -#define BIT20 1<<20 -#define BIT21 1<<21 -#define BIT22 1<<22 -#define BIT23 1<<23 -#define BIT24 1<<24 -#define BIT25 1<<25 -#define BIT26 1<<26 -#define BIT27 1<<27 -#define BIT28 1<<28 -#define BIT29 1<<29 -#define BIT30 1<<30 -#define BIT31 1<<31 - - -/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ -#define MEI_DATA_XFR (0x0000 + MEI_SPACE_ACCESS) -#define MEI_VERSION (0x0200 + MEI_SPACE_ACCESS) -#define ARC_GP_STAT (0x0204 + MEI_SPACE_ACCESS) -#define MEI_XFR_ADDR (0x020C + MEI_SPACE_ACCESS) -#define MEI_TO_ARC_INT (0x021C + MEI_SPACE_ACCESS) -#define ARC_TO_MEI_INT (0x0220 + MEI_SPACE_ACCESS) -#define ARC_TO_MEI_INT_MASK (0x0224 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_WAD (0x0228 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_RAD (0x022C + MEI_SPACE_ACCESS) -#define MEI_DEBUG_DATA (0x0230 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_DEC (0x0234 + MEI_SPACE_ACCESS) -#define MEI_CONTROL (0x0238 + MEI_SPACE_ACCESS) -#define AT_CELLRDY_BC0 (0x023C + MEI_SPACE_ACCESS) -#define AT_CELLRDY_BC1 (0x0240 + MEI_SPACE_ACCESS) -#define AR_CELLRDY_BC0 (0x0244 + MEI_SPACE_ACCESS) -#define AR_CELLRDY_BC1 (0x0248 + MEI_SPACE_ACCESS) -#define AAI_ACCESS (0x024C + MEI_SPACE_ACCESS) -#define AAITXCB0 (0x0300 + MEI_SPACE_ACCESS) -#define AAITXCB1 (0x0304 + MEI_SPACE_ACCESS) -#define AAIRXCB0 (0x0308 + MEI_SPACE_ACCESS) -#define AAIRXCB1 (0x030C + MEI_SPACE_ACCESS) - - -// MEI_TO_ARC_INTERRUPT Register definitions -#define MEI_TO_ARC_INT1 BIT3 -#define MEI_TO_ARC_INT0 BIT2 -#define MEI_TO_ARC_CS_DONE BIT1 -#define MEI_TO_ARC_MSGAV BIT0 - -// ARC_TO_MEI_INTERRUPT Register definitions -#define ARC_TO_MEI_INT1 BIT8 -#define ARC_TO_MEI_INT0 BIT7 -#define ARC_TO_MEI_CS_REQ BIT6 -#define ARC_TO_MEI_DBG_DONE BIT5 -#define ARC_TO_MEI_MSGACK BIT4 -#define ARC_TO_MEI_NO_ACCESS BIT3 -#define ARC_TO_MEI_CHECK_AAITX BIT2 -#define ARC_TO_MEI_CHECK_AAIRX BIT1 -#define ARC_TO_MEI_MSGAV BIT0 - -// ARC_TO_MEI_INTERRUPT_MASK Register definitions -#define GP_INT1_EN BIT8 -#define GP_INT0_EN BIT7 -#define CS_REQ_EN BIT6 -#define DBG_DONE_EN BIT5 -#define MSGACK_EN BIT4 -#define NO_ACC_EN BIT3 -#define AAITX_EN BIT2 -#define AAIRX_EN BIT1 -#define MSGAV_EN BIT0 - -// MEI_CONTROL Register definitions -#define INT_LEVEL BIT2 -#define SOFT_RESET BIT1 -#define HOST_MSTR BIT0 - -// MEI_DEBUG_DECODE Register definitions -#define MEI_DEBUG_DEC_MASK (0x3) -#define MEI_DEBUG_DEC_AUX_MASK (0x0) -#define MEI_DEBUG_DEC_DMP1_MASK (0x1) -#define MEI_DEBUG_DEC_DMP2_MASK (0x2) -#define MEI_DEBUG_DEC_CORE_MASK (0x3) - - -// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate -// page swap requests. -#define MEI_TO_ARC_MAILBOX (0x15FC0) -#define MEI_TO_ARC_MAILBOXR (0x15FEC) -#define ARC_TO_MEI_MAILBOX (0x15F90) -#define ARC_MEI_MAILBOXR (0x15FBC) - -// Codeswap request messages are indicated by setting BIT31 -#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000) - -/* -** Swap page header -*/ -// Page must be loaded at boot time if size field has BIT31 set -#define BOOT_FLAG (BIT31) -#define BOOT_FLAG_MASK ~BOOT_FLAG - -// Swap page header describes size in 32-bit words, load location, and image offset -// for program and/or data segments -typedef struct _arc_swp_page_hdr -{ - u32 p_offset; // Offset bytes of progseg from beginning of image - u32 p_dest; // Destination addr of progseg on processor - u32 p_size; // Size in 32-bitwords of program segment - u32 d_offset; // Offset bytes of dataseg from beginning of image - u32 d_dest; // Destination addr of dataseg on processor - u32 d_size; // Size in 32-bitwords of data segment -}ARC_SWP_PAGE_HDR; - - -/* -** Swap image header -*/ -#define GET_PROG 0 // Flag used for program mem segment -#define GET_DATA 1 // Flag used for data mem segment - -// Image header contains size of image, checksum for image, and count of -// page headers. Following that are 'count' page headers followed by -// the code and/or data segments to be loaded -typedef struct _arc_img_hdr -{ - u32 size; // Size of binary image in bytes - u32 checksum; // Checksum for image - u32 count; // Count of swp pages in image - ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy -}ARC_IMG_HDR; - - - -/* -** Native size for the Stratiphy interface is 32-bits. All reads and writes -** MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or -** byte data. Read routines are provided. Write routines are probably a bad idea, as the -** Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle -** could very well have unintended results. -*/ -MEI_ERROR meiCMV(u16 *, int); // first arg is CMV to ARC, second to indicate whether need reply - -void meiLongwordWrite(u32 ul_address, u32 ul_data); -void meiLongwordRead(u32 ul_address, u32 *pul_data); - - -MEI_ERROR meiDMAWrite(u32 destaddr, u32 *databuff, u32 databuffsize); -MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize); - -MEI_ERROR meiDMARead(u32 srcaddr, u32 *databuff, u32 databuffsize); -MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize); - -void meiPollForDbgDone(void); - -void meiMailboxInterruptsDisable(void); -void meiMailboxInterruptsEnable(void); - -MEI_ERROR meiMailboxWrite(u16 *msgsrcbuffer, u16 msgsize); -MEI_ERROR meiMailboxRead(u16 *msgdestbuffer, u16 msgsize); - -int meiGetPage( u32 Page, u32 data, u32 MaxSize, u32 *Buffer, u32 *Dest); - -MEI_ERROR meiHaltArc(void); -MEI_ERROR meiRunArc(void); - -MEI_ERROR meiDownloadBootCode(void); - -MEI_ERROR meiForceRebootAdslModem(void); - -void makeCMV(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data); - -#endif - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app.h deleted file mode 100644 index 89700d9d7..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app.h +++ /dev/null @@ -1,54 +0,0 @@ -//509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl - -#ifndef _AMAZON_MEI_APP_H -#define _AMAZON_MEI_APP_H - -///////////////////////////////////////////////////////////////////////////////////////////////////// - - // ioctl control -#define AMAZON_MEI_START 300 -#define AMAZON_MEI_REPLY 301 -#define AMAZON_MEI_NOREPLY 302 - -#define AMAZON_MEI_RESET 303 -#define AMAZON_MEI_REBOOT 304 -#define AMAZON_MEI_HALT 305 -#define AMAZON_MEI_CMV_WINHOST 306 -#define AMAZON_MEI_CMV_READ 307 -#define AMAZON_MEI_CMV_WRITE 308 -#define AMAZON_MEI_MIB_DAEMON 309 -#define AMAZON_MEI_SHOWTIME 310 -#define AMAZON_MEI_REMOTE 311 -#define AMAZON_MEI_READDEBUG 312 -#define AMAZON_MEI_WRITEDEBUG 313 -#define AMAZON_MEI_LOP 314 - -#define AMAZON_MEI_PCM_SETUP 315 -#define AMAZON_MEI_PCM_START_TIMER 316 -#define AMAZON_MEI_PCM_STOP_TIMER 317 -#define AMAZON_MEI_PCM_CHECK 318 -#define AMAZON_MEI_GET_EOC_LEN 319 -#define AMAZON_MEI_GET_EOC_DATA 320 -#define AMAZON_MEI_PCM_GETDATA 321 -#define AMAZON_MEI_PCM_GPIO 322 -#define AMAZON_MEI_EOC_SEND 323 -//MIB -#define AMAZON_MIB_LO_ATUC 324 -#define AMAZON_MIB_LO_ATUR 325 -#define AMAZON_MEI_DOWNLOAD 326 - -#define AMAZON_MEI_DEBUG_MODE 327 //509221:tc.chen -#define LOOP_DIAGNOSTIC_MODE_COMPLETE 328 - - -/*** Enums ***/ -typedef enum mei_error -{ - MEI_SUCCESS = 0, - MEI_FAILURE = -1, - MEI_MAILBOX_FULL = -2, - MEI_MAILBOX_EMPTY = -3, - MEI_MAILBOX_TIMEOUT = -4, -}MEI_ERROR; - -#endif diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app_ioctl.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app_ioctl.h deleted file mode 100644 index d98f60b17..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app_ioctl.h +++ /dev/null @@ -1,1169 +0,0 @@ -// 603221:tc.chen 2006/03/21 added APIs to support the WEB related parameters for ADSL Statistics - -#ifndef __AMAZON_MEI_APP_IOCTL_H -#define __AMAZON_MEI_APP_IOCTL_H - -#ifdef __KERNEL__ -#include "amazon_mei_ioctl.h" -#endif - -/* Interface Name */ -//#define INTERFACE_NAME - -/* adslLineTable constants */ -#define GET_ADSL_LINE_CODE 1 - -/* adslAtucPhysTable constants */ -#define GET_ADSL_ATUC_PHY 4 - -/* adslAturPhysTable constants */ -#define GET_ADSL_ATUR_PHY 10 - -/* adslAtucChanTable constants */ -#define GET_ADSL_ATUC_CHAN_INFO 15 - -/* adslAturChanTable constants */ -#define GET_ADSL_ATUR_CHAN_INFO 18 - -/* adslAtucPerfDataTable constants */ -#define GET_ADSL_ATUC_PERF_DATA 21 - -/* adslAturPerfDataTable constants */ -#define GET_ADSL_ATUR_PERF_DATA 40 - -/* adslAtucIntervalTable constants */ -#define GET_ADSL_ATUC_INTVL_INFO 60 - -/* adslAturIntervalTable constants */ -#define GET_ADSL_ATUR_INTVL_INFO 65 - -/* adslAtucChanPerfDataTable constants */ -#define GET_ADSL_ATUC_CHAN_PERF_DATA 70 - -/* adslAturChanPerfDataTable constants */ -#define GET_ADSL_ATUR_CHAN_PERF_DATA 90 - -/* adslAtucChanIntervalTable constants */ -#define GET_ADSL_ATUC_CHAN_INTVL_INFO 110 - -/* adslAturChanIntervalTable constants */ -#define GET_ADSL_ATUR_CHAN_INTVL_INFO 115 - -/* adslLineAlarmConfProfileTable constants */ -#define GET_ADSL_ALRM_CONF_PROF 120 -#define SET_ADSL_ALRM_CONF_PROF 121 - -/* adslAturTrap constants */ -#define ADSL_ATUR_TRAPS 135 - -////////////////// RFC-3440 ////////////// - -#ifdef AMAZON_MEI_MIB_RFC3440 -/* adslLineExtTable */ -#define GET_ADSL_ATUC_LINE_EXT 201 -#define SET_ADSL_ATUC_LINE_EXT 203 - -/* adslAtucPerfDateExtTable */ -#define GET_ADSL_ATUC_PERF_DATA_EXT 205 - -/* adslAtucIntervalExtTable */ -#define GET_ADSL_ATUC_INTVL_EXT_INFO 221 - -/* adslAturPerfDataExtTable */ -#define GET_ADSL_ATUR_PERF_DATA_EXT 225 - -/* adslAturIntervalExtTable */ -#define GET_ADSL_ATUR_INTVL_EXT_INFO 233 - -/* adslAlarmConfProfileExtTable */ -#define GET_ADSL_ALRM_CONF_PROF_EXT 235 -#define SET_ADSL_ALRM_CONF_PROF_EXT 236 - -/* adslAturExtTrap */ -#define ADSL_ATUR_EXT_TRAPS 240 - -#endif - -// 603221:tc.chen start -/* The following constants are added to support the WEB related ADSL Statistics */ - -/* adslLineStatus constants */ -#define GET_ADSL_LINE_STATUS 245 - -/* adslLineRate constants */ -#define GET_ADSL_LINE_RATE 250 - -/* adslLineInformation constants */ -#define GET_ADSL_LINE_INFO 255 - -/* adslNearEndPerformanceStats constants */ -#define GET_ADSL_NEAREND_STATS 270 - -/* adslFarEndPerformanceStats constants */ -#define GET_ADSL_FAREND_STATS 290 - -// 603221:tc.chen end - -/* Loop diagnostics mode of the ADSL line related constants */ -#define GET_ADSL_LOOP_DIAGNOSTICS_MODE 295 -#define SET_ADSL_LOOP_DIAGNOSTICS_MODE 296 -#define IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE 299 - -/* Sub-carrier related parameters */ -#define GET_ADSL_ATUC_SUBCARRIER_STATS 297 -#define GET_ADSL_ATUR_SUBCARRIER_STATS 298 -#define GET_ADSL_LINE_INIT_STATS 150 -#define GET_ADSL_POWER_SPECTRAL_DENSITY 151 - - -/////////////////////////////////////////////////////////// -// makeCMV(Opcode, Group, Address, Index, Size, Data) - -/* adslLineCode Flags */ -#define LINE_CODE_FLAG 0x1 /* BIT 0th position */ - -/* adslAtucPhysTable Flags */ -#define ATUC_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 57, 0, 12, data) -#define ATUC_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 57, 12, 4, data) - -#define ATUC_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */ -#define ATUC_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 64, 0, 4, data) - -#define ATUC_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */ -#define ATUC_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 58, 0, 8, data) - -#define ATUC_CURR_STAT_FLAG 0x8 /* BIT 3 */ - -#define ATUC_CURR_OUT_PWR_FLAG 0x10 /* BIT 4 */ -#define ATUC_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 5, 1, data) - -#define ATUC_CURR_ATTR_FLAG 0x20 /* BIT 5 */ -#define ATUC_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 0, 2, data) - - -/* adslAturPhysTable Flags */ -#define ATUR_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */ -#define ATUR_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 62, 0, 12, data) -#define ATUR_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 62, 12, 4, data) - -#define ATUR_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */ -#define ATUR_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 65, 0, 4, data) - -#define ATUR_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */ -#define ATUR_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 61, 0, 8, data) - -#define ATUR_SNRMGN_FLAG 0x8 -#define ATUR_SNRMGN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 1, data) - -#define ATUR_ATTN_FLAG 0x10 -#define ATUR_ATTN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data) - -#define ATUR_CURR_STAT_FLAG 0x20 /* BIT 3 */ - -#define ATUR_CURR_OUT_PWR_FLAG 0x40 /* BIT 4 */ -#define ATUR_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 5, 1, data) - -#define ATUR_CURR_ATTR_FLAG 0x80 /* BIT 5 */ -#define ATUR_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 0, 2, data) - -/* adslAtucChanTable Flags */ -#define ATUC_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */ -#define ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 1, 1, data) - -#define ATUC_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */ -#define ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data) - -#define ATUC_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */ - -/* adslAturChanTable Flags */ -#define ATUR_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */ -#define ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 2, 1, 1, data) - -#define ATUR_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */ -#define ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data) - -#define ATUR_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */ - -#define ATUR_CHAN_CRC_BLK_LEN_FLAG 0x8 /* BIT 3 */ - -/* adslAtucPerfDataTable Flags */ -#define ATUC_PERF_LOFS_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PERF_LOSS_FLAG 0x2 /* BIT 1 */ -#define ATUC_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data) -#define ATUC_PERF_ESS_FLAG 0x4 /* BIT 2 */ -#define ATUC_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data) -#define ATUC_PERF_INITS_FLAG 0x8 /* BIT 3 */ -#define ATUC_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */ -#define ATUC_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */ -#define ATUC_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUC_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */ -#define ATUC_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */ -#define ATUC_PERF_CURR_15MIN_ESS_FLAG 0x200 /* BIT 9 */ -#define ATUC_PERF_CURR_15MIN_INIT_FLAG 0x400 /* BIT 10 */ -#define ATUC_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ -#define ATUC_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */ -#define ATUC_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */ -#define ATUC_PERF_CURR_1DAY_ESS_FLAG 0x4000 /* BIT 14 */ -#define ATUC_PERF_CURR_1DAY_INIT_FLAG 0x8000 /* BIT 15 */ -#define ATUC_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUC_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */ -#define ATUC_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */ -#define ATUC_PERF_PREV_1DAY_ESS_FLAG 0x80000 /* BIT 19 */ -#define ATUC_PERF_PREV_1DAY_INITS_FLAG 0x100000 /* BIT 20 */ - -/* adslAturPerfDataTable Flags */ -#define ATUR_PERF_LOFS_FLAG 0x1 /* BIT 0th position */ -#define ATUR_PERF_LOSS_FLAG 0x2 /* BIT 1 */ -#define ATUR_PERF_LPR_FLAG 0x4 /* BIT 2 */ -#define ATUR_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data) -#define ATUR_PERF_ESS_FLAG 0x8 /* BIT 3 */ -#define ATUR_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data) -#define ATUR_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */ -#define ATUR_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */ -#define ATUR_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUR_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */ -#define ATUR_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */ -#define ATUR_PERF_CURR_15MIN_LPR_FLAG 0x200 /* BIT 9 */ -#define ATUR_PERF_CURR_15MIN_ESS_FLAG 0x400 /* BIT 10 */ -#define ATUR_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ -#define ATUR_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */ -#define ATUR_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */ -#define ATUR_PERF_CURR_1DAY_LPR_FLAG 0x4000 /* BIT 14 */ -#define ATUR_PERF_CURR_1DAY_ESS_FLAG 0x8000 /* BIT 15 */ -#define ATUR_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUR_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */ -#define ATUR_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */ -#define ATUR_PERF_PREV_1DAY_LPR_FLAG 0x80000 /* BIT 19 */ -#define ATUR_PERF_PREV_1DAY_ESS_FLAG 0x100000 /* BIT 20 */ - -/* adslAtucIntervalTable Flags */ -#define ATUC_INTVL_LOF_FLAG 0x1 /* BIT 0th position */ -#define ATUC_INTVL_LOS_FLAG 0x2 /* BIT 1 */ -#define ATUC_INTVL_ESS_FLAG 0x4 /* BIT 2 */ -#define ATUC_INTVL_INIT_FLAG 0x8 /* BIT 3 */ -#define ATUC_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */ - -/* adslAturIntervalTable Flags */ -#define ATUR_INTVL_LOF_FLAG 0x1 /* BIT 0th position */ -#define ATUR_INTVL_LOS_FLAG 0x2 /* BIT 1 */ -#define ATUR_INTVL_LPR_FLAG 0x4 /* BIT 2 */ -#define ATUR_INTVL_ESS_FLAG 0x8 /* BIT 3 */ -#define ATUR_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */ - -/* adslAtucChanPerfDataTable Flags */ -#define ATUC_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */ -#define ATUC_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */ -#define ATUC_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */ -#define ATUC_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */ -#define ATUC_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */ -#define ATUC_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */ -#define ATUC_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUC_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */ -#define ATUC_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */ -#define ATUC_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */ -#define ATUC_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */ -#define ATUC_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11*/ -#define ATUC_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */ -#define ATUC_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */ -#define ATUC_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */ -#define ATUC_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */ -#define ATUC_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUC_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */ -#define ATUC_CHAN_PERF_PREV_1DAY_TX_BLK_FLAG 0x40000 /* BIT 18 */ -#define ATUC_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */ -#define ATUC_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */ - - -/* adslAturChanPerfDataTable Flags */ -#define ATUR_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */ -#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data) -#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data) -#define ATUR_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */ -#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data) -#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data) -#define ATUR_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */ -#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data) -#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data) -#define ATUR_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */ -#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data) -#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data) -#define ATUR_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */ -#define ATUR_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */ -#define ATUR_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ -#define ATUR_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */ -#define ATUR_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */ -#define ATUR_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */ -#define ATUR_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */ -#define ATUR_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ -#define ATUR_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */ -#define ATUR_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */ -#define ATUR_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */ -#define ATUR_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */ -#define ATUR_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */ -#define ATUR_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */ -#define ATUR_CHAN_PERF_PREV_1DAY_TRANS_BLK_FLAG 0x40000 /* BIT 18 */ -#define ATUR_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */ -#define ATUR_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */ - -/* adslAtucChanIntervalTable Flags */ -#define ATUC_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th position */ -#define ATUC_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */ -#define ATUC_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */ -#define ATUC_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */ -#define ATUC_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */ -#define ATUC_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */ - -/* adslAturChanIntervalTable Flags */ -#define ATUR_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th Position */ -#define ATUR_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */ -#define ATUR_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */ -#define ATUR_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */ -#define ATUR_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */ -#define ATUR_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */ - -/* adslLineAlarmConfProfileTable Flags */ -#define ATUC_THRESH_15MIN_LOFS_FLAG 0x01 /* BIT 0th position */ -#define ATUC_THRESH_15MIN_LOSS_FLAG 0x02 /* BIT 1 */ -#define ATUC_THRESH_15MIN_ESS_FLAG 0x04 /* BIT 2 */ -#define ATUC_THRESH_FAST_RATEUP_FLAG 0x08 /* BIT 3 */ -#define ATUC_THRESH_INTERLEAVE_RATEUP_FLAG 0x10 /* BIT 4 */ -#define ATUC_THRESH_FAST_RATEDOWN_FLAG 0x20 /* BIT 5 */ -#define ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x40 /* BIT 6 */ -#define ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG 0x80 /* BIT 7 */ -#define ATUR_THRESH_15MIN_LOFS_FLAG 0x100 /* BIT 8 */ -#define ATUR_THRESH_15MIN_LOSS_FLAG 0x200 /* BIT 9 */ -#define ATUR_THRESH_15MIN_LPRS_FLAG 0x400 /* BIT 10 */ -#define ATUR_THRESH_15MIN_ESS_FLAG 0x800 /* BIT 11 */ -#define ATUR_THRESH_FAST_RATEUP_FLAG 0x1000 /* BIT 12 */ -#define ATUR_THRESH_INTERLEAVE_RATEUP_FLAG 0x2000 /* BIT 13 */ -#define ATUR_THRESH_FAST_RATEDOWN_FLAG 0x4000 /* BIT 14 */ -#define ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x8000 /* BIT 15 */ -#define LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG 0x10000 /* BIT 16 */ - - -/* adslAturTraps Flags */ -#define ATUC_PERF_LOFS_THRESH_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PERF_LOSS_THRESH_FLAG 0x2 /* BIT 1 */ -#define ATUC_PERF_ESS_THRESH_FLAG 0x4 /* BIT 2 */ -#define ATUC_RATE_CHANGE_FLAG 0x8 /* BIT 3 */ -#define ATUR_PERF_LOFS_THRESH_FLAG 0x10 /* BIT 4 */ -#define ATUR_PERF_LOSS_THRESH_FLAG 0x20 /* BIT 5 */ -#define ATUR_PERF_LPRS_THRESH_FLAG 0x40 /* BIT 6 */ -#define ATUR_PERF_ESS_THRESH_FLAG 0x80 /* BIT 7 */ -#define ATUR_RATE_CHANGE_FLAG 0x100 /* BIT 8 */ - -//RFC- 3440 FLAG DEFINITIONS - -#ifdef AMAZON_MEI_MIB_RFC3440 -/* adslLineExtTable flags */ -#define ATUC_LINE_TRANS_CAP_FLAG 0x1 /* BIT 0th position */ -#define ATUC_LINE_TRANS_CAP_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data) -#define ATUC_LINE_TRANS_CONFIG_FLAG 0x2 /* BIT 1 */ -#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data) -#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV_WR makeCMV(H2D_CMV_WRITE,INFO, 67, 0, 1, data) -#define ATUC_LINE_TRANS_ACTUAL_FLAG 0x4 /* BIT 2 */ -#define ATUC_LINE_TRANS_ACTUAL_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 1, 0, 1, data) -#define LINE_GLITE_POWER_STATE_FLAG 0x8 /* BIT 3 */ -#define LINE_GLITE_POWER_STATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 0, 0, 1, data) - -/* adslAtucPerfDataExtTable flags */ -#define ATUC_PERF_STAT_FASTR_FLAG 0x1 /* BIT 0th position */ -#define ATUC_PERF_STAT_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data) -#define ATUC_PERF_STAT_FAILED_FASTR_FLAG 0x2 /* BIT 1 */ -#define ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data) -#define ATUC_PERF_STAT_SESL_FLAG 0X4 /* BIT 2 */ -#define ATUC_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data) -#define ATUC_PERF_STAT_UASL_FLAG 0X8 /* BIT 3 */ -#define ATUC_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data) -#define ATUC_PERF_CURR_15MIN_FASTR_FLAG 0X10 /* BIT 4 */ -#define ATUC_PERF_CURR_15MIN_FAILED_FASTR_FLAG 0X20 /* BIT 5 */ -#define ATUC_PERF_CURR_15MIN_SESL_FLAG 0X40 /* BIT 6 */ -#define ATUC_PERF_CURR_15MIN_UASL_FLAG 0X80 /* BIT 7 */ -#define ATUC_PERF_CURR_1DAY_FASTR_FLAG 0X100 /* BIT 8 */ -#define ATUC_PERF_CURR_1DAY_FAILED_FASTR_FLAG 0X200 /* BIT 9 */ -#define ATUC_PERF_CURR_1DAY_SESL_FLAG 0X400 /* BIT 10 */ -#define ATUC_PERF_CURR_1DAY_UASL_FLAG 0X800 /* BIT 11 */ -#define ATUC_PERF_PREV_1DAY_FASTR_FLAG 0X1000 /* BIT 12 */ -#define ATUC_PERF_PREV_1DAY_FAILED_FASTR_FLAG 0X2000 /* BIT 13 */ -#define ATUC_PERF_PREV_1DAY_SESL_FLAG 0X4000 /* BIT 14 */ -#define ATUC_PERF_PREV_1DAY_UASL_FLAG 0X8000 /* BIT 15 */ - -/* adslAturPerfDataExtTable */ -#define ATUR_PERF_STAT_SESL_FLAG 0X1 /* BIT 0th position */ -#define ATUR_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data) -#define ATUR_PERF_STAT_UASL_FLAG 0X2 /* BIT 1 */ -#define ATUR_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data) -#define ATUR_PERF_CURR_15MIN_SESL_FLAG 0X4 /* BIT 2 */ -#define ATUR_PERF_CURR_15MIN_UASL_FLAG 0X8 /* BIT 3 */ -#define ATUR_PERF_CURR_1DAY_SESL_FLAG 0X10 /* BIT 4 */ -#define ATUR_PERF_CURR_1DAY_UASL_FLAG 0X20 /* BIT 5 */ -#define ATUR_PERF_PREV_1DAY_SESL_FLAG 0X40 /* BIT 6 */ -#define ATUR_PERF_PREV_1DAY_UASL_FLAG 0X80 /* BIT 7 */ - -/* adslAutcIntervalExtTable flags */ -#define ATUC_INTERVAL_FASTR_FLAG 0x1 /* Bit 0 */ -#define ATUC_INTERVAL_FAILED_FASTR_FLAG 0x2 /* Bit 1 */ -#define ATUC_INTERVAL_SESL_FLAG 0x4 /* Bit 2 */ -#define ATUC_INTERVAL_UASL_FLAG 0x8 /* Bit 3 */ - -/* adslAturIntervalExtTable */ -#define ATUR_INTERVAL_SESL_FLAG 0X1 /* BIT 0th position */ -#define ATUR_INTERVAL_UASL_FLAG 0X2 /* BIT 1 */ - -/* adslAlarmConfProfileExtTable */ -#define ATUC_THRESH_15MIN_FAILED_FASTR_FLAG 0X1/* BIT 0th position */ -#define ATUC_THRESH_15MIN_SESL_FLAG 0X2 /* BIT 1 */ -#define ATUC_THRESH_15MIN_UASL_FLAG 0X4 /* BIT 2 */ -#define ATUR_THRESH_15MIN_SESL_FLAG 0X8 /* BIT 3 */ -#define ATUR_THRESH_15MIN_UASL_FLAG 0X10 /* BIT 4 */ - -/* adslAturExtTraps */ -#define ATUC_15MIN_FAILED_FASTR_TRAP_FLAG 0X1 /* BIT 0th position */ -#define ATUC_15MIN_SESL_TRAP_FLAG 0X2 /* BIT 1 */ -#define ATUC_15MIN_UASL_TRAP_FLAG 0X4 /* BIT 2 */ -#define ATUR_15MIN_SESL_TRAP_FLAG 0X8 /* BIT 3 */ -#define ATUR_15MIN_UASL_TRAP_FLAG 0X10 /* BIT 4 */ - -// 603221:tc.chen start -/* adslLineStatus Flags */ -#define LINE_STAT_MODEM_STATUS_FLAG 0x1 /* BIT 0th position */ -#define LINE_STAT_MODEM_STATUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data) -#define LINE_STAT_MODE_SEL_FLAG 0x2 /* BIT 1 */ -#define LINE_STAT_MODE_SEL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data) -#define LINE_STAT_TRELLCOD_ENABLE_FLAG 0x4 /* BIT 2 */ -#define LINE_STAT_TRELLCOD_ENABLE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, OPTN, 2, 0, 1, data) -#define LINE_STAT_LATENCY_FLAG 0x8 /* BIT 3 */ -#define LINE_STAT_LATENCY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 12, 0, 1, data) - -/* adslLineRate Flags */ -#define LINE_RATE_DATA_RATEDS_FLAG 0x1 /* BIT 0th position */ -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 2, 2, data) - - -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 0, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 0, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 0, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 0, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 0, 2, data) - -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 1, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 1, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 1, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 1, 1, data) -#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 2, 2, data) - -#define LINE_RATE_DATA_RATEUS_FLAG 0x2 /* BIT 1 */ -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 2, 2, data) - - -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 0, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 0, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 0, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 0, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 0, 2, data) - -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 1, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 1, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 1, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 1, 1, data) -#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 2, 2, data) - -#define LINE_RATE_ATTNDRDS_FLAG 0x4 /* BIT 2 */ -#define LINE_RATE_ATTNDRDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 2, data) - -#define LINE_RATE_ATTNDRUS_FLAG 0x8 /* BIT 3 */ -#define LINE_RATE_ATTNDRUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 4, 2, data) - -/* adslLineInformation Flags */ -#define LINE_INFO_INTLV_DEPTHDS_FLAG 0x1 /* BIT 0th position */ -#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 0, 1, data) -#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 1, 1, data) -#define LINE_INFO_INTLV_DEPTHUS_FLAG 0x2 /* BIT 1 */ -#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 0, 1, data) -#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 1, 1, data) -#define LINE_INFO_LATNDS_FLAG 0x4 /* BIT 2 */ -#define LINE_INFO_LATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 1, 1, data) -#define LINE_INFO_LATNUS_FLAG 0x8 /* BIT 3 */ -#define LINE_INFO_LATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 1, 1, data) -#define LINE_INFO_SATNDS_FLAG 0x10 /* BIT 4 */ -#define LINE_INFO_SATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data) -#define LINE_INFO_SATNUS_FLAG 0x20 /* BIT 5 */ -#define LINE_INFO_SATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 2, 1, data) -#define LINE_INFO_SNRMNDS_FLAG 0x40 /* BIT 6 */ -#define LINE_INFO_SNRMNDS_FLAG_ADSL1_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 3, 1, data) -#define LINE_INFO_SNRMNDS_FLAG_ADSL2_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 0, 1, data) -#define LINE_INFO_SNRMNDS_FLAG_ADSL2PLUS_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 46, 0, 1, data) -#define LINE_INFO_SNRMNUS_FLAG 0x80 /* BIT 7 */ -#define LINE_INFO_SNRMNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 3, 1, data) -#define LINE_INFO_ACATPDS_FLAG 0x100 /* BIT 8 */ -#define LINE_INFO_ACATPDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 6, 1, data) -#define LINE_INFO_ACATPUS_FLAG 0x200 /* BIT 9 */ -#define LINE_INFO_ACATPUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 6, 1, data) - -/* adslNearEndPerformanceStats Flags */ -#define NEAREND_PERF_SUPERFRAME_FLAG_LSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data) -#define NEAREND_PERF_SUPERFRAME_FLAG_MSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data) -#define NEAREND_PERF_SUPERFRAME_FLAG 0x1 /* BIT 0th position */ -#define NEAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data) -#define NEAREND_PERF_LOS_FLAG 0x2 /* BIT 1 */ -#define NEAREND_PERF_LOF_FLAG 0x4 /* BIT 2 */ -#define NEAREND_PERF_LPR_FLAG 0x8 /* BIT 3 */ -#define NEAREND_PERF_NCD_FLAG 0x10 /* BIT 4 */ -#define NEAREND_PERF_LCD_FLAG 0x20 /* BIT 5 */ -#define NEAREND_PERF_CRC_FLAG 0x40 /* BIT 6 */ -#define NEAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data) -#define NEAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data) -#define NEAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data) -#define NEAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data) -#define NEAREND_PERF_RSCORR_FLAG 0x80 /* BIT 7 */ -#define NEAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 6, 0, 1, data) -#define NEAREND_PERF_FECS_FLAG 0x100 /* BIT 8 */ -#define NEAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data) -#define NEAREND_PERF_ES_FLAG 0x200 /* BIT 9 */ -#define NEAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data) -#define NEAREND_PERF_SES_FLAG 0x400 /* BIT 10 */ -#define NEAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 9, 0, 1, data) -#define NEAREND_PERF_LOSS_FLAG 0x800 /* BIT 11 */ -#define NEAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data) -#define NEAREND_PERF_UAS_FLAG 0x1000 /* BIT 12 */ -#define NEAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 0, 2, data) -#define NEAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 2, 2, data) -#define NEAREND_PERF_HECERR_FLAG 0x2000 /* BIT 13 */ - -/* adslFarEndPerformanceStats Flags */ -#define FAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data) -#define FAREND_PERF_LOS_FLAG 0x1 /* BIT 0th position */ -#define FAREND_PERF_LOF_FLAG 0x2 /* BIT 1 */ -#define FAREND_PERF_LPR_FLAG 0x4 /* BIT 2 */ -#define FAREND_PERF_NCD_FLAG 0x8 /* BIT 3 */ -#define FAREND_PERF_LCD_FLAG 0x10 /* BIT 4 */ -#define FAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 0, 1, data) -#define FAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 1, 1, data) -#define FAREND_PERF_CRC_FLAG 0x20 /* BIT 5 */ -#define FAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 0, 1, data) -#define FAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 1, 1, data) -#define FAREND_PERF_RSCORR_FLAG 0x40 /* BIT 6 */ -#define FAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 32, 0, 1, data) -#define FAREND_PERF_FECS_FLAG 0x80 /* BIT 7 */ -#define FAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data) -#define FAREND_PERF_ES_FLAG 0x100 /* BIT 8 */ -#define FAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data) -#define FAREND_PERF_SES_FLAG 0x200 /* BIT 9 */ -#define FAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 35, 0, 1, data) -#define FAREND_PERF_LOSS_FLAG 0x400 /* BIT 10 */ -#define FAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data) -#define FAREND_PERF_UAS_FLAG 0x800 /* BIT 11 */ -#define FAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 0, 2, data) -#define FAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 2, 2, data) -#define FAREND_PERF_HECERR_FLAG 0x1000 /* BIT 12 */ -// 603221:tc.chen end -/* TR-69 related additional parameters - defines */ -/* Defines for struct adslATURSubcarrierInfo */ -#define NEAREND_HLINSC 0x1 -#define NEAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 71, 2, 1, data) -#define NEAREND_HLINPS 0x2 -#define NEAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 73, idx, size, data) -#define NEAREND_HLOGMT 0x4 -#define NEAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 0, 1, data) -#define NEAREND_HLOGPS 0x8 -#define NEAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 75, idx, size, data) -#define NEAREND_QLNMT 0x10 -#define NEAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 1, 1, data) -#define NEAREND_QLNPS 0x20 -#define NEAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 77, idx, size, data) -#define NEAREND_SNRMT 0x40 -#define NEAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 2, 1, data) -#define NEAREND_SNRPS 0x80 -#define NEAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 78, idx, size, data) -#define NEAREND_BITPS 0x100 -#define NEAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 22, idx, size, data) -#define NEAREND_GAINPS 0x200 -#define NEAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 24, idx, size, data) - -/* Defines for struct adslATUCSubcarrierInfo */ -#define FAREND_HLINSC 0x1 -#define FAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 70, 0, 1, data) -#define FAREND_HLINPS 0x2 -#define FAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 72, idx, size, data) -#define FAREND_HLOGMT 0x4 -#define FAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 0, 1, data) -#define FAREND_HLOGPS 0x8 -#define FAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 74, idx, size, data) -#define FAREND_QLNMT 0x10 -#define FAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 1, 1, data) -#define FAREND_QLNPS 0x20 -#define FAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 76, idx, size, data) -#define FAREND_SNRMT 0x40 -#define FAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 2, 1, data) -#define FAREND_SNRPS 0x80 -#define FAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 10, idx, size, data) -#define FAREND_BITPS 0x100 -#define FAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 23, idx, size, data) -#define FAREND_GAINPS 0x200 -#define FAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 25, idx, size, data) - - -// GET_ADSL_POWER_SPECTRAL_DENSITY -#define NOMPSD_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 0, 1, data) -#define NOMPSD_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 1, 1, data) -#define PCB_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 6, 1, data) -#define PCB_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 7, 1, data) -#define RMSGI_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 10, 1, data) -#define RMSGI_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 11, 1, data) - - -#endif -/////////////////////////////////////////////////Macro Definitions ? FLAG Setting & Testing - -#define SET_FLAG(flags, flag_val) ((*flags) = ((*flags) | flag_val)) -// -- This macro sets the flags with the flag_val. Here flags is passed as a pointer - -#define IS_FLAG_SET(flags, test_flag) (((*flags) & (test_flag)) == (test_flag)? test_flag:0) -// -- This macro verifies whether test_flag has been set in flags. Here flags is passed as a pointer - - -#define CLR_FLAG(flags, flag_bit) ((*flags) = (*flags) & (~flag_bit)) -// -- This macro resets the specified flag_bit in the flags. Here flags is passed as a pointer - - -////////////////////////////////////////////////DATA STRUCTURES ORGANIZATION - -//Here are the data structures used for accessing mib parameters. The ioctl call includes the third parameter as a void pointer. This parameter has to be type-casted in the driver code to the corresponding structure depending upon the command type. For Ex: consider the ioctl used to get the adslLineCode type, ioctl(fd,GET_ADSL_LINE_CODE,void *struct_adslLineTableEntry). In the driver code we check on the type of the command, i.e GET_ADSL_LINE_CODE and type-cast the void pointer to struct adslLineTableEntry type. - // -#define u32 unsigned int -#define u16 unsigned short -#define s16 short -#define u8 unsigned char - - -typedef u32 AdslPerfTimeElapsed; -typedef u32 AdslPerfPrevDayCount; -typedef u32 PerfCurrentCount; -typedef u32 PerfIntervalCount; -typedef u32 AdslPerfCurrDayCount; - - -//ioctl(int fd, GET_ADSL_LINE_CODE, void *struct_adslLineTableEntry) - -typedef struct adslLineTableEntry { - int ifIndex; - int adslLineCode; - u8 flags; -} adslLineTableEntry; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct adslLineExtTableEntry { - int ifIndex; - u16 adslLineTransAtucCap; - u16 adslLineTransAtucConfig; - u16 adslLineTransAtucActual; - int adslLineGlitePowerState; - u32 flags; -}adslLineExtTableEntry; -#endif -//ioctl(int fd, GET_ADSL_ATUC_PHY, void *struct_adslAtucPhysEntry) - -typedef struct adslVendorId { - u16 country_code; - u_char provider_id[4]; /* Ascii characters */ - u_char revision_info[2]; -}adslVendorId; - - -typedef struct adslAtucPhysEntry { - int ifIndex; - char serial_no[32]; - union { - char vendor_id[16]; - adslVendorId vendor_info; - } vendor_id; - - char version_no[16]; - u32 status; - int outputPwr; - u32 attainableRate; - u8 flags; -} adslAtucPhysEntry; - - -//ioctl(int fd, GET_ADSL_ATUR_PHY, void *struct_adslAturPhysEntry) - -typedef struct adslAturPhysEntry { - int ifIndex; - char serial_no[32]; - union { - char vendor_id[16]; - adslVendorId vendor_info; - } vendor_id; - char version_no[16]; - int SnrMgn; - u32 Attn; - u32 status; - int outputPwr; - u32 attainableRate; - u8 flags; -} adslAturPhysEntry; - - -//ioctl(int fd, GET_ADSL_ATUC_CHAN_INFO, void *struct_adslAtucChanInfo) - -typedef struct adslAtucChanInfo { - int ifIndex; - u32 interleaveDelay; - u32 currTxRate; - u32 prevTxRate; - u8 flags; -} adslAtucChanInfo; - - -//ioctl(int fd, GET_ADSL_ATUR_CHAN_INFO, void *struct_adslAturChanInfo) - -typedef struct adslAturChanInfo { - int ifIndex; - u32 interleaveDelay; - u32 currTxRate; - u32 prevTxRate; - u32 crcBlkLen; - u8 flags; -} adslAturChanInfo; - - -//ioctl(int fd, GET_ADSL_ATUC_PERF_DATA, void *struct_atucPerfDataEntry) - -typedef struct atucPerfDataEntry -{ - int ifIndex; - u32 adslAtucPerfLofs; - u32 adslAtucPerfLoss; - u32 adslAtucPerfESs; - u32 adslAtucPerfInits; - int adslAtucPerfValidIntervals; - int adslAtucPerfInvalidIntervals; - AdslPerfTimeElapsed adslAtucPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAtucPerfCurr15MinLofs; - PerfCurrentCount adslAtucPerfCurr15MinLoss; - PerfCurrentCount adslAtucPerfCurr15MinESs; - PerfCurrentCount adslAtucPerfCurr15MinInits; - AdslPerfTimeElapsed adslAtucPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAtucPerfCurr1DayLofs; - AdslPerfCurrDayCount adslAtucPerfCurr1DayLoss; - AdslPerfCurrDayCount adslAtucPerfCurr1DayESs; - AdslPerfCurrDayCount adslAtucPerfCurr1DayInits; - int adslAtucPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAtucPerfPrev1DayLofs; - AdslPerfPrevDayCount adslAtucPerfPrev1DayLoss; - AdslPerfPrevDayCount adslAtucPerfPrev1DayESs; - AdslPerfPrevDayCount adslAtucPerfPrev1DayInits; - u32 flags; -} atucPerfDataEntry; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct atucPerfDataExtEntry - { - int ifIndex; - u32 adslAtucPerfStatFastR; - u32 adslAtucPerfStatFailedFastR; - u32 adslAtucPerfStatSesL; - u32 adslAtucPerfStatUasL; - u32 adslAtucPerfCurr15MinFastR; - u32 adslAtucPerfCurr15MinFailedFastR; - u32 adslAtucPerfCurr15MinSesL; - u32 adslAtucPerfCurr15MinUasL; - u32 adslAtucPerfCurr1DayFastR; - u32 adslAtucPerfCurr1DayFailedFastR; - u32 adslAtucPerfCurr1DaySesL; - u32 adslAtucPerfCurr1DayUasL; - u32 adslAtucPerfPrev1DayFastR; - u32 adslAtucPerfPrev1DayFailedFastR; - u32 adslAtucPerfPrev1DaySesL; - u32 adslAtucPerfPrev1DayUasL; - u32 flags; -} atucPerfDataExtEntry; - -#endif -//ioctl(int fd, GET_ADSL_ATUR_PERF_DATA, void *struct_aturPerfDataEntry) - -typedef struct aturPerfDataEntry -{ - int ifIndex; - u32 adslAturPerfLofs; - u32 adslAturPerfLoss; - u32 adslAturPerfLprs; - u32 adslAturPerfESs; - int adslAturPerfValidIntervals; - int adslAturPerfInvalidIntervals; - AdslPerfTimeElapsed adslAturPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAturPerfCurr15MinLofs; - PerfCurrentCount adslAturPerfCurr15MinLoss; - PerfCurrentCount adslAturPerfCurr15MinLprs; - PerfCurrentCount adslAturPerfCurr15MinESs; - AdslPerfTimeElapsed adslAturPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAturPerfCurr1DayLofs; - AdslPerfCurrDayCount adslAturPerfCurr1DayLoss; - AdslPerfCurrDayCount adslAturPerfCurr1DayLprs; - AdslPerfCurrDayCount adslAturPerfCurr1DayESs; - int adslAturPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAturPerfPrev1DayLofs; - AdslPerfPrevDayCount adslAturPerfPrev1DayLoss; - AdslPerfPrevDayCount adslAturPerfPrev1DayLprs; - AdslPerfPrevDayCount adslAturPerfPrev1DayESs; - u32 flags; -} aturPerfDataEntry; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct aturPerfDataExtEntry - { - int ifIndex; - u32 adslAturPerfStatSesL; - u32 adslAturPerfStatUasL; - u32 adslAturPerfCurr15MinSesL; - u32 adslAturPerfCurr15MinUasL; - u32 adslAturPerfCurr1DaySesL; - u32 adslAturPerfCurr1DayUasL; - u32 adslAturPerfPrev1DaySesL; - u32 adslAturPerfPrev1DayUasL; - u32 flags; -} aturPerfDataExtEntry; -#endif -//ioctl(int fd, GET_ADSL_ATUC_INTVL_INFO, void *struct_adslAtucInvtInfo) - -typedef struct adslAtucIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount intervalLOF; - PerfIntervalCount intervalLOS; - PerfIntervalCount intervalES; - PerfIntervalCount intervalInits; - int intervalValidData; - u8 flags; -} adslAtucIntvlInfo; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct adslAtucInvtlExtInfo - { - int ifIndex; - int IntervalNumber; - u32 adslAtucIntervalFastR; - u32 adslAtucIntervalFailedFastR; - u32 adslAtucIntervalSesL; - u32 adslAtucIntervalUasL; - u32 flags; -} adslAtucInvtlExtInfo; -#endif -//ioctl(int fd, GET_ADSL_ATUR_INTVL_INFO, void *struct_adslAturInvtlInfo) - -typedef struct adslAturIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount intervalLOF; - PerfIntervalCount intervalLOS; - PerfIntervalCount intervalLPR; - PerfIntervalCount intervalES; - int intervalValidData; - u8 flags; -} adslAturIntvlInfo; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct adslAturInvtlExtInfo - { - int ifIndex; - int IntervalNumber; - u32 adslAturIntervalSesL; - u32 adslAturIntervalUasL; - u32 flags; -} adslAturInvtlExtInfo; -#endif -//ioctl(int fd, GET_ADSL_ATUC_CHAN_PERF_DATA, void *struct_atucChannelPerfDataEntry) - -typedef struct atucChannelPerfDataEntry -{ - int ifIndex; - u32 adslAtucChanReceivedBlks; - u32 adslAtucChanTransmittedBlks; - u32 adslAtucChanCorrectedBlks; - u32 adslAtucChanUncorrectBlks; - int adslAtucChanPerfValidIntervals; - int adslAtucChanPerfInvalidIntervals; - AdslPerfTimeElapsed adslAtucChanPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAtucChanPerfCurr15MinReceivedBlks; - PerfCurrentCount adslAtucChanPerfCurr15MinTransmittedBlks; - PerfCurrentCount adslAtucChanPerfCurr15MinCorrectedBlks; - PerfCurrentCount adslAtucChanPerfCurr15MinUncorrectBlks; - AdslPerfTimeElapsed adslAtucChanPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayReceivedBlks; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayTransmittedBlks; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayCorrectedBlks; - AdslPerfCurrDayCount adslAtucChanPerfCurr1DayUncorrectBlks; - int adslAtucChanPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayReceivedBlks; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayTransmittedBlks; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayCorrectedBlks; - AdslPerfPrevDayCount adslAtucChanPerfPrev1DayUncorrectBlks; - u32 flags; -}atucChannelPerfDataEntry; - - -//ioctl(int fd, GET_ADSL_ATUR_CHAN_PERF_DATA, void *struct_aturChannelPerfDataEntry) - -typedef struct aturChannelPerfDataEntry -{ - int ifIndex; - u32 adslAturChanReceivedBlks; - u32 adslAturChanTransmittedBlks; - u32 adslAturChanCorrectedBlks; - u32 adslAturChanUncorrectBlks; - int adslAturChanPerfValidIntervals; - int adslAturChanPerfInvalidIntervals; - AdslPerfTimeElapsed adslAturChanPerfCurr15MinTimeElapsed; - PerfCurrentCount adslAturChanPerfCurr15MinReceivedBlks; - PerfCurrentCount adslAturChanPerfCurr15MinTransmittedBlks; - PerfCurrentCount adslAturChanPerfCurr15MinCorrectedBlks; - PerfCurrentCount adslAturChanPerfCurr15MinUncorrectBlks; - AdslPerfTimeElapsed adslAturChanPerfCurr1DayTimeElapsed; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayReceivedBlks; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayTransmittedBlks; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayCorrectedBlks; - AdslPerfCurrDayCount adslAturChanPerfCurr1DayUncorrectBlks; - int adslAturChanPerfPrev1DayMoniSecs; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayReceivedBlks; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayTransmittedBlks; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayCorrectedBlks; - AdslPerfPrevDayCount adslAturChanPerfPrev1DayUncorrectBlks; - u32 flags; -} aturChannelPerfDataEntry; - - -//ioctl(int fd, GET_ADSL_ATUC_CHAN_INTVL_INFO, void *struct_adslAtucChanIntvlInfo) - -typedef struct adslAtucChanIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount chanIntervalRecvdBlks; - PerfIntervalCount chanIntervalXmitBlks; - PerfIntervalCount chanIntervalCorrectedBlks; - PerfIntervalCount chanIntervalUncorrectBlks; - int intervalValidData; - u8 flags; -} adslAtucChanIntvlInfo; - - -//ioctl(int fd, GET_ADSL_ATUR_CHAN_INTVL_INFO, void *struct_adslAturChanIntvlInfo) - -typedef struct adslAturChanIntvlInfo { - int ifIndex; - int IntervalNumber; - PerfIntervalCount chanIntervalRecvdBlks; - PerfIntervalCount chanIntervalXmitBlks; - PerfIntervalCount chanIntervalCorrectedBlks; - PerfIntervalCount chanIntervalUncorrectBlks; - int intervalValidData; - u8 flags; -} adslAturChanIntvlInfo; - - -//ioctl(int fd, GET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry) -//ioctl(int fd, SET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry) - -typedef struct adslLineAlarmConfProfileEntry - { - unsigned char adslLineAlarmConfProfileName[32]; - int adslAtucThresh15MinLofs; - int adslAtucThresh15MinLoss; - int adslAtucThresh15MinESs; - u32 adslAtucThreshFastRateUp; - u32 adslAtucThreshInterleaveRateUp; - u32 adslAtucThreshFastRateDown; - u32 adslAtucThreshInterleaveRateDown; - int adslAtucInitFailureTrapEnable; - int adslAturThresh15MinLofs; - int adslAturThresh15MinLoss; - int adslAturThresh15MinLprs; - int adslAturThresh15MinESs; - u32 adslAturThreshFastRateUp; - u32 adslAturThreshInterleaveRateUp; - u32 adslAturThreshFastRateDown; - u32 adslAturThreshInterleaveRateDown; - int adslLineAlarmConfProfileRowStatus; - u32 flags; -} adslLineAlarmConfProfileEntry; - -#ifdef AMAZON_MEI_MIB_RFC3440 -typedef struct adslLineAlarmConfProfileExtEntry - { - u8 adslLineAlarmConfProfileExtName[32]; - u32 adslAtucThreshold15MinFailedFastR; - u32 adslAtucThreshold15MinSesL; - u32 adslAtucThreshold15MinUasL; - u32 adslAturThreshold15MinSesL; - u32 adslAturThreshold15MinUasL; - u32 flags; -} adslLineAlarmConfProfileExtEntry; -#endif -//TRAPS - -// 603221:tc.chen start -/* The following Data Sturctures are added to support the WEB related parameters for ADSL Statistics */ -typedef struct adslLineStatus - { - int adslModemStatus; - u32 adslModeSelected; - int adslAtucThresh15MinESs; - int adslTrellisCodeEnable; - int adslLatency; - u8 flags; - } adslLineStatusInfo; - -typedef struct adslLineRate - { - u32 adslDataRateds; - u32 adslDataRateus; - u32 adslATTNDRds; - u32 adslATTNDRus; - u8 flags; - } adslLineRateInfo; - -typedef struct adslLineInfo - { - u32 adslInterleaveDepthds; - u32 adslInterleaveDepthus; - u32 adslLATNds; - u32 adslLATNus; - u32 adslSATNds; - u32 adslSATNus; - int adslSNRMds; - int adslSNRMus; - int adslACATPds; - int adslACATPus; - u32 flags; - } adslLineInfo; - -typedef struct adslNearEndPerfStats - { - u32 adslSuperFrames; - u32 adslneLOS; - u32 adslneLOF; - u32 adslneLPR; - u32 adslneNCD; - u32 adslneLCD; - u32 adslneCRC; - u32 adslneRSCorr; - u32 adslneFECS; - u32 adslneES; - u32 adslneSES; - u32 adslneLOSS; - u32 adslneUAS; - u32 adslneHECErrors; - u32 flags; - } adslNearEndPerfStats; - -typedef struct adslFarEndPerfStats - { - u32 adslfeLOS; - u32 adslfeLOF; - u32 adslfeLPR; - u32 adslfeNCD; - u32 adslfeLCD; - u32 adslfeCRC; - u32 adslfeRSCorr; - u32 adslfeFECS; - u32 adslfeES; - u32 adslfeSES; - u32 adslfeLOSS; - u32 adslfeUAS; - u32 adslfeHECErrors; - u32 flags; - } adslFarEndPerfStats; -// 603221:tc.chen end - -/* The number of tones (and hence indexes) is dependent on the ADSL mode - G.992.1, G.992.2, G.992.3, * G.992.4 and G.992.5 */ -typedef struct adslATURSubcarrierInfo { - int ifindex; - u16 HLINSCds; - u16 HLINpsds[1024];/* Even index = real part; Odd Index - = imaginary part for each tone */ - u16 HLOGMTds; - u16 HLOGpsds[512]; - u16 QLNMTds; - u16 QLNpsds[512]; - u16 SNRMTds; - u16 SNRpsds[512]; - u16 BITpsds[512]; - u16 GAINpsds[512]; - u16 flags; -}adslATURSubcarrierInfo; - -typedef struct adslATUCSubcarrierInfo { - int ifindex; - u16 HLINSCus; - u16 HLINpsus[128];/* Even index = real part; Odd Index - = imaginary part for each tone */ - u16 HLOGMTus; - u16 HLOGpsus[64]; - u16 QLNMTus; - u16 QLNpsus[64]; - u16 SNRMTus; - u16 SNRpsus[64]; - u16 BITpsus[64]; - u16 GAINpsus[64]; - u16 flags; -}adslATUCSubcarrierInfo; - -#ifndef u_int16 -#define u_int16 u16 -#endif - -typedef struct adslInitStats { - u_int16 FullInitializationCount; - u_int16 FailedFullInitializationCount; - u_int16 LINIT_Errors; - u_int16 Init_Timeouts; -}adslInitStats; - -typedef struct adslPowerSpectralDensity { - int ACTPSDds; - int ACTPSDus; -}adslPowerSpectralDensity; - - -//ioctl(int fd, ADSL_ATUR_TRAPS, void *uint16_flags) -typedef union structpts { - adslLineTableEntry * adslLineTableEntry_pt; - adslAtucPhysEntry * adslAtucPhysEntry_pt; - adslAturPhysEntry * adslAturPhysEntry_pt; - adslAtucChanInfo * adslAtucChanInfo_pt; - adslAturChanInfo * adslAturChanInfo_pt; - atucPerfDataEntry * atucPerfDataEntry_pt; - aturPerfDataEntry * aturPerfDataEntry_pt; - adslAtucIntvlInfo * adslAtucIntvlInfo_pt; - adslAturIntvlInfo * adslAturIntvlInfo_pt; - atucChannelPerfDataEntry * atucChannelPerfDataEntry_pt; - aturChannelPerfDataEntry * aturChannelPerfDataEntry_pt; - adslAtucChanIntvlInfo * adslAtucChanIntvlInfo_pt; - adslAturChanIntvlInfo * adslAturChanIntvlInfo_pt; - adslLineAlarmConfProfileEntry * adslLineAlarmConfProfileEntry_pt; - // RFC 3440 - - #ifdef AMAZON_MEI_MIB_RFC3440 - adslLineExtTableEntry * adslLineExtTableEntry_pt; - atucPerfDataExtEntry * atucPerfDataExtEntry_pt; - adslAtucInvtlExtInfo * adslAtucInvtlExtInfo_pt; - aturPerfDataExtEntry * aturPerfDataExtEntry_pt; - adslAturInvtlExtInfo * adslAturInvtlExtInfo_pt; - adslLineAlarmConfProfileExtEntry * adslLineAlarmConfProfileExtEntry_pt; - #endif -// 603221:tc.chen start - adslLineStatusInfo * adslLineStatusInfo_pt; - adslLineRateInfo * adslLineRateInfo_pt; - adslLineInfo * adslLineInfo_pt; - adslNearEndPerfStats * adslNearEndPerfStats_pt; - adslFarEndPerfStats * adslFarEndPerfStats_pt; -// 603221:tc.chen end - adslATUCSubcarrierInfo * adslATUCSubcarrierInfo_pt; - adslATURSubcarrierInfo * adslATURSubcarrierInfo_pt; - adslPowerSpectralDensity * adslPowerSpectralDensity_pt; -}structpts; - -#endif /* ] __AMAZON_MEI_APP_IOCTL_H */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_ioctl.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_ioctl.h deleted file mode 100644 index 02a150eac..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_ioctl.h +++ /dev/null @@ -1,757 +0,0 @@ -//509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl -#ifndef _AMAZON_MEI_IOCTL_H -#define _AMAZON_MEI_IOCTL_H - -///////////////////////////////////////////////////////////////////////////////////////////////////// -#define PCM_BUFF_SIZE 1024 //bytes -// interrupt numbers - -#ifndef _AMAZON_ADSL_APP - -typedef struct pcm_data_struct{ - u16 S; - u16 temp; - u16 LSW; - u16 MSW; - u16 len; - u16 rdindex; - u16 wrindex; - u16 flow; - - int finish; - u8 buff[PCM_BUFF_SIZE]; - int point; -}pcm_data_struct; - -typedef struct amazon_clreoc_pkt{ - struct list_head list; - u8 * command; //point to clreoc command data - int len; //command length -}amazon_clreoc_pkt; - -// Number of intervals -#define INTERVAL_NUM 192 //two days -typedef struct amazon_mei_mib{ - struct list_head list; - struct timeval start_time; //start of current interval - - int AtucPerfLof; - int AtucPerfLos; - int AtucPerfEs; - int AtucPerfInit; - - int AturPerfLof; - int AturPerfLos; - int AturPerfLpr; - int AturPerfEs; - - int AturChanPerfRxBlk; - int AturChanPerfTxBlk; - int AturChanPerfCorrBlk; - int AturChanPerfUncorrBlk; - - //RFC-3440 - int AtucPerfStatFastR; - int AtucPerfStatFailedFastR; - int AtucPerfStatSesL; - int AtucPerfStatUasL; - int AturPerfStatSesL; - int AturPerfStatUasL; -}amazon_mei_mib; - -typedef struct adslChanPrevTxRate{ - u32 adslAtucChanPrevTxRate; - u32 adslAturChanPrevTxRate; -}adslChanPrevTxRate; - -typedef struct adslPhysCurrStatus{ - u32 adslAtucCurrStatus; - u32 adslAturCurrStatus; -}adslPhysCurrStatus; - -typedef struct ChanType{ - int interleave; - int fast; -// 603221:tc.chen start - int bearchannel0; - int bearchannel1; -// 603221:tc.chen end -}ChanType; - -typedef struct mib_previous_read{ - u16 ATUC_PERF_ESS; - u16 ATUR_PERF_ESS; - u32 ATUR_CHAN_RECV_BLK; - u16 ATUR_CHAN_CORR_BLK_INTL; - u16 ATUR_CHAN_CORR_BLK_FAST; - u16 ATUR_CHAN_UNCORR_BLK_INTL; - u16 ATUR_CHAN_UNCORR_BLK_FAST; - u16 ATUC_PERF_STAT_FASTR; - u16 ATUC_PERF_STAT_FAILED_FASTR; - u16 ATUC_PERF_STAT_SESL; - u16 ATUC_PERF_STAT_UASL; - u16 ATUR_PERF_STAT_SESL; -}mib_previous_read; - -typedef struct mib_flags_pretime{ - struct timeval ATUC_PERF_LOSS_PTIME; - struct timeval ATUC_PERF_LOFS_PTIME; - struct timeval ATUR_PERF_LOSS_PTIME; - struct timeval ATUR_PERF_LOFS_PTIME; - struct timeval ATUR_PERF_LPR_PTIME; -}mib_flags_pretime; - - // cmv message structures -#define MP_PAYLOAD_SIZE 12 -typedef struct mpmessage{ - u16 iFunction; - u16 iGroup; - u16 iAddress; - u16 iIndex; - u16 iPayload[MP_PAYLOAD_SIZE]; -}MPMessage; -#endif - - -typedef struct meireg{ - u32 iAddress; - u32 iData; -}meireg; - -#define MEIDEBUG_BUFFER_SIZES 50 -typedef struct meidebug{ - u32 iAddress; - u32 iCount; - u32 buffer[MEIDEBUG_BUFFER_SIZES]; -}meidebug; - -//============================================================================== -// Group definitions -//============================================================================== -#define OPTN 5 -#define CNFG 8 -#define CNTL 1 -#define STAT 2 -#define RATE 6 -#define PLAM 7 -#define INFO 3 -#define TEST 4 -//============================================================================== -// Opcode definitions -//============================================================================== -#define H2D_CMV_READ 0x00 -#define H2D_CMV_WRITE 0x04 -#define H2D_CMV_INDICATE_REPLY 0x10 -#define H2D_ERROR_OPCODE_UNKNOWN 0x20 -#define H2D_ERROR_CMV_UNKNOWN 0x30 - -#define D2H_CMV_READ_REPLY 0x01 -#define D2H_CMV_WRITE_REPLY 0x05 -#define D2H_CMV_INDICATE 0x11 -#define D2H_ERROR_OPCODE_UNKNOWN 0x21 -#define D2H_ERROR_CMV_UNKNOWN 0x31 -#define D2H_ERROR_CMV_READ_NOT_AVAILABLE 0x41 -#define D2H_ERROR_CMV_WRITE_ONLY 0x51 -#define D2H_ERROR_CMV_READ_ONLY 0x61 - -#define H2D_DEBUG_READ_DM 0x02 -#define H2D_DEBUG_READ_PM 0x06 -#define H2D_DEBUG_WRITE_DM 0x0a -#define H2D_DEBUG_WRITE_PM 0x0e - -#define D2H_DEBUG_READ_DM_REPLY 0x03 -#define D2H_DEBUG_READ_FM_REPLY 0x07 -#define D2H_DEBUG_WRITE_DM_REPLY 0x0b -#define D2H_DEBUG_WRITE_FM_REPLY 0x0f -#define D2H_ERROR_ADDR_UNKNOWN 0x33 - -#define D2H_AUTONOMOUS_MODEM_READY_MSG 0xf1 -//============================================================================== -// INFO register address field definitions -//============================================================================== - -#define INFO_TxState 0 -#define INFO_RxState 1 -#define INFO_TxNextState 2 -#define INFO_RxNextState 3 -#define INFO_TxStateJumpFrom 4 -#define INFO_RxStateJumpFrom 5 - -#define INFO_ReverbSnrBuf 8 -#define INFO_ReverbEchoSnrBuf 9 -#define INFO_MedleySnrBuf 10 -#define INFO_RxShowtimeSnrBuf 11 -#define INFO_DECdelay 12 -#define INFO_DECExponent 13 -#define INFO_DECTaps 14 -#define INFO_AECdelay 15 -#define INFO_AECExponent 16 -#define INFO_AECTaps 17 -#define INFO_TDQExponent 18 -#define INFO_TDQTaps 19 -#define INFO_FDQExponent 20 -#define INFO_FDQTaps 21 -#define INFO_USBat 22 -#define INFO_DSBat 23 -#define INFO_USFineGains 24 -#define INFO_DSFineGains 25 -#define INFO_BitloadFirstChannel 26 -#define INFO_BitloadLastChannel 27 -#define INFO_PollEOCData 28 // CO specific -#define INFO_CSNRMargin 29 // CO specific -#define INFO_RCMsgs1 30 -#define INFO_RMsgs1 31 -#define INFO_RMsgRA 32 -#define INFO_RCMsgRA 33 -#define INFO_RMsg2 34 -#define INFO_RCMsg2 35 -#define INFO_BitLoadOK 36 -#define INFO_RCRates1 37 -#define INFO_RRates1Tab 38 -#define INFO_RMsgs1Tab 39 -#define INFO_RMsgRATab 40 -#define INFO_RRatesRA 41 -#define INFO_RCRatesRA 42 -#define INFO_RRates2 43 -#define INFO_RCRates2 44 -#define INFO_PackedRMsg2 45 -#define INFO_RxBitSwapFlag 46 -#define INFO_TxBitSwapFlag 47 -#define INFO_ShowtimeSNRUpdateCount 48 -#define INFO_ShowtimeFDQUpdateCount 49 -#define INFO_ShowtimeDECUpdateCount 50 -#define INFO_CopyRxBuffer 51 -#define INFO_RxToneBuf 52 -#define INFO_TxToneBuf 53 -#define INFO_Version 54 -#define INFO_TimeStamp 55 -#define INFO_feVendorID 56 -#define INFO_feSerialNum 57 -#define INFO_feVersionNum 58 -#define INFO_BulkMemory 59 //Points to start of bulk memory -#define INFO_neVendorID 60 -#define INFO_neVersionNum 61 -#define INFO_neSerialNum 62 - -//============================================================================== -// RATE register address field definitions -//============================================================================== - - -#define RATE_UsRate 0 -#define RATE_DsRate 1 - - -//============================================================================== -// PLAM (Physical Layer Management) register address field definitions -// (See G997.1 for reference) -//============================================================================== - - - // /// - // Failure Flags /// - // /// - -#define PLAM_NearEndFailureFlags 0 -#define PLAM_FarEndFailureFlags 1 - - // /// - // Near End Failure Flags Bit Definitions /// - // /// - -// ADSL Failures /// -#define PLAM_LOS_FailureBit 0x0001 -#define PLAM_LOF_FailureBit 0x0002 -#define PLAM_LPR_FailureBit 0x0004 -#define PLAM_RFI_FailureBit 0x0008 - -// ATM Failures /// -#define PLAM_NCD_LP0_FailureBit 0x0010 -#define PLAM_NCD_LP1_FailureBit 0x0020 -#define PLAM_LCD_LP0_FailureBit 0x0040 -#define PLAM_LCD_LP1_FailureBit 0x0080 - -#define PLAM_NCD_BC0_FailureBit 0x0100 -#define PLAM_NCD_BC1_FailureBit 0x0200 -#define PLAM_LCD_BC0_FailureBit 0x0400 -#define PLAM_LCD_BC1_FailureBit 0x0800 - // /// - // Performance Counts /// - // /// - -#define PLAM_NearEndCrcCnt 2 -#define PLAM_CorrectedRSErrors 3 - -#define PLAM_NearEndECSCnt 6 -#define PLAM_NearEndESCnt 7 -#define PLAM_NearEndSESCnt 8 -#define PLAM_NearEndLOSSCnt 9 -#define PLAM_NearEndUASLCnt 10 - -#define PLAM_NearEndHECErrCnt 11 - -#define PLAM_NearEndHECTotCnt 16 -#define PLAM_NearEndCellTotCnt 18 -#define PLAM_NearEndSfCntLSW 20 -#define PLAM_NearEndSfCntMSW 21 - -#define PLAM_FarEndFebeCnt 24 - -#define PLAM_FarEndFecCnt 28 - -#define PLAM_FarEndFECSCnt 32 -#define PLAM_FarEndESCnt 33 -#define PLAM_FarEndSESCnt 34 -#define PLAM_FarEndLOSSCnt 35 -#define PLAM_FarEndUASLCnt 36 - -#define PLAM_FarEndHECErrCnt 37 - -#define PLAM_FarEndHECTotCnt 41 - -#define PLAM_FarEndCellTotCnt 43 - -#define PLAM_LineAttn 45 -#define PLAM_SNRMargin 46 - - -//============================================================================== -// CNTL register address and bit field definitions -//============================================================================== - - -#define CNTL_ModemControl 0 - -#define CNTL_ModemReset 0x0 -#define CNTL_ModemStart 0x2 - - -//============================================================================== -// STAT register address and bit field definitions -//============================================================================== - -#define STAT_MacroState 0 -#define STAT_Mode 1 -#define STAT_DMTFramingMode 2 -#define STAT_SleepState 3 -#define STAT_Misc 4 -#define STAT_FailureState 5 - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // STAT_OLRStatus provides status of OLR - //16-bit STAT_OLRStatus_DS - // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted - // [3:2]: Reserved - // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA) - // [7:6]: Reserved - // [10:8]: >0=Request. 0=not. For DS, # of request transmissions/retransmissions (3 bits). - // [11]: 1=Receive Response, 0=not - // [15:12]: Reserved - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /// -#define STAT_OLRStatus_DS 6 - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // STAT_OLRStatus provides status of OLR - // 16-bit STAT_OLRStatus_US CMV - // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted - // [3:2]: Reserved - // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA) - // [7:6]: Reserved - // [8]: 1=Request Received. 0=not. - // [10:9]: Reserved - // [11]: 1=Response Sent, 0=not - // [15:12]: Reserved - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/// -#define STAT_OLRStatus_US 7 - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // STAT_PMStatus provides status of PM - // 16-bit STAT_PMStatus CMV - // [1:0] : PM Status 00=IDLE, 01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted - // [2] : 0=ATU_R initiated PM; 1 = ATU_C initiated PM - // [3]: Reserved - // [5:4]: PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim) - // [7:6]: Reserved - // [10:8]: >0=Request. 0=not. # of request transmissions/retransmissions (3 bits). - // [11]: 1=Response, 0=not - // [15:12]: Reserved - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /// -#define STAT_PMStatus 8 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError - // [3:0]: OLR/PM response reason code - // [7:4]: OLR/PM Internal error code - // [15:8]: OLR/PM Reserved for future - ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - /// -#define STAT_OLRError_DS 9 -#define STAT_OLRError_US 10 -#define STAT_PMError 11 - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_MacroState -// MacroState reflects the high level state of the modem - -#define STAT_InitState 0x0000 -#define STAT_ReadyState 0x0001 -#define STAT_FailState 0x0002 -#define STAT_IdleState 0x0003 -#define STAT_QuietState 0x0004 -#define STAT_GhsState 0x0005 -#define STAT_FullInitState 0x0006 -#define STAT_ShowTimeState 0x0007 -#define STAT_FastRetrainState 0x0008 -#define STAT_LoopDiagMode 0x0009 -#define STAT_ShortInit 0x000A // Bis short initialization /// - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_Mode -// ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use -// G.Hs or some other mechanism to negotiate the specific mode of operation. -// The OPTN_modeControl CMV is used to select a set of desired modes. -// The STAT_Mode CMV indicates which mode was actually selected. - -#define STAT_ConfigMode_T1413 0x0001 -#define STAT_ConfigMode_G992_2_AB 0x0002 -#define STAT_ConfigMode_G992_1_A 0x0004 -#define STAT_ConfigMode_G992_1_B 0x0008 -#define STAT_ConfigMode_G992_1_C 0x0010 -#define STAT_ConfigMode_G992_2_C 0x0020 - -#define STAT_ConfigMode_G992_3_A 0x0100 -#define STAT_ConfigMode_G992_3_B 0x0200 -#define STAT_ConfigMode_G992_3_I 0x0400 -#define STAT_ConfigMode_G992_3_J 0x0800 -#define STAT_ConfigMode_G992_3_L 0x1000 - -#define STAT_ConfigMode_G992_4_A 0x2000 -#define STAT_ConfigMode_G992_4_I 0x4000 - -#define STAT_ConfigMode_G992_5 0x8000 - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_DMTFramingMode -// FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode -// status is not applicable in BIS mode and its value is undefined -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define STAT_FramingModeMask 0x0003 - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_Misc -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define STAT_OverlappedSpectrum 0x0008 -#define STAT_TCM 0x0010 -#define STAT_TDQ_at_1104 0x0020 -#define STAT_T1413_Signal_Detected 0x0040 -#define STAT_AnnexL_US_Mask1_PSD 0x1000 //indicate we actually selected G992.3 AnnexL US PSD mask1 -#define STAT_AnnexL_US_Mask2_PSD 0x2000 //indicate we actually selected G992.3 AnnexL US PSD mask2 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STAT_FailureState -// when the MacroSTate indicates the fail state, FailureState provides a failure code -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -#define E_CODE_NO_ERROR 0 -#define E_CODE_BAT_TX 1 // TX BAT table is incorrect */ -#define E_CODE_BAT_RX 2 // RX BAT table is incorrect */ -#define E_CODE_PROFILE 3 // profile is not selected in fast retrain */ -#define E_CODE_TX_AOC_FIFO_OVERFLOW 4 -#define E_CODE_TRUNCATE_FR 5 //Fast Retrain truncated due to no stored profiles*/ -#define E_CODE_BITLOAD 6 // bit loading fails */ -#define E_CODE_ST_ERROR 7 // showtime CRC error */ -#define E_CODE_RESERVED 8 // using parameters reserved by the ITU-T */ -#define E_CODE_C_TONES 9 // detected C_TONES */ -#define E_CODE_CODESWAP_ERR 10 // codeswap not finished in time */ -#define E_CODE_FIFO_OVERFLOW 11 // we have run out of fifo space */ -#define E_CODE_C_BG_DECODE_ERR 12 // error in decoding C-BG message */ -#define E_CODE_C_RATES2_DECODE_ERR 13 // error in decoding C-MSGS2 and C-RATES2 */ -#define E_CODE_RCMedleyRx_C_SEGUE2_Failure 14 // Timeout after RCMedleyRx waiting for C_SEGUE2 */ -#define E_CODE_RReverbRATx_C_SEGUE2_Failure 15 // Timeout after RReverbRATx waiting for C_SEGUE2 */ -#define E_CODE_RReverb3Tx_C_SEGUE1_Failure 16 // Timeout after RReverb3Tx waiting for C_SEGUE1 */ -#define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR 17 // Received CRC not equal to computed CRC */ -#define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR 18 // Received CRC not equal to computed CRC */ -#define E_CODE_RReverb5Tx_C_SEGUE2_Failure 19 // Timeout after RReverb5Tx waiting for C_SEGUE2 */ -#define E_CODE_RReverb6Tx_C_SEGUE3_Failure 20 // Timeout after RReverb6Tx waiting for C_SEGUE3 */ -#define E_CODE_RSegue5Tx_C_SEGUE3_Failure 21 // Timeout after RSegue5Tx waiting for C_SEGUE3 */ -#define E_CODE_RCReverb5Rx_C_SEGUE_Failure 22 // Timeout after RCReverb5Rx waiting for C_SEGUE */ -#define E_CODE_RCReverbRARx_C_SEGUE2_Failure 23 // Timeout after RCReverbRARx waiting for C_SEGUE2 */ -#define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR 24 // Received CRC not equal to computed CRC */ -#define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR 25 // Received CRC not equal to computed CRC */ -#define E_CODE_RCCRC3Rx_DECOD_ERR 26 // Received CRC not equal to computed CRC */ -#define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT 27 // DEC Path Delay timeout */ -#define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT 28 // DEC Training timeout */ -#define E_CODE_RCReverb3Rx_C_SEGUE1_Failure 29 // Timeout after RCReverb3Rx waiting for C_SEGUE1 */ -#define E_CODE_RCReverb2Rx_SignalEnd_Failure 30 // Timeout waiting for the end of RCReverb2Rx signal */ -#define E_CODE_RQuiet2_SignalEnd_Failure 31 // Timeout waiting for the end of RQuiet2 signal */ -#define E_CODE_RCReverbFR1Rx_Failure 32 // Timeout waiting for the end of RCReverbFR1Rx signal */ -#define E_CODE_RCPilotFR1Rx_SignalEnd_Failure 33 // Timeout waiting for the end of RCPilotFR1Rx signal */ -#define E_CODE_RCReverbFR2Rx_C_Segue_Failure 34 // Timeout after RCReverbFR2Rx waiting for C_SEGUE */ -#define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT 35 // Timeout waiting for the end of RCReverbFR5Rx signal */ -#define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure 36 // Timeout after RCReverbFR6Rx waiting for C_SEGUE */ -#define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure 37 // Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */ -#define E_CODE_RCReverbFR8Rx_No_PROFILE 38 // Timeout since no profile was selected */ -#define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT 39 // Timeout waiting for the end of RCReverbFR8Rx signal */ -#define E_CODE_RCCRCFR1_DECOD_ERR 40 // Received CRC not equal to computed CRC */ -#define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT 41 // Timeout waiting for the end of RCRecovRx signal */ -#define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT 42 // Timeout after RSegueFR5Tx waiting for C_SEGUE2 */ -#define E_CODE_RRecovTx_SignalEnd_TIMEOUT 43 // Timeout waiting for the end of RRecovTx signal */ -#define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure 44 // Timeout after RCMedleyFRRx waiting for C_SEGUE2 */ -#define E_CODE_CONFIGURATION_PARAMETERS_ERROR 45 // one of the configuration parameters do not meet the standard */ -#define E_CODE_BAD_MEM_ACCESS 46 -#define E_CODE_BAD_INSTRUCTION_ACCESS 47 -#define E_CODE_TX_EOC_FIFO_OVERFLOW 48 -#define E_CODE_RX_EOC_FIFO_OVERFLOW 49 -#define E_CODE_GHS_CD_FLAG_TIME_OUT 50 // Timeout when transmitting Flag in handshake cleardown */ - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//STAT_OLRStatus: -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define STAT_OLRPM_IDLE 0x0000 -#define STAT_OLRPM_IN_PROGRESS 0x0001 -#define STAT_OLRPM_COMPLETE 0x0002 -#define STAT_OLRPM_ABORTED 0x0003 -#define STAT_OLRPM_RESPONSE 0x0800 - -#define STAT_OLR_BITSWAP 0x0010 -#define STAT_OLR_DRR 0x0020 -#define STAT_OLR_SRA 0x0030 - -//STAT_PMStatus_US: -#define STAT_PM_CO_REQ 0x0004 -#define STAT_PM_SIMPLE_REQ 0x0010 -#define STAT_PM_L2_REQ 0x0020 -#define STAT_PM_L2_TRIM_REQ 0x0030 - -// STAT_OLRError_DS, STAT_OLRError_US -//4 bit response reason code: -#define RESP_BUSY 0x01 -#define RESP_INVALID_PARAMETERS 0x02 -#define RESP_NOT_ENABLED 0x03 -#define RESP_NOT_SUPPORTED 0x04 - -//4 bit internal error code (common for OLR and PM) -#define REQ_INVALID_BiGi 0x10 -#define REQ_INVALID_Lp 0x20 -#define REQ_INVALID_Bpn 0x30 -#define REQ_INVALID_FRAMING_CONSTRAINT 0x40 -#define REQ_NOT_IN_L0_STATE 0x50 -#define REQ_NOT_IN_L2_STATE 0x60 -#define REQ_INVALID_PCB 0x70 -#define REQ_VIOLATES_MARGIN 0x80 - -//STAT_PMError -//4 bit response reason code: -#define RESP_STATE_NOT_DESIRED 0x03 -#define RESP_INFEASIBLE_PARAMETERS 0x04 - - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN register address and bit field definitions -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_ModeControl 0 -#define OPTN_DMTLnkCtl 1 -// Reserved 2 -#define OPTN_GhsControl 3 -// Reserved 4 -#define OPTN_PwrManControl 5 -#define OPTN_AnnexControl 6 -#define OPTN_ModeControl1 7 -// Reserved 8 -#define OPTN_StateMachineCtrl 9 -// Reserved 10 -// Reserved 11 -#define OPTN_BisLinkControl 12 -#define OPTN_ATMAddrConfig 13 -#define OPTN_ATMNumCellConfig 14 - -// Mode control defines the allowable operating modes of an ADSL link. In general, a modem may /// -// use G.Hs or some other mechanism to negotiate the specific mode of operation. /// -// The OPTN_ModeControl CMV is used to select a set of desired modes /// -// The STAT_ModeControl CMV indicates which mode was actually selected /// - -// OPTN_ModeControl -#define OPTN_ConfigMode_T1413 0x0001 -#define OPTN_ConfigMode_G992_2_AB 0x0002 -#define OPTN_ConfigMode_G992_1_A 0x0004 -#define OPTN_ConfigMode_G992_1_B 0x0008 -#define OPTN_ConfigMode_G992_1_C 0x0010 -#define OPTN_ConfigMode_G992_2_C 0x0020 - -#define OPTN_ConfigMode_G992_3_A 0x0100 -#define OPTN_ConfigMode_G992_3_B 0x0200 -#define OPTN_ConfigMode_G992_3_I 0x0400 -#define OPTN_ConfigMode_G992_3_J 0x0800 -#define OPTN_ConfigMode_G992_3_L 0x1000 - -#define OPTN_ConfigMode_G992_4_A 0x2000 -#define OPTN_ConfigMode_G992_4_I 0x4000 - -#define OPTN_ConfigMode_G992_5 0x8000 - -// OPTN_PwrManControl -#define OPTN_PwrManWakeUpGhs 0x1 -#define OPTN_PwrManWakeUpFR 0x2 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_DMT Link Control -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#define OPTN_DMT_DualLatency_Dis 0x200 -#define OPTN_DMT_S_Dis 0x100 -#define OPTN_DMT_FRAMINGMODE 0x1 -#define OPTN_DMT_FRAMINGMODE_MASK 0x7 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_BIS Link Control -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#define OPTN_BisLinkContrl_LineProbeDis 0x1 -#define OPTN_BisLinkContrl_DSBlackBitsEn 0x2 -#define OPTN_BisLinkContrl_DiagnosticModeEn 0x4 -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_GhsControl -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// -// for OPTN_GhsControl, we will assign 16bit word as follows -// bit 0~3: set the control over which start(initial) message CPE will send: -// -// BIT: 2 1 0 -// 0 0 1 CLR -// 0 1 0 MR -// 0 1 1 MS -// 1 0 0 MP -// -// // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange -// BIT: 5 4 -// 0 1 MS -// 1 0 MR -// 1 1 MP -// -// // bit 15: RT initiated G.hs sample sessions one through eight. Session one is default. -// BIT: 15 -// 1 means session one -// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_GHS_ST_GHS 0x8000 -#define OPTN_GHS_INIT_MASK 0x000F -#define OPTN_GHS_RESP_MASK 0x00F0 - -#define OPTN_RTInitTxMsg_CLR 0x0001 -#define OPTN_RTInitTxMsg_MR 0x0002 -#define OPTN_RTInitTxMsg_MS 0x0003 -#define OPTN_RTInitTxMsg_MP 0x0004 - -#define OPTN_RTRespTxMsg_MS 0x0010 -#define OPTN_RTRespTxMsg_MR 0x0020 -#define OPTN_RTRespTxMsg_MP 0x0030 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// OPTN_AnnexControl -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -// G.992.3 Annex A/L1/L2 US PSD Mask preferred - -#define OPTN_G992_3_AnnexA_PreferredModeMask 0x3000 -#define OPTN_G992_3_AnnexA_PreferredModeA 0x0000 // default AnnexA PSD mask /// -#define OPTN_G992_3_AnnexA_PreferredModeL1 0x1000 // AnnexL wide spectrum upstream PSD mask /// -#define OPTN_G992_3_AnnexA_PreferredModeL2 0x2000 // AnnexL narrow spectrum upstream PSD mask /// - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//OPTN_ATMAddrConfig -// Bits 4:0 are Utopia address for BC1 -// Bits 9:5 are Utopia address for BC0 -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_UTPADDR_BC1 0x001F -#define OPTN_UTPADDR_BC0 0x03E0 - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//OPTN_ATMNumCellConfig -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -#define OPTN_BC1_NUM_CELL_PAGES 0x000F // Bits 0:3 /// -#define OPTN_BC0_NUM_CELL_PAGES 0x00F0 // Bits 4:7 /// - - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// CNFG register address field /// -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -/////////////////////////////////////////// -// these cmvs are used by bis handshake /// -/////////////////////////////////////////// - -// Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t) -#define CNFG_TPS_TC_DS0 0 -#define CNFG_TPS_TC_DS1 1 -#define CNFG_TPS_TC_US0 2 -#define CNFG_TPS_TC_US1 3 - -#define CNFG_HDLC_Overhead_Requirements 4 - -// Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t) -#define CNFG_PMS_TC_DS0 5 -#define CNFG_PMS_TC_DS1 6 -#define CNFG_PMS_TC_US0 7 -#define CNFG_PMS_TC_US1 8 - -// CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t) -#define CNFG_PMD_PARAMETERS 9 - -//////////////////////////////////////////////////////////// -// these cmvs are used by bis training and showtime code /// -//////////////////////////////////////////////////////////// - -//////////////// -// Tx Config /// -//////////////// -#define CNFG_tx_Cnfg_Nbc 10 -#define CNFG_tx_Cnfg_Nlp 11 -#define CNFG_tx_Cnfg_Rp 12 -#define CNFG_tx_Cnfg_Mp 13 -#define CNFG_tx_Cnfg_Lp 14 -#define CNFG_tx_Cnfg_Tp 15 -#define CNFG_tx_Cnfg_Dp 16 -#define CNFG_tx_Cnfg_Bpn 17 -#define CNFG_tx_Cnfg_FramingMode 18 -#define CNFG_tx_Cnfg_MSGLp 19 -#define CNFG_tx_Cnfg_MSGc 20 - - -//////////////// -// Rx Config /// -//////////////// -#define CNFG_rx_Cnfg_Nbc 21 -#define CNFG_rx_Cnfg_Nlp 22 -#define CNFG_rx_Cnfg_Rp 23 -#define CNFG_rx_Cnfg_Mp 24 -#define CNFG_rx_Cnfg_Lp 25 -#define CNFG_rx_Cnfg_Tp 26 -#define CNFG_rx_Cnfg_Dp 27 -#define CNFG_rx_Cnfg_Bpn 28 -#define CNFG_rx_Cnfg_FramingMode 29 -#define CNFG_rx_Cnfg_MSGLp 30 -#define CNFG_rx_Cnfg_MSGc 31 - -#define CNFG_tx_Cnfg_BCnToLPp 32 -#define CNFG_rx_Cnfg_BCnToLPp 33 - - - -#endif - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_sw.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_sw.h deleted file mode 100644 index 13273813a..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_sw.h +++ /dev/null @@ -1,177 +0,0 @@ -#ifndef AMAZON_SW_H -#define AMAZON_SW_H -#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE -#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 -#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 -#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 -#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 -#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 -#define SET_ETH_REG SIOCDEVPRIVATE+6 -#define VLAN_TOOLS SIOCDEVPRIVATE+7 -#define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8 - - -/*===mac table commands==*/ -#define RESET_MAC_TABLE 0 -#define READ_MAC_ENTRY 1 -#define WRITE_MAC_ENTRY 2 -#define ADD_MAC_ENTRY 3 - -/*====vlan commands===*/ - -#define CHANGE_VLAN_CTRL 0 -#define READ_VLAN_ENTRY 1 -#define UPDATE_VLAN_ENTRY 2 -#define CLEAR_VLAN_ENTRY 3 -#define RESET_VLAN_TABLE 4 -#define ADD_VLAN_ENTRY 5 - -/* -** MDIO constants. -*/ - -#define MDIO_BASE_STATUS_REG 0x1 -#define MDIO_BASE_CONTROL_REG 0x0 -#define MDIO_PHY_ID_HIGH_REG 0x2 -#define MDIO_PHY_ID_LOW_REG 0x3 -#define MDIO_BC_NEGOTIATE 0x0200 -#define MDIO_BC_FULL_DUPLEX_MASK 0x0100 -#define MDIO_BC_AUTO_NEG_MASK 0x1000 -#define MDIO_BC_SPEED_SELECT_MASK 0x2000 -#define MDIO_STATUS_100_FD 0x4000 -#define MDIO_STATUS_100_HD 0x2000 -#define MDIO_STATUS_10_FD 0x1000 -#define MDIO_STATUS_10_HD 0x0800 -#define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800 -#define MDIO_ADVERTISMENT_REG 0x4 -#define MDIO_ADVERT_100_FD 0x100 -#define MDIO_ADVERT_100_HD 0x080 -#define MDIO_ADVERT_10_FD 0x040 -#define MDIO_ADVERT_10_HD 0x020 -#define MDIO_LINK_UP_MASK 0x4 -#define MDIO_START 0x1 -#define MDIO_READ 0x2 -#define MDIO_WRITE 0x1 -#define MDIO_PREAMBLE 0xfffffffful - -#define PHY_RESET 0x8000 -#define AUTO_NEGOTIATION_ENABLE 0X1000 -#define AUTO_NEGOTIATION_COMPLETE 0x20 -#define RESTART_AUTO_NEGOTIATION 0X200 - - -#define PHY0_ADDR 0 -#define PHY1_ADDR 1 -#define P1M 0 - -#define AMAZON_SW_REG32(reg_num) *((volatile u32*)(reg_num)) - -#define OK 0; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -typedef struct mac_table_entry{ - u64 mac_address:48; - u64 p0:1; - u64 p1:1; - u64 p2:1; - u64 cr:1; - u64 ma_st:3; - u64 res:9; -}_mac_table_entry; - -typedef struct IFX_Switch_VLanTableEntry{ - u32 vlan_id:12; - u32 mp0:1; - u32 mp1:1; - u32 mp2:1; - u32 v:1; - u32 res:16; -}_IFX_Switch_VLanTableEntry; - -typedef struct mac_table_req{ - int cmd; - int index; - u32 data; - u64 entry_value; -}_mac_table_req; - -#else //not CONFIG_CPU_LITTLE_ENDIAN -typedef struct mac_table_entry{ - u64 mac_address:48; - u64 p0:1; - u64 p1:1; - u64 p2:1; - u64 cr:1; - u64 ma_st:3; - u64 res:9; -}_mac_table_entry; - -typedef struct IFX_Switch_VLanTableEntry{ - u32 vlan_id:12; - u32 mp0:1; - u32 mp1:1; - u32 mp2:1; - u32 v:1; - u32 res:16; -}_IFX_Switch_VLanTableEntry; - - -typedef struct mac_table_req{ - int cmd; - int index; - u32 data; - u64 entry_value; -}_mac_table_req; - -#endif //CONFIG_CPU_LITTLE_ENDIAN - - - -typedef struct vlan_req{ - int cmd; - int index; - u32 data; - u32 entry_value; -}_vlan_req; - -typedef struct data_req{ - int index; - u32 value; -}_data_req; - -enum duplex -{ - half, - full, - autoneg -}; - -struct switch_priv { - struct net_device_stats stats; - int rx_packetlen; - u8 *rx_packetdata; - int rx_status; - int tx_packetlen; -#ifdef CONFIG_NET_HW_FLOWCONTROL - int fc_bit; -#endif //CONFIG_NET_HW_FLOWCONTROL - u8 *tx_packetdata; - int tx_status; - struct dma_device_info *dma_device; - struct sk_buff *skb; - spinlock_t lock; - int mdio_phy_addr; - int current_speed; - int current_speed_selection; - int rx_queue_len; - int full_duplex; - enum duplex current_duplex; - int num; -}; - -#endif //AMAZON_SW_H - - - - - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_tpe.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_tpe.h deleted file mode 100644 index a64e6f9f8..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_tpe.h +++ /dev/null @@ -1,258 +0,0 @@ -#ifndef AMAZON_TPE_H -#define AMAZON_TPE_H -#include -#include -#include -#include - -#ifdef CONFIG_IFX_ATM_MIB -/* For ATM-MIB lists */ -#include -#endif -#include - -/* CBM Queue arranagement - * Q0: free cells pool - * Q1~ Q15: upstream queues - * Q16: QAM downstream - * Q17~Q31: downstream queues - */ -#define AMAZON_ATM_MAX_QUEUE_NUM 32 -#define AMAZON_ATM_PORT_NUM 2 -#define AMAZON_ATM_FREE_CELLS 4000 -#define AMAZON_ATM_MAX_VCC_NUM (AMAZON_ATM_MAX_QUEUE_NUM/2 - 1) -#define AMAZON_AAL0_SDU (ATM_AAL0_SDU+4) //one more word for status -#define CBM_RX_OFFSET 16 //offset from the same q for tx -#define AMAZON_ATM_OAM_Q_ID 16 -#define AMAZON_ATM_RM_Q_ID 16 -#define AMAZON_ATM_OTHER_Q_ID 16 -#define CBM_DEFAULT_Q_OFFSET 1 -#define HTUTIMEOUT 0xffff//timeoutofhtutocbm -#define QSB_WFQ_NONUBR_MAX 0x3f00 -#define QSB_WFQ_UBR_BYPASS 0x3fff -#define QSB_TP_TS_MAX 65472 -#define QSB_TAUS_MAX 64512 -#define QSB_GCR_MIN 18 -#define HTU_RAM_ACCESS_MAX 1024//maxium time for HTU RAM access - -#define SWIE_LOCK 1 -#define PROC_ATM 1 -#define PROC_MIB 2 -#define PROC_VCC 3 -#define PROC_AAL5 4 -#define PROC_CBM 5 -#define PROC_HTU 6 -#define PROC_QSB 7 -#define PROC_SWIE 8 - -/***************** internal data structure ********************/ -typedef int (*push_back_t)(struct atm_vcc *vcc,struct sk_buff *skb,int err) ; -/* Device private data */ -typedef struct{ - u8 padding_byte; - u32 tx_max_sdu; - u32 rx_max_sdu; - u32 cnt_cpy; //no. of packets that need a copy due to alignment -}amazon_aal5_dev_t; - -typedef struct{ - u32 max_q_off; //maxium queues used in real scenario - u32 nrt_thr; - u32 clp0_thr; - u32 clp1_thr; - u32 free_cell_cnt; -#ifdef CONFIG_USE_VENUS - u8 * qd_addr_free; //to work around a bug, bit15 of QDOFF address should be 1 -#endif - u8 * qd_addr; - u8 * mem_addr; - u8 allocated; -}amazon_cbm_dev_t; - -typedef struct{ - -}amazon_htu_dev_t; - -typedef struct{ - u32 tau; //cell delay variation due to concurrency(?) - u32 tstepc; //time step, all legal values are 1,2,4 - u32 sbl; //scheduler burse length (for PHY) -}amazon_qsb_dev_t; - -typedef struct{ - u32 qid; //QID of the current extraction queue - struct semaphore in_sem; // Software-Insertion semaphore - volatile long lock; //lock that avoids race contions between SWIN and SWEX - wait_queue_head_t sleep; //wait queue for SWIE and SWEX - u32 sw; //status word -}amazon_swie_dev_t; - -//AAL5 MIB Counter -typedef struct{ - u32 tx,rx; //number AAL5 CPCS PDU from/to higher-layer - u32 tx_err,rx_err; //ifInErrors and ifOutErros - u32 tx_drop,rx_drop; //discarded received packets due to mm shortage - u32 htu_unp; //number of unknown received cells - u32 rx_cnt_h; //number of octets received, high 32 bits - u32 rx_cnt_l; //number of octets received, low 32 bits - u32 tx_cnt_h; //number of octets transmitted, high 32 bits - u32 tx_cnt_l; //number of octets transmitted, low 32 bits - u32 tx_ppd; //number of cells for AAL5 upstream PPD discards - u64 rx_cells; //number of cells for downstream - u64 tx_cells; //number of cells for upstream - u32 rx_err_cells; //number of cells dropped due to uncorrectable HEC errors -}amazon_mib_counter_t; - - - -typedef enum {QS_PKT,QS_LEN,QS_ERR,QS_HW_DROP,QS_SW_DROP,QS_MAX} qs_t; -//queue statics no. of packet received / sent -//queue statics no. of bytes received / sent -//queue statics no. of packets with error -//queue statics no. of packets dropped by hw -//queue statics no. of packets dropped by sw - -typedef struct{ - push_back_t push; //call back function - struct atm_vcc * vcc; //opened vcc - struct timeval access_time; //time when last F4/F5 user cells arrive - int free; //whether this queue is occupied, 0: occupied, 1: free - u32 aal5VccCrcErrors; //MIB counter - u32 aal5VccOverSizedSDUs; //MIB counter - -#if defined(AMAZON_ATM_DEBUG) || defined (CONFIG_IFX_ATM_MIB) - u32 qs[QS_MAX]; -#endif -}amazon_atm_queue_t; - - -typedef struct{ - int enable; //enable / disable - u32 max_conn; //maximum number of connections per port - u32 tx_max_cr; //Remaining cellrate for this device for tx direction - u32 tx_rem_cr; //Remaining cellrate for this device for tx direction - u32 tx_cur_cr; //Current cellrate for this device for tx direction -}amazon_atm_port_t; - -typedef struct{ - amazon_aal5_dev_t aal5; - amazon_cbm_dev_t cbm; - amazon_htu_dev_t htu; - amazon_qsb_dev_t qsb; - amazon_swie_dev_t swie; - amazon_mib_counter_t mib_counter; - amazon_atm_queue_t queues[AMAZON_ATM_MAX_QUEUE_NUM]; - amazon_atm_port_t ports[AMAZON_ATM_PORT_NUM]; - atomic_t dma_tx_free_0;//TX_CH0 has availabe descriptors -} amazon_atm_dev_t; - -struct oam_last_activity{ - u8 vpi; //vpi for this connection - u16 vci; //vci for t his connection - struct timeval stamp; //time when last F4/F5 user cells arrive - struct oam_last_activity * next;//for link list purpose -}; - -typedef union{ -#ifdef CONFIG_CPU_LITTLE_ENDIAN - struct{ - u32 tprs :16; - u32 twfq :14; - u32 vbr :1; - u32 reserved :1; - }bit; - u32 w0; -#else - struct{ - u32 reserved :1; - u32 vbr :1; - u32 twfq :14; - u32 tprs :16; - }bit; - u32 w0; -#endif - -}qsb_qptl_t; - -typedef union{ -#ifdef CONFIG_CPU_LITTLE_ENDIAN - struct{ - u32 ts :16; - u32 taus :16; - }bit; - u32 w0; -#else - struct{ - u32 taus :16; - u32 ts :16; - }bit; - u32 w0; -#endif -}qsb_qvpt_t; - - - -struct amazon_atm_cell_header { -#ifdef CONFIG_CPU_LITTLE_ENDIAN - struct{ - u32 clp :1; // Cell Loss Priority - u32 pti :3; // Payload Type Identifier - u32 vci :16; // Virtual Channel Identifier - u32 vpi :8; // Vitual Path Identifier - u32 gfc :4; // Generic Flow Control - }bit; -#else - struct{ - u32 gfc :4; // Generic Flow Control - u32 vpi :8; // Vitual Path Identifier - u32 vci :16; // Virtual Channel Identifier - u32 pti :3; // Payload Type Identifier - u32 clp :1; // Cell Loss Priority - }bit; -#endif -}; - - -/************************ Function Declarations **************************/ -amazon_atm_dev_t * amazon_atm_create(void); -int amazon_atm_open(struct atm_vcc *vcc,push_back_t); -int amazon_atm_send(struct atm_vcc *vcc,struct sk_buff *skb); -int amazon_atm_send_oam(struct atm_vcc *vcc,void *cell, int flags); -void amazon_atm_close(struct atm_vcc *vcc); -void amazon_atm_cleanup(void); -const struct oam_last_activity* get_oam_time_stamp(void); - -//mib-related -int amazon_atm_cell_mib(atm_cell_ifEntry_t * to,u32 itf); -int amazon_atm_aal5_mib(atm_aal5_ifEntry_t * to); -int amazon_atm_vcc_mib(struct atm_vcc *vcc,atm_aal5_vcc_t * to); -int amazon_atm_vcc_mib_x(int vpi, int vci,atm_aal5_vcc_t* to); - -#define AMAZON_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data); wmb();} while (0) -#define AMAZON_READ_REGISTER_L(addr) (*((volatile u32*)(addr))) -/******************************* ioctl stuff****************************************/ -#define NUM(dev) (MINOR(dev) & 0xf) -/* - * Ioctl definitions - */ -/* Use 'o' as magic number */ -#define AMAZON_ATM_IOC_MAGIC 'o' -/* MIB_CELL: get atm cell level mib counter - * MIB_AAL5: get aal5 mib counter - * MIB_VCC: get vcc mib counter - */ -typedef struct{ - int vpi; - int vci; - atm_aal5_vcc_t mib_vcc; -}atm_aal5_vcc_x_t; -#define AMAZON_ATM_MIB_CELL _IOWR(AMAZON_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) -#define AMAZON_ATM_MIB_AAL5 _IOWR(AMAZON_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) -#define AMAZON_ATM_MIB_VCC _IOWR(AMAZON_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) -#define AMAZON_ATM_IOC_MAXNR 3 - -//sockopt -#define SO_AMAZON_ATM_MIB_VCC __SO_ENCODE(SOL_ATM,5,atm_aal5_vcc_t) - -#endif // AMAZON_TPE_H - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_wdt.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_wdt.h deleted file mode 100644 index 775dabccf..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/amazon_wdt.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef AMAZON_WDT_H -#define AMAZON_WDT_H -#ifdef __KERNEL__ -typedef struct wdt_dev{ - char name[16]; - int major; - int minor; - - int full; - char buff[10]; -}wdt_dev; -#define AMAZON_WDT_REG32(addr) (*((volatile u32*)(addr))) -#endif //__KERNEL__ - -//AMAZON_WDT_IOC_START: start the WDT timer (must provide a initial timeout value) -//AMAZON_WDT_IOC_STOP: stop the WDT -//AMAZON_WDT_IOC_PING: reload the timer to initial value (must happend after a AMAZON_WDT_IOC_START) -#define AMAZON_WDT_IOC_MAGIC 0xc0 -#define AMAZON_WDT_IOC_START _IOW( AMAZON_WDT_IOC_MAGIC,0, int) -#define AMAZON_WDT_IOC_STOP _IO( AMAZON_WDT_IOC_MAGIC,1) -#define AMAZON_WDT_IOC_PING _IO( AMAZON_WDT_IOC_MAGIC,2) - -#endif //AMAZON_WDT_H diff --git a/target/linux/amazon/files/include/asm-mips/amazon/atm_defines.h b/target/linux/amazon/files/include/asm-mips/amazon/atm_defines.h deleted file mode 100644 index 8adda2005..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/atm_defines.h +++ /dev/null @@ -1,540 +0,0 @@ -#ifndef ATM_DEFINES_H -#define ATM_DEFINES_H - -//Registers Base Address -#define IO_BASE_ADDR 0xA0000000 -#define AAL5_BASE_ADDRESS 0x10104400+IO_BASE_ADDR -#define CBM_BASE_ADDRESS 0x10104000+IO_BASE_ADDR -#define HTU_BASE_ADDRESS 0x10105100+IO_BASE_ADDR -#define QSB_BASE_ADDRESS 0x10105000+IO_BASE_ADDR -#define SWIE_BASE_ADDRESS 0x10105200+IO_BASE_ADDR - -//AAL5 Registers -#define AAL5_SISR0_ADDR AAL5_BASE_ADDRESS+0x20 -#define AAL5_SIMR0_ADDR AAL5_BASE_ADDRESS+0x24 -#define AAL5_SISR1_ADDR AAL5_BASE_ADDRESS+0x28 -#define AAL5_SIMR1_ADDR AAL5_BASE_ADDRESS+0x2C -#define AAL5_SMFL_ADDR AAL5_BASE_ADDRESS+0x30 -#define AAL5_SATMHD_ADDR AAL5_BASE_ADDRESS+0x34 -#define AAL5_SCON_ADDR AAL5_BASE_ADDRESS+0x38 -#define AAL5_SCMD_ADDR AAL5_BASE_ADDRESS+0x3C -#define AAL5_RISR0_ADDR AAL5_BASE_ADDRESS+0x40 -#define AAL5_RIMR0_ADDR AAL5_BASE_ADDRESS+0x44 -#define AAL5_RISR1_ADDR AAL5_BASE_ADDRESS+0x48 -#define AAL5_RIMR1_ADDR AAL5_BASE_ADDRESS+0x4C -#define AAL5_RMFL_ADDR AAL5_BASE_ADDRESS+0x50 -#define AAL5_RINTINF0_ADDR AAL5_BASE_ADDRESS+0x54 -#define AAL5_RINTINF1_ADDR AAL5_BASE_ADDRESS+0x58 -#define AAL5_RES5C_ADDR AAL5_BASE_ADDRESS+0x5C -#define AAL5_RIOL_ADDR AAL5_BASE_ADDRESS+0x60 -#define AAL5_RIOM_ADDR AAL5_BASE_ADDRESS+0x64 -#define AAL5_SOOL_ADDR AAL5_BASE_ADDRESS+0x68 -#define AAL5_SOOM_ADDR AAL5_BASE_ADDRESS+0x6C -#define AAL5_RES70_ADDR AAL5_BASE_ADDRESS+0x70 -#define AAL5_RES74_ADDR AAL5_BASE_ADDRESS+0x74 -#define AAL5_RES78_ADDR AAL5_BASE_ADDRESS+0x78 -#define AAL5_RES7C_ADDR AAL5_BASE_ADDRESS+0x7C -#define AAL5_RES80_ADDR AAL5_BASE_ADDRESS+0x80 -#define AAL5_RES84_ADDR AAL5_BASE_ADDRESS+0x84 -#define AAL5_RES88_ADDR AAL5_BASE_ADDRESS+0x88 -#define AAL5_RES8C_ADDR AAL5_BASE_ADDRESS+0x8C -#define AAL5_RES90_ADDR AAL5_BASE_ADDRESS+0x90 -#define AAL5_RES94_ADDR AAL5_BASE_ADDRESS+0x94 -#define AAL5_RES98_ADDR AAL5_BASE_ADDRESS+0x98 -#define AAL5_RES9C_ADDR AAL5_BASE_ADDRESS+0x9C -#define AAL5_RESA0_ADDR AAL5_BASE_ADDRESS+0xA0 -#define AAL5_RESA4_ADDR AAL5_BASE_ADDRESS+0xA4 -#define AAL5_RESA8_ADDR AAL5_BASE_ADDRESS+0xA8 -#define AAL5_RESAC_ADDR AAL5_BASE_ADDRESS+0xAC -#define AAL5_RESB0_ADDR AAL5_BASE_ADDRESS+0xB0 -#define AAL5_RESB4_ADDR AAL5_BASE_ADDRESS+0xB4 -#define AAL5_RESB8_ADDR AAL5_BASE_ADDRESS+0xB8 -#define AAL5_RESBC_ADDR AAL5_BASE_ADDRESS+0xBC -#define AAL5_RESC0_ADDR AAL5_BASE_ADDRESS+0xC0 -#define AAL5_RESC4_ADDR AAL5_BASE_ADDRESS+0xC4 -#define AAL5_RESC8_ADDR AAL5_BASE_ADDRESS+0xC8 -#define AAL5_RESCC_ADDR AAL5_BASE_ADDRESS+0xCC -#define AAL5_RESD0_ADDR AAL5_BASE_ADDRESS+0xD0 -#define AAL5_RESD4_ADDR AAL5_BASE_ADDRESS+0xD4 -#define AAL5_RESD8_ADDR AAL5_BASE_ADDRESS+0xD8 -#define AAL5_RESDC_ADDR AAL5_BASE_ADDRESS+0xDC -#define AAL5_RESE0_ADDR AAL5_BASE_ADDRESS+0xE0 -#define AAL5_RESE4_ADDR AAL5_BASE_ADDRESS+0xE4 -#define AAL5_RESE8_ADDR AAL5_BASE_ADDRESS+0xE8 -#define AAL5_RESEC_ADDR AAL5_BASE_ADDRESS+0xEC -#define AAL5_SSRC0_ADDR AAL5_BASE_ADDRESS+0xF0 -#define AAL5_SSRC1_ADDR AAL5_BASE_ADDRESS+0xF4 -#define AAL5_RSRC0_ADDR AAL5_BASE_ADDRESS+0xF8 -#define AAL5_RSRC1_ADDR AAL5_BASE_ADDRESS+0xFC - -#define AAL5S_ISR_QID_MASK 0xFF000000 -#define AAL5S_ISR_SAB 0x00000100 -#define AAL5S_ISR_SE 0x00000080 -#define AAL5S_ISR_MFLE 0x00000040 -#define AAL5S_ISR_SBE0 0x00000020 -#define AAL5S_ISR_SEG0 0x00000010 -#define AAL5S_ISR_TAB 0x00000004 - -#define AAL5_SIMR_MASK 0x000001c7 -#define AAL5_SIMR_SAB 0x00000100 -#define AAL5_SIMR_SE 0x00000080 -#define AAL5_SIMR_MFLE 0x00000040 -#define AAL5_SIMR_TAB 0x00000004 -#define AAL5_SIMR_SBE0 0x00000002 -#define AAL5_SIMR_SEG0 0x00000001 - -#define AAL5_SCMD_SEQCOUNT_MASK 0x0000ff00 -#define AAL5_SCMD_MODE_POLL 0x00000008 -#define AAL5_SCMD_MODE_COUNT 0x00000000 -#define AAL5_SCMD_AS 0x00000004 -#define AAL5_SCMD_SS 0x00000002 -#define AAL5_SCMD_AR 0x00000001 - -#define AAL5R_ISR_CID_MASK 0xFF000000//ConnectionID -#define AAL5R_ISR_DBC_MASK 0x00FF0000//DiscardedByteCounter -#define AAL5R_ISR_END 0x00002000//End -#define AAL5R_ISR_ICID 0x00001000//InvalidConnectionID -#define AAL5R_ISR_CLP 0x00000800//CellLossPriority -#define AAL5R_ISR_CGST 0x00000400//Congestion -#define AAL5R_ISR_UUE 0x00000200//CPCSUUError -#define AAL5R_ISR_CPIE 0x00000100//CPIError -#define AAL5R_ISR_FE 0x00000080//FrameEnd -#define AAL5R_ISR_MFLE 0x00000040//MaximumFrameLengthExceeded -#define AAL5R_ISR_DBCE 0x00000020//DiscardedByteCounterExceeded -#define AAL5R_ISR_CRC 0x00000010//CRCError -#define AAL5R_ISR_ILEN 0x00000008//InvalidLength -#define AAL5R_ISR_RAB 0x00000004//ReceiveAbort - -#define AAL5_RIMR1_MASK 0x00003ffc -#define AAL5_RIMR1_END 0x00002000//End -#define AAL5_RIMR1_ICID 0x00001000//InvalidConnectionID -#define AAL5_RIMR1_CLP 0x00000800//CellLossPriority -#define AAL5_RIMR1_CGST 0x00000400//Congestion -#define AAL5_RIMR1_UUE 0x00000200//CPCSUUError -#define AAL5_RIMR1_CPIE 0x00000100//CPIError -#define AAL5_RIMR1_FE 0x00000080//FrameEnd -#define AAL5_RIMR1_MFLE 0x00000040//MaximumFrameLengthExceeded -#define AAL5_RIMR1_DBCE 0x00000020//DiscardedByteCounterExceeded -#define AAL5_RIMR1_CRC 0x00000010//CRCError -#define AAL5_RIMR1_ILEN 0x00000008//InvalidLength -#define AAL5_RIMR1_RAB 0x00000004//ReceiveAbort - -//AAL5 Reassambly Errors -#define AAL5_STW1_MASK 0x33//Error mask -#define AAL5_STW0_MASK 0x5c//Error mask -#define AAL5_STW0_BE 0x3//padding bytes mask -#define AAL5_STW1_CBM 0x20//Transfer from CBM to A5R abnormally ended -#define AAL5_STW1_CH 0x10//Invalid Channel number error -#define AAL5_STW1_CLP 0x8//CLP value of cells in packet is 1 -#define AAL5_STW1_CG 0x4//Cell in packet expired congestion -#define AAL5_STW1_UU 0x2//CPCS-UU value error -#define AAL5_STW1_CPI 0x1//CPI value error -#define AAL5_STW0_FE 0x80//Frame end -#define AAL5_STW0_MFL 0x40//Maximum frame length error -#define AAL5_STW0_CRC 0x10//CRC error -#define AAL5_STW0_IL 0x8//Invalid length -#define AAL5_STW0_RA 0x4//Received abort - - - -//CBM Registers -#define CBM_NRTTHR_ADDR CBM_BASE_ADDRESS+0x10//NonRealTimeThreshold -#define CBM_CLP0THR_ADDR CBM_BASE_ADDRESS+0x14//CLP0Threshold -#define CBM_CLP1THR_ADDR CBM_BASE_ADDRESS+0x18//CLP1Threshold -#define CBM_QDOFF_ADDR CBM_BASE_ADDRESS+0x1C//QueueDescriptorOffset -#define CBM_CFG_ADDR CBM_BASE_ADDRESS+0x20//Configuration -#define CBM_HWEXPAR0_ADDR CBM_BASE_ADDRESS+0x24//HWExtractParameter0 -#define CBM_RES28_ADDR CBM_BASE_ADDRESS+0x28 -#define CBM_WMSTAT0_ADDR CBM_BASE_ADDRESS+0x2C -#define CBM_HWEXCMD_ADDR CBM_BASE_ADDRESS+0x30//HWExtractCommand0 -#define CBM_RES34_ADDR CBM_BASE_ADDRESS+0x34 -#define CBM_HWEXSTAT0_ADDR CBM_BASE_ADDRESS+0x38//HWExtractStatus0 -#define CBM_RES3C_ADDR CBM_BASE_ADDRESS+0x3C -#define CBM_RES40_ADDR CBM_BASE_ADDRESS+0x40 -#define CBM_CNT_ADDR CBM_BASE_ADDRESS+0x44//CellCount -#define CBM_RES48_ADDR CBM_BASE_ADDRESS+0x48 -#define CBM_LFR_ADDR CBM_BASE_ADDRESS+0x4C//PointertolastCellinfreeCellQueue -#define CBM_FFR_ADDR CBM_BASE_ADDRESS+0x50//PointertofirstCellinfreeCellQueue -#define CBM_RES54_ADDR CBM_BASE_ADDRESS+0x54 -#define CBM_RES58_ADDR CBM_BASE_ADDRESS+0x58 -#define CBM_RES5C_ADDR CBM_BASE_ADDRESS+0x5C -#define CBM_RES60_ADDR CBM_BASE_ADDRESS+0x60 -#define CBM_RES64_ADDR CBM_BASE_ADDRESS+0x64 -#define CBM_RES68_ADDR CBM_BASE_ADDRESS+0x68 -#define CBM_RES6C_ADDR CBM_BASE_ADDRESS+0x6C -#define CBM_RES70_ADDR CBM_BASE_ADDRESS+0x70 -#define CBM_RES74_ADDR CBM_BASE_ADDRESS+0x74 -#define CBM_RES78_ADDR CBM_BASE_ADDRESS+0x78 -#define CBM_RES7C_ADDR CBM_BASE_ADDRESS+0x7C -#define CBM_RES80_ADDR CBM_BASE_ADDRESS+0x80 -#define CBM_RES84_ADDR CBM_BASE_ADDRESS+0x84 -#define CBM_RES88_ADDR CBM_BASE_ADDRESS+0x88 -#define CBM_RES8C_ADDR CBM_BASE_ADDRESS+0x8C -#define CBM_RES90_ADDR CBM_BASE_ADDRESS+0x90 -#define CBM_RES94_ADDR CBM_BASE_ADDRESS+0x94 -#define CBM_RES98_ADDR CBM_BASE_ADDRESS+0x98 -#define CBM_RES9C_ADDR CBM_BASE_ADDRESS+0x9C -#define CBM_RESA0_ADDR CBM_BASE_ADDRESS+0xA0 -#define CBM_RESA4_ADDR CBM_BASE_ADDRESS+0xA4 -#define CBM_RESA8_ADDR CBM_BASE_ADDRESS+0xA8 -#define CBM_RESAC_ADDR CBM_BASE_ADDRESS+0xAC -#define CBM_RESB0_ADDR CBM_BASE_ADDRESS+0xB0 -#define CBM_RESB4_ADDR CBM_BASE_ADDRESS+0xB4 -#define CBM_RESB8_ADDR CBM_BASE_ADDRESS+0xB8 -#define CBM_RESBC_ADDR CBM_BASE_ADDRESS+0xBC -#define CBM_INTINF0_ADDR CBM_BASE_ADDRESS+0xC0//InterruptInfo0 -#define CBM_INTCMD_ADDR CBM_BASE_ADDRESS+0xC4//InterruptCommand0 -#define CBM_IMR0_ADDR CBM_BASE_ADDRESS+0xC8//InterruptMask -#define CBM_SRC0_ADDR CBM_BASE_ADDRESS+0xCC//ServiceRequestControl -#define CBM_RESD0_ADDR CBM_BASE_ADDRESS+0xD0 -#define CBM_RESD4_ADDR CBM_BASE_ADDRESS+0xD4 -#define CBM_RESD8_ADDR CBM_BASE_ADDRESS+0xD8 -#define CBM_RESDC_ADDR CBM_BASE_ADDRESS+0xDC -#define CBM_RESE0_ADDR CBM_BASE_ADDRESS+0xE0 -#define CBM_AAL5IDIS_ADDR CBM_BASE_ADDRESS+0xE4//MIB-No.EPDdiscardedpacketsupstream -#define CBM_AAL5ODIS_ADDR CBM_BASE_ADDRESS+0xE8//MIB-No.PPDdiscardedpacketsupstream -#define CBM_RESEC_ADDR CBM_BASE_ADDRESS+0xEC -#define CBM_RESF0_ADDR CBM_BASE_ADDRESS+0xF0 -#define CBM_RESF4_ADDR CBM_BASE_ADDRESS+0xF4 -#define CBM_RESF8_ADDR CBM_BASE_ADDRESS+0xF8 -#define CBM_RESFC_ADDR CBM_BASE_ADDRESS+0xFC - -//CBMCFG -#define CBM_CFG_INTLCK0EN 0x00000008 -#define CBM_CFG_INT0HLT 0x00000004 -#define CBM_CFG_START 0x00000001 - -#define CBM_HWEXPAR_PN_A5 0x00002000 -#define CBM_HWEXPAR_PN_CM 0x00000000 -#define CBM_HWEXPAR_SUBADD_PORTMASK 0x00000070 -#define CBM_HWEXPAR_SUBADD_ADU 0x00000000 -#define CBM_HWEXPAR_SUBADD_AAL2 0x00000080 -#define CBM_HWEXPAR_SUBADD_SWIE 0x00000100 - -#define CBM_HWEXCMD_SFE2 0x00000100 -#define CBM_HWEXCMD_FE2 0x00000080 -#define CBM_HWEXCMD_SCE2 0x00000040 -#define CBM_HWEXCMD_SFE1 0x00000020 -#define CBM_HWEXCMD_FE1 0x00000010 -#define CBM_HWEXCMD_SCE1 0x00000008 -#define CBM_HWEXCMD_SFE0 0x00000004 -#define CBM_HWEXCMD_FE0 0x00000002 -#define CBM_HWEXCMD_SCE0 0x00000001 - -#define CBM_INTINF0_QID_MASK 0xFF000000 -#define CBM_INTINF0_ORIGIN_MASK 0x00F00000 -#define CBM_INTINF0_EF 0x00004000 -#define CBM_INTINF0_ACA 0x00002000 -#define CBM_INTINF0_ERR 0x00001000 -#define CBM_INTINF0_DISC 0x00000800 -#define CBM_INTINF0_QSBV 0x00000400 -#define CBM_INTINF0_Q0E 0x00000200 -#define CBM_INTINF0_Q0I 0x00000100 -#define CBM_INTINF0_RDE 0x00000080 -#define CBM_INTINF0_OPF 0x00000040 -#define CBM_INTINF0_NFCA 0x00000020 -#define CBM_INTINF0_CLP1TR 0x00000010 -#define CBM_INTINF0_CLP0TR 0x00000008 -#define CBM_INTINF0_NRTTR 0x00000004 -#define CBM_INTINF0_QFD 0x00000002 -#define CBM_INTINF0_QTR 0x00000001 -#define CBM_INTINF0_QID_SHIFT 24 -//CBM QD Word 3 -#define CBM_QD_W3_QOS_0 0x00000000 -#define CBM_QD_W3_QOS_1 0x40000000 -#define CBM_QD_W3_QOS_2 0x80000000 -#define CBM_QD_W3_QOS_3 0xc0000000 - -#define CBM_QD_W3_DIR_UP 0x20000000 -#define CBM_QD_W3_DIR_DOWN 0x00000000 - -#define CBM_QD_W3_CLPt 0x10000000 -#define CBM_QD_W3_RT 0x08000000 -#define CBM_QD_W3_AAL5 0x04000000 - -#define CBM_QD_W3_INT_NOINT 0x00000000 -#define CBM_QD_W3_INT_ACA 0x01000000 -#define CBM_QD_W3_INT_EOF 0x02000000 -#define CBM_QD_W3_INT_BOTH 0x03000000 - -#define CBM_QD_W3_THRESHOLD_MASK 0x00ff0000 -#define CBM_QD_W3_WM_EN 0x00000010 -#define CBM_QD_W3_HCR 0x00000008 -#define CBM_QD_W3_SBID_MASK 0x00000001 - -#define CBM_QD_W3_THRESHOLD_SHIFT 16 - -//WATER MARK STATUS -#define CBM_WM_NRT_MASK 0x00040000 -#define CBM_WM_CLP0_MASK 0x00020000 -#define CBM_WM_CLP1_MASK 0x00010000 - -//CBMNRTTHR, CBMCLP0THR, CBMCLP0THR -#define CBM_NRT_WM_NONE 0x00000000//no water mark -#define CBM_WM_3_1 0x00010000//3/4 to set, 1/4 to release -#define CBM_WM_3_2 0x00020000//3/4 to set, 2/4 to release -#define CBM_WM_2_1 0x00030000//2/4 to set, 1/4 to release -#define CBM_THR_MASK 0x0000FFFF - -#define CBM_IMR_MASK 0x0000fbff -#define CBM_IMR_reserved 0xFFFF0400 -#define CBM_IMR_RFULL 0x00008000//EndofFrame -#define CBM_IMR_EF 0x00004000//EndofFrame -#define CBM_IMR_ACA 0x00002000//AnyCellArrived -#define CBM_IMR_ERR 0x00001000//FPI Error -#define CBM_IMR_DISC 0x00000800//Discard -#define CBM_IMR_reserved1 0x00000400//reserved -#define CBM_IMR_Q0E 0x00000200//Queue0Extract -#define CBM_IMR_Q0I 0x00000100//Queue0Insert -#define CBM_IMR_RDE 0x00000080//ReadEmptyQueue -#define CBM_IMR_OPF 0x00000040//OncePerFrame -#define CBM_IMR_NFCA 0x00000020//NoFreeCellAvailable -#define CBM_IMR_CLP1TR 0x00000010//CLP1ThresholdReached -#define CBM_IMR_CLP0TR 0x00000008//CLP0ThresholdReached -#define CBM_IMR_NRTTR 0x00000004//NonRealTimeThresholdReached -#define CBM_IMR_QFD 0x00000002//QueueFrameDiscard -#define CBM_IMR_QTR 0x00000001//QueueThresholdReached - -#define CBM_EXSTAT_FB 0x00000010 -#define CBM_EXSTAT_SCB 0x00000008 -#define CBM_EXSTAT_Q0 0x00000004 -#define CBM_EXSTAT_RDE 0x00000002 -#define CBM_EXSTAT_QV 0x00000001 - -//HTU Registers -#define HTU_RX0_ADDR HTU_BASE_ADDRESS+0x10 -#define HTU_RX1_ADDR HTU_BASE_ADDRESS+0x14 -#define HTU_RES18_ADDR HTU_BASE_ADDRESS+0x18 -#define HTU_RES1C_ADDR HTU_BASE_ADDRESS+0x1C -#define HTU_RES20_ADDR HTU_BASE_ADDRESS+0x20 -#define HTU_RES24_ADDR HTU_BASE_ADDRESS+0x24 -#define HTU_RES28_ADDR HTU_BASE_ADDRESS+0x28 -#define HTU_RES2C_ADDR HTU_BASE_ADDRESS+0x2C -#define HTU_PCF0PAT_ADDR HTU_BASE_ADDRESS+0x30 -#define HTU_PCF1PAT_ADDR HTU_BASE_ADDRESS+0x34 -#define HTU_RES38_ADDR HTU_BASE_ADDRESS+0x38 -#define HTU_RES3C_ADDR HTU_BASE_ADDRESS+0x3C -#define HTU_RES40_ADDR HTU_BASE_ADDRESS+0x40 -#define HTU_RES44_ADDR HTU_BASE_ADDRESS+0x44 -#define HTU_RES48_ADDR HTU_BASE_ADDRESS+0x48 -#define HTU_RES4C_ADDR HTU_BASE_ADDRESS+0x4C -#define HTU_PCF0MASK_ADDR HTU_BASE_ADDRESS+0x50 -#define HTU_PCF1MASK_ADDR HTU_BASE_ADDRESS+0x54 -#define HTU_RES58_ADDR HTU_BASE_ADDRESS+0x58 -#define HTU_RES5C_ADDR HTU_BASE_ADDRESS+0x5C -#define HTU_RES60_ADDR HTU_BASE_ADDRESS+0x60 -#define HTU_RES64_ADDR HTU_BASE_ADDRESS+0x64 -#define HTU_RES68_ADDR HTU_BASE_ADDRESS+0x68 -#define HTU_RES6C_ADDR HTU_BASE_ADDRESS+0x6C -#define HTU_TIMEOUT_ADDR HTU_BASE_ADDRESS+0x70 -#define HTU_DESTOAM_ADDR HTU_BASE_ADDRESS+0x74 -#define HTU_DESTRM_ADDR HTU_BASE_ADDRESS+0x78 -#define HTU_DESTOTHER_ADDR HTU_BASE_ADDRESS+0x7C -#define HTU_CFG_ADDR HTU_BASE_ADDRESS+0x80 -#define HTU_RES84_ADDR HTU_BASE_ADDRESS+0x84 -#define HTU_RES88_ADDR HTU_BASE_ADDRESS+0x88 -#define HTU_RES8C_ADDR HTU_BASE_ADDRESS+0x8C -#define HTU_INFNOENTRY_ADDR HTU_BASE_ADDRESS+0x90 -#define HTU_INFTIMEOUT_ADDR HTU_BASE_ADDRESS+0x94 -#define HTU_RES98_STAT HTU_BASE_ADDRESS+0x98 -#define HTU_RES9C_ADDR HTU_BASE_ADDRESS+0x9C -#define HTU_MIBCIUP HTU_BASE_ADDRESS+0xA0//MIB Counter In Unknown Protoc Register -#define HTU_CNTTIMEOUT_ADDR HTU_BASE_ADDRESS+0xA4 -#define HTU_RESA8_ADDR HTU_BASE_ADDRESS+0xA8 -#define HTU_RESAC_ADDR HTU_BASE_ADDRESS+0xAC -#define HTU_RAMADDR_ADDR HTU_BASE_ADDRESS+0xB0 -#define HTU_RAMCMD_ADDR HTU_BASE_ADDRESS+0xB4 -#define HTU_RAMSTAT_ADDR HTU_BASE_ADDRESS+0xB8 -#define HTU_RESBC_ADDR HTU_BASE_ADDRESS+0xBC -#define HTU_RAMDAT1_ADDR HTU_BASE_ADDRESS+0xC0 -#define HTU_RAMDAT2_ADDR HTU_BASE_ADDRESS+0xC4 -#define HTU_RESCC_ADDR HTU_BASE_ADDRESS+0xCC -#define HTU_RESD0_ADDR HTU_BASE_ADDRESS+0xD0 -#define HTU_RESD4_ADDR HTU_BASE_ADDRESS+0xD4 -#define HTU_RESD8_ADDR HTU_BASE_ADDRESS+0xD8 -#define HTU_RESDC_ADDR HTU_BASE_ADDRESS+0xDC -#define HTU_RESE0_ADDR HTU_BASE_ADDRESS+0xE0 -#define HTU_RESE4_ADDR HTU_BASE_ADDRESS+0xE4 -#define HTU_IMR0_ADDR HTU_BASE_ADDRESS+0xE8 -#define HTU_RESEC_ADDR HTU_BASE_ADDRESS+0xEC -#define HTU_ISR0_ADDR HTU_BASE_ADDRESS+0xF0 -#define HTU_RESF4_ADDR HTU_BASE_ADDRESS+0xF4 -#define HTU_SRC0_ADDR HTU_BASE_ADDRESS+0xF8 -#define HTU_RESFC_ADDR HTU_BASE_ADDRESS+0xFC - -//HTU_CFG -#define HTU_CFG_START 0x00000001 - -#define HTU_RAMCMD_RMW 0x00000004 -#define HTU_RAMCMD_RD 0x00000002 -#define HTU_RAMCMD_WR 0x00000001 - -#define HTU_RAMDAT1_VCON 0x00000080//validconnection -#define HTU_RAMDAT1_VCT 0x00000040//vcivalueistransparent -#define HTU_RAMDAT1_QIDS 0x00000020//qid selects a cell in cbm -#define HTU_RAMDAT1_VCI3 0x00000010//vci3->oamqueue -#define HTU_RAMDAT1_VCI4 0x00000008//vci4->oamqueue -#define HTU_RAMDAT1_VCI6 0x00000004//vci6->rmqueue -#define HTU_RAMDAT1_PTI4 0x00000002//pti4->oamqueue -#define HTU_RAMDAT1_PTI5 0x00000001//pti5->oamqueue - -#define HTU_RAMDAT2_PTI6 0x00000800 -#define HTU_RAMDAT2_PTI7 0x00000400 -#define HTU_RAMDAT2_F4U 0x00000200 -#define HTU_RAMDAT2_F5U 0x00000100 -#define HTU_RAMDAT2_QID_MASK 0x000000ff - -#define HTU_ISR_NE 0x00000001 -#define HTU_ISR_TORD 0x00000002 -#define HTU_ISR_IT 0x00000008 -#define HTU_ISR_OTOC 0x00000010 -#define HTU_ISR_ONEC 0x00000020 -#define HTU_ISR_PNE 0x00000040 -#define HTU_ISR_PT 0x00000080 -#define HTU_ISR_MASK 0x000000ff - - -//QSB Registers -#define QSB_BIP0_ADDR QSB_BASE_ADDRESS+0x00 -#define QSB_BIP1_ADDR QSB_BASE_ADDRESS+0x04 -#define QSB_BIP2_ADDR QSB_BASE_ADDRESS+0x08 -#define QSB_BIP3_ADDR QSB_BASE_ADDRESS+0x0C -#define QSB_RSVP_ADDR QSB_BASE_ADDRESS+0x10 -#define QSB_TNOW_ADDR QSB_BASE_ADDRESS+0x14 -#define QSB_TNOWCYC_ADDR QSB_BASE_ADDRESS+0x18 -#define QSB_TAU_ADDR QSB_BASE_ADDRESS+0x1C -#define QSB_L1BRS_ADDR QSB_BASE_ADDRESS+0x20 -#define QSB_SBL_ADDR QSB_BASE_ADDRESS+0x24 -#define QSB_CONFIG_ADDR QSB_BASE_ADDRESS+0x28 -#define QSB_RTM_ADDR QSB_BASE_ADDRESS+0x2C -#define QSB_RTD_ADDR QSB_BASE_ADDRESS+0x30 -#define QSB_RAMAC_ADDR QSB_BASE_ADDRESS+0x34 -#define QSB_ISR_ADDR QSB_BASE_ADDRESS+0x38 -#define QSB_IMR_ADDR QSB_BASE_ADDRESS+0x3C -#define QSB_SRC_ADDR QSB_BASE_ADDRESS+0x40 - -#define QSB_TABLESEL_QVPT 8 -#define QSB_TABLESEL_QPT 1 -#define QSB_TABLESEL_SCT 2 -#define QSB_TABLESEL_SPT 3 -#define QSB_TABLESEL_CALENDARWFQ 4/*notusedbyFW*/ -#define QSB_TABLESEL_L2WFQ 5/*notusedbyFW*/ -#define QSB_TABLESEL_CALENDARRS 6/*notusedbyFW*/ -#define QSB_TABLESEL_L2BITMAPRS 7/*notusedbyFW*/ -#define QSB_TABLESEL_SHIFT 24 -#define QSB_TWFQ_MASK 0x3FFF0000 -#define QSB_TPRS_MASK 0x0000FFFF -#define QSB_SBID_MASK 0xF -#define QSB_TWFQ_SHIFT 16 -#define QSB_SCDRATE_MASK 0x00007FFF -#define QSB_SBVALID_MASK 0x80000000 - -#define QSB_ISR_WFQLE 0x00000001 -#define QSB_ISR_WFQBE 0x00000002 -#define QSB_ISR_RSLE 0x00000004 -#define QSB_ISR_RSBE 0x00000008 -#define QSB_ISR_MUXOV 0x00000010 -#define QSB_ISR_CDVOV 0x00000020 -#define QSB_ISR_PARAMI 0x00000040 -#define QSB_ISR_SLOSS 0x00000080 -#define QSB_ISR_IIPS 0x00000100 - -#define QSB_IMR_WFQLE 0x00000001 -#define QSB_IMR_WFQBE 0x00000002 -#define QSB_IMR_RSLE 0x00000004 -#define QSB_IMR_RSBE 0x00000008 -#define QSB_IMR_MUXOV 0x00000010 -#define QSB_IMR_CDVOV 0x00000020 -#define QSB_IMR_PARAMI 0x00000040 -#define QSB_IMR_SLOSS 0x00000080 -#define QSB_IMR_IIPS 0x00000100 - -#define QSB_READ 0x0 -#define QSB_WRITE 0x80000000 -#define QSB_READ_ALL 0xFFFFFFFF - -#if 1 //some bug with QSB access mask -#define QSB_QPT_SET_MASK 0x0 -#define QSB_QVPT_SET_MASK 0x0 -#define QSB_SET_SCT_MASK 0x0 -#define QSB_SET_SPT_MASK 0x0 -#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF -#else //some bug with QSB access mask -#define QSB_QPT_SET_MASK 0x80000000 -#define QSB_QVPT_SET_MASK 0x0 -#define QSB_SET_SCT_MASK 0xFFFFFFE0 -#define QSB_SET_SPT_MASK 0x7FF8C000 -#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF -#endif //some bug with QSB access mask - -#define QSB_SPT_SBVALID 0x80000000 - -#define QSB_RAMAC_REG_LOW 0x0 -#define QSB_RAMAC_REG_HIGH 0x00010000 - -#define SRC_SRE_ENABLE 0x1000 -#define SRC_CLRR 0x4000 //request clear bit - - - -//SWIE Registers -#define SWIE_IQID_ADDR SWIE_BASE_ADDRESS+0x0c//SWIEInsertQueueDescriptor -#define SWIE_ICMD_ADDR SWIE_BASE_ADDRESS+0x10//SWIEInsertCommand -#define SWIE_ISTAT_ADDR SWIE_BASE_ADDRESS+0x14//SWIEInsertStatus -#define SWIE_ESTAT_ADDR SWIE_BASE_ADDRESS+0x18//SWIEExtractStatus -#define SWIE_ISRC_ADDR SWIE_BASE_ADDRESS+0x74//SWIEInsertServiceRequestControl -#define SWIE_ESRC_ADDR SWIE_BASE_ADDRESS+0x78//SWIEExtractServiceRequestControl -#define SWIE_ICELL_ADDR SWIE_BASE_ADDRESS+0x80//SWIEInsertCell(0x80-0xb4) -#define SWIE_ECELL_ADDR SWIE_BASE_ADDRESS+0xc0//SWIEExtractCell(0xc0-0xf4) - -#define SWIE_ISTAT_DONE 0x1 -#define SWIE_ESTAT_DONE 0x1 -#define SWIE_ICMD_START 0x00000001//Startcommandforinsertion -#define SWIE_CBM_SCE0 CBM_HWEXCMD_SCE0//CBMcommandforSingle-Cell-Extract -#define SWIE_CBM_PID_SUBADDR 0x00001000//CBMPortIDandSubAddressforUTOPIA - -//Extracted cell format -//52bytes AAL0 PDU + "Input cell additional data"(14bits) -#define SWIE_ADDITION_DATA_MASK 0x7fff -#define SWIE_EPORT_MASK 0x7000//Source ID (000 AUB0, 001 AUB1) -#define SWIE_EF4USER_MASK 0x800 -#define SWIE_EF5USER_MASK 0x400 -#define SWIE_EOAM_MASK 0x200 -#define SWIE_EAUU_MASK 0x100 -#define SWIE_EVCI3_MASK 0x80 -#define SWIE_EVCI4_MASK 0x40 -#define SWIE_EVCI6_MASK 0x20 -#define SWIE_EPTI4_MASK 0x10 -#define SWIE_EPTI5_MASK 0x8 -#define SWIE_EPTI6_MASK 0x4 -#define SWIE_EPTI7_MASK 0x2 -#define SWIE_ECRC10ERROR_MASK 0x1 - -#define CBM_CELL_SIZE 0x40 -#define CBM_QD_SIZE 0x10 -#define AAL5R_TRAILER_LEN 12 -#define AAL5S_INBOUND_HEADER 8 - -//constants -//TODO: to be finalized by system guys -//DMA QOS defined by ATM QoS Service type -#define DMA_RX_CH0 0 -#define DMA_RX_CH1 1 -#define DMA_TX_CH0 0 -#define DMA_TX_CH1 1 -#define CBR_DMA_QOS CBM_QD_W3_QOS_0 -#define VBR_RT_DMA_QOS CBM_QD_W3_QOS_0 -#define VBR_NRT_DMA_QOS CBM_QD_W3_QOS_0 -#define UBR_PLUS_DMA_QOS CBM_QD_W3_QOS_0 -#define UBR_DMA_QOS CBM_QD_W3_QOS_0 - -#define SRC_TOS_MIPS 0 -#define AAL5R_SRPN 0x00000006//a5rneedshigherprioritythanDR -#define AAL5S_SRPN 0x00000005 -#define CBM_MIPS_SRPN 0x00000004 -#define QSB_SRPN 0x00000023 -#define HTU_SRPN1 0x00000022 -#define HTU_SRPN0 0x00000021 - -#endif //ATM_DEFINES_H - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/atm_mib.h b/target/linux/amazon/files/include/asm-mips/amazon/atm_mib.h deleted file mode 100644 index f86334258..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/atm_mib.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef AMAZON_ATM_MIB_H -#define AMAZON_ATM_MIB_H - -#ifdef CONFIG_IFX_ATM_MIB -#include -#ifdef __KERNEL__ -#include -#endif -#endif /* CONFIG_IFX_ATM_MIB */ - -#ifndef __KERNEL__ -#include -typedef unsigned int __u32; -#endif - -typedef struct{ - __u32 ifHCInOctets_h; - __u32 ifHCInOctets_l; - __u32 ifHCOutOctets_h; - __u32 ifHCOutOctets_l; - __u32 ifInErrors; - __u32 ifInUnknownProtos; - __u32 ifOutErrors; -}atm_cell_ifEntry_t; - -typedef struct{ - __u32 ifHCInOctets_h; - __u32 ifHCInOctets_l; - __u32 ifHCOutOctets_h; - __u32 ifHCOutOctets_l; - __u32 ifInUcastPkts; - __u32 ifOutUcastPkts; - __u32 ifInErrors; - __u32 ifInDiscards; - __u32 ifOutErros; - __u32 ifOutDiscards; -}atm_aal5_ifEntry_t; - -typedef struct{ - __u32 aal5VccCrcErrors; - __u32 aal5VccSarTimeOuts;//no timer support yet - __u32 aal5VccOverSizedSDUs; -}atm_aal5_vcc_t; - -#if defined(CONFIG_IFX_ATM_MIB) || defined(IFX_CONFIG_SNMP_ATM_MIB) -/* ATM-MIB data structures */ -typedef struct atmIfConfEntry { - int ifIndex; - int atmInterfaceMaxVpcs; - int atmInterfaceMaxVccs; - int atmInterfaceConfVpcs; - int atmInterfaceConfVccs; - int atmInterfaceMaxActiveVpiBits; - int atmInterfaceMaxActiveVciBits; - int atmInterfaceIlmiVpi; - int atmInterfaceIlmiVci; - int atmInterfaceAddressType; - char atmInterfaceAdminAddress[40]; - unsigned long atmInterfaceMyNeighborIpAddress; - char atmInterfaceMyNeighborIfName[20]; - int atmInterfaceCurrentMaxVpiBits; - int atmInterfaceCurrentMaxVciBits; - char atmInterfaceSubscrAddress[40]; - int flags; -}atmIfConfEntry; - -typedef struct atmTrafficDescParamEntry { - /* Following three parameters are used to update VCC QoS values */ - int ifIndex; - short atmVclvpi; - int atmVclvci; - - unsigned int atmTrafficParamIndex; - unsigned char traffic_class; - int max_pcr; - /* Subramani: Added min_pcr */ - int min_pcr; - int cdv; - int scr; - int mbs; - int atmTrafficRowStatus; - int atmTrafficFrameDiscard; - struct list_head vpivci_head; - struct list_head list; -}atmTrafficDescParamEntry; - - -typedef struct atmVclEntry { - int ifIndex; - short atmVclvpi; - int atmVclvci; - char vpivci[20]; - int atmVclAdminStatus; - int atmVclOperStatus; - unsigned long atmVclLastChange; - struct atmTrafficDescParamEntry *atmVclRxTrafficPtr; - struct atmTrafficDescParamEntry *atmVclTxTrafficPtr; - unsigned char atmVccAalType; - unsigned int atmVccAal5TxSduSize; - unsigned int atmVccAal5RxSduSize; - int atmVccAal5Encap; - int atmVclRowStatus; - int atmVclCastType; - int atmVclConnKind; - struct list_head list; - int flags; -}atmVclEntry; - - -typedef union union_atmptrs { - struct atmIfConfEntry *atmIfConfEntry_ptr; - struct atmTrafficDescParamEntry *atmTrafficDescParamEntry_ptr; - struct atmVclEntry *atmVclEntry_ptr; -}union_atmptrs; - -/* ATM Character device major number */ -#define ATM_MEI_MAJOR 107 - -/* Protocol Constants */ -#define IFX_PROTO_RAW 0 -#define IFX_PROTO_BR2684 1 -#define IFX_PROTO_PPPOATM 2 -#define IFX_PROTO_CLIP 3 - -/* IOCTL Command Set for ATM-MIB */ -#define GET_ATM_IF_CONF_DATA 0x0AB0 -#define SET_ATM_IF_CONF_DATA 0x0AB1 - -#define SET_ATM_QOS_DATA 0x0BC0 - -#define GET_ATM_VCL_DATA 0x0CD0 -#define SET_ATM_VCL_DATA 0x0CD1 - -#define FIND_VCC_IN_KERNEL 0x0DE0 - -/* User defined flags for VCL Table */ -#define ATMVCCAAL5CPCSTRANSMITSDUSIZE 9 -#define ATMVCCAAL5CPCSRECEIVESDUSIZE 10 - -#endif /* CONFIG_IFX_ATM_MIB || IFX_CONFIG_SNMP_ATM_MIB */ - -#endif //AMAZON_ATM_MIB_H diff --git a/target/linux/amazon/files/include/asm-mips/amazon/ifx_peripheral_definitions.h b/target/linux/amazon/files/include/asm-mips/amazon/ifx_peripheral_definitions.h deleted file mode 100644 index 65f14e405..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/ifx_peripheral_definitions.h +++ /dev/null @@ -1,96 +0,0 @@ -//************************************************************************* -//* Summary of definitions which are used in each peripheral * -//************************************************************************* - -#ifndef peripheral_definitions_h -#define peripheral_definitions_h - -typedef unsigned char UINT8; -typedef signed char INT8; -typedef unsigned short UINT16; -typedef signed short INT16; -typedef unsigned int UINT32; -typedef signed int INT32; -typedef unsigned long long UINT64; -typedef signed long long INT64; - -#define REG8( addr ) (*(volatile UINT8 *) (addr)) -#define REG16( addr ) (*(volatile UINT16 *)(addr)) -#define REG32( addr ) (*(volatile UINT32 *)(addr)) -#define REG64( addr ) (*(volatile UINT64 *)(addr)) - -/* define routine to set FPI access in Supervisor Mode */ -#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01 -/* Supervisor mode ends, following functions will be done in User mode */ -#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00 -/* Supervisor mode ends, following functions will be done in User mode */ -#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG) -/* Supervisor mode ends, following functions will be done in User mode */ -#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm -/* enable all Interrupts in IIU */ -//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask -///* get all high priority interrupt bits in IIU */ -//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED) -///* signal ends of interrupt to IIU */ -//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit -///* force IIU interrupt register */ -//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data -///* get all bits of interrupt register */ -//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR) -/* insert a NOP instruction */ -#define NOP _nop() -/* CPU goes to power down mode until interrupt occurs */ -#define IFX_CPU_SLEEP _sleep() -/* enable all interrupts to CPU */ -#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int() -/* get all low priority interrupt bits in peripheral */ -#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg) -/* clear low priority interrupt bit in peripheral */ -#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit -/* write FPI bus */ -#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data -#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data -#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data -/* read FPI bus */ -#define READ_FPI_BYTE(addr) REG8(addr) -#define READ_FPI_16BIT(addr) REG16(addr) -#define READ_FPI_32BIT(addr) REG32(addr) -/* write peripheral register */ -#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data -#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data -#else //not CONFIG_CPU_LITTLE_ENDIAN -#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data -#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data -#endif //CONFIG_CPU_LITTLE_ENDIAN - -/* read peripheral register */ -#define READ_PERIPHERAL_REGISTER(addr) REG32(addr) - -/* read/modify(or)/write peripheral register */ -#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data -/* read/modify(and)/write peripheral register */ -#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data - -/* CPU-independent mnemonic constants */ -/* CLC register bits */ -#define IFX_CLC_ENABLE 0x00000000 -#define IFX_CLC_DISABLE 0x00000001 -#define IFX_CLC_DISABLE_STATUS 0x00000002 -#define IFX_CLC_SUSPEND_ENABLE 0x00000004 -#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008 -#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010 -#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020 -#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00 -#define IFX_CLC_RUN_DIVIDER_OFFSET 8 -#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000 -#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16 -#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000 -#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24 - -/* number of cycles to wait for interrupt service routine to be called */ -#define WAIT_CYCLES 50 - -#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc.h b/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc.h deleted file mode 100644 index e5d73ad4e..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * ifx_ssc.h defines some data sructures used in ifx_ssc.c - * - * Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT) - * - * - */ - -#ifndef __IFX_SSC_H -#define __IFX_SSC_H -#ifdef __KERNEL__ -#include -#endif //__KERNEL__ - -#define PORT_CNT 1 // assume default value - -/* symbolic constants to be used in SSC routines */ - -// ### TO DO: bad performance -#define IFX_SSC_TXFIFO_ITL 1 -#define IFX_SSC_RXFIFO_ITL 1 - - - -struct ifx_ssc_statistics{ - unsigned int abortErr; /* abort error */ - unsigned int modeErr; /* master/slave mode error */ - unsigned int txOvErr; /* TX Overflow error */ - unsigned int txUnErr; /* TX Underrun error */ - unsigned int rxOvErr; /* RX Overflow error */ - unsigned int rxUnErr; /* RX Underrun error */ - unsigned int rxBytes; - unsigned int txBytes; -}; - - -struct ifx_ssc_hwopts { - unsigned int AbortErrDetect :1; /* Abort Error detection (in slave mode) */ - unsigned int rxOvErrDetect :1; /* Receive Overflow Error detection */ - unsigned int rxUndErrDetect :1; /* Receive Underflow Error detection */ - unsigned int txOvErrDetect :1; /* Transmit Overflow Error detection */ - unsigned int txUndErrDetect :1; /* Transmit Underflow Error detection */ - unsigned int echoMode :1; /* Echo mode */ - unsigned int loopBack :1; /* Loopback mode */ - unsigned int idleValue :1; /* Idle value */ - unsigned int clockPolarity :1; /* Idle clock is high or low */ - unsigned int clockPhase :1; /* Tx on trailing or leading edge*/ - unsigned int headingControl :1; /* LSB first or MSB first */ - unsigned int dataWidth :6; /* from 2 up to 32 bits */ - unsigned int masterSelect :1; /* Master or Slave mode */ - unsigned int modeRxTx :2; /* rx/tx mode */ - unsigned int gpoCs :8; /* choose outputs to use for chip select */ - unsigned int gpoInv :8; /* invert GPO outputs */ -}; - - -struct ifx_ssc_frm_opts { - bool FrameEnable; // SFCON.SFEN - unsigned int DataLength; // SFCON.DLEN - unsigned int PauseLength; // SFCON.PLEN - unsigned int IdleData; // SFCON.IDAT - unsigned int IdleClock; // SFCON.ICLK - bool StopAfterPause; // SFCON.STOP -}; - -struct ifx_ssc_frm_status { - bool DataBusy; // SFSTAT.DBSY - bool PauseBusy; // SFSTAT.PBSY - unsigned int DataCount; // SFSTAT.DCNT - unsigned int PauseCount; // SFSTAT.PCNT - bool EnIntAfterData; // SFCON.IBEN - bool EnIntAfterPause;// SFCON.IAEN -}; - -typedef struct { - char *buf; - size_t len; -} ifx_ssc_buf_item_t; - - -// data structures for batch execution -typedef union { - struct { - bool save_options; - } init; - ifx_ssc_buf_item_t read; - ifx_ssc_buf_item_t write; - ifx_ssc_buf_item_t rd_wr; - unsigned int set_baudrate; - struct ifx_ssc_frm_opts set_frm; - unsigned int set_gpo; - struct ifx_ssc_hwopts set_hwopts; -}ifx_ssc_batch_cmd_param; - -struct ifx_ssc_batch_list { - unsigned int cmd; - ifx_ssc_batch_cmd_param cmd_param; - struct ifx_ssc_batch_list *next; -}; - -#ifdef __KERNEL__ -#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE) - - -struct ifx_ssc_port{ - unsigned long mapbase; - struct ifx_ssc_hwopts opts; - struct ifx_ssc_statistics stats; - struct ifx_ssc_frm_status frm_status; - struct ifx_ssc_frm_opts frm_opts; - /* wait queue for ifx_ssc_read() */ - wait_queue_head_t rwait, pwait; - int port_nr; - char port_is_open; /* exclusive open - boolean */ -// int no_of_bits; /* number of _valid_ bits */ -// int elem_size; /* shift for element (no of bytes)*/ - /* buffer and pointers to the read/write position */ - char *rxbuf; /* buffer for RX */ - char *rxbuf_end; /* buffer end pointer for RX */ - volatile char *rxbuf_ptr; /* buffer write pointer for RX */ - char *txbuf; /* buffer for TX */ - char *txbuf_end; /* buffer end pointer for TX */ - volatile char *txbuf_ptr; /* buffer read pointer for TX */ - unsigned int baud; - /* each channel has its own interrupts */ - /* (transmit/receive/error/frame) */ - unsigned int txirq, rxirq, errirq, frmirq; -}; -/* default values for SSC configuration */ -// values of CON -#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */ -#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */ -#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */ -#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */ -#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */ -#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */ -#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */ -#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */ -#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */ -#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST -#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX -// other values -#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */ -#define IFX_SSC_DEF_BAUDRATE 1000000 -#define IFX_SSC_DEF_RMC 0x10 - -#define IFX_SSC_DEF_TXFIFO_FL 8 -#define IFX_SSC_DEF_RXFIFO_FL 1 - -#if 1 //TODO -#define IFX_SSC_DEF_GPO_CS 2 /* no chip select */ -#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */ -#else -#error "what is ur Chip Select???" -#endif -#define IFX_SSC_DEF_SFCON 0 /* no serial framing */ -#if 0 -#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\ - IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT -#endif -#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\ - IFX_SSC_R_BIT | IFX_SSC_E_BIT -#endif /* __KERNEL__ */ - -// batch execution commands -#define IFX_SSC_BATCH_CMD_INIT 1 -#define IFX_SSC_BATCH_CMD_READ 2 -#define IFX_SSC_BATCH_CMD_WRITE 3 -#define IFX_SSC_BATCH_CMD_RD_WR 4 -#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5 -#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6 -#define IFX_SSC_BATCH_CMD_SET_FRM 7 -#define IFX_SSC_BATCH_CMD_SET_GPO 8 -#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9 -//#define IFX_SSC_BATCH_CMD_ -//#define IFX_SSC_BATCH_CMD_ -#define IFX_SSC_BATCH_CMD_END_EXEC 0 - -/* Macros to configure SSC hardware */ -/* headingControl: */ -#define IFX_SSC_LSB_FIRST 0 -#define IFX_SSC_MSB_FIRST 1 -/* dataWidth: */ -#define IFX_SSC_MIN_DATA_WIDTH 2 -#define IFX_SSC_MAX_DATA_WIDTH 32 -/* master/slave mode select */ -#define IFX_SSC_MASTER_MODE 1 -#define IFX_SSC_SLAVE_MODE 0 -/* rx/tx mode */ -// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h -#define IFX_SSC_MODE_RXTX 0 -#define IFX_SSC_MODE_RX 1 -#define IFX_SSC_MODE_TX 2 -#define IFX_SSC_MODE_OFF 3 -#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX - -/* GPO values */ -#define IFX_SSC_MAX_GPO_OUT 7 - -#define IFX_SSC_RXREQ_BLOCK_SIZE 32768 - -/***********************/ -/* defines for ioctl's */ -/***********************/ -#define IFX_SSC_IOCTL_MAGIC 'S' -/* read out the statistics */ -#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics) -/* clear the statistics */ -#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2) -/* set the baudrate */ -#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int) -/* get the current baudrate */ -#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int) -/* set hardware options */ -#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts) -/* get the current hardware options */ -#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts) -/* set transmission mode */ -#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int) -/* get the current transmission mode */ -#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int) -/* abort transmission */ -#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9) -#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9) - -/* set general purpose outputs */ -#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int) -/* clear general purpose outputs */ -#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int) -/* get general purpose outputs */ -#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int) - -/*** serial framing ***/ -/* get status of serial framing */ -#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status) -/* get counter reload values and control bits */ -#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts) -/* set counter reload values and control bits */ -#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts) - - -/*** batch execution ***/ -/* do batch execution */ -#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list) - - -#ifdef __KERNEL__ -// routines from ifx_ssc.c -// ### TO DO -/* kernel interface for read and write */ -ssize_t ifx_ssc_kread(int, char *, size_t); -ssize_t ifx_ssc_kwrite(int, const char *, size_t); - -#ifdef CONFIG_IFX_VP_KERNEL_TEST -void ifx_ssc_tc(void); -#endif // CONFIG_IFX_VP_KERNEL_TEST - -#endif //__KERNEL__ -#endif // __IFX_SSC_H - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc_defines.h b/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc_defines.h deleted file mode 100644 index 46157dcbd..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc_defines.h +++ /dev/null @@ -1,552 +0,0 @@ -#ifndef IFX_SSC_DEFINES_H -#define IFX_SSC_DEFINES_H - -#include "ifx_peripheral_definitions.h" - -/* maximum SSC FIFO size */ -#define IFX_SSC_MAX_FIFO_SIZE 32 - -/* register map of SSC */ - -/* address of the Clock Control Register of the SSC */ -#define IFX_SSC_CLC 0x00000000 -/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0 - bit 1 is hardware modified*/ -#define IFX_SSC_CLC_readmask 0x00FFFFEF -#define IFX_SSC_CLC_writemask 0x00FFFF3D -#define IFX_SSC_CLC_hwmask 0x00000002 -#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask) - -/* address of Port Input Select Register of the SSC */ -#define IFX_SSC_PISEL 0x00000004 -/* IFX_SSC_PISEL register is significant in lowest three bits only */ -#define IFX_SSC_PISEL_readmask 0x00000007 -#define IFX_SSC_PISEL_writemask 0x00000007 -#define IFX_SSC_PISEL_hwmask 0x00000000 -#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask) - -/* address of Identification Register of the SSC */ -#define IFX_SSC_ID 0x00000008 -/* IFX_SSC_ID register is significant in no bit */ -#define IFX_SSC_ID_readmask 0x0000FF3F -#define IFX_SSC_ID_writemask 0x00000000 -#define IFX_SSC_ID_hwmask 0x00000000 -#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask) - -/* address of the Control Register of the SSC */ -#define IFX_SSC_CON 0x00000010 -/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */ -#define IFX_SSC_CON_readmask 0x01DF1FFF -#define IFX_SSC_CON_writemask 0x01DF1FFF -#define IFX_SSC_CON_hwmask 0x00000000 -#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask) - - -/* address of the Status Register of the SSC */ -#define IFX_SSC_STATE 0x00000014 -/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0 - all bits except 1:0 are hardware modified */ -#define IFX_SSC_STATE_readmask 0x771F3F87 -#define IFX_SSC_STATE_writemask 0x00000000 -#define IFX_SSC_STATE_hwmask 0x771F3F84 -#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask) - -/* address of the Write Hardware Modified Control Register Bits of the SSC */ -#define IFX_SSC_WHBSTATE 0x00000018 -/* IFX_SSC_WHBSTATE register is write only */ -#define IFX_SSC_WHBSTATE_readmask 0x00000000 -#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF -#define IFX_SSC_WHBSTATE_hwmask 0x00000000 -#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask) - -/* address of the Baudrate Timer Reload Register of the SSC */ -#define IFX_SSC_BR 0x00000040 -/* IFX_SSC_BR register is significant in bit 15 downto 0*/ -#define IFX_SSC_BR_readmask 0x0000FFFF -#define IFX_SSC_BR_writemask 0x0000FFFF -#define IFX_SSC_BR_hwmask 0x00000000 -#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask) - -/* address of the Baudrate Timer Status Register of the SSC */ -#define IFX_SSC_BRSTAT 0x00000044 -/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/ -#define IFX_SSC_BRSTAT_readmask 0x0000FFFF -#define IFX_SSC_BRSTAT_writemask 0x00000000 -#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF -#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask) - -/* address of the Transmitter Buffer Register of the SSC */ -#define IFX_SSC_TB 0x00000020 -/* IFX_SSC_TB register is significant in bit 31 downto 0*/ -#define IFX_SSC_TB_readmask 0xFFFFFFFF -#define IFX_SSC_TB_writemask 0xFFFFFFFF -#define IFX_SSC_TB_hwmask 0x00000000 -#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask) - -/* address of the Reciver Buffer Register of the SSC */ -#define IFX_SSC_RB 0x00000024 -/* IFX_SSC_RB register is significant in no bits*/ -#define IFX_SSC_RB_readmask 0xFFFFFFFF -#define IFX_SSC_RB_writemask 0x00000000 -#define IFX_SSC_RB_hwmask 0xFFFFFFFF -#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask) - -/* address of the Receive FIFO Control Register of the SSC */ -#define IFX_SSC_RXFCON 0x00000030 -/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ -#define IFX_SSC_RXFCON_readmask 0x00003F03 -#define IFX_SSC_RXFCON_writemask 0x00003F03 -#define IFX_SSC_RXFCON_hwmask 0x00000000 -#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask) - -/* address of the Transmit FIFO Control Register of the SSC */ -#define IFX_SSC_TXFCON 0x00000034 -/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ -#define IFX_SSC_TXFCON_readmask 0x00003F03 -#define IFX_SSC_TXFCON_writemask 0x00003F03 -#define IFX_SSC_TXFCON_hwmask 0x00000000 -#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask) - -/* address of the FIFO Status Register of the SSC */ -#define IFX_SSC_FSTAT 0x00000038 -/* IFX_SSC_FSTAT register is significant in no bit*/ -#define IFX_SSC_FSTAT_readmask 0x00003F3F -#define IFX_SSC_FSTAT_writemask 0x00000000 -#define IFX_SSC_FSTAT_hwmask 0x00003F3F -#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask) - -/* address of the Data Frame Control register of the SSC */ -#define IFX_SSC_SFCON 0x00000060 -#define IFX_SSC_SFCON_readmask 0xFFDFFFFD -#define IFX_SSC_SFCON_writemask 0xFFDFFFFD -#define IFX_SSC_SFCON_hwmask 0x00000000 -#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask) - -/* address of the Data Frame Status register of the SSC */ -#define IFX_SSC_SFSTAT 0x00000064 -#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3 -#define IFX_SSC_SFSTAT_writemask 0x00000000 -#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3 -#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask) - -/* address of the General Purpose Output Control register of the SSC */ -#define IFX_SSC_GPOCON 0x00000070 -#define IFX_SSC_GPOCON_readmask 0x0000FFFF -#define IFX_SSC_GPOCON_writemask 0x0000FFFF -#define IFX_SSC_GPOCON_hwmask 0x00000000 -#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask) - -/* address of the General Purpose Output Status register of the SSC */ -#define IFX_SSC_GPOSTAT 0x00000074 -#define IFX_SSC_GPOSTAT_readmask 0x000000FF -#define IFX_SSC_GPOSTAT_writemask 0x00000000 -#define IFX_SSC_GPOSTAT_hwmask 0x00000000 -#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask) - -/* address of the Force GPO Status register of the SSC */ -#define IFX_SSC_WHBGPOSTAT 0x00000078 -#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000 -#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF -#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000 -#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask) - -/* address of the Receive Request Register of the SSC */ -#define IFX_SSC_RXREQ 0x00000080 -#define IFX_SSC_RXREQ_readmask 0x0000FFFF -#define IFX_SSC_RXREQ_writemask 0x0000FFFF -#define IFX_SSC_RXREQ_hwmask 0x00000000 -#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask) - -/* address of the Receive Count Register of the SSC */ -#define IFX_SSC_RXCNT 0x00000084 -#define IFX_SSC_RXCNT_readmask 0x0000FFFF -#define IFX_SSC_RXCNT_writemask 0x00000000 -#define IFX_SSC_RXCNT_hwmask 0x0000FFFF -#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask) - -/* address of the DMA Configuration Register of the SSC */ -#define IFX_SSC_DMACON 0x000000EC -#define IFX_SSC_DMACON_readmask 0x0000FFFF -#define IFX_SSC_DMACON_writemask 0x00000000 -#define IFX_SSC_DMACON_hwmask 0x0000FFFF -#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask) - -//------------------------------------------------------ -// interrupt register for enabling interrupts, mask register of irq_reg -#define IFX_SSC_IRN_EN 0xF4 -// read/write -#define IFX_SSC_IRN_EN_readmask 0x0000000F -#define IFX_SSC_IRN_EN_writemask 0x0000000F -#define IFX_SSC_IRN_EN_hwmask 0x00000000 -#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask) - -// interrupt register for accessing interrupts -#define IFX_SSC_IRN_CR 0xF8 -// read/write -#define IFX_SSC_IRN_CR_readmask 0x0000000F -#define IFX_SSC_IRN_CR_writemask 0x0000000F -#define IFX_SSC_IRN_CR_hwmask 0x0000000F -#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask) - -// interrupt register for stimulating interrupts -#define IFX_SSC_IRN_ICR 0xFC -// read/write -#define IFX_SSC_IRN_ICR_readmask 0x0000000F -#define IFX_SSC_IRN_ICR_writemask 0x0000000F -#define IFX_SSC_IRN_ICR_hwmask 0x00000000 -#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask) - -//--------------------------------------------------------------------- -// Number of IRQs and bitposition of IRQ -#define IFX_SSC_NUM_IRQ 4 -#define IFX_SSC_T_BIT 0x00000001 -#define IFX_SSC_R_BIT 0x00000002 -#define IFX_SSC_E_BIT 0x00000004 -#define IFX_SSC_F_BIT 0x00000008 - -/* bit masks for SSC registers */ - -/* ID register */ -#define IFX_SSC_PERID_REV_MASK 0x0000001F -#define IFX_SSC_PERID_CFG_MASK 0x00000020 -#define IFX_SSC_PERID_ID_MASK 0x0000FF00 -#define IFX_SSC_PERID_REV_OFFSET 0 -#define IFX_SSC_PERID_CFG_OFFSET 5 -#define IFX_SSC_PERID_ID_OFFSET 8 -#define IFX_SSC_PERID_ID 0x45 -#define IFX_SSC_PERID_DMA_ON 0x00000020 -#define IFX_SSC_PERID_RXFS_MASK 0x003F0000 -#define IFX_SSC_PERID_RXFS_OFFSET 16 -#define IFX_SSC_PERID_TXFS_MASK 0x3F000000 -#define IFX_SSC_PERID_TXFS_OFFSET 24 - -/* PISEL register */ -#define IFX_SSC_PISEL_MASTER_IN_A 0x0000 -#define IFX_SSC_PISEL_MASTER_IN_B 0x0001 -#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000 -#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002 -#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000 -#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004 - - -/* IFX_SSC_CON register */ -#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000 -#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000 -#define IFX_SSC_CON_IDLE_HIGH 0x00800000 -#define IFX_SSC_CON_IDLE_LOW 0x00000000 -#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000 -#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000 -#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16 -#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000 -#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK) - -#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000 -#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000 - -#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000 -#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000 -#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800 -#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000 -#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400 -#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000 -#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200 -#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000 -#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100 -#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000 -#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00 -#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000 - -#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080 -#define IFX_SSC_CON_NO_LOOPBACK 0x00000000 -#define IFX_SSC_CON_HALF_DUPLEX 0x00000080 -#define IFX_SSC_CON_FULL_DUPLEX 0x00000000 -#define IFX_SSC_CON_CLOCK_FALL 0x00000040 -#define IFX_SSC_CON_CLOCK_RISE 0x00000000 -#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000 -#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020 -#define IFX_SSC_CON_MSB_FIRST 0x00000010 -#define IFX_SSC_CON_LSB_FIRST 0x00000000 -#define IFX_SSC_CON_ENABLE_CSB 0x00000008 -#define IFX_SSC_CON_DISABLE_CSB 0x00000000 -#define IFX_SSC_CON_INVERT_CSB 0x00000004 -#define IFX_SSC_CON_TRUE_CSB 0x00000000 -#define IFX_SSC_CON_RX_OFF 0x00000002 -#define IFX_SSC_CON_RX_ON 0x00000000 -#define IFX_SSC_CON_TX_OFF 0x00000001 -#define IFX_SSC_CON_TX_ON 0x00000000 - - -/* IFX_SSC_STATE register */ -#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28 -#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000 -#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET) -#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24 -#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000 -#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET) -#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16 -#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000 -#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1) -#define IFX_SSC_STATE_BUSY 0x00002000 -#define IFX_SSC_STATE_RX_UFL 0x00001000 -#define IFX_SSC_STATE_TX_UFL 0x00000800 -#define IFX_SSC_STATE_ABORT_ERR 0x00000400 -#define IFX_SSC_STATE_RX_OFL 0x00000200 -#define IFX_SSC_STATE_TX_OFL 0x00000100 -#define IFX_SSC_STATE_MODE_ERR 0x00000080 -#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004 -#define IFX_SSC_STATE_IS_MASTER 0x00000002 -#define IFX_SSC_STATE_IS_ENABLED 0x00000001 - -/* WHBSTATE register */ -#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001 -#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001 -#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001 - -#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002 -#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002 -#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002 - -#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004 -#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004 - -#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008 -#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008 - -#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010 -#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020 - -#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040 -#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080 - -#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100 -#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200 -#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400 -#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800 -#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000 -#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000 -#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000 -#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000 -#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50 -#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0 - -/* BR register */ -#define IFX_SSC_BR_BAUDRATE_OFFSET 0 -#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF - -/* BR_STAT register */ -#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0 -#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF - -/* TB register */ -#define IFX_SSC_TB_DATA_OFFSET 0 -#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF - -/* RB register */ -#define IFX_SSC_RB_DATA_OFFSET 0 -#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF - - -/* RXFCON and TXFCON registers */ -#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000 -#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001 -#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002 -#define IFX_SSC_XFCON_ITL_MASK 0x00003F00 -#define IFX_SSC_XFCON_ITL_OFFSET 8 - -/* FSTAT register */ -#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0 -#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F -#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8 -#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00 - -/* GPOCON register */ -#define IFX_SSC_GPOCON_INVOUT0_POS 0 -#define IFX_SSC_GPOCON_INV_OUT0 0x00000001 -#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000 -#define IFX_SSC_GPOCON_INVOUT1_POS 1 -#define IFX_SSC_GPOCON_INV_OUT1 0x00000002 -#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000 -#define IFX_SSC_GPOCON_INVOUT2_POS 2 -#define IFX_SSC_GPOCON_INV_OUT2 0x00000003 -#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000 -#define IFX_SSC_GPOCON_INVOUT3_POS 3 -#define IFX_SSC_GPOCON_INV_OUT3 0x00000008 -#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000 -#define IFX_SSC_GPOCON_INVOUT4_POS 4 -#define IFX_SSC_GPOCON_INV_OUT4 0x00000010 -#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000 -#define IFX_SSC_GPOCON_INVOUT5_POS 5 -#define IFX_SSC_GPOCON_INV_OUT5 0x00000020 -#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000 -#define IFX_SSC_GPOCON_INVOUT6_POS 6 -#define IFX_SSC_GPOCON_INV_OUT6 0x00000040 -#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000 -#define IFX_SSC_GPOCON_INVOUT7_POS 7 -#define IFX_SSC_GPOCON_INV_OUT7 0x00000080 -#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000 -#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF -#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000 - -#define IFX_SSC_GPOCON_ISCSB0_POS 8 -#define IFX_SSC_GPOCON_IS_CSB0 0x00000100 -#define IFX_SSC_GPOCON_IS_GPO0 0x00000000 -#define IFX_SSC_GPOCON_ISCSB1_POS 9 -#define IFX_SSC_GPOCON_IS_CSB1 0x00000200 -#define IFX_SSC_GPOCON_IS_GPO1 0x00000000 -#define IFX_SSC_GPOCON_ISCSB2_POS 10 -#define IFX_SSC_GPOCON_IS_CSB2 0x00000400 -#define IFX_SSC_GPOCON_IS_GPO2 0x00000000 -#define IFX_SSC_GPOCON_ISCSB3_POS 11 -#define IFX_SSC_GPOCON_IS_CSB3 0x00000800 -#define IFX_SSC_GPOCON_IS_GPO3 0x00000000 -#define IFX_SSC_GPOCON_ISCSB4_POS 12 -#define IFX_SSC_GPOCON_IS_CSB4 0x00001000 -#define IFX_SSC_GPOCON_IS_GPO4 0x00000000 -#define IFX_SSC_GPOCON_ISCSB5_POS 13 -#define IFX_SSC_GPOCON_IS_CSB5 0x00002000 -#define IFX_SSC_GPOCON_IS_GPO5 0x00000000 -#define IFX_SSC_GPOCON_ISCSB6_POS 14 -#define IFX_SSC_GPOCON_IS_CSB6 0x00004000 -#define IFX_SSC_GPOCON_IS_GPO6 0x00000000 -#define IFX_SSC_GPOCON_ISCSB7_POS 15 -#define IFX_SSC_GPOCON_IS_CSB7 0x00008000 -#define IFX_SSC_GPOCON_IS_GPO7 0x00000000 -#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00 -#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000 - -/* GPOSTAT register */ -#define IFX_SSC_GPOSTAT_OUT0 0x00000001 -#define IFX_SSC_GPOSTAT_OUT1 0x00000002 -#define IFX_SSC_GPOSTAT_OUT2 0x00000004 -#define IFX_SSC_GPOSTAT_OUT3 0x00000008 -#define IFX_SSC_GPOSTAT_OUT4 0x00000010 -#define IFX_SSC_GPOSTAT_OUT5 0x00000020 -#define IFX_SSC_GPOSTAT_OUT6 0x00000040 -#define IFX_SSC_GPOSTAT_OUT7 0x00000080 -#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF - -/* WHBGPOSTAT register */ -#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001 -#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002 -#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004 -#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008 -#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010 -#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020 -#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040 -#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080 -#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF - -#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0 -#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1 -#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2 -#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3 -#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4 -#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5 -#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6 -#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7 - - -#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8 -#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100 -#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9 -#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200 -#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10 -#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400 -#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11 -#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800 -#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12 -#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000 -#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13 -#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000 -#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14 -#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000 -#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15 -#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000 -#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00 - -/* SFCON register */ -#define IFX_SSC_SFCON_SF_ENABLE 0x00000001 -#define IFX_SSC_SFCON_SF_DISABLE 0x00000000 -#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004 -#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000 -#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008 -#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000 -#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0 -#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4 -#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000 -#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16 -#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000 -#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000 -#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18 -#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000 -#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000 -#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000 -#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000 -#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000 -#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22 -#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096 -#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024 - -#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET) -#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) -#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK) -#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) - -/* SFSTAT register */ -#define IFX_SSC_SFSTAT_IN_DATA 0x00000001 -#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002 -#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0 -#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4 -#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000 -#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20 - -#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET) -#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET) - -/* RXREQ register */ -#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF -#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0 - -/* RXCNT register */ -#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF -#define IFX_SSC_RXCNT_TODO_OFFSET 0 - -/* DMACON register */ -#define IFX_SSC_DMACON_RXON 0x00000001 -#define IFX_SSC_DMACON_RXOFF 0x00000000 -#define IFX_SSC_DMACON_TXON 0x00000002 -#define IFX_SSC_DMACON_TXOFF 0x00000000 -#define IFX_SSC_DMACON_DMAON 0x00000003 -#define IFX_SSC_DMACON_DMAOFF 0x00000000 -#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C -#define IFX_SSC_DMACON_CLASS_OFFSET 2 - -/* register access macros */ -#define ifx_ssc_fstat_received_words(status) (status & 0x003F) -#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8) - -#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE)) -#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON)) -#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON)) -#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE)) -#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB)) -#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB)) -#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT)) -#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR)) - -#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET) -#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) - -#endif diff --git a/target/linux/amazon/files/include/asm-mips/amazon/irq.h b/target/linux/amazon/files/include/asm-mips/amazon/irq.h deleted file mode 100644 index c575dd64b..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/irq.h +++ /dev/null @@ -1,200 +0,0 @@ -/* irq.h - AMAZON interrupts */ - -#ifndef __AMAZON_IRQ -#define __AMAZON_IRQ - -/************************************************************************ - * Interrupt information -*************************************************************************/ - -/* these vectors are to handle the interrupts from the internal AMAZON - interrupt controller. THe INT_NUM values are really just indices into - an array and are set up so that we can use the INT_NUM as a shift - to calculate a mask value. */ -#define INT_NUM_IRQ0 8 -#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) -#define INT_NUM_IM0_IRL1 (INT_NUM_IRQ0 + 1) -#define INT_NUM_IM0_IRL2 (INT_NUM_IRQ0 + 2) -#define INT_NUM_IM0_IRL3 (INT_NUM_IRQ0 + 3) -#define INT_NUM_IM0_IRL4 (INT_NUM_IRQ0 + 4) -#define INT_NUM_IM0_IRL5 (INT_NUM_IRQ0 + 5) -#define INT_NUM_IM0_IRL6 (INT_NUM_IRQ0 + 6) -#define INT_NUM_IM0_IRL7 (INT_NUM_IRQ0 + 7) -#define INT_NUM_IM0_IRL8 (INT_NUM_IRQ0 + 8) -#define INT_NUM_IM0_IRL9 (INT_NUM_IRQ0 + 9) -#define INT_NUM_IM0_IRL10 (INT_NUM_IRQ0 + 10) -#define INT_NUM_IM0_IRL11 (INT_NUM_IRQ0 + 11) -#define INT_NUM_IM0_IRL12 (INT_NUM_IRQ0 + 12) -#define INT_NUM_IM0_IRL13 (INT_NUM_IRQ0 + 13) -#define INT_NUM_IM0_IRL14 (INT_NUM_IRQ0 + 14) -#define INT_NUM_IM0_IRL15 (INT_NUM_IRQ0 + 15) -#define INT_NUM_IM0_IRL16 (INT_NUM_IRQ0 + 16) -#define INT_NUM_IM0_IRL17 (INT_NUM_IRQ0 + 17) -#define INT_NUM_IM0_IRL18 (INT_NUM_IRQ0 + 18) -#define INT_NUM_IM0_IRL19 (INT_NUM_IRQ0 + 19) -#define INT_NUM_IM0_IRL20 (INT_NUM_IRQ0 + 20) -#define INT_NUM_IM0_IRL21 (INT_NUM_IRQ0 + 21) -#define INT_NUM_IM0_IRL22 (INT_NUM_IRQ0 + 22) -#define INT_NUM_IM0_IRL23 (INT_NUM_IRQ0 + 23) -#define INT_NUM_IM0_IRL24 (INT_NUM_IRQ0 + 24) -#define INT_NUM_IM0_IRL25 (INT_NUM_IRQ0 + 25) -#define INT_NUM_IM0_IRL26 (INT_NUM_IRQ0 + 26) -#define INT_NUM_IM0_IRL27 (INT_NUM_IRQ0 + 27) -#define INT_NUM_IM0_IRL28 (INT_NUM_IRQ0 + 28) -#define INT_NUM_IM0_IRL29 (INT_NUM_IRQ0 + 29) -#define INT_NUM_IM0_IRL30 (INT_NUM_IRQ0 + 30) -#define INT_NUM_IM0_IRL31 (INT_NUM_IRQ0 + 31) - -#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) -#define INT_NUM_IM1_IRL1 (INT_NUM_IM1_IRL0 + 1) -#define INT_NUM_IM1_IRL2 (INT_NUM_IM1_IRL0 + 2) -#define INT_NUM_IM1_IRL3 (INT_NUM_IM1_IRL0 + 3) -#define INT_NUM_IM1_IRL4 (INT_NUM_IM1_IRL0 + 4) -#define INT_NUM_IM1_IRL5 (INT_NUM_IM1_IRL0 + 5) -#define INT_NUM_IM1_IRL6 (INT_NUM_IM1_IRL0 + 6) -#define INT_NUM_IM1_IRL7 (INT_NUM_IM1_IRL0 + 7) -#define INT_NUM_IM1_IRL8 (INT_NUM_IM1_IRL0 + 8) -#define INT_NUM_IM1_IRL9 (INT_NUM_IM1_IRL0 + 9) -#define INT_NUM_IM1_IRL10 (INT_NUM_IM1_IRL0 + 10) -#define INT_NUM_IM1_IRL11 (INT_NUM_IM1_IRL0 + 11) -#define INT_NUM_IM1_IRL12 (INT_NUM_IM1_IRL0 + 12) -#define INT_NUM_IM1_IRL13 (INT_NUM_IM1_IRL0 + 13) -#define INT_NUM_IM1_IRL14 (INT_NUM_IM1_IRL0 + 14) -#define INT_NUM_IM1_IRL15 (INT_NUM_IM1_IRL0 + 15) -#define INT_NUM_IM1_IRL16 (INT_NUM_IM1_IRL0 + 16) -#define INT_NUM_IM1_IRL17 (INT_NUM_IM1_IRL0 + 17) -#define INT_NUM_IM1_IRL18 (INT_NUM_IM1_IRL0 + 18) -#define INT_NUM_IM1_IRL19 (INT_NUM_IM1_IRL0 + 19) -#define INT_NUM_IM1_IRL20 (INT_NUM_IM1_IRL0 + 20) -#define INT_NUM_IM1_IRL21 (INT_NUM_IM1_IRL0 + 21) -#define INT_NUM_IM1_IRL22 (INT_NUM_IM1_IRL0 + 22) -#define INT_NUM_IM1_IRL23 (INT_NUM_IM1_IRL0 + 23) -#define INT_NUM_IM1_IRL24 (INT_NUM_IM1_IRL0 + 24) -#define INT_NUM_IM1_IRL25 (INT_NUM_IM1_IRL0 + 25) -#define INT_NUM_IM1_IRL26 (INT_NUM_IM1_IRL0 + 26) -#define INT_NUM_IM1_IRL27 (INT_NUM_IM1_IRL0 + 27) -#define INT_NUM_IM1_IRL28 (INT_NUM_IM1_IRL0 + 28) -#define INT_NUM_IM1_IRL29 (INT_NUM_IM1_IRL0 + 29) -#define INT_NUM_IM1_IRL30 (INT_NUM_IM1_IRL0 + 30) -#define INT_NUM_IM1_IRL31 (INT_NUM_IM1_IRL0 + 31) - -#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64) -#define INT_NUM_IM2_IRL1 (INT_NUM_IM2_IRL0 + 1) -#define INT_NUM_IM2_IRL2 (INT_NUM_IM2_IRL0 + 2) -#define INT_NUM_IM2_IRL3 (INT_NUM_IM2_IRL0 + 3) -#define INT_NUM_IM2_IRL4 (INT_NUM_IM2_IRL0 + 4) -#define INT_NUM_IM2_IRL5 (INT_NUM_IM2_IRL0 + 5) -#define INT_NUM_IM2_IRL6 (INT_NUM_IM2_IRL0 + 6) -#define INT_NUM_IM2_IRL7 (INT_NUM_IM2_IRL0 + 7) -#define INT_NUM_IM2_IRL8 (INT_NUM_IM2_IRL0 + 8) -#define INT_NUM_IM2_IRL9 (INT_NUM_IM2_IRL0 + 9) -#define INT_NUM_IM2_IRL10 (INT_NUM_IM2_IRL0 + 10) -#define INT_NUM_IM2_IRL11 (INT_NUM_IM2_IRL0 + 11) -#define INT_NUM_IM2_IRL12 (INT_NUM_IM2_IRL0 + 12) -#define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13) -#define INT_NUM_IM2_IRL14 (INT_NUM_IM2_IRL0 + 14) -#define INT_NUM_IM2_IRL15 (INT_NUM_IM2_IRL0 + 15) -#define INT_NUM_IM2_IRL16 (INT_NUM_IM2_IRL0 + 16) -#define INT_NUM_IM2_IRL17 (INT_NUM_IM2_IRL0 + 17) -#define INT_NUM_IM2_IRL18 (INT_NUM_IM2_IRL0 + 18) -#define INT_NUM_IM2_IRL19 (INT_NUM_IM2_IRL0 + 19) -#define INT_NUM_IM2_IRL20 (INT_NUM_IM2_IRL0 + 20) -#define INT_NUM_IM2_IRL21 (INT_NUM_IM2_IRL0 + 21) -#define INT_NUM_IM2_IRL22 (INT_NUM_IM2_IRL0 + 22) -#define INT_NUM_IM2_IRL23 (INT_NUM_IM2_IRL0 + 23) -#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24) -#define INT_NUM_IM2_IRL25 (INT_NUM_IM2_IRL0 + 25) -#define INT_NUM_IM2_IRL26 (INT_NUM_IM2_IRL0 + 26) -#define INT_NUM_IM2_IRL27 (INT_NUM_IM2_IRL0 + 27) -#define INT_NUM_IM2_IRL28 (INT_NUM_IM2_IRL0 + 28) -#define INT_NUM_IM2_IRL29 (INT_NUM_IM2_IRL0 + 29) -#define INT_NUM_IM2_IRL30 (INT_NUM_IM2_IRL0 + 30) -#define INT_NUM_IM2_IRL31 (INT_NUM_IM2_IRL0 + 31) - -#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96) -#define INT_NUM_IM3_IRL1 (INT_NUM_IM3_IRL0 + 1) -#define INT_NUM_IM3_IRL2 (INT_NUM_IM3_IRL0 + 2) -#define INT_NUM_IM3_IRL3 (INT_NUM_IM3_IRL0 + 3) -#define INT_NUM_IM3_IRL4 (INT_NUM_IM3_IRL0 + 4) -#define INT_NUM_IM3_IRL5 (INT_NUM_IM3_IRL0 + 5) -#define INT_NUM_IM3_IRL6 (INT_NUM_IM3_IRL0 + 6) -#define INT_NUM_IM3_IRL7 (INT_NUM_IM3_IRL0 + 7) -#define INT_NUM_IM3_IRL8 (INT_NUM_IM3_IRL0 + 8) -#define INT_NUM_IM3_IRL9 (INT_NUM_IM3_IRL0 + 9) -#define INT_NUM_IM3_IRL10 (INT_NUM_IM3_IRL0 + 10) -#define INT_NUM_IM3_IRL11 (INT_NUM_IM3_IRL0 + 11) -#define INT_NUM_IM3_IRL12 (INT_NUM_IM3_IRL0 + 12) -#define INT_NUM_IM3_IRL13 (INT_NUM_IM3_IRL0 + 13) -#define INT_NUM_IM3_IRL14 (INT_NUM_IM3_IRL0 + 14) -#define INT_NUM_IM3_IRL15 (INT_NUM_IM3_IRL0 + 15) -#define INT_NUM_IM3_IRL16 (INT_NUM_IM3_IRL0 + 16) -#define INT_NUM_IM3_IRL17 (INT_NUM_IM3_IRL0 + 17) -#define INT_NUM_IM3_IRL18 (INT_NUM_IM3_IRL0 + 18) -#define INT_NUM_IM3_IRL19 (INT_NUM_IM3_IRL0 + 19) -#define INT_NUM_IM3_IRL20 (INT_NUM_IM3_IRL0 + 20) -#define INT_NUM_IM3_IRL21 (INT_NUM_IM3_IRL0 + 21) -#define INT_NUM_IM3_IRL22 (INT_NUM_IM3_IRL0 + 22) -#define INT_NUM_IM3_IRL23 (INT_NUM_IM3_IRL0 + 23) -#define INT_NUM_IM3_IRL24 (INT_NUM_IM3_IRL0 + 24) -#define INT_NUM_IM3_IRL25 (INT_NUM_IM3_IRL0 + 25) -#define INT_NUM_IM3_IRL26 (INT_NUM_IM3_IRL0 + 26) -#define INT_NUM_IM3_IRL27 (INT_NUM_IM3_IRL0 + 27) -#define INT_NUM_IM3_IRL28 (INT_NUM_IM3_IRL0 + 28) -#define INT_NUM_IM3_IRL29 (INT_NUM_IM3_IRL0 + 29) -#define INT_NUM_IM3_IRL30 (INT_NUM_IM3_IRL0 + 30) -#define INT_NUM_IM3_IRL31 (INT_NUM_IM3_IRL0 + 31) - -#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) -#define INT_NUM_IM4_IRL1 (INT_NUM_IM4_IRL0 + 1) -#define INT_NUM_IM4_IRL2 (INT_NUM_IM4_IRL0 + 2) -#define INT_NUM_IM4_IRL3 (INT_NUM_IM4_IRL0 + 3) -#define INT_NUM_IM4_IRL4 (INT_NUM_IM4_IRL0 + 4) -#define INT_NUM_IM4_IRL5 (INT_NUM_IM4_IRL0 + 5) -#define INT_NUM_IM4_IRL6 (INT_NUM_IM4_IRL0 + 6) -#define INT_NUM_IM4_IRL7 (INT_NUM_IM4_IRL0 + 7) -#define INT_NUM_IM4_IRL8 (INT_NUM_IM4_IRL0 + 8) -#define INT_NUM_IM4_IRL9 (INT_NUM_IM4_IRL0 + 9) -#define INT_NUM_IM4_IRL10 (INT_NUM_IM4_IRL0 + 10) -#define INT_NUM_IM4_IRL11 (INT_NUM_IM4_IRL0 + 11) -#define INT_NUM_IM4_IRL12 (INT_NUM_IM4_IRL0 + 12) -#define INT_NUM_IM4_IRL13 (INT_NUM_IM4_IRL0 + 13) -#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) -#define INT_NUM_IM4_IRL15 (INT_NUM_IM4_IRL0 + 15) -#define INT_NUM_IM4_IRL16 (INT_NUM_IM4_IRL0 + 16) -#define INT_NUM_IM4_IRL17 (INT_NUM_IM4_IRL0 + 17) -#define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18) -#define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19) -#define INT_NUM_IM4_IRL20 (INT_NUM_IM4_IRL0 + 20) -#define INT_NUM_IM4_IRL21 (INT_NUM_IM4_IRL0 + 21) -#define INT_NUM_IM4_IRL22 (INT_NUM_IM4_IRL0 + 22) -#define INT_NUM_IM4_IRL23 (INT_NUM_IM4_IRL0 + 23) -#define INT_NUM_IM4_IRL24 (INT_NUM_IM4_IRL0 + 24) -#define INT_NUM_IM4_IRL25 (INT_NUM_IM4_IRL0 + 25) -#define INT_NUM_IM4_IRL26 (INT_NUM_IM4_IRL0 + 26) -#define INT_NUM_IM4_IRL27 (INT_NUM_IM4_IRL0 + 27) -#define INT_NUM_IM4_IRL28 (INT_NUM_IM4_IRL0 + 28) -#define INT_NUM_IM4_IRL29 (INT_NUM_IM4_IRL0 + 29) -#define INT_NUM_IM4_IRL30 (INT_NUM_IM4_IRL0 + 30) -#define INT_NUM_IM4_IRL31 (INT_NUM_IM4_IRL0 + 31) - -/****** Interrupt Assigments ***********/ -#define AMAZON_DMA_INT INT_NUM_IM0_IRL0 -#define IFX_SSC_TIR INT_NUM_IM0_IRL29 -#define IFX_SSC_RIR INT_NUM_IM0_IRL30 -#define IFX_SSC_EIR INT_NUM_IM0_IRL31 - -#define AMAZON_MEI_INT INT_NUM_IM2_IRL8 - -#define AMAZONASC_TIR INT_NUM_IM4_IRL15/* TX interrupt */ -#define AMAZONASC_RIR INT_NUM_IM4_IRL16/* RX interrupt */ -#define AMAZONASC_EIR INT_NUM_IM4_IRL17/* ERROR interrupt */ - -#define AMAZON_TIMER6_INT INT_NUM_IM1_IRL23 - -#define AMAZON_SWIE_INT INT_NUM_IM3_IRL8 -#define AMAZON_CBM_INT INT_NUM_IM3_IRL9 -#define AMAZON_AAL5_INT INT_NUM_IM3_IRL10 -#define AMAZON_HTU_INT INT_NUM_IM3_IRL11 -#define AMAZON_QSB_INT INT_NUM_IM3_IRL12 -#define MIPS_CPU_TIMER_IRQ 7 -#endif /* __AMAZON_IRQ */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/model.h b/target/linux/amazon/files/include/asm-mips/amazon/model.h deleted file mode 100644 index 4e43ab5f1..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/model.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef AMAZON_MODEL_H -#define AMAZON_MODEL_H -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ -#define BOARD_SYSTEM_TYPE "AMAZON" -#define SYSTEM_MODEL_NAME "Amazon Gateway Package 3.2 Version" -#endif diff --git a/target/linux/amazon/files/include/asm-mips/amazon/port.h b/target/linux/amazon/files/include/asm-mips/amazon/port.h deleted file mode 100644 index 21825794c..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/port.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * port.h - * - * Global Amazon port driver header file - * - */ - -/* Modification history */ -/* 21Jun2004 btxu Generate from Inca_IP project */ - - -#ifndef PORT_H -#define PORT_H - -struct amazon_port_ioctl_parm { - int port; - int pin; - int value; -}; -#define AMAZON_PORT_IOC_MAGIC 0xbf -#define AMAZON_PORT_IOCOD _IOW( AMAZON_PORT_IOC_MAGIC,0,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCPUDSEL _IOW( AMAZON_PORT_IOC_MAGIC,1,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCPUDEN _IOW( AMAZON_PORT_IOC_MAGIC,2,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCSTOFF _IOW( AMAZON_PORT_IOC_MAGIC,3,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCDIR _IOW( AMAZON_PORT_IOC_MAGIC,4,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCOUTPUT _IOW( AMAZON_PORT_IOC_MAGIC,5,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCINPUT _IOWR(AMAZON_PORT_IOC_MAGIC,6,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCALTSEL0 _IOW( AMAZON_PORT_IOC_MAGIC,7,struct amazon_port_ioctl_parm) -#define AMAZON_PORT_IOCALTSEL1 _IOW( AMAZON_PORT_IOC_MAGIC,8,struct amazon_port_ioctl_parm) - -int amazon_port_reserve_pin(int port, int pin, int module_id); -int amazon_port_free_pin(int port, int pin, int module_id); -int amazon_port_set_open_drain(int port, int pin, int module_id); -int amazon_port_clear_open_drain(int port, int pin, int module_id); -int amazon_port_set_pudsel(int port, int pin, int module_id); -int amazon_port_clear_pudsel(int port, int pin, int module_id); -int amazon_port_set_puden(int port, int pin, int module_id); -int amazon_port_clear_puden(int port, int pin, int module_id); -int amazon_port_set_stoff(int port, int pin, int module_id); -int amazon_port_clear_stoff(int port, int pin, int module_id); -int amazon_port_set_dir_out(int port, int pin, int module_id); -int amazon_port_set_dir_in(int port, int pin, int module_id); -int amazon_port_set_output(int port, int pin, int module_id); -int amazon_port_clear_output(int port, int pin, int module_id); -int amazon_port_get_input(int port, int pin, int module_id); - -int amazon_port_set_altsel0(int port, int pin, int module_id); -int amazon_port_clear_altsel0(int port, int pin, int module_id); -int amazon_port_set_altsel1(int port, int pin, int module_id); -int amazon_port_clear_altsel1(int port, int pin, int module_id); - - -#endif /* PORT_H */ - - diff --git a/target/linux/amazon/files/include/asm-mips/amazon/serial.h b/target/linux/amazon/files/include/asm-mips/amazon/serial.h deleted file mode 100644 index 3ff3efc28..000000000 --- a/target/linux/amazon/files/include/asm-mips/amazon/serial.h +++ /dev/null @@ -1,146 +0,0 @@ -/* incaAscSio.h - (AMAZON) ASC UART tty driver header */ - -#ifndef __AMAZON_ASC_H -#define __AMAZON_ASC_H - -/* channel operating modes */ -#define ASCOPT_CSIZE 0x00000003 -#define ASCOPT_CS7 0x00000001 -#define ASCOPT_CS8 0x00000002 -#define ASCOPT_PARENB 0x00000004 -#define ASCOPT_STOPB 0x00000008 -#define ASCOPT_PARODD 0x00000010 -#define ASCOPT_CREAD 0x00000020 - -#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) - -/* ASC input select (0 or 1) */ -#define CONSOLE_TTY 0 - -/* use fractional divider for baudrate settings */ -#define AMAZONASC_USE_FDV - -#ifdef AMAZONASC_USE_FDV - #define AMAZONASC_FDV_LOW_BAUDRATE 71 -#ifdef CONFIG_USE_IKOS - #define AMAZONASC_FDV_HIGH_BAUDRATE 443 -#else - #define AMAZONASC_FDV_HIGH_BAUDRATE 498 -#endif //CONFIG_USE_IKOS -#endif /*AMAZONASC_USE_FDV*/ - - -#define AMAZONASC_TXFIFO_FL 1 -#define AMAZONASC_RXFIFO_FL 1 -#define AMAZONASC_TXFIFO_FULL 16 - -/* interrupt lines masks for the ASC device interrupts*/ -/* change these macroses if it's necessary */ -#define AMAZONASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */ - -#define AMAZONASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */ -#define AMAZONASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */ -#define AMAZONASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */ -#define AMAZONASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/ - -/* CLC register's bits and bitfields */ -#define ASCCLC_DISR 0x00000001 -#define ASCCLC_DISS 0x00000002 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 - -/* CON register's bits and bitfields */ -#define ASCCON_MODEMASK 0x0007 - #define ASCCON_M_8SYNC 0x0 - #define ASCCON_M_8ASYNC 0x1 - #define ASCCON_M_8IRDAASYNC 0x2 - #define ASCCON_M_7ASYNCPAR 0x3 - #define ASCCON_M_9ASYNC 0x4 - #define ASCCON_M_8WAKEUPASYNC 0x5 - #define ASCCON_M_8ASYNCPAR 0x7 -#define ASCCON_STP 0x0008 -#define ASCCON_REN 0x0010 -#define ASCCON_PEN 0x0020 -#define ASCCON_FEN 0x0040 -#define ASCCON_OEN 0x0080 -#define ASCCON_PE 0x0100 -#define ASCCON_FE 0x0200 -#define ASCCON_OE 0x0400 -#define ASCCON_FDE 0x0800 -#define ASCCON_ODD 0x1000 -#define ASCCON_BRS 0x2000 -#define ASCCON_LB 0x4000 -#define ASCCON_R 0x8000 -#define ASCCON_ANY (ASCCON_PE|ASCCON_FE|ASCCON_OE) - -/* WHBCON register's bits and bitfields */ -#define ASCWHBCON_CLRREN 0x0010 -#define ASCWHBCON_SETREN 0x0020 -#define ASCWHBCON_CLRPE 0x0100 -#define ASCWHBCON_CLRFE 0x0200 -#define ASCWHBCON_CLROE 0x0400 -#define ASCWHBCON_SETPE 0x0800 -#define ASCWHBCON_SETFE 0x1000 -#define ASCWHBCON_SETOE 0x2000 - -/* ABCON register's bits and bitfields */ -#define ASCABCON_ABEN 0x0001 -#define ASCABCON_AUREN 0x0002 -#define ASCABCON_ABSTEN 0x0004 -#define ASCABCON_ABDETEN 0x0008 -#define ASCABCON_FCDETEN 0x0010 -#define ASCABCON_EMMASK 0x0300 - #define ASCABCON_EMOFF 8 - #define ASCABCON_EM_DISAB 0x0 - #define ASCABCON_EM_DURAB 0x1 - #define ASCABCON_EM_ALWAYS 0x2 -#define ASCABCON_TXINV 0x0400 -#define ASCABCON_RXINV 0x0800 - -/* FDV register mask, offset and bitfields*/ -#define ASCFDV_VALUE_MASK 0x000001FF - -/* WHBABCON register's bits and bitfields */ -#define ASCWHBABCON_SETABEN 0x0001 -#define ASCWHBABCON_CLRABEN 0x0002 - -/* ABSTAT register's bits and bitfields */ -#define ASCABSTAT_FCSDET 0x0001 -#define ASCABSTAT_FCCDET 0x0002 -#define ASCABSTAT_SCSDET 0x0004 -#define ASCABSTAT_SCCDET 0x0008 -#define ASCABSTAT_DETWAIT 0x0010 - -/* WHBABSTAT register's bits and bitfields */ -#define ASCWHBABSTAT_CLRFCSDET 0x0001 -#define ASCWHBABSTAT_SETFCSDET 0x0002 -#define ASCWHBABSTAT_CLRFCCDET 0x0004 -#define ASCWHBABSTAT_SETFCCDET 0x0008 -#define ASCWHBABSTAT_CLRSCSDET 0x0010 -#define ASCWHBABSTAT_SETSCSDET 0x0020 -#define ASCWHBABSTAT_SETSCCDET 0x0040 -#define ASCWHBABSTAT_CLRSCCDET 0x0080 -#define ASCWHBABSTAT_CLRDETWAIT 0x0100 -#define ASCWHBABSTAT_SETDETWAIT 0x0200 - -/* TXFCON register's bits and bitfields */ -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXTMEN 0x0004 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 - -/* RXFCON register's bits and bitfields */ -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXTMEN 0x0004 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 - -/* FSTAT register's bits and bitfields */ -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - -#endif /* __AMAZON_ASC_H */ - diff --git a/target/linux/amazon/patches-2.6.30/000-mips-bad-intctl.patch b/target/linux/amazon/patches-2.6.30/000-mips-bad-intctl.patch deleted file mode 100644 index 5de5064dc..000000000 --- a/target/linux/amazon/patches-2.6.30/000-mips-bad-intctl.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- a/arch/mips/kernel/traps.c -+++ b/arch/mips/kernel/traps.c -@@ -1542,7 +1542,16 @@ void __cpuinit per_cpu_trap_init(void) - */ - if (cpu_has_mips_r2) { - cp0_compare_irq = (read_c0_intctl() >> 29) & 7; -+ if (!cp0_compare_irq) -+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; -+ - cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; -+ if (!cp0_perfcount_irq) -+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ; -+ -+ if (arch_fixup_c0_irqs) -+ arch_fixup_c0_irqs(); -+ - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; - } else { ---- a/arch/mips/include/asm/irq.h -+++ b/arch/mips/include/asm/irq.h -@@ -157,8 +157,10 @@ extern void free_irqno(unsigned int irq) - * IE7. Since R2 their number has to be read from the c0_intctl register. - */ - #define CP0_LEGACY_COMPARE_IRQ 7 -+#define CP0_LEGACY_PERFCNT_IRQ 7 - - extern int cp0_compare_irq; - extern int cp0_perfcount_irq; -+extern void __weak arch_fixup_c0_irqs(void); - - #endif /* _ASM_IRQ_H */ diff --git a/target/linux/amazon/patches-2.6.30/010-mips_clocksource_init_war.patch b/target/linux/amazon/patches-2.6.30/010-mips_clocksource_init_war.patch deleted file mode 100644 index ac44c308f..000000000 --- a/target/linux/amazon/patches-2.6.30/010-mips_clocksource_init_war.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -21,6 +21,22 @@ - - #ifndef CONFIG_MIPS_MT_SMTC - -+/* -+ * Compare interrupt can be routed and latched outside the core, -+ * so a single execution hazard barrier may not be enough to give -+ * it time to clear as seen in the Cause register. 4 time the -+ * pipeline depth seems reasonably conservative, and empirically -+ * works better in configurations with high CPU/bus clock ratios. -+ */ -+ -+#define compare_change_hazard() \ -+ do { \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ } while (0) -+ - static int mips_next_event(unsigned long delta, - struct clock_event_device *evt) - { -@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -+ compare_change_hazard(); - res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - return res; - } diff --git a/target/linux/amazon/patches-2.6.30/017-wdt-driver.patch b/target/linux/amazon/patches-2.6.30/017-wdt-driver.patch deleted file mode 100644 index bee390bbb..000000000 --- a/target/linux/amazon/patches-2.6.30/017-wdt-driver.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/watchdog/Makefile -+++ b/drivers/watchdog/Makefile -@@ -105,6 +105,7 @@ obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o -+obj-$(CONFIG_AMAZON_WDT) += amazon_wdt.o - - # PARISC Architecture - diff --git a/target/linux/amazon/patches-2.6.30/100-board.patch b/target/linux/amazon/patches-2.6.30/100-board.patch deleted file mode 100644 index 66d5fd62d..000000000 --- a/target/linux/amazon/patches-2.6.30/100-board.patch +++ /dev/null @@ -1,49 +0,0 @@ ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -60,6 +60,22 @@ config BCM47XX - help - Support for BCM47XX based boards - -+config AMAZON -+ bool "Amazon support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select CEVT_R4K -+ select CSRC_R4K -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_HAS_CPU_MIPS32_R2 -+ select HAVE_STD_PC_SERIAL_PORT -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_HAS_EARLY_PRINTK -+ select HW_HAS_PCI -+ select SWAP_IO_SPACE -+ - config MIPS_COBALT - bool "Cobalt Server" - select CEVT_R4K -@@ -633,6 +649,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD - - endchoice - -+source "arch/mips/amazon/Kconfig" - source "arch/mips/alchemy/Kconfig" - source "arch/mips/basler/excite/Kconfig" - source "arch/mips/jazz/Kconfig" ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -283,6 +283,13 @@ libs-$(CONFIG_MIPS_XXS1500) += arch/mips - load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 - - # -+# Infineon AMAZON -+# -+core-$(CONFIG_AMAZON) += arch/mips/amazon/ -+cflags-$(CONFIG_AMAZON) += -I$(srctree)/arch/mips/include/asm/mach-amazon -+load-$(CONFIG_AMAZON) += 0xffffffff80002000 -+ -+# - # Cobalt Server - # - core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/ diff --git a/target/linux/amazon/patches-2.6.30/130-mtd_drivers.patch b/target/linux/amazon/patches-2.6.30/130-mtd_drivers.patch deleted file mode 100644 index aaf3a8d8a..000000000 --- a/target/linux/amazon/patches-2.6.30/130-mtd_drivers.patch +++ /dev/null @@ -1,7 +0,0 @@ ---- a/drivers/mtd/maps/Makefile -+++ b/drivers/mtd/maps/Makefile -@@ -62,3 +62,4 @@ obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_ - obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-async-flash.o - obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o - obj-$(CONFIG_MTD_VMU) += vmu-flash.o -+obj-$(CONFIG_AMAZON_MTD) += amazon.o diff --git a/target/linux/amazon/patches-2.6.30/140-net_drivers.patch b/target/linux/amazon/patches-2.6.30/140-net_drivers.patch deleted file mode 100644 index 5c677fd2e..000000000 --- a/target/linux/amazon/patches-2.6.30/140-net_drivers.patch +++ /dev/null @@ -1,9 +0,0 @@ ---- a/drivers/net/Makefile -+++ b/drivers/net/Makefile -@@ -272,3 +272,6 @@ obj-$(CONFIG_VIRTIO_NET) += virtio_net.o - obj-$(CONFIG_SFC) += sfc/ - - obj-$(CONFIG_WIMAX) += wimax/ -+ -+obj-$(CONFIG_AMAZON_NET_SW) += amazon_sw.o -+obj-$(CONFIG_ADM6996_SUPPORT) += admmod.o diff --git a/target/linux/amazon/patches-2.6.30/150-serial_driver.patch b/target/linux/amazon/patches-2.6.30/150-serial_driver.patch deleted file mode 100644 index 8b7741c93..000000000 --- a/target/linux/amazon/patches-2.6.30/150-serial_driver.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/serial/Makefile -+++ b/drivers/serial/Makefile -@@ -3,6 +3,7 @@ - # - - obj-$(CONFIG_SERIAL_CORE) += serial_core.o -+obj-$(CONFIG_AMAZON_ASC_UART) += amazon_asc.o - obj-$(CONFIG_SERIAL_21285) += 21285.o - - # These Sparc drivers have to appear before others such as 8250 diff --git a/target/linux/amazon/patches-2.6.30/160-cfi-swap.patch b/target/linux/amazon/patches-2.6.30/160-cfi-swap.patch deleted file mode 100644 index 4809fccd8..000000000 --- a/target/linux/amazon/patches-2.6.30/160-cfi-swap.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -1090,6 +1090,9 @@ static int __xipram do_write_oneword(str - int retry_cnt = 0; - - adr += chip->start; -+#ifdef CONFIG_AMAZON -+ adr ^= 2; -+#endif - - spin_lock(chip->mutex); - ret = get_chip(map, chip, adr, FL_WRITING); -@@ -1372,7 +1375,11 @@ static int __xipram do_write_buffer(stru - z = 0; - while(z < words * map_bankwidth(map)) { - datum = map_word_load(map, buf); -+#ifdef CONFIG_AMAZON -+ map_write(map, datum, (adr + z) ^ 0x2); -+#else - map_write(map, datum, adr + z); -+#endif - - z += map_bankwidth(map); - buf += map_bankwidth(map); -@@ -1617,6 +1624,9 @@ static int __xipram do_erase_oneblock(st - int ret = 0; - - adr += chip->start; -+#ifdef CONFIG_AMAZON -+ adr ^= 2; -+#endif - - spin_lock(chip->mutex); - ret = get_chip(map, chip, adr, FL_ERASING); -@@ -1745,6 +1755,10 @@ static int do_atmel_lock(struct map_info - struct cfi_private *cfi = map->fldrv_priv; - int ret; - -+#ifdef CONFIG_AMAZON -+ adr ^= 2; -+#endif -+ - spin_lock(chip->mutex); - ret = get_chip(map, chip, adr + chip->start, FL_LOCKING); - if (ret) -@@ -1781,6 +1795,10 @@ static int do_atmel_unlock(struct map_in - struct cfi_private *cfi = map->fldrv_priv; - int ret; - -+#ifdef CONFIG_AMAZON -+ adr ^= 2; -+#endif -+ - spin_lock(chip->mutex); - ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING); - if (ret) diff --git a/target/linux/amazon/patches-2.6.32/000-mips-bad-intctl.patch b/target/linux/amazon/patches-2.6.32/000-mips-bad-intctl.patch deleted file mode 100644 index ad3fe9fb3..000000000 --- a/target/linux/amazon/patches-2.6.32/000-mips-bad-intctl.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- a/arch/mips/kernel/traps.c -+++ b/arch/mips/kernel/traps.c -@@ -1537,7 +1537,16 @@ void __cpuinit per_cpu_trap_init(void) - */ - if (cpu_has_mips_r2) { - cp0_compare_irq = (read_c0_intctl() >> 29) & 7; -+ if (!cp0_compare_irq) -+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; -+ - cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; -+ if (!cp0_perfcount_irq) -+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ; -+ -+ if (arch_fixup_c0_irqs) -+ arch_fixup_c0_irqs(); -+ - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; - } else { ---- a/arch/mips/include/asm/irq.h -+++ b/arch/mips/include/asm/irq.h -@@ -158,8 +158,10 @@ extern void free_irqno(unsigned int irq) - * IE7. Since R2 their number has to be read from the c0_intctl register. - */ - #define CP0_LEGACY_COMPARE_IRQ 7 -+#define CP0_LEGACY_PERFCNT_IRQ 7 - - extern int cp0_compare_irq; - extern int cp0_perfcount_irq; -+extern void __weak arch_fixup_c0_irqs(void); - - #endif /* _ASM_IRQ_H */ diff --git a/target/linux/amazon/patches-2.6.32/010-mips_clocksource_init_war.patch b/target/linux/amazon/patches-2.6.32/010-mips_clocksource_init_war.patch deleted file mode 100644 index 81eabc6dc..000000000 --- a/target/linux/amazon/patches-2.6.32/010-mips_clocksource_init_war.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -22,6 +22,22 @@ - - #ifndef CONFIG_MIPS_MT_SMTC - -+/* -+ * Compare interrupt can be routed and latched outside the core, -+ * so a single execution hazard barrier may not be enough to give -+ * it time to clear as seen in the Cause register. 4 time the -+ * pipeline depth seems reasonably conservative, and empirically -+ * works better in configurations with high CPU/bus clock ratios. -+ */ -+ -+#define compare_change_hazard() \ -+ do { \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ } while (0) -+ - static int mips_next_event(unsigned long delta, - struct clock_event_device *evt) - { -@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -+ compare_change_hazard(); - res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - return res; - } diff --git a/target/linux/amazon/patches-2.6.32/017-wdt-driver.patch b/target/linux/amazon/patches-2.6.32/017-wdt-driver.patch deleted file mode 100644 index 433abd51e..000000000 --- a/target/linux/amazon/patches-2.6.32/017-wdt-driver.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/watchdog/Makefile -+++ b/drivers/watchdog/Makefile -@@ -113,6 +113,7 @@ obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o -+obj-$(CONFIG_AMAZON_WDT) += amazon_wdt.o - - # PARISC Architecture - diff --git a/target/linux/amazon/patches-2.6.32/100-board.patch b/target/linux/amazon/patches-2.6.32/100-board.patch deleted file mode 100644 index d1d9c471a..000000000 --- a/target/linux/amazon/patches-2.6.32/100-board.patch +++ /dev/null @@ -1,49 +0,0 @@ ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -96,6 +96,22 @@ config BCM63XX - help - Support for BCM63XX based boards - -+config AMAZON -+ bool "Amazon support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select CEVT_R4K -+ select CSRC_R4K -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_HAS_CPU_MIPS32_R2 -+ select HAVE_STD_PC_SERIAL_PORT -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_HAS_EARLY_PRINTK -+ select HW_HAS_PCI -+ select SWAP_IO_SPACE -+ - config MIPS_COBALT - bool "Cobalt Server" - select CEVT_R4K -@@ -673,6 +689,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD - - endchoice - -+source "arch/mips/amazon/Kconfig" - source "arch/mips/alchemy/Kconfig" - source "arch/mips/basler/excite/Kconfig" - source "arch/mips/bcm63xx/Kconfig" ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -296,6 +296,13 @@ cflags-$(CONFIG_SOC_AU1X00) += -I$(srctr - - - # -+# Infineon AMAZON -+# -+core-$(CONFIG_AMAZON) += arch/mips/amazon/ -+cflags-$(CONFIG_AMAZON) += -I$(srctree)/arch/mips/include/asm/mach-amazon -+load-$(CONFIG_AMAZON) += 0xffffffff80002000 -+ -+# - # Cobalt Server - # - core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/ diff --git a/target/linux/amazon/patches-2.6.32/130-mtd_drivers.patch b/target/linux/amazon/patches-2.6.32/130-mtd_drivers.patch deleted file mode 100644 index fafd99670..000000000 --- a/target/linux/amazon/patches-2.6.32/130-mtd_drivers.patch +++ /dev/null @@ -1,7 +0,0 @@ ---- a/drivers/mtd/maps/Makefile -+++ b/drivers/mtd/maps/Makefile -@@ -61,3 +61,4 @@ obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-asy - obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o - obj-$(CONFIG_MTD_VMU) += vmu-flash.o - obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o -+obj-$(CONFIG_AMAZON_MTD) += amazon.o diff --git a/target/linux/amazon/patches-2.6.32/140-net_drivers.patch b/target/linux/amazon/patches-2.6.32/140-net_drivers.patch deleted file mode 100644 index e64908c76..000000000 --- a/target/linux/amazon/patches-2.6.32/140-net_drivers.patch +++ /dev/null @@ -1,9 +0,0 @@ ---- a/drivers/net/Makefile -+++ b/drivers/net/Makefile -@@ -286,3 +286,6 @@ obj-$(CONFIG_VIRTIO_NET) += virtio_net.o - obj-$(CONFIG_SFC) += sfc/ - - obj-$(CONFIG_WIMAX) += wimax/ -+ -+obj-$(CONFIG_AMAZON_NET_SW) += amazon_sw.o -+obj-$(CONFIG_ADM6996_SUPPORT) += admmod.o diff --git a/target/linux/amazon/patches-2.6.32/150-serial_driver.patch b/target/linux/amazon/patches-2.6.32/150-serial_driver.patch deleted file mode 100644 index 8b7741c93..000000000 --- a/target/linux/amazon/patches-2.6.32/150-serial_driver.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/serial/Makefile -+++ b/drivers/serial/Makefile -@@ -3,6 +3,7 @@ - # - - obj-$(CONFIG_SERIAL_CORE) += serial_core.o -+obj-$(CONFIG_AMAZON_ASC_UART) += amazon_asc.o - obj-$(CONFIG_SERIAL_21285) += 21285.o - - # These Sparc drivers have to appear before others such as 8250 diff --git a/target/linux/amazon/patches-2.6.32/160-cfi-swap.patch b/target/linux/amazon/patches-2.6.32/160-cfi-swap.patch deleted file mode 100644 index bb89f6110..000000000 --- a/target/linux/amazon/patches-2.6.32/160-cfi-swap.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -1079,6 +1079,9 @@ static int __xipram do_write_oneword(str - int retry_cnt = 0; - - adr += chip->start; -+#ifdef CONFIG_AMAZON -+ adr ^= 2; -+#endif - - spin_lock(chip->mutex); - ret = get_chip(map, chip, adr, FL_WRITING); -@@ -1361,7 +1364,11 @@ static int __xipram do_write_buffer(stru - z = 0; - while(z < words * map_bankwidth(map)) { - datum = map_word_load(map, buf); -+#ifdef CONFIG_AMAZON -+ map_write(map, datum, (adr + z) ^ 0x2); -+#else - map_write(map, datum, adr + z); -+#endif - - z += map_bankwidth(map); - buf += map_bankwidth(map); -@@ -1606,6 +1613,9 @@ static int __xipram do_erase_oneblock(st - int ret = 0; - - adr += chip->start; -+#ifdef CONFIG_AMAZON -+ adr ^= 2; -+#endif - - spin_lock(chip->mutex); - ret = get_chip(map, chip, adr, FL_ERASING); -@@ -1734,6 +1744,10 @@ static int do_atmel_lock(struct map_info - struct cfi_private *cfi = map->fldrv_priv; - int ret; - -+#ifdef CONFIG_AMAZON -+ adr ^= 2; -+#endif -+ - spin_lock(chip->mutex); - ret = get_chip(map, chip, adr + chip->start, FL_LOCKING); - if (ret) -@@ -1770,6 +1784,10 @@ static int do_atmel_unlock(struct map_in - struct cfi_private *cfi = map->fldrv_priv; - int ret; - -+#ifdef CONFIG_AMAZON -+ adr ^= 2; -+#endif -+ - spin_lock(chip->mutex); - ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING); - if (ret) diff --git a/target/linux/ar71xx/config-2.6.33 b/target/linux/ar71xx/config-2.6.33 deleted file mode 100644 index e147b0149..000000000 --- a/target/linux/ar71xx/config-2.6.33 +++ /dev/null @@ -1,292 +0,0 @@ -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_AG71XX=y -CONFIG_AG71XX_AR8216_SUPPORT=y -# CONFIG_AG71XX_DEBUG is not set -# CONFIG_AG71XX_DEBUG_FS is not set -# CONFIG_ALCHEMY_GPIO_INDIRECT is not set -# CONFIG_AR7 is not set -CONFIG_AR71XX_DEV_AP91_ETH=y -CONFIG_AR71XX_DEV_AP91_PCI=y -CONFIG_AR71XX_DEV_AP94_PCI=y -CONFIG_AR71XX_DEV_AR913X_WMAC=y -CONFIG_AR71XX_DEV_DSA=y -CONFIG_AR71XX_DEV_GPIO_BUTTONS=y -CONFIG_AR71XX_DEV_LEDS_GPIO=y -CONFIG_AR71XX_DEV_M25P80=y -CONFIG_AR71XX_DEV_PB42_PCI=y -CONFIG_AR71XX_DEV_PB9X_PCI=y -CONFIG_AR71XX_DEV_USB=y -CONFIG_AR71XX_MACH_AP81=y -CONFIG_AR71XX_MACH_AP83=y -CONFIG_AR71XX_MACH_AW_NR580=y -CONFIG_AR71XX_MACH_DIR_600_A1=y -CONFIG_AR71XX_MACH_DIR_615_C1=y -CONFIG_AR71XX_MACH_DIR_825_B1=y -CONFIG_AR71XX_MACH_MZK_W04NU=y -CONFIG_AR71XX_MACH_MZK_W300NH=y -CONFIG_AR71XX_MACH_PB42=y -CONFIG_AR71XX_MACH_PB44=y -CONFIG_AR71XX_MACH_PB92=y -CONFIG_AR71XX_MACH_RB4XX=y -CONFIG_AR71XX_MACH_RB750=y -CONFIG_AR71XX_MACH_TEW_632BRP=y -CONFIG_AR71XX_MACH_TL_WR1043ND=y -CONFIG_AR71XX_MACH_TL_WR741ND=y -CONFIG_AR71XX_MACH_TL_WR841N_V1=y -CONFIG_AR71XX_MACH_TL_WR941ND=y -CONFIG_AR71XX_MACH_UBNT=y -CONFIG_AR71XX_MACH_WNDR3700=y -CONFIG_AR71XX_MACH_WNR2000=y -CONFIG_AR71XX_MACH_WP543=y -CONFIG_AR71XX_MACH_WRT160NL=y -CONFIG_AR71XX_MACH_WRT400N=y -CONFIG_AR71XX_MACH_WZR_HP_G300NH=y -CONFIG_AR71XX_NVRAM=y -CONFIG_AR71XX_WDT=y -CONFIG_AR8216_PHY=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_ARCH_REQUIRE_GPIOLIB=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ATHEROS_AR71XX=y -# CONFIG_BCM47XX is not set -# CONFIG_BCM63XX is not set -CONFIG_BITREVERSE=y -# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set -# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_R4K_LIB=y -CONFIG_CMDLINE="rootfstype=squashfs,yaffs,jffs2 noinitrd console=ttyS0,115200" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_CAVIUM_OCTEON is not set -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_CPU_LOONGSON2E is not set -# CONFIG_CPU_LOONGSON2F is not set -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR2=y -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -CONFIG_CSRC_R4K=y -CONFIG_CSRC_R4K_LIB=y -CONFIG_DECOMPRESS_LZMA=y -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEVPORT=y -# CONFIG_DM9000 is not set -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_EARLY_PRINTK=y -# CONFIG_FSNOTIFY is not set -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_NXP_74HC153=y -CONFIG_GPIO_PCF857X=y -CONFIG_GPIO_SYSFS=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HW_HAS_PCI=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_GPIO=y -CONFIG_ICPLUS_PHY=y -CONFIG_IMAGE_CMDLINE_HACK=y -# CONFIG_INITRAMFS_COMPRESSION_LZO is not set -CONFIG_INITRAMFS_ROOT_GID=0 -CONFIG_INITRAMFS_ROOT_UID=0 -CONFIG_INITRAMFS_SOURCE="../../root" -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -CONFIG_IRQ_CPU=y -# CONFIG_LEDS_GPIO is not set -# CONFIG_LEDS_RB750 is not set -# CONFIG_LEDS_WNDR3700_USB is not set -CONFIG_LOONGSON_UART_BASE=y -# CONFIG_M25PXX_USE_FAST_READ is not set -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_LOONGSON is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MACH_VR41XX is not set -CONFIG_MICREL_PHY=y -# CONFIG_MIKROTIK_RB532 is not set -CONFIG_MIPS=y -# CONFIG_MIPS_COBALT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_MACHINE=y -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MTD_AR91XX_FLASH=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_MYLOADER_PARTS=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_RB4XX=y -CONFIG_MTD_NAND_RB750=y -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2 -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_WRT160NL_PARTS=y -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_MYLOADER=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_AR7240=y -CONFIG_NET_DSA_MV88E6060=y -CONFIG_NET_DSA_MV88E6063=y -# CONFIG_NET_DSA_MV88E6123_61_65 is not set -# CONFIG_NET_DSA_MV88E6131 is not set -# CONFIG_NET_DSA_MV88E6XXX is not set -# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set -# CONFIG_NET_DSA_TAG_DSA is not set -# CONFIG_NET_DSA_TAG_EDSA is not set -CONFIG_NET_DSA_TAG_QINQ=y -CONFIG_NET_DSA_TAG_TRAILER=y -# CONFIG_NO_IOPORT is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PCI=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PHYLIB=y -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_POWERTV is not set -CONFIG_RTL8306_PHY=y -CONFIG_RTL8366RB_PHY=y -CONFIG_RTL8366S_PHY=y -CONFIG_RTL8366_SMI=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y -# CONFIG_SCSI_DMA is not set -# CONFIG_SERIAL_8250_EXTENDED is not set -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SLAB is not set -CONFIG_SLUB=y -CONFIG_SPI=y -CONFIG_SPI_AP83=y -CONFIG_SPI_AR71XX=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_PB44=y -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_VSC7385 is not set -CONFIG_SWCONFIG=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -# CONFIG_TC35815 is not set -# CONFIG_TINY_RCU is not set -CONFIG_TRAD_SIGNALS=y -# CONFIG_TREE_PREEMPT_RCU is not set -CONFIG_TREE_RCU=y -CONFIG_USB_SUPPORT=y -CONFIG_YAFFS_9BYTE_TAGS=y -CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y -CONFIG_YAFFS_AUTO_YAFFS2=y -# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set -# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set -CONFIG_YAFFS_FS=y -CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y -CONFIG_YAFFS_YAFFS1=y -CONFIG_YAFFS_YAFFS2=y -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ar71xx/config-2.6.34 b/target/linux/ar71xx/config-2.6.34 deleted file mode 100644 index 549b7a8c7..000000000 --- a/target/linux/ar71xx/config-2.6.34 +++ /dev/null @@ -1,317 +0,0 @@ -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_AG71XX=y -CONFIG_AG71XX_AR8216_SUPPORT=y -# CONFIG_AG71XX_DEBUG is not set -# CONFIG_ALCHEMY_GPIO_INDIRECT is not set -# CONFIG_AR7 is not set -CONFIG_AR71XX_DEV_AP91_ETH=y -CONFIG_AR71XX_DEV_AP91_PCI=y -CONFIG_AR71XX_DEV_AP94_PCI=y -CONFIG_AR71XX_DEV_AR913X_WMAC=y -CONFIG_AR71XX_DEV_DSA=y -CONFIG_AR71XX_DEV_GPIO_BUTTONS=y -CONFIG_AR71XX_DEV_LEDS_GPIO=y -CONFIG_AR71XX_DEV_M25P80=y -CONFIG_AR71XX_DEV_PB42_PCI=y -CONFIG_AR71XX_DEV_PB9X_PCI=y -CONFIG_AR71XX_DEV_USB=y -CONFIG_AR71XX_MACH_AP81=y -CONFIG_AR71XX_MACH_AP83=y -CONFIG_AR71XX_MACH_AW_NR580=y -CONFIG_AR71XX_MACH_DIR_600_A1=y -CONFIG_AR71XX_MACH_DIR_615_C1=y -CONFIG_AR71XX_MACH_DIR_825_B1=y -CONFIG_AR71XX_MACH_MZK_W04NU=y -CONFIG_AR71XX_MACH_MZK_W300NH=y -CONFIG_AR71XX_MACH_PB42=y -CONFIG_AR71XX_MACH_PB44=y -CONFIG_AR71XX_MACH_PB92=y -CONFIG_AR71XX_MACH_RB4XX=y -CONFIG_AR71XX_MACH_RB750=y -CONFIG_AR71XX_MACH_TEW_632BRP=y -CONFIG_AR71XX_MACH_TL_WR1043ND=y -CONFIG_AR71XX_MACH_TL_WR741ND=y -CONFIG_AR71XX_MACH_TL_WR841N_V1=y -CONFIG_AR71XX_MACH_TL_WR941ND=y -CONFIG_AR71XX_MACH_UBNT=y -CONFIG_AR71XX_MACH_WNDR3700=y -CONFIG_AR71XX_MACH_WNR2000=y -CONFIG_AR71XX_MACH_WP543=y -CONFIG_AR71XX_MACH_WRT160NL=y -CONFIG_AR71XX_MACH_WRT400N=y -CONFIG_AR71XX_MACH_WZR_HP_G300NH=y -CONFIG_AR71XX_NVRAM=y -CONFIG_AR71XX_WDT=y -CONFIG_AR8216_PHY=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_ARCH_REQUIRE_GPIOLIB=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ATHEROS_AR71XX=y -# CONFIG_BCM47XX is not set -# CONFIG_BCM63XX is not set -CONFIG_BITREVERSE=y -CONFIG_BRIDGE=m -CONFIG_BRIDGE_IGMP_SNOOPING=y -# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set -# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_R4K_LIB=y -CONFIG_CMDLINE="rootfstype=squashfs,yaffs,jffs2 noinitrd console=ttyS0,115200" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_CAVIUM_OCTEON is not set -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_CPU_LOONGSON2E is not set -# CONFIG_CPU_LOONGSON2F is not set -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR2=y -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CRYSTALHD is not set -CONFIG_CSRC_R4K=y -CONFIG_CSRC_R4K_LIB=y -# CONFIG_DEBUG_FS is not set -CONFIG_DECOMPRESS_LZMA=y -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEVPORT=y -# CONFIG_DM9000 is not set -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DT3155 is not set -CONFIG_EARLY_PRINTK=y -# CONFIG_FSNOTIFY is not set -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_GPIOLIB=y -# CONFIG_GPIO_IT8761E is not set -# CONFIG_GPIO_MAX7300 is not set -CONFIG_GPIO_NXP_74HC153=y -CONFIG_GPIO_PCF857X=y -# CONFIG_GPIO_SCH is not set -CONFIG_GPIO_SYSFS=y -# CONFIG_HAMRADIO is not set -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_HTC_I2CPLD is not set -CONFIG_HW_HAS_PCI=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_GPIO=y -# CONFIG_I2C_SMBUS is not set -# CONFIG_I2C_XILINX is not set -CONFIG_ICPLUS_PHY=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_IMAGE_CMDLINE_HACK=y -# CONFIG_INITRAMFS_COMPRESSION_LZO is not set -CONFIG_INITRAMFS_ROOT_GID=0 -CONFIG_INITRAMFS_ROOT_UID=0 -CONFIG_INITRAMFS_SOURCE="../../root" -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -CONFIG_IRQ_CPU=y -# CONFIG_KSZ884X_PCI is not set -# CONFIG_LEDS_GPIO is not set -# CONFIG_LEDS_RB750 is not set -# CONFIG_LEDS_WNDR3700_USB is not set -CONFIG_LLC=m -# CONFIG_LOGFS is not set -CONFIG_LOONGSON_UART_BASE=y -# CONFIG_LPC_SCH is not set -# CONFIG_M25PXX_USE_FAST_READ is not set -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_LOONGSON is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_MAX63XX_WATCHDOG is not set -# CONFIG_MFD_88PM860X is not set -# CONFIG_MFD_MAX8925 is not set -# CONFIG_MFD_TIMBERDALE is not set -# CONFIG_MFD_WM8994 is not set -CONFIG_MICREL_PHY=y -# CONFIG_MIKROTIK_RB532 is not set -CONFIG_MIPS=y -# CONFIG_MIPS_COBALT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_MACHINE=y -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MTD_AR91XX_FLASH=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_MYLOADER_PARTS=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_RB4XX=y -CONFIG_MTD_NAND_RB750=y -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2 -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_WRT160NL_PARTS=y -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_MYLOADER=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_AR7240=y -CONFIG_NET_DSA_MV88E6060=y -CONFIG_NET_DSA_MV88E6063=y -# CONFIG_NET_DSA_MV88E6123_61_65 is not set -# CONFIG_NET_DSA_MV88E6131 is not set -# CONFIG_NET_DSA_MV88E6XXX is not set -# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set -# CONFIG_NET_DSA_TAG_DSA is not set -# CONFIG_NET_DSA_TAG_EDSA is not set -CONFIG_NET_DSA_TAG_QINQ=y -CONFIG_NET_DSA_TAG_TRAILER=y -CONFIG_NO_HZ=y -# CONFIG_NO_IOPORT is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PHYLIB=y -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_POWERTV is not set -CONFIG_RTL8306_PHY=y -CONFIG_RTL8366RB_PHY=y -CONFIG_RTL8366S_PHY=y -CONFIG_RTL8366_SMI=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y -# CONFIG_SCSI_DMA is not set -# CONFIG_SERIAL_8250_EXTENDED is not set -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_SERIAL_TIMBERDALE is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SLAB is not set -CONFIG_SLUB=y -CONFIG_SPI=y -CONFIG_SPI_AP83=y -CONFIG_SPI_AR71XX=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_PB44=y -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_VSC7385 is not set -CONFIG_STP=m -# CONFIG_SWAP is not set -CONFIG_SWCONFIG=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -# CONFIG_TC35815 is not set -CONFIG_TRAD_SIGNALS=y -# CONFIG_TREE_PREEMPT_RCU is not set -CONFIG_USB_SUPPORT=y -CONFIG_VLAN_8021Q=m -CONFIG_YAFFS_9BYTE_TAGS=y -CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y -CONFIG_YAFFS_AUTO_YAFFS2=y -# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set -# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set -CONFIG_YAFFS_FS=y -CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y -CONFIG_YAFFS_YAFFS1=y -CONFIG_YAFFS_YAFFS2=y -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c index eecdd9f71..4e1da167d 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c @@ -21,6 +21,8 @@ #include +static int ip2_flush_reg; + static void ar71xx_gpio_irq_dispatch(void) { void __iomem *base = ar71xx_gpio_base; @@ -239,8 +241,17 @@ asmlinkage void plat_irq_dispatch(void) if (pending & STATUSF_IP7) do_IRQ(AR71XX_CPU_IRQ_TIMER); - else if (pending & STATUSF_IP2) + else if (pending & STATUSF_IP2) { + /* + * This IRQ is meant for a PCI device. Drivers for PCI devices + * typically allocate coherent DMA memory for the descriptor + * ring, however the DMA controller may still have some + * unsynchronized data in the FIFO. + * Issue a flush here to ensure that the driver sees the update. + */ + ar71xx_ddr_flush(ip2_flush_reg); do_IRQ(AR71XX_CPU_IRQ_IP2); + } else if (pending & STATUSF_IP4) do_IRQ(AR71XX_CPU_IRQ_GE0); @@ -260,6 +271,20 @@ asmlinkage void plat_irq_dispatch(void) void __init arch_init_irq(void) { + switch(ar71xx_soc) { + case AR71XX_SOC_AR7240: + case AR71XX_SOC_AR7241: + case AR71XX_SOC_AR7242: + ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; + break; + case AR71XX_SOC_AR9130: + case AR71XX_SOC_AR9132: + ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC; + break; + default: + ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; + break; + } mips_cpu_irq_init(); ar71xx_misc_irq_init(); diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w04nu.c b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w04nu.c index bc8438f73..63fbeb855 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w04nu.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w04nu.c @@ -61,7 +61,7 @@ static struct mtd_partition mzk_w04nu_partitions[] = { } , { .name = "firmware", .offset = 0x050000, - .size = 0x770000, + .size = 0x790000, } }; #endif /* CONFIG_MTD_PARTITIONS */ diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w300nh.c b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w300nh.c index dfe7d0d6f..f5862ebbd 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w300nh.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w300nh.c @@ -51,11 +51,7 @@ static struct mtd_partition mzk_w300nh_partitions[] = { } , { .name = "rootfs", .offset = 0x1b0000, - .size = 0x610000, - } , { - .name = "config", - .offset = 0x7c0000, - .size = 0x020000, + .size = 0x630000, } , { .name = "art", .offset = 0x7e0000, @@ -64,7 +60,7 @@ static struct mtd_partition mzk_w300nh_partitions[] = { } , { .name = "firmware", .offset = 0x050000, - .size = 0x770000, + .size = 0x790000, } }; #endif /* CONFIG_MTD_PARTITIONS */ diff --git a/target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile index 1eafa09bd..f8ecb42c0 100644 --- a/target/linux/ar71xx/image/Makefile +++ b/target/linux/ar71xx/image/Makefile @@ -81,27 +81,40 @@ define Image/Build/WRT400N -d $(KDIR)/vmlinux-$(2).bin.lzma $(KDIR)/vmlinux-$(2).uImage; \ ( \ dd if=$(KDIR)/vmlinux-$(2).uImage bs=1280k conv=sync; \ - dd if=$(KDIR)/root.$(1) bs=6336k conv=sync; \ - echo -n $(4); \ - ) > $(call imgname,$(1),$(2)).bin; \ - wrt400n $(KDIR)/vmlinux-$(2).uImage $(KDIR)/root.$(1) $(call imgname,$(1),$(2)).webui; \ + dd if=$(KDIR)/root.$(1) \ + ) > $(call imgname,$(1),$(2))-sysupgrade.bin; \ + wrt400n $(KDIR)/vmlinux-$(2).uImage $(KDIR)/root.$(1) $(call imgname,$(1),$(2))-factory.bin; \ fi; fi endef dir825b1_mtdlayout=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,1024k(kernel),5184k(rootfs),64k(caldata)ro,1600k(unknown)ro,6208k@0x50000(firmware) define Image/Build/DIR825B1 $(call PatchKernelLzma,$(2),$(3) $(dir825b1_mtdlayout)) - $(call MkImageLzma,$(KDIR)/vmlinux-$(2).bin.lzma,$(call imgname,$(1),$(2)).bin) - if [ `stat -c%s "$(call imgname,$(1),$(2)).bin"` -gt 1048576 ]; then \ + if [ `stat -c%s "$(KDIR)/vmlinux-$(2).bin.lzma"` -gt 1048576 ]; then \ echo "Warning: $(KDIR)/vmlinux-$(2).bin.lzma is too big"; \ - rm -f $(call imgname,$(1),$(2)).bin; \ else if [ `stat -c%s $(KDIR)/root.$(1)` -gt 5308416 ]; then \ echo "Warning: $(KDIR)/root.$(1) is too big"; \ - rm -f $(call imgname,$(1),$(2)).bin; \ else \ - dd if=$(KDIR)/root.$(1) of=$(call imgname,$(1),$(2)).bin bs=1k seek=1024; \ - cp $(call imgname,$(1),$(2)).bin $(call imgname,$(1),$(2))-backup-loader.bin; \ - echo -n "01AP94-AR7161-RT-080619-00" >> $(call imgname,$(1),$(2))-backup-loader.bin; \ + mkimage -A mips -O linux -T kernel -a 0x80060000 -C lzma -e \ + 0x80060000 \ + -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(KDIR)/vmlinux-$(2).bin.lzma $(KDIR)/vmlinux-$(2).uImage; \ + ( \ + dd if=$(KDIR)/vmlinux-$(2).uImage bs=1024k conv=sync; \ + dd if=$(KDIR)/root.$(1) \ + ) > $(call imgname,$(1),$(2))-sysupgrade.bin; \ + ( \ + dd if=$(call imgname,$(1),$(2))-sysupgrade.bin; \ + echo -n "01AP94-AR7161-RT-080619-00"; \ + ) > $(call imgname,$(1),$(2))-backup-loader.bin; \ + if [ `stat -c%s $(call imgname,$(1),$(2))-sysupgrade.bin` -gt 4194304 ]; then \ + echo "Warning: $(call imgname,$(1),$(2))-sysupgrade.bin is too big"; \ + else \ + ( \ + dd if=$(call imgname,$(1),$(2))-sysupgrade.bin bs=4096k conv=sync; \ + echo -n "00AP94-AR7161-RT-080619-00"; \ + ) > $(call imgname,$(1),$(2))-factory.bin; \ + fi; \ fi; fi endef @@ -127,7 +140,7 @@ define Image/Build/WZRHPG300NH fi; fi endef -cameo_mtdlayout=mtdparts=spi0.0:128k(u-boot)ro,64k(config)ro,896k(kernel),2880k(rootfs),64k(art)ro,3776k@0x30000(firmware) +cameo_mtdlayout=mtdparts=spi0.0:128k(u-boot)ro,64k(config)ro,896k(kernel),2944k(rootfs),64k(art)ro,3840k@0x30000(firmware) define Image/Build/Cameo $(call PatchKernelLzma,$(2),$(3) $(cameo_mtdlayout)) if [ `stat -c%s "$(KDIR)/vmlinux-$(2).bin.lzma"` -gt 917504 ]; then \ @@ -198,27 +211,6 @@ define Image/Build/AP83 fi; fi endef -define Image/Build/PB92 - $(call PatchKernelGzip,$(2),$(3)) - if [ `stat -c%s $(KDIR)/root.$(1)` -gt 2818048 ]; then \ - echo "Warning: $(KDIR)/root.$(1) is too big"; \ - else \ - mkimage -A mips -O linux -T kernel -a 0x80060000 -C gzip -e \ - 0x80060000 \ - -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ - -d $(KDIR)/vmlinux-$(2).bin.gz \ - $(KDIR)/vmlinux-$(2).uImage; \ - dd if=$(KDIR)/vmlinux-$(2).uImage \ - of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync; \ - dd if=$(KDIR)/root.$(1) \ - of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync; \ - ( \ - dd if=$(KDIR)/vmlinux-$(2).uImage bs=896k conv=sync; \ - dd if=$(KDIR)/root.$(1); \ - ) > $(call imgname,$(1),$(2))-sysupgrade.bin; \ - fi -endef - define Image/Build/PB4X $(call PatchKernelLzma,$(2),$(3)) dd if=$(KDIR)/vmlinux-$(2).bin.lzma \ @@ -281,13 +273,13 @@ define Image/Build/Planex -d $(KDIR)/vmlinux-$(2).bin.gz $(KDIR)/vmlinux-$(2).uImage; \ ( \ dd if=$(KDIR)/vmlinux-$(2).uImage bs=1408k conv=sync; \ - dd if=$(KDIR)/root.$(1) bs=6208k conv=sync; \ - ) > $(call imgname,$(1),$(2)).bin; \ + dd if=$(KDIR)/root.$(1); \ + ) > $(call imgname,$(1),$(2))-sysupgrade.bin; \ $(STAGING_DIR_HOST)/bin/mkplanexfw \ -B $(2) \ -v 2.00.00 \ - -i $(call imgname,$(1),$(2)).bin \ - -o $(call imgname,$(1),$(2)).webui; \ + -i $(call imgname,$(1),$(2))-sysupgrade.bin \ + -o $(call imgname,$(1),$(2))-factory.bin; \ fi; fi endef @@ -320,7 +312,10 @@ define Image/Build/CyberTAN -x 32 -a 0x10000 -x -32 -f $(KDIR)/root.$(1) -$(STAGING_DIR_HOST)/bin/addpattern -B $(2) -v v$(4) \ -i $(KDIR)/image.tmp \ - -o $(call imgname,$(1),$(2)).bin + -o $(call imgname,$(1),$(2))-sysupgrade.bin + -$(STAGING_DIR_HOST)/bin/addpattern -B $(2) -v v$(4) -g \ + -i $(KDIR)/image.tmp \ + -o $(call imgname,$(1),$(2))-factory.bin rm $(KDIR)/image.tmp endef @@ -419,10 +414,6 @@ define Image/Build/Profile/PB44 $(call Image/Build/Template/$(fs_64k)/$(1),PB4X,pb44,board=PB44) endef -define Image/Build/Profile/PB92 - $(call Image/Build/Template/$(fs_64k)/$(1),PB92,pb92,board=PB92) -endef - define Image/Build/Profile/WP543 $(call Image/Build/Template/$(fs_64k)/$(1),MyLoader,wp543,0x200000,2M) $(call Image/Build/Template/$(fs_64k)/$(1),MyLoader,wp543,0x400000,4M) @@ -515,6 +506,10 @@ define Image/Build/Profile/TLWR941NDV2 $(call Image/Build/Template/$(fs_squash)/$(1),TPLINK,tl-wr941nd-v2,board=TL-WR941ND,TL-WR941NDv2) endef +define Image/Build/Profile/TLWR941NDV3 + $(call Image/Build/Template/$(fs_squash)/$(1),TPLINK,tl-wr941nd-v3,board=TL-WR941ND,TL-WR941NDv2) +endef + define Image/Build/Profile/TLWR941NDV4 $(call Image/Build/Template/$(fs_4k)/$(1),TPLINK,tl-wr941nd-v4,board=TL-WR741ND,TL-WR941NDv4) endef @@ -555,7 +550,6 @@ define Image/Build/Profile/Default $(call Image/Build/Profile/MZKW300NH,$(1)) $(call Image/Build/Profile/PB42,$(1)) $(call Image/Build/Profile/PB44,$(1)) - $(call Image/Build/Profile/PB92,$(1)) $(call Image/Build/Profile/TEW632BRP,$(1)) $(call Image/Build/Profile/TEW652BRP,$(1)) $(call Image/Build/Profile/TLWR741NDV1,$(1)) @@ -563,6 +557,7 @@ define Image/Build/Profile/Default $(call Image/Build/Profile/TLWR841NDV3,$(1)) $(call Image/Build/Profile/TLWR841NDV5,$(1)) $(call Image/Build/Profile/TLWR941NDV2,$(1)) + $(call Image/Build/Profile/TLWR941NDV3,$(1)) $(call Image/Build/Profile/TLWR941NDV4,$(1)) $(call Image/Build/Profile/TLWR1043NDV1,$(1)) $(call Image/Build/Profile/UBNT,$(1)) diff --git a/target/linux/ar71xx/patches-2.6.33/001-ar71xx_core.patch b/target/linux/ar71xx/patches-2.6.33/001-ar71xx_core.patch deleted file mode 100644 index 5073652dd..000000000 --- a/target/linux/ar71xx/patches-2.6.33/001-ar71xx_core.patch +++ /dev/null @@ -1,50 +0,0 @@ ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -166,6 +166,13 @@ ifeq (,$(findstring march=octeon, $(cfla - cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon - endif - -+# -+# Atheros AR71xx -+# -+core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/ -+cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx -+load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000 -+ - cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) - cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) - cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -48,6 +48,23 @@ config AR7 - Support for the Texas Instruments AR7 System-on-a-Chip - family: TNETD7100, 7200 and 7300. - -+config ATHEROS_AR71XX -+ bool "Atheros AR71xx based boards" -+ select CEVT_R4K -+ select CSRC_R4K -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select ARCH_REQUIRE_GPIOLIB -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_HAS_CPU_MIPS32_R2 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_HAS_EARLY_PRINTK -+ select MIPS_MACHINE -+ help -+ Support for Atheros AR71xx based boards. -+ - config BCM47XX - bool "BCM47XX based boards" - select CEVT_R4K -@@ -682,6 +699,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD - endchoice - - source "arch/mips/alchemy/Kconfig" -+source "arch/mips/ar71xx/Kconfig" - source "arch/mips/bcm63xx/Kconfig" - source "arch/mips/jazz/Kconfig" - source "arch/mips/lasat/Kconfig" diff --git a/target/linux/ar71xx/patches-2.6.33/002-ar71xx_pci.patch b/target/linux/ar71xx/patches-2.6.33/002-ar71xx_pci.patch deleted file mode 100644 index 3facce9d7..000000000 --- a/target/linux/ar71xx/patches-2.6.33/002-ar71xx_pci.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o - obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o - obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ - ops-bcm63xx.o -+obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o pci-ar724x.o - - # - # These are still pretty much in the old state, watch, go blind. diff --git a/target/linux/ar71xx/patches-2.6.33/003-ar71xx_usb_host.patch b/target/linux/ar71xx/patches-2.6.33/003-ar71xx_usb_host.patch deleted file mode 100644 index 238a79c9b..000000000 --- a/target/linux/ar71xx/patches-2.6.33/003-ar71xx_usb_host.patch +++ /dev/null @@ -1,58 +0,0 @@ ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -109,6 +109,13 @@ config XPS_USB_HCD_XILINX - support both high speed and full speed devices, or high speed - devices only. - -+config USB_EHCI_AR71XX -+ bool "USB EHCI support for AR71xx" -+ depends on USB_EHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in EHCI controller -+ - config USB_EHCI_FSL - bool "Support for Freescale on-chip EHCI USB controller" - depends on USB_EHCI_HCD && FSL_SOC -@@ -207,6 +214,13 @@ config USB_OHCI_HCD - To compile this driver as a module, choose M here: the - module will be called ohci-hcd. - -+config USB_OHCI_AR71XX -+ bool "USB OHCI support for Atheros AR71xx" -+ depends on USB_OHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in OHCI controller -+ - config USB_OHCI_HCD_PPC_SOC - bool "OHCI support for on-chip PPC USB controller" - depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) ---- a/drivers/usb/host/ehci-hcd.c -+++ b/drivers/usb/host/ehci-hcd.c -@@ -1158,6 +1158,11 @@ MODULE_LICENSE ("GPL"); - #define PLATFORM_DRIVER ehci_atmel_driver - #endif - -+#ifdef CONFIG_USB_EHCI_AR71XX -+#include "ehci-ar71xx.c" -+#define PLATFORM_DRIVER ehci_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ - !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) - #error "missing bus glue for ehci-hcd" ---- a/drivers/usb/host/ohci-hcd.c -+++ b/drivers/usb/host/ohci-hcd.c -@@ -1085,6 +1085,11 @@ MODULE_LICENSE ("GPL"); - #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver - #endif - -+#ifdef CONFIG_USB_OHCI_AR71XX -+#include "ohci-ar71xx.c" -+#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && \ - !defined(PLATFORM_DRIVER) && \ - !defined(OF_PLATFORM_DRIVER) && \ diff --git a/target/linux/ar71xx/patches-2.6.33/004-ar71xx_spi_controller.patch b/target/linux/ar71xx/patches-2.6.33/004-ar71xx_spi_controller.patch deleted file mode 100644 index 9c196e077..000000000 --- a/target/linux/ar71xx/patches-2.6.33/004-ar71xx_spi_controller.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -53,6 +53,13 @@ if SPI_MASTER - - comment "SPI Master Controller Drivers" - -+config SPI_AR71XX -+ tristate "Atheros AR71xx SPI Controller" -+ depends on SPI_MASTER && ATHEROS_AR71XX -+ select SPI_BITBANG -+ help -+ This is the SPI contoller driver for Atheros AR71xx. -+ - config SPI_ATMEL - tristate "Atmel SPI Controller" - depends on (ARCH_AT91 || AVR32) ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -11,6 +11,7 @@ endif - obj-$(CONFIG_SPI_MASTER) += spi.o - - # SPI master controller drivers (bus) -+obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o - obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o - obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o - obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o diff --git a/target/linux/ar71xx/patches-2.6.33/005-ar71xx_mac_driver.patch b/target/linux/ar71xx/patches-2.6.33/005-ar71xx_mac_driver.patch deleted file mode 100644 index 3721a9b86..000000000 --- a/target/linux/ar71xx/patches-2.6.33/005-ar71xx_mac_driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/net/Kconfig -+++ b/drivers/net/Kconfig -@@ -2128,6 +2128,8 @@ config ACENIC_OMIT_TIGON_I - - The safe and default value for this is N. - -+source drivers/net/ag71xx/Kconfig -+ - config DL2K - tristate "DL2000/TC902x-based Gigabit Ethernet support" - depends on PCI ---- a/drivers/net/Makefile -+++ b/drivers/net/Makefile -@@ -106,6 +106,7 @@ obj-$(CONFIG_STMMAC_ETH) += stmmac/ - # end link order section - # - -+obj-$(CONFIG_AG71XX) += ag71xx/ - obj-$(CONFIG_SUNDANCE) += sundance.o - obj-$(CONFIG_HAMACHI) += hamachi.o - obj-$(CONFIG_NET) += Space.o loopback.o diff --git a/target/linux/ar71xx/patches-2.6.33/006-ar71xx_wdt_driver.patch b/target/linux/ar71xx/patches-2.6.33/006-ar71xx_wdt_driver.patch deleted file mode 100644 index d71a11b86..000000000 --- a/target/linux/ar71xx/patches-2.6.33/006-ar71xx_wdt_driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -840,6 +840,13 @@ config TXX9_WDT - help - Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs. - -+config AR71XX_WDT -+ tristate "Atheros AR71xx Watchdog Timer" -+ depends on ATHEROS_AR71XX -+ help -+ Hardware driver for the built-in watchdog timer on the Atheros -+ AR71xx SoCs. -+ - # PARISC Architecture - - # POWERPC Architecture ---- a/drivers/watchdog/Makefile -+++ b/drivers/watchdog/Makefile -@@ -112,6 +112,7 @@ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o -+obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o - - # PARISC Architecture - diff --git a/target/linux/ar71xx/patches-2.6.33/007-ar91xx_flash_driver.patch b/target/linux/ar71xx/patches-2.6.33/007-ar91xx_flash_driver.patch deleted file mode 100644 index 127db55b6..000000000 --- a/target/linux/ar71xx/patches-2.6.33/007-ar91xx_flash_driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/mtd/maps/Kconfig -+++ b/drivers/mtd/maps/Kconfig -@@ -257,6 +257,13 @@ config MTD_ALCHEMY - help - Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards - -+config MTD_AR91XX_FLASH -+ tristate "Atheros AR91xx parallel flash support" -+ depends on ATHEROS_AR71XX -+ select MTD_COMPLEX_MAPPINGS -+ help -+ Parallel flash driver for the Atheros AR91xx based boards. -+ - config MTD_DILNETPC - tristate "CFI Flash device mapped on DIL/Net PC" - depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN ---- a/drivers/mtd/maps/Makefile -+++ b/drivers/mtd/maps/Makefile -@@ -41,6 +41,7 @@ obj-$(CONFIG_MTD_DBOX2) += dbox2-flash. - obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o - obj-$(CONFIG_MTD_PCI) += pci.o - obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o -+obj-$(CONFIG_MTD_AR91XX_FLASH) += ar91xx_flash.o - obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o - obj-$(CONFIG_MTD_EDB7312) += edb7312.o - obj-$(CONFIG_MTD_IMPA7) += impa7.o diff --git a/target/linux/ar71xx/patches-2.6.33/101-ksz8041_phy_driver.patch b/target/linux/ar71xx/patches-2.6.33/101-ksz8041_phy_driver.patch deleted file mode 100644 index 503604610..000000000 --- a/target/linux/ar71xx/patches-2.6.33/101-ksz8041_phy_driver.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -114,6 +114,11 @@ config RTL8306_PHY - tristate "Driver for Realtek RTL8306S switches" - select SWCONFIG - -+config MICREL_PHY -+ tristate "Drivers for Micrel/Kendin PHYs" -+ ---help--- -+ Currently has a driver for the KSZ8041 -+ - config FIXED_PHY - bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" - depends on PHYLIB=y ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi - obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o - obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o - obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o -+obj-$(CONFIG_MICREL) += micrel.o - obj-$(CONFIG_FIXED_PHY) += fixed.o - obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o - obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o diff --git a/target/linux/ar71xx/patches-2.6.33/102-mtd_m25p80_add_myloader_parser.patch b/target/linux/ar71xx/patches-2.6.33/102-mtd_m25p80_add_myloader_parser.patch deleted file mode 100644 index 45f743e06..000000000 --- a/target/linux/ar71xx/patches-2.6.33/102-mtd_m25p80_add_myloader_parser.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -922,6 +922,16 @@ static int __devinit m25p_probe(struct s - part_probes, &parts, 0); - } - -+#ifdef CONFIG_MTD_MYLOADER_PARTS -+ if (nr_parts <= 0) { -+ static const char *part_probes[] -+ = { "MyLoader", NULL, }; -+ -+ nr_parts = parse_mtd_partitions(&flash->mtd, -+ part_probes, &parts, 0); -+ } -+#endif -+ - if (nr_parts <= 0 && data && data->parts) { - parts = data->parts; - nr_parts = data->nr_parts; diff --git a/target/linux/ar71xx/patches-2.6.33/104-mtd_m25p80_add_redboot_parser.patch b/target/linux/ar71xx/patches-2.6.33/104-mtd_m25p80_add_redboot_parser.patch deleted file mode 100644 index 43fe987df..000000000 --- a/target/linux/ar71xx/patches-2.6.33/104-mtd_m25p80_add_redboot_parser.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -932,6 +932,15 @@ static int __devinit m25p_probe(struct s - } - #endif - -+#ifdef CONFIG_MTD_REDBOOT_PARTS -+ if (nr_parts <= 0) { -+ static const char *part_probes[] -+ = { "RedBoot", NULL, }; -+ -+ nr_parts = parse_mtd_partitions(&flash->mtd, -+ part_probes, &parts, 0); -+ } -+#endif - if (nr_parts <= 0 && data && data->parts) { - parts = data->parts; - nr_parts = data->nr_parts; diff --git a/target/linux/ar71xx/patches-2.6.33/107-mtd-SST39VF6401B-support.patch b/target/linux/ar71xx/patches-2.6.33/107-mtd-SST39VF6401B-support.patch deleted file mode 100644 index 2fdfcb7cd..000000000 --- a/target/linux/ar71xx/patches-2.6.33/107-mtd-SST39VF6401B-support.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/drivers/mtd/chips/jedec_probe.c -+++ b/drivers/mtd/chips/jedec_probe.c -@@ -166,6 +166,7 @@ - #define SST39LF160 0x2782 - #define SST39VF1601 0x234b - #define SST39VF3201 0x235b -+#define SST39VF6401B 0x236d - #define SST39LF512 0x00D4 - #define SST39LF010 0x00D5 - #define SST39LF020 0x00D6 -@@ -1556,6 +1557,18 @@ static const struct amd_flash_info jedec - ERASEINFO(0x10000,64), - } - }, { -+ .mfr_id = MANUFACTURER_SST, -+ .dev_id = SST39VF6401B, -+ .name = "SST 39VF6401B", -+ .devtypes = CFI_DEVICETYPE_X16, -+ .uaddr = MTD_UADDR_0xAAAA_0x5555, -+ .dev_size = SIZE_8MiB, -+ .cmd_set = P_ID_AMD_STD, -+ .nr_regions = 1, -+ .regions = { -+ ERASEINFO(0x10000,128) -+ } -+ }, { - .mfr_id = MANUFACTURER_ST, - .dev_id = M29F800AB, - .name = "ST M29F800AB", diff --git a/target/linux/ar71xx/patches-2.6.33/108-mtd_fix_cfi_cmdset_0002_status_check.patch b/target/linux/ar71xx/patches-2.6.33/108-mtd_fix_cfi_cmdset_0002_status_check.patch deleted file mode 100644 index e0676cae9..000000000 --- a/target/linux/ar71xx/patches-2.6.33/108-mtd_fix_cfi_cmdset_0002_status_check.patch +++ /dev/null @@ -1,69 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -1130,8 +1130,8 @@ static int __xipram do_write_oneword(str - break; - } - -- if (chip_ready(map, adr)) -- break; -+ if (chip_good(map, adr, datum)) -+ goto enable_xip; - - /* Latency issues. Drop the lock, wait a while and retry */ - UDELAY(map, chip, adr, 1); -@@ -1147,6 +1147,8 @@ static int __xipram do_write_oneword(str - - ret = -EIO; - } -+ -+ enable_xip: - xip_enable(map, chip, adr); - op_done: - chip->state = FL_READY; -@@ -1493,7 +1495,6 @@ static int cfi_amdstd_write_buffers(stru - return 0; - } - -- - /* - * Handle devices with one erase region, that only implement - * the chip erase command. -@@ -1557,8 +1558,8 @@ static int __xipram do_erase_chip(struct - chip->erase_suspended = 0; - } - -- if (chip_ready(map, adr)) -- break; -+ if (chip_good(map, adr, map_word_ff(map))) -+ goto op_done; - - if (time_after(jiffies, timeo)) { - printk(KERN_WARNING "MTD %s(): software timeout\n", -@@ -1578,6 +1579,7 @@ static int __xipram do_erase_chip(struct - ret = -EIO; - } - -+ op_done: - chip->state = FL_READY; - xip_enable(map, chip, adr); - put_chip(map, chip, adr); -@@ -1645,9 +1647,9 @@ static int __xipram do_erase_oneblock(st - chip->erase_suspended = 0; - } - -- if (chip_ready(map, adr)) { -+ if (chip_good(map, adr, map_word_ff(map))) { - xip_enable(map, chip, adr); -- break; -+ goto op_done; - } - - if (time_after(jiffies, timeo)) { -@@ -1669,6 +1671,7 @@ static int __xipram do_erase_oneblock(st - ret = -EIO; - } - -+ op_done: - chip->state = FL_READY; - put_chip(map, chip, adr); - spin_unlock(chip->mutex); diff --git a/target/linux/ar71xx/patches-2.6.33/109-mtd-wrt160nl-trx-parser.patch b/target/linux/ar71xx/patches-2.6.33/109-mtd-wrt160nl-trx-parser.patch deleted file mode 100644 index 037795b33..000000000 --- a/target/linux/ar71xx/patches-2.6.33/109-mtd-wrt160nl-trx-parser.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -941,6 +941,16 @@ static int __devinit m25p_probe(struct s - part_probes, &parts, 0); - } - #endif -+ -+#ifdef CONFIG_MTD_WRT160NL_PARTS -+ if (nr_parts <= 0) { -+ static const char *part_probes[] -+ = { "wrt160nl", NULL, }; -+ -+ nr_parts = parse_mtd_partitions(&flash->mtd, -+ part_probes, &parts, 0); -+ } -+#endif - if (nr_parts <= 0 && data && data->parts) { - parts = data->parts; - nr_parts = data->nr_parts; ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -181,6 +181,12 @@ config MTD_AR7_PARTS - ---help--- - TI AR7 partitioning support - -+config MTD_WRT160NL_PARTS -+ tristate "Linksys WRT160NL partitioning support" -+ depends on MTD_PARTITIONS && AR71XX_MACH_WRT160NL -+ ---help--- -+ Linksys WRT160NL partitioning support -+ - config MTD_MYLOADER_PARTS - tristate "MyLoader partition parsing" - depends on MTD_PARTITIONS && (ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX) ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -12,6 +12,7 @@ obj-$(CONFIG_MTD_REDBOOT_PARTS) += redbo - obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o - obj-$(CONFIG_MTD_AFS_PARTS) += afs.o - obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o -+obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o - obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o - obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o - diff --git a/target/linux/ar71xx/patches-2.6.33/110-usb-ehci-add-war-for-synopsys-hc-bug.patch b/target/linux/ar71xx/patches-2.6.33/110-usb-ehci-add-war-for-synopsys-hc-bug.patch deleted file mode 100644 index 076c39ea2..000000000 --- a/target/linux/ar71xx/patches-2.6.33/110-usb-ehci-add-war-for-synopsys-hc-bug.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/drivers/usb/host/ehci-q.c -+++ b/drivers/usb/host/ehci-q.c -@@ -1194,6 +1194,9 @@ static void end_unlink_async (struct ehc - ehci->reclaim = NULL; - start_unlink_async (ehci, next); - } -+ -+ if (ehci->has_synopsys_hc_bug) -+ writel((u32)ehci->async->qh_dma, &ehci->regs->async_next); - } - - /* makes sure the async qh will become idle */ ---- a/drivers/usb/host/ehci.h -+++ b/drivers/usb/host/ehci.h -@@ -129,6 +129,7 @@ struct ehci_hcd { /* one per controlle - unsigned has_amcc_usb23:1; - unsigned need_io_watchdog:1; - unsigned broken_periodic:1; -+ unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ - - /* required for usb32 quirk */ - #define OHCI_CTRL_HCFS (3 << 6) diff --git a/target/linux/ar71xx/patches-2.6.33/111-mtd-cfi_cmdset_0002-force-word-write.patch b/target/linux/ar71xx/patches-2.6.33/111-mtd-cfi_cmdset_0002-force-word-write.patch deleted file mode 100644 index 3215a7d9d..000000000 --- a/target/linux/ar71xx/patches-2.6.33/111-mtd-cfi_cmdset_0002-force-word-write.patch +++ /dev/null @@ -1,61 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -39,7 +39,7 @@ - #include - - #define AMD_BOOTLOC_BUG --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - #define MAX_WORD_RETRIES 3 - -@@ -55,7 +55,9 @@ - - static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); - static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); -+#if !FORCE_WORD_WRITE - static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); -+#endif - static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); - static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); - static void cfi_amdstd_sync (struct mtd_info *); -@@ -190,6 +192,7 @@ static void fixup_amd_bootblock(struct m - } - #endif - -+#if !FORCE_WORD_WRITE - static void fixup_use_write_buffers(struct mtd_info *mtd, void *param) - { - struct map_info *map = mtd->priv; -@@ -199,6 +202,7 @@ static void fixup_use_write_buffers(stru - mtd->write = cfi_amdstd_write_buffers; - } - } -+#endif /* !FORCE_WORD_WRITE */ - - /* Atmel chips don't use the same PRI format as AMD chips */ - static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param) -@@ -1304,6 +1308,7 @@ static int cfi_amdstd_write_words(struct - /* - * FIXME: interleaved mode not tested, and probably not supported! - */ -+#if !FORCE_WORD_WRITE - static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, - unsigned long adr, const u_char *buf, - int len) -@@ -1415,7 +1420,6 @@ static int __xipram do_write_buffer(stru - return ret; - } - -- - static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) - { -@@ -1494,6 +1498,7 @@ static int cfi_amdstd_write_buffers(stru - - return 0; - } -+#endif /* !FORCE_WORD_WRITE */ - - /* - * Handle devices with one erase region, that only implement diff --git a/target/linux/ar71xx/patches-2.6.33/120-dsa-trailer-tag-validation-fix.patch b/target/linux/ar71xx/patches-2.6.33/120-dsa-trailer-tag-validation-fix.patch deleted file mode 100644 index b58aeedc3..000000000 --- a/target/linux/ar71xx/patches-2.6.33/120-dsa-trailer-tag-validation-fix.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/net/dsa/tag_trailer.c -+++ b/net/dsa/tag_trailer.c -@@ -86,7 +86,7 @@ static int trailer_rcv(struct sk_buff *s - - trailer = skb_tail_pointer(skb) - 4; - if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 || -- (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00) -+ (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00) - goto out_drop; - - source_port = trailer[1] & 7; diff --git a/target/linux/ar71xx/patches-2.6.33/121-dsa-add-88e6063-driver.patch b/target/linux/ar71xx/patches-2.6.33/121-dsa-add-88e6063-driver.patch deleted file mode 100644 index 1a11a69c6..000000000 --- a/target/linux/ar71xx/patches-2.6.33/121-dsa-add-88e6063-driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/net/dsa/Kconfig -+++ b/net/dsa/Kconfig -@@ -36,6 +36,13 @@ config NET_DSA_MV88E6060 - This enables support for the Marvell 88E6060 ethernet switch - chip. - -+config NET_DSA_MV88E6063 -+ bool "Marvell 88E6063 ethernet switch chip support" -+ select NET_DSA_TAG_TRAILER -+ ---help--- -+ This enables support for the Marvell 88E6063 ethernet switch -+ chip -+ - config NET_DSA_MV88E6XXX_NEED_PPU - bool - default n ---- a/net/dsa/Makefile -+++ b/net/dsa/Makefile -@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag - # switch drivers - obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o - obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o -+obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o - obj-$(CONFIG_NET_DSA_MV88E6123_61_65) += mv88e6123_61_65.o - obj-$(CONFIG_NET_DSA_MV88E6131) += mv88e6131.o - diff --git a/target/linux/ar71xx/patches-2.6.33/122-dsa-add-qinq-tagging-format.patch b/target/linux/ar71xx/patches-2.6.33/122-dsa-add-qinq-tagging-format.patch deleted file mode 100644 index dc03fd6eb..000000000 --- a/target/linux/ar71xx/patches-2.6.33/122-dsa-add-qinq-tagging-format.patch +++ /dev/null @@ -1,79 +0,0 @@ ---- a/include/linux/if_ether.h -+++ b/include/linux/if_ether.h -@@ -81,6 +81,7 @@ - #define ETH_P_1588 0x88F7 /* IEEE 1588 Timesync */ - #define ETH_P_FCOE 0x8906 /* Fibre Channel over Ethernet */ - #define ETH_P_FIP 0x8914 /* FCoE Initialization Protocol */ -+#define ETH_P_QINQ 0x9100 /* QinQ VLAN Stacking Protocol */ - #define ETH_P_EDSA 0xDADA /* Ethertype DSA [ NOT AN OFFICIALLY REGISTERED ID ] */ - - /* ---- a/net/dsa/dsa_priv.h -+++ b/net/dsa/dsa_priv.h -@@ -174,6 +174,9 @@ netdev_tx_t dsa_xmit(struct sk_buff *skb - /* tag_edsa.c */ - netdev_tx_t edsa_xmit(struct sk_buff *skb, struct net_device *dev); - -+/* tag_qinq.c */ -+netdev_tx_t qinq_xmit(struct sk_buff *skb, struct net_device *dev); -+ - /* tag_trailer.c */ - netdev_tx_t trailer_xmit(struct sk_buff *skb, struct net_device *dev); - ---- a/net/dsa/Kconfig -+++ b/net/dsa/Kconfig -@@ -23,6 +23,10 @@ config NET_DSA_TAG_TRAILER - bool - default n - -+config NET_DSA_TAG_QINQ -+ bool -+ default y -+ - - # switch drivers - config NET_DSA_MV88E6XXX ---- a/net/dsa/Makefile -+++ b/net/dsa/Makefile -@@ -1,6 +1,7 @@ - # tagging formats - obj-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o - obj-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o -+obj-$(CONFIG_NET_DSA_TAG_QINQ) += tag_qinq.o - obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o - - # switch drivers ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -321,6 +321,19 @@ static const struct net_device_ops edsa_ - .ndo_do_ioctl = dsa_slave_ioctl, - }; - #endif -+#ifdef CONFIG_NET_DSA_TAG_QINQ -+static const struct net_device_ops qinq_netdev_ops = { -+ .ndo_init = dsa_slave_init, -+ .ndo_open = dsa_slave_open, -+ .ndo_stop = dsa_slave_close, -+ .ndo_start_xmit = qinq_xmit, -+ .ndo_change_rx_flags = dsa_slave_change_rx_flags, -+ .ndo_set_rx_mode = dsa_slave_set_rx_mode, -+ .ndo_set_multicast_list = dsa_slave_set_rx_mode, -+ .ndo_set_mac_address = dsa_slave_set_mac_address, -+ .ndo_do_ioctl = dsa_slave_ioctl, -+}; -+#endif - #ifdef CONFIG_NET_DSA_TAG_TRAILER - static const struct net_device_ops trailer_netdev_ops = { - .ndo_init = dsa_slave_init, -@@ -366,6 +379,11 @@ dsa_slave_create(struct dsa_switch *ds, - slave_dev->netdev_ops = &edsa_netdev_ops; - break; - #endif -+#ifdef CONFIG_NET_DSA_TAG_QINQ -+ case htons(ETH_P_QINQ): -+ slave_dev->netdev_ops = &qinq_netdev_ops; -+ break; -+#endif - #ifdef CONFIG_NET_DSA_TAG_TRAILER - case htons(ETH_P_TRAILER): - slave_dev->netdev_ops = &trailer_netdev_ops; diff --git a/target/linux/ar71xx/patches-2.6.33/123-dsa-add-ar7240-built-in-switch-support.patch b/target/linux/ar71xx/patches-2.6.33/123-dsa-add-ar7240-built-in-switch-support.patch deleted file mode 100644 index 50e6e5de2..000000000 --- a/target/linux/ar71xx/patches-2.6.33/123-dsa-add-ar7240-built-in-switch-support.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/net/dsa/Kconfig -+++ b/net/dsa/Kconfig -@@ -29,6 +29,15 @@ config NET_DSA_TAG_QINQ - - - # switch drivers -+config NET_DSA_AR7240 -+ bool "Atheros AR7240 built-in ethernet switch support" -+ depends on ATHEROS_AR71XX -+ default n -+ select NET_DSA_TAG_QINQ -+ ---help--- -+ This enables support for the built-in ethernet switch of the -+ Atheros AR7240 SoC. -+ - config NET_DSA_MV88E6XXX - bool - default n ---- a/net/dsa/Makefile -+++ b/net/dsa/Makefile -@@ -5,6 +5,7 @@ obj-$(CONFIG_NET_DSA_TAG_QINQ) += tag_qi - obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o - - # switch drivers -+obj-$(CONFIG_NET_DSA_AR7240) += ar7240.o - obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o - obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o - obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o diff --git a/target/linux/ar71xx/patches-2.6.33/140-redboot_partition_scan.patch b/target/linux/ar71xx/patches-2.6.33/140-redboot_partition_scan.patch deleted file mode 100644 index 289d4eb99..000000000 --- a/target/linux/ar71xx/patches-2.6.33/140-redboot_partition_scan.patch +++ /dev/null @@ -1,54 +0,0 @@ ---- a/drivers/mtd/redboot.c -+++ b/drivers/mtd/redboot.c -@@ -60,31 +60,32 @@ static int parse_redboot_partitions(stru - static char nullstring[] = "unallocated"; - #endif - -+ buf = vmalloc(master->erasesize); -+ if (!buf) -+ return -ENOMEM; -+ -+ restart: - if ( directory < 0 ) { - offset = master->size + directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - if (!offset) { - nogood: - printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); -+ vfree(buf); - return -EIO; - } - offset -= master->erasesize; - } - } else { - offset = directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - offset += master->erasesize; - if (offset == master->size) - goto nogood; - } - } -- buf = vmalloc(master->erasesize); -- -- if (!buf) -- return -ENOMEM; -- - printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", - master->name, offset); - -@@ -156,6 +157,11 @@ static int parse_redboot_partitions(stru - } - if (i == numslots) { - /* Didn't find it */ -+ if (offset + master->erasesize < master->size) { -+ /* not at the end of the flash yet, maybe next block :) */ -+ directory++; -+ goto restart; -+ } - printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", - master->name); - ret = 0; diff --git a/target/linux/ar71xx/patches-2.6.33/200-rb4xx_nand_driver.patch b/target/linux/ar71xx/patches-2.6.33/200-rb4xx_nand_driver.patch deleted file mode 100644 index 1e64e0a36..000000000 --- a/target/linux/ar71xx/patches-2.6.33/200-rb4xx_nand_driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -488,4 +488,8 @@ config MTD_NAND_W90P910 - This enables the driver for the NAND Flash on evaluation board based - on w90p910. - -+config MTD_NAND_RB4XX -+ tristate "NAND flash driver for RouterBoard 4xx series" -+ depends on MTD_NAND && AR71XX_MACH_RB4XX -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -30,6 +30,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27 - obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o - obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o -+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o - obj-$(CONFIG_MTD_ALAUDA) += alauda.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o diff --git a/target/linux/ar71xx/patches-2.6.33/201-ap83_spi_controller.patch b/target/linux/ar71xx/patches-2.6.33/201-ap83_spi_controller.patch deleted file mode 100644 index a8e889a7b..000000000 --- a/target/linux/ar71xx/patches-2.6.33/201-ap83_spi_controller.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -11,6 +11,7 @@ endif - obj-$(CONFIG_SPI_MASTER) += spi.o - - # SPI master controller drivers (bus) -+obj-$(CONFIG_SPI_AP83) += ap83_spi.o - obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o - obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o - obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -53,6 +53,14 @@ if SPI_MASTER - - comment "SPI Master Controller Drivers" - -+config SPI_AP83 -+ tristate "Atheros AP83 specific SPI Controller" -+ depends on SPI_MASTER && AR71XX_MACH_AP83 -+ select SPI_BITBANG -+ help -+ This is a specific SPI controller driver for the Atheros AP83 -+ reference board. -+ - config SPI_AR71XX - tristate "Atheros AR71xx SPI Controller" - depends on SPI_MASTER && ATHEROS_AR71XX diff --git a/target/linux/ar71xx/patches-2.6.33/202-spi_vsc7385_driver.patch b/target/linux/ar71xx/patches-2.6.33/202-spi_vsc7385_driver.patch deleted file mode 100644 index 487785a94..000000000 --- a/target/linux/ar71xx/patches-2.6.33/202-spi_vsc7385_driver.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -365,6 +365,11 @@ config SPI_TLE62X0 - sysfs interface, with each line presented as a kind of GPIO - exposing both switch control and diagnostic feedback. - -+config SPI_VSC7385 -+ tristate "Vitesse VSC7385 ethernet switch driver" -+ help -+ SPI driver for the Vitesse VSC7385 ethernet switch. -+ - # - # Add new SPI protocol masters in alphabetical order above this line - # ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -54,6 +54,7 @@ spi_s3c24xx_hw-$(CONFIG_SPI_S3C24XX_FIQ) - - # SPI protocol drivers (device/link on bus) - obj-$(CONFIG_SPI_SPIDEV) += spidev.o -+obj-$(CONFIG_SPI_VSC7385) += spi_vsc7385.o - obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o - # ... add above this line ... - diff --git a/target/linux/ar71xx/patches-2.6.33/203-pb44_spi_controller.patch b/target/linux/ar71xx/patches-2.6.33/203-pb44_spi_controller.patch deleted file mode 100644 index 2a6edeb18..000000000 --- a/target/linux/ar71xx/patches-2.6.33/203-pb44_spi_controller.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -68,6 +68,14 @@ config SPI_AR71XX - help - This is the SPI contoller driver for Atheros AR71xx. - -+config SPI_PB44 -+ tristate "Atheros PB44 board specific SPI controller" -+ depends on SPI_MASTER && AR71XX_MACH_PB44 -+ select SPI_BITBANG -+ help -+ This is a specific SPI controller driver for the Atheros PB44 -+ reference board. -+ - config SPI_ATMEL - tristate "Atmel SPI Controller" - depends on (ARCH_AT91 || AVR32) ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_SPI_GPIO) += spi_gpio.o - obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o - obj-$(CONFIG_SPI_IMX) += spi_imx.o - obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o -+obj-$(CONFIG_SPI_PB44) += pb44_spi.o - obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o - obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o - obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o diff --git a/target/linux/ar71xx/patches-2.6.33/205-wndr3700-usb-led-driver.patch b/target/linux/ar71xx/patches-2.6.33/205-wndr3700-usb-led-driver.patch deleted file mode 100644 index d2fbc9c76..000000000 --- a/target/linux/ar71xx/patches-2.6.33/205-wndr3700-usb-led-driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -269,6 +269,13 @@ config LEDS_ADP5520 - To compile this driver as a module, choose M here: the module will - be called leds-adp5520. - -+config LEDS_WNDR3700_USB -+ tristate "NETGEAR WNDR3700 USB LED driver" -+ depends on LEDS_CLASS && AR71XX_MACH_WNDR3700 -+ help -+ This option enables support for the USB LED found on the -+ NETGEAR WNDR3700 board. -+ - comment "LED Triggers" - - config LEDS_TRIGGERS ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -29,6 +29,7 @@ obj-$(CONFIG_LEDS_DA903X) += leds-da903 - obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o - obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o - obj-$(CONFIG_LEDS_PWM) += leds-pwm.o -+obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o - obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o - obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o - obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o diff --git a/target/linux/ar71xx/patches-2.6.33/206-nxp-74hc153-gpio-chip-driver.patch b/target/linux/ar71xx/patches-2.6.33/206-nxp-74hc153-gpio-chip-driver.patch deleted file mode 100644 index 575f7bbd8..000000000 --- a/target/linux/ar71xx/patches-2.6.33/206-nxp-74hc153-gpio-chip-driver.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -255,4 +255,12 @@ config GPIO_UCB1400 - To compile this driver as a module, choose M here: the - module will be called ucb1400_gpio. - -+comment "Other GPIO expanders" -+ -+config GPIO_NXP_74HC153 -+ tristate "NXP 74HC153 Dual 4-input multiplexer" -+ help -+ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This -+ provides a GPIO interface supporting inputs. -+ - endif ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -11,6 +11,7 @@ obj-$(CONFIG_GPIO_MAX7301) += max7301.o - obj-$(CONFIG_GPIO_MAX732X) += max732x.o - obj-$(CONFIG_GPIO_MC33880) += mc33880.o - obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o -+obj-$(CONFIG_GPIO_NXP_74HC153) += nxp_74hc153.o - obj-$(CONFIG_GPIO_PCA953X) += pca953x.o - obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o - obj-$(CONFIG_GPIO_PL061) += pl061.o diff --git a/target/linux/ar71xx/patches-2.6.33/207-rb750-led-driver.patch b/target/linux/ar71xx/patches-2.6.33/207-rb750-led-driver.patch deleted file mode 100644 index 500604fe2..000000000 --- a/target/linux/ar71xx/patches-2.6.33/207-rb750-led-driver.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -276,6 +276,10 @@ config LEDS_WNDR3700_USB - This option enables support for the USB LED found on the - NETGEAR WNDR3700 board. - -+config LEDS_RB750 -+ tristate "LED driver for the Mikrotik RouterBOARD 750" -+ depends on LEDS_CLASS && AR71XX_MACH_RB750 -+ - comment "LED Triggers" - - config LEDS_TRIGGERS ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -34,6 +34,7 @@ obj-$(CONFIG_LEDS_REGULATOR) += leds-re - obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o - obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o - obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o -+obj-$(CONFIG_LEDS_RB750) += leds-rb750.o - - # LED SPI Drivers - obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o diff --git a/target/linux/ar71xx/patches-2.6.33/208-rb750-nand-driver.patch b/target/linux/ar71xx/patches-2.6.33/208-rb750-nand-driver.patch deleted file mode 100644 index 3766a1cd8..000000000 --- a/target/linux/ar71xx/patches-2.6.33/208-rb750-nand-driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -492,4 +492,8 @@ config MTD_NAND_RB4XX - tristate "NAND flash driver for RouterBoard 4xx series" - depends on MTD_NAND && AR71XX_MACH_RB4XX - -+config MTD_NAND_RB750 -+ tristate "NAND flash driver for the RouterBoard 750" -+ depends on MTD_NAND && AR71XX_MACH_RB750 -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -31,6 +31,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx - obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o - obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o -+obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o - obj-$(CONFIG_MTD_ALAUDA) += alauda.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o diff --git a/target/linux/ar71xx/patches-2.6.33/300-mips_fw_myloader.patch b/target/linux/ar71xx/patches-2.6.33/300-mips_fw_myloader.patch deleted file mode 100644 index 48d0de83a..000000000 --- a/target/linux/ar71xx/patches-2.6.33/300-mips_fw_myloader.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -190,6 +190,7 @@ endif - # - libs-$(CONFIG_ARC) += arch/mips/fw/arc/ - libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ -+libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/ - libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ - libs-y += arch/mips/fw/lib/ - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -877,6 +877,9 @@ config MIPS_NILE4 - config MIPS_DISABLE_OBSOLETE_IDE - bool - -+config MYLOADER -+ bool -+ - config SYNC_R4K - bool - diff --git a/target/linux/ar71xx/patches-2.6.33/400-mips-multi-machine-update.patch b/target/linux/ar71xx/patches-2.6.33/400-mips-multi-machine-update.patch deleted file mode 100644 index d63587901..000000000 --- a/target/linux/ar71xx/patches-2.6.33/400-mips-multi-machine-update.patch +++ /dev/null @@ -1,134 +0,0 @@ ---- a/arch/mips/kernel/mips_machine.c -+++ b/arch/mips/kernel/mips_machine.c -@@ -7,12 +7,13 @@ - * - */ - #include -+#include - - #include --#include - - static struct list_head mips_machines __initdata = - LIST_HEAD_INIT(mips_machines); -+static char *mips_machid __initdata; - - char *mips_machine_name = "Unknown"; - -@@ -55,20 +56,65 @@ void __init mips_machine_set_name(char * - } - } - --void __init mips_machine_setup(unsigned long machtype) -+void __init mips_machine_setup(void) - { - struct mips_machine *mach; - -- mach = mips_machine_find(machtype); -+ mach = mips_machine_find(mips_machtype); - if (!mach) { -- printk(KERN_ALERT "MIPS: no machine registered for " -- "machtype %lu\n", machtype); -+ printk(KERN_WARNING "MIPS: no machine registered for " -+ "machtype %lu\n", mips_machtype); - return; - } - - mips_machine_set_name(mach->mach_name); -- printk(KERN_INFO "MIPS: machine is %s\n", mips_machine_name); -+ printk(KERN_NOTICE "MIPS: machine is %s\n", mips_machine_name); - - if (mach->mach_setup) - mach->mach_setup(); - } -+ -+int __init mips_machtype_setup(char *id) -+{ -+ if (mips_machid == NULL) -+ mips_machid = id; -+ -+ return 1; -+} -+ -+__setup("machtype=", mips_machtype_setup); -+ -+static int __init mips_machtype_init(void) -+{ -+ struct list_head *this; -+ struct mips_machine *mach; -+ -+ if (mips_machid == NULL) -+ return 0; -+ -+ list_for_each(this, &mips_machines) { -+ mach = list_entry(this, struct mips_machine, list); -+ if (mach->mach_id == NULL) -+ continue; -+ -+ if (strcmp(mach->mach_id, mips_machid) == 0) { -+ mips_machtype = mach->mach_type; -+ return 0; -+ } -+ } -+ -+ printk(KERN_WARNING -+ "MIPS: no machine found for id: '%s', registered machines:\n", -+ mips_machid); -+ printk(KERN_WARNING "%32s %s\n", "id", "name"); -+ -+ list_for_each(this, &mips_machines) { -+ mach = list_entry(this, struct mips_machine, list); -+ printk(KERN_WARNING "%32s %s\n", -+ mach->mach_id ? mach->mach_id : "", mach->mach_name); -+ } -+ -+ return 0; -+} -+ -+core_initcall(mips_machtype_init); ---- a/arch/mips/include/asm/mips_machine.h -+++ b/arch/mips/include/asm/mips_machine.h -@@ -13,25 +13,33 @@ - #include - #include - -+#include -+ - struct mips_machine { - unsigned long mach_type; -- void (*mach_setup)(void); -+ char *mach_id; - char *mach_name; -+ void (*mach_setup)(void); - struct list_head list; - }; - - void mips_machine_register(struct mips_machine *) __init; --void mips_machine_setup(unsigned long machtype) __init; -+void mips_machine_setup(void) __init; -+int mips_machtype_setup(char *id) __init; - void mips_machine_set_name(char *name) __init; - - extern char *mips_machine_name; - --#define MIPS_MACHINE(_type, _name, _setup) \ --static char machine_name_##_type[] __initdata = _name; \ -+#define MIPS_MACHINE(_type, _id, _name, _setup) \ -+static const char machine_name_##_type[] __initconst \ -+ __aligned(1) = _name; \ -+static const char machine_id_##_type[] __initconst \ -+ __aligned(1) = _id; \ - static struct mips_machine machine_##_type __initdata = \ - { \ - .mach_type = _type, \ -- .mach_name = machine_name_##_type, \ -+ .mach_id = (char *) machine_id_##_type, \ -+ .mach_name = (char *) machine_name_##_type, \ - .mach_setup = _setup, \ - }; \ - \ -@@ -44,4 +52,3 @@ static int __init register_machine_##_ty - pure_initcall(register_machine_##_type) - - #endif /* __ASM_MIPS_MACHINE_H */ -- diff --git a/target/linux/ar71xx/patches-2.6.33/901-get_c0_compare_irq_function.patch b/target/linux/ar71xx/patches-2.6.33/901-get_c0_compare_irq_function.patch deleted file mode 100644 index 596e6697e..000000000 --- a/target/linux/ar71xx/patches-2.6.33/901-get_c0_compare_irq_function.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/mips/kernel/traps.c -+++ b/arch/mips/kernel/traps.c -@@ -50,6 +50,7 @@ - #include - #include - #include -+#include - - extern void check_wait(void); - extern asmlinkage void r4k_wait(void); -@@ -1496,6 +1497,8 @@ void __cpuinit per_cpu_trap_init(void) - if (cpu_has_mips_r2) { - cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; - cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; -+ if (get_c0_compare_irq) -+ cp0_compare_irq = get_c0_compare_irq(); - cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; ---- a/arch/mips/include/asm/time.h -+++ b/arch/mips/include/asm/time.h -@@ -52,6 +52,7 @@ extern int (*perf_irq)(void); - */ - #ifdef CONFIG_CEVT_R4K_LIB - extern unsigned int __weak get_c0_compare_int(void); -+extern unsigned int __weak get_c0_compare_irq(void); - extern int r4k_clockevent_init(void); - #endif - diff --git a/target/linux/ar71xx/patches-2.6.34/001-ar71xx_core.patch b/target/linux/ar71xx/patches-2.6.34/001-ar71xx_core.patch deleted file mode 100644 index 5073652dd..000000000 --- a/target/linux/ar71xx/patches-2.6.34/001-ar71xx_core.patch +++ /dev/null @@ -1,50 +0,0 @@ ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -166,6 +166,13 @@ ifeq (,$(findstring march=octeon, $(cfla - cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon - endif - -+# -+# Atheros AR71xx -+# -+core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/ -+cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx -+load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000 -+ - cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) - cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) - cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -48,6 +48,23 @@ config AR7 - Support for the Texas Instruments AR7 System-on-a-Chip - family: TNETD7100, 7200 and 7300. - -+config ATHEROS_AR71XX -+ bool "Atheros AR71xx based boards" -+ select CEVT_R4K -+ select CSRC_R4K -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select ARCH_REQUIRE_GPIOLIB -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_HAS_CPU_MIPS32_R2 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_HAS_EARLY_PRINTK -+ select MIPS_MACHINE -+ help -+ Support for Atheros AR71xx based boards. -+ - config BCM47XX - bool "BCM47XX based boards" - select CEVT_R4K -@@ -682,6 +699,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD - endchoice - - source "arch/mips/alchemy/Kconfig" -+source "arch/mips/ar71xx/Kconfig" - source "arch/mips/bcm63xx/Kconfig" - source "arch/mips/jazz/Kconfig" - source "arch/mips/lasat/Kconfig" diff --git a/target/linux/ar71xx/patches-2.6.34/002-ar71xx_pci.patch b/target/linux/ar71xx/patches-2.6.34/002-ar71xx_pci.patch deleted file mode 100644 index 3facce9d7..000000000 --- a/target/linux/ar71xx/patches-2.6.34/002-ar71xx_pci.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o - obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o - obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ - ops-bcm63xx.o -+obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o pci-ar724x.o - - # - # These are still pretty much in the old state, watch, go blind. diff --git a/target/linux/ar71xx/patches-2.6.34/003-ar71xx_usb_host.patch b/target/linux/ar71xx/patches-2.6.34/003-ar71xx_usb_host.patch deleted file mode 100644 index 238a79c9b..000000000 --- a/target/linux/ar71xx/patches-2.6.34/003-ar71xx_usb_host.patch +++ /dev/null @@ -1,58 +0,0 @@ ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -109,6 +109,13 @@ config XPS_USB_HCD_XILINX - support both high speed and full speed devices, or high speed - devices only. - -+config USB_EHCI_AR71XX -+ bool "USB EHCI support for AR71xx" -+ depends on USB_EHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in EHCI controller -+ - config USB_EHCI_FSL - bool "Support for Freescale on-chip EHCI USB controller" - depends on USB_EHCI_HCD && FSL_SOC -@@ -207,6 +214,13 @@ config USB_OHCI_HCD - To compile this driver as a module, choose M here: the - module will be called ohci-hcd. - -+config USB_OHCI_AR71XX -+ bool "USB OHCI support for Atheros AR71xx" -+ depends on USB_OHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in OHCI controller -+ - config USB_OHCI_HCD_PPC_SOC - bool "OHCI support for on-chip PPC USB controller" - depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) ---- a/drivers/usb/host/ehci-hcd.c -+++ b/drivers/usb/host/ehci-hcd.c -@@ -1158,6 +1158,11 @@ MODULE_LICENSE ("GPL"); - #define PLATFORM_DRIVER ehci_atmel_driver - #endif - -+#ifdef CONFIG_USB_EHCI_AR71XX -+#include "ehci-ar71xx.c" -+#define PLATFORM_DRIVER ehci_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ - !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) - #error "missing bus glue for ehci-hcd" ---- a/drivers/usb/host/ohci-hcd.c -+++ b/drivers/usb/host/ohci-hcd.c -@@ -1085,6 +1085,11 @@ MODULE_LICENSE ("GPL"); - #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver - #endif - -+#ifdef CONFIG_USB_OHCI_AR71XX -+#include "ohci-ar71xx.c" -+#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && \ - !defined(PLATFORM_DRIVER) && \ - !defined(OF_PLATFORM_DRIVER) && \ diff --git a/target/linux/ar71xx/patches-2.6.34/004-ar71xx_spi_controller.patch b/target/linux/ar71xx/patches-2.6.34/004-ar71xx_spi_controller.patch deleted file mode 100644 index 9c196e077..000000000 --- a/target/linux/ar71xx/patches-2.6.34/004-ar71xx_spi_controller.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -53,6 +53,13 @@ if SPI_MASTER - - comment "SPI Master Controller Drivers" - -+config SPI_AR71XX -+ tristate "Atheros AR71xx SPI Controller" -+ depends on SPI_MASTER && ATHEROS_AR71XX -+ select SPI_BITBANG -+ help -+ This is the SPI contoller driver for Atheros AR71xx. -+ - config SPI_ATMEL - tristate "Atmel SPI Controller" - depends on (ARCH_AT91 || AVR32) ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -11,6 +11,7 @@ endif - obj-$(CONFIG_SPI_MASTER) += spi.o - - # SPI master controller drivers (bus) -+obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o - obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o - obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o - obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o diff --git a/target/linux/ar71xx/patches-2.6.34/005-ar71xx_mac_driver.patch b/target/linux/ar71xx/patches-2.6.34/005-ar71xx_mac_driver.patch deleted file mode 100644 index 3721a9b86..000000000 --- a/target/linux/ar71xx/patches-2.6.34/005-ar71xx_mac_driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/net/Kconfig -+++ b/drivers/net/Kconfig -@@ -2128,6 +2128,8 @@ config ACENIC_OMIT_TIGON_I - - The safe and default value for this is N. - -+source drivers/net/ag71xx/Kconfig -+ - config DL2K - tristate "DL2000/TC902x-based Gigabit Ethernet support" - depends on PCI ---- a/drivers/net/Makefile -+++ b/drivers/net/Makefile -@@ -106,6 +106,7 @@ obj-$(CONFIG_STMMAC_ETH) += stmmac/ - # end link order section - # - -+obj-$(CONFIG_AG71XX) += ag71xx/ - obj-$(CONFIG_SUNDANCE) += sundance.o - obj-$(CONFIG_HAMACHI) += hamachi.o - obj-$(CONFIG_NET) += Space.o loopback.o diff --git a/target/linux/ar71xx/patches-2.6.34/006-ar71xx_wdt_driver.patch b/target/linux/ar71xx/patches-2.6.34/006-ar71xx_wdt_driver.patch deleted file mode 100644 index d71a11b86..000000000 --- a/target/linux/ar71xx/patches-2.6.34/006-ar71xx_wdt_driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -840,6 +840,13 @@ config TXX9_WDT - help - Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs. - -+config AR71XX_WDT -+ tristate "Atheros AR71xx Watchdog Timer" -+ depends on ATHEROS_AR71XX -+ help -+ Hardware driver for the built-in watchdog timer on the Atheros -+ AR71xx SoCs. -+ - # PARISC Architecture - - # POWERPC Architecture ---- a/drivers/watchdog/Makefile -+++ b/drivers/watchdog/Makefile -@@ -112,6 +112,7 @@ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o -+obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o - - # PARISC Architecture - diff --git a/target/linux/ar71xx/patches-2.6.34/007-ar91xx_flash_driver.patch b/target/linux/ar71xx/patches-2.6.34/007-ar91xx_flash_driver.patch deleted file mode 100644 index 5dbdd293c..000000000 --- a/target/linux/ar71xx/patches-2.6.34/007-ar91xx_flash_driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/mtd/maps/Kconfig -+++ b/drivers/mtd/maps/Kconfig -@@ -257,6 +257,13 @@ config MTD_ALCHEMY - help - Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards - -+config MTD_AR91XX_FLASH -+ tristate "Atheros AR91xx parallel flash support" -+ depends on ATHEROS_AR71XX -+ select MTD_COMPLEX_MAPPINGS -+ help -+ Parallel flash driver for the Atheros AR91xx based boards. -+ - config MTD_DILNETPC - tristate "CFI Flash device mapped on DIL/Net PC" - depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN ---- a/drivers/mtd/maps/Makefile -+++ b/drivers/mtd/maps/Makefile -@@ -40,6 +40,7 @@ - obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o - obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o - obj-$(CONFIG_MTD_PCI) += pci.o -+obj-$(CONFIG_MTD_AR91XX_FLASH) += ar91xx_flash.o - obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o - obj-$(CONFIG_MTD_EDB7312) += edb7312.o - obj-$(CONFIG_MTD_IMPA7) += impa7.o diff --git a/target/linux/ar71xx/patches-2.6.34/101-ksz8041_phy_driver.patch b/target/linux/ar71xx/patches-2.6.34/101-ksz8041_phy_driver.patch deleted file mode 100644 index 503604610..000000000 --- a/target/linux/ar71xx/patches-2.6.34/101-ksz8041_phy_driver.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -114,6 +114,11 @@ config RTL8306_PHY - tristate "Driver for Realtek RTL8306S switches" - select SWCONFIG - -+config MICREL_PHY -+ tristate "Drivers for Micrel/Kendin PHYs" -+ ---help--- -+ Currently has a driver for the KSZ8041 -+ - config FIXED_PHY - bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" - depends on PHYLIB=y ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi - obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o - obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o - obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o -+obj-$(CONFIG_MICREL) += micrel.o - obj-$(CONFIG_FIXED_PHY) += fixed.o - obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o - obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o diff --git a/target/linux/ar71xx/patches-2.6.34/102-mtd_m25p80_add_myloader_parser.patch b/target/linux/ar71xx/patches-2.6.34/102-mtd_m25p80_add_myloader_parser.patch deleted file mode 100644 index 45f743e06..000000000 --- a/target/linux/ar71xx/patches-2.6.34/102-mtd_m25p80_add_myloader_parser.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -922,6 +922,16 @@ static int __devinit m25p_probe(struct s - part_probes, &parts, 0); - } - -+#ifdef CONFIG_MTD_MYLOADER_PARTS -+ if (nr_parts <= 0) { -+ static const char *part_probes[] -+ = { "MyLoader", NULL, }; -+ -+ nr_parts = parse_mtd_partitions(&flash->mtd, -+ part_probes, &parts, 0); -+ } -+#endif -+ - if (nr_parts <= 0 && data && data->parts) { - parts = data->parts; - nr_parts = data->nr_parts; diff --git a/target/linux/ar71xx/patches-2.6.34/104-mtd_m25p80_add_redboot_parser.patch b/target/linux/ar71xx/patches-2.6.34/104-mtd_m25p80_add_redboot_parser.patch deleted file mode 100644 index 43fe987df..000000000 --- a/target/linux/ar71xx/patches-2.6.34/104-mtd_m25p80_add_redboot_parser.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -932,6 +932,15 @@ static int __devinit m25p_probe(struct s - } - #endif - -+#ifdef CONFIG_MTD_REDBOOT_PARTS -+ if (nr_parts <= 0) { -+ static const char *part_probes[] -+ = { "RedBoot", NULL, }; -+ -+ nr_parts = parse_mtd_partitions(&flash->mtd, -+ part_probes, &parts, 0); -+ } -+#endif - if (nr_parts <= 0 && data && data->parts) { - parts = data->parts; - nr_parts = data->nr_parts; diff --git a/target/linux/ar71xx/patches-2.6.34/107-mtd-SST39VF6401B-support.patch b/target/linux/ar71xx/patches-2.6.34/107-mtd-SST39VF6401B-support.patch deleted file mode 100644 index 2fdfcb7cd..000000000 --- a/target/linux/ar71xx/patches-2.6.34/107-mtd-SST39VF6401B-support.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/drivers/mtd/chips/jedec_probe.c -+++ b/drivers/mtd/chips/jedec_probe.c -@@ -166,6 +166,7 @@ - #define SST39LF160 0x2782 - #define SST39VF1601 0x234b - #define SST39VF3201 0x235b -+#define SST39VF6401B 0x236d - #define SST39LF512 0x00D4 - #define SST39LF010 0x00D5 - #define SST39LF020 0x00D6 -@@ -1556,6 +1557,18 @@ static const struct amd_flash_info jedec - ERASEINFO(0x10000,64), - } - }, { -+ .mfr_id = MANUFACTURER_SST, -+ .dev_id = SST39VF6401B, -+ .name = "SST 39VF6401B", -+ .devtypes = CFI_DEVICETYPE_X16, -+ .uaddr = MTD_UADDR_0xAAAA_0x5555, -+ .dev_size = SIZE_8MiB, -+ .cmd_set = P_ID_AMD_STD, -+ .nr_regions = 1, -+ .regions = { -+ ERASEINFO(0x10000,128) -+ } -+ }, { - .mfr_id = MANUFACTURER_ST, - .dev_id = M29F800AB, - .name = "ST M29F800AB", diff --git a/target/linux/ar71xx/patches-2.6.34/108-mtd_fix_cfi_cmdset_0002_status_check.patch b/target/linux/ar71xx/patches-2.6.34/108-mtd_fix_cfi_cmdset_0002_status_check.patch deleted file mode 100644 index e0676cae9..000000000 --- a/target/linux/ar71xx/patches-2.6.34/108-mtd_fix_cfi_cmdset_0002_status_check.patch +++ /dev/null @@ -1,69 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -1130,8 +1130,8 @@ static int __xipram do_write_oneword(str - break; - } - -- if (chip_ready(map, adr)) -- break; -+ if (chip_good(map, adr, datum)) -+ goto enable_xip; - - /* Latency issues. Drop the lock, wait a while and retry */ - UDELAY(map, chip, adr, 1); -@@ -1147,6 +1147,8 @@ static int __xipram do_write_oneword(str - - ret = -EIO; - } -+ -+ enable_xip: - xip_enable(map, chip, adr); - op_done: - chip->state = FL_READY; -@@ -1493,7 +1495,6 @@ static int cfi_amdstd_write_buffers(stru - return 0; - } - -- - /* - * Handle devices with one erase region, that only implement - * the chip erase command. -@@ -1557,8 +1558,8 @@ static int __xipram do_erase_chip(struct - chip->erase_suspended = 0; - } - -- if (chip_ready(map, adr)) -- break; -+ if (chip_good(map, adr, map_word_ff(map))) -+ goto op_done; - - if (time_after(jiffies, timeo)) { - printk(KERN_WARNING "MTD %s(): software timeout\n", -@@ -1578,6 +1579,7 @@ static int __xipram do_erase_chip(struct - ret = -EIO; - } - -+ op_done: - chip->state = FL_READY; - xip_enable(map, chip, adr); - put_chip(map, chip, adr); -@@ -1645,9 +1647,9 @@ static int __xipram do_erase_oneblock(st - chip->erase_suspended = 0; - } - -- if (chip_ready(map, adr)) { -+ if (chip_good(map, adr, map_word_ff(map))) { - xip_enable(map, chip, adr); -- break; -+ goto op_done; - } - - if (time_after(jiffies, timeo)) { -@@ -1669,6 +1671,7 @@ static int __xipram do_erase_oneblock(st - ret = -EIO; - } - -+ op_done: - chip->state = FL_READY; - put_chip(map, chip, adr); - spin_unlock(chip->mutex); diff --git a/target/linux/ar71xx/patches-2.6.34/109-mtd-wrt160nl-trx-parser.patch b/target/linux/ar71xx/patches-2.6.34/109-mtd-wrt160nl-trx-parser.patch deleted file mode 100644 index 037795b33..000000000 --- a/target/linux/ar71xx/patches-2.6.34/109-mtd-wrt160nl-trx-parser.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -941,6 +941,16 @@ static int __devinit m25p_probe(struct s - part_probes, &parts, 0); - } - #endif -+ -+#ifdef CONFIG_MTD_WRT160NL_PARTS -+ if (nr_parts <= 0) { -+ static const char *part_probes[] -+ = { "wrt160nl", NULL, }; -+ -+ nr_parts = parse_mtd_partitions(&flash->mtd, -+ part_probes, &parts, 0); -+ } -+#endif - if (nr_parts <= 0 && data && data->parts) { - parts = data->parts; - nr_parts = data->nr_parts; ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -181,6 +181,12 @@ config MTD_AR7_PARTS - ---help--- - TI AR7 partitioning support - -+config MTD_WRT160NL_PARTS -+ tristate "Linksys WRT160NL partitioning support" -+ depends on MTD_PARTITIONS && AR71XX_MACH_WRT160NL -+ ---help--- -+ Linksys WRT160NL partitioning support -+ - config MTD_MYLOADER_PARTS - tristate "MyLoader partition parsing" - depends on MTD_PARTITIONS && (ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX) ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -12,6 +12,7 @@ obj-$(CONFIG_MTD_REDBOOT_PARTS) += redbo - obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o - obj-$(CONFIG_MTD_AFS_PARTS) += afs.o - obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o -+obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o - obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o - obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o - diff --git a/target/linux/ar71xx/patches-2.6.34/110-usb-ehci-add-war-for-synopsys-hc-bug.patch b/target/linux/ar71xx/patches-2.6.34/110-usb-ehci-add-war-for-synopsys-hc-bug.patch deleted file mode 100644 index 076c39ea2..000000000 --- a/target/linux/ar71xx/patches-2.6.34/110-usb-ehci-add-war-for-synopsys-hc-bug.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/drivers/usb/host/ehci-q.c -+++ b/drivers/usb/host/ehci-q.c -@@ -1194,6 +1194,9 @@ static void end_unlink_async (struct ehc - ehci->reclaim = NULL; - start_unlink_async (ehci, next); - } -+ -+ if (ehci->has_synopsys_hc_bug) -+ writel((u32)ehci->async->qh_dma, &ehci->regs->async_next); - } - - /* makes sure the async qh will become idle */ ---- a/drivers/usb/host/ehci.h -+++ b/drivers/usb/host/ehci.h -@@ -129,6 +129,7 @@ struct ehci_hcd { /* one per controlle - unsigned has_amcc_usb23:1; - unsigned need_io_watchdog:1; - unsigned broken_periodic:1; -+ unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ - - /* required for usb32 quirk */ - #define OHCI_CTRL_HCFS (3 << 6) diff --git a/target/linux/ar71xx/patches-2.6.34/111-mtd-cfi_cmdset_0002-force-word-write.patch b/target/linux/ar71xx/patches-2.6.34/111-mtd-cfi_cmdset_0002-force-word-write.patch deleted file mode 100644 index 3215a7d9d..000000000 --- a/target/linux/ar71xx/patches-2.6.34/111-mtd-cfi_cmdset_0002-force-word-write.patch +++ /dev/null @@ -1,61 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -39,7 +39,7 @@ - #include - - #define AMD_BOOTLOC_BUG --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - #define MAX_WORD_RETRIES 3 - -@@ -55,7 +55,9 @@ - - static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); - static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); -+#if !FORCE_WORD_WRITE - static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); -+#endif - static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); - static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); - static void cfi_amdstd_sync (struct mtd_info *); -@@ -190,6 +192,7 @@ static void fixup_amd_bootblock(struct m - } - #endif - -+#if !FORCE_WORD_WRITE - static void fixup_use_write_buffers(struct mtd_info *mtd, void *param) - { - struct map_info *map = mtd->priv; -@@ -199,6 +202,7 @@ static void fixup_use_write_buffers(stru - mtd->write = cfi_amdstd_write_buffers; - } - } -+#endif /* !FORCE_WORD_WRITE */ - - /* Atmel chips don't use the same PRI format as AMD chips */ - static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param) -@@ -1304,6 +1308,7 @@ static int cfi_amdstd_write_words(struct - /* - * FIXME: interleaved mode not tested, and probably not supported! - */ -+#if !FORCE_WORD_WRITE - static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, - unsigned long adr, const u_char *buf, - int len) -@@ -1415,7 +1420,6 @@ static int __xipram do_write_buffer(stru - return ret; - } - -- - static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) - { -@@ -1494,6 +1498,7 @@ static int cfi_amdstd_write_buffers(stru - - return 0; - } -+#endif /* !FORCE_WORD_WRITE */ - - /* - * Handle devices with one erase region, that only implement diff --git a/target/linux/ar71xx/patches-2.6.34/120-dsa-trailer-tag-validation-fix.patch b/target/linux/ar71xx/patches-2.6.34/120-dsa-trailer-tag-validation-fix.patch deleted file mode 100644 index b58aeedc3..000000000 --- a/target/linux/ar71xx/patches-2.6.34/120-dsa-trailer-tag-validation-fix.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/net/dsa/tag_trailer.c -+++ b/net/dsa/tag_trailer.c -@@ -86,7 +86,7 @@ static int trailer_rcv(struct sk_buff *s - - trailer = skb_tail_pointer(skb) - 4; - if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 || -- (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00) -+ (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00) - goto out_drop; - - source_port = trailer[1] & 7; diff --git a/target/linux/ar71xx/patches-2.6.34/121-dsa-add-88e6063-driver.patch b/target/linux/ar71xx/patches-2.6.34/121-dsa-add-88e6063-driver.patch deleted file mode 100644 index 1a11a69c6..000000000 --- a/target/linux/ar71xx/patches-2.6.34/121-dsa-add-88e6063-driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/net/dsa/Kconfig -+++ b/net/dsa/Kconfig -@@ -36,6 +36,13 @@ config NET_DSA_MV88E6060 - This enables support for the Marvell 88E6060 ethernet switch - chip. - -+config NET_DSA_MV88E6063 -+ bool "Marvell 88E6063 ethernet switch chip support" -+ select NET_DSA_TAG_TRAILER -+ ---help--- -+ This enables support for the Marvell 88E6063 ethernet switch -+ chip -+ - config NET_DSA_MV88E6XXX_NEED_PPU - bool - default n ---- a/net/dsa/Makefile -+++ b/net/dsa/Makefile -@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag - # switch drivers - obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o - obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o -+obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o - obj-$(CONFIG_NET_DSA_MV88E6123_61_65) += mv88e6123_61_65.o - obj-$(CONFIG_NET_DSA_MV88E6131) += mv88e6131.o - diff --git a/target/linux/ar71xx/patches-2.6.34/122-dsa-add-qinq-tagging-format.patch b/target/linux/ar71xx/patches-2.6.34/122-dsa-add-qinq-tagging-format.patch deleted file mode 100644 index dc03fd6eb..000000000 --- a/target/linux/ar71xx/patches-2.6.34/122-dsa-add-qinq-tagging-format.patch +++ /dev/null @@ -1,79 +0,0 @@ ---- a/include/linux/if_ether.h -+++ b/include/linux/if_ether.h -@@ -81,6 +81,7 @@ - #define ETH_P_1588 0x88F7 /* IEEE 1588 Timesync */ - #define ETH_P_FCOE 0x8906 /* Fibre Channel over Ethernet */ - #define ETH_P_FIP 0x8914 /* FCoE Initialization Protocol */ -+#define ETH_P_QINQ 0x9100 /* QinQ VLAN Stacking Protocol */ - #define ETH_P_EDSA 0xDADA /* Ethertype DSA [ NOT AN OFFICIALLY REGISTERED ID ] */ - - /* ---- a/net/dsa/dsa_priv.h -+++ b/net/dsa/dsa_priv.h -@@ -174,6 +174,9 @@ netdev_tx_t dsa_xmit(struct sk_buff *skb - /* tag_edsa.c */ - netdev_tx_t edsa_xmit(struct sk_buff *skb, struct net_device *dev); - -+/* tag_qinq.c */ -+netdev_tx_t qinq_xmit(struct sk_buff *skb, struct net_device *dev); -+ - /* tag_trailer.c */ - netdev_tx_t trailer_xmit(struct sk_buff *skb, struct net_device *dev); - ---- a/net/dsa/Kconfig -+++ b/net/dsa/Kconfig -@@ -23,6 +23,10 @@ config NET_DSA_TAG_TRAILER - bool - default n - -+config NET_DSA_TAG_QINQ -+ bool -+ default y -+ - - # switch drivers - config NET_DSA_MV88E6XXX ---- a/net/dsa/Makefile -+++ b/net/dsa/Makefile -@@ -1,6 +1,7 @@ - # tagging formats - obj-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o - obj-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o -+obj-$(CONFIG_NET_DSA_TAG_QINQ) += tag_qinq.o - obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o - - # switch drivers ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -321,6 +321,19 @@ static const struct net_device_ops edsa_ - .ndo_do_ioctl = dsa_slave_ioctl, - }; - #endif -+#ifdef CONFIG_NET_DSA_TAG_QINQ -+static const struct net_device_ops qinq_netdev_ops = { -+ .ndo_init = dsa_slave_init, -+ .ndo_open = dsa_slave_open, -+ .ndo_stop = dsa_slave_close, -+ .ndo_start_xmit = qinq_xmit, -+ .ndo_change_rx_flags = dsa_slave_change_rx_flags, -+ .ndo_set_rx_mode = dsa_slave_set_rx_mode, -+ .ndo_set_multicast_list = dsa_slave_set_rx_mode, -+ .ndo_set_mac_address = dsa_slave_set_mac_address, -+ .ndo_do_ioctl = dsa_slave_ioctl, -+}; -+#endif - #ifdef CONFIG_NET_DSA_TAG_TRAILER - static const struct net_device_ops trailer_netdev_ops = { - .ndo_init = dsa_slave_init, -@@ -366,6 +379,11 @@ dsa_slave_create(struct dsa_switch *ds, - slave_dev->netdev_ops = &edsa_netdev_ops; - break; - #endif -+#ifdef CONFIG_NET_DSA_TAG_QINQ -+ case htons(ETH_P_QINQ): -+ slave_dev->netdev_ops = &qinq_netdev_ops; -+ break; -+#endif - #ifdef CONFIG_NET_DSA_TAG_TRAILER - case htons(ETH_P_TRAILER): - slave_dev->netdev_ops = &trailer_netdev_ops; diff --git a/target/linux/ar71xx/patches-2.6.34/123-dsa-add-ar7240-built-in-switch-support.patch b/target/linux/ar71xx/patches-2.6.34/123-dsa-add-ar7240-built-in-switch-support.patch deleted file mode 100644 index 50e6e5de2..000000000 --- a/target/linux/ar71xx/patches-2.6.34/123-dsa-add-ar7240-built-in-switch-support.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/net/dsa/Kconfig -+++ b/net/dsa/Kconfig -@@ -29,6 +29,15 @@ config NET_DSA_TAG_QINQ - - - # switch drivers -+config NET_DSA_AR7240 -+ bool "Atheros AR7240 built-in ethernet switch support" -+ depends on ATHEROS_AR71XX -+ default n -+ select NET_DSA_TAG_QINQ -+ ---help--- -+ This enables support for the built-in ethernet switch of the -+ Atheros AR7240 SoC. -+ - config NET_DSA_MV88E6XXX - bool - default n ---- a/net/dsa/Makefile -+++ b/net/dsa/Makefile -@@ -5,6 +5,7 @@ obj-$(CONFIG_NET_DSA_TAG_QINQ) += tag_qi - obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o - - # switch drivers -+obj-$(CONFIG_NET_DSA_AR7240) += ar7240.o - obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o - obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o - obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o diff --git a/target/linux/ar71xx/patches-2.6.34/140-redboot_partition_scan.patch b/target/linux/ar71xx/patches-2.6.34/140-redboot_partition_scan.patch deleted file mode 100644 index 289d4eb99..000000000 --- a/target/linux/ar71xx/patches-2.6.34/140-redboot_partition_scan.patch +++ /dev/null @@ -1,54 +0,0 @@ ---- a/drivers/mtd/redboot.c -+++ b/drivers/mtd/redboot.c -@@ -60,31 +60,32 @@ static int parse_redboot_partitions(stru - static char nullstring[] = "unallocated"; - #endif - -+ buf = vmalloc(master->erasesize); -+ if (!buf) -+ return -ENOMEM; -+ -+ restart: - if ( directory < 0 ) { - offset = master->size + directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - if (!offset) { - nogood: - printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); -+ vfree(buf); - return -EIO; - } - offset -= master->erasesize; - } - } else { - offset = directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - offset += master->erasesize; - if (offset == master->size) - goto nogood; - } - } -- buf = vmalloc(master->erasesize); -- -- if (!buf) -- return -ENOMEM; -- - printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", - master->name, offset); - -@@ -156,6 +157,11 @@ static int parse_redboot_partitions(stru - } - if (i == numslots) { - /* Didn't find it */ -+ if (offset + master->erasesize < master->size) { -+ /* not at the end of the flash yet, maybe next block :) */ -+ directory++; -+ goto restart; -+ } - printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", - master->name); - ret = 0; diff --git a/target/linux/ar71xx/patches-2.6.34/200-rb4xx_nand_driver.patch b/target/linux/ar71xx/patches-2.6.34/200-rb4xx_nand_driver.patch deleted file mode 100644 index 1e64e0a36..000000000 --- a/target/linux/ar71xx/patches-2.6.34/200-rb4xx_nand_driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -488,4 +488,8 @@ config MTD_NAND_W90P910 - This enables the driver for the NAND Flash on evaluation board based - on w90p910. - -+config MTD_NAND_RB4XX -+ tristate "NAND flash driver for RouterBoard 4xx series" -+ depends on MTD_NAND && AR71XX_MACH_RB4XX -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -30,6 +30,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27 - obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o - obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o -+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o - obj-$(CONFIG_MTD_ALAUDA) += alauda.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o diff --git a/target/linux/ar71xx/patches-2.6.34/201-ap83_spi_controller.patch b/target/linux/ar71xx/patches-2.6.34/201-ap83_spi_controller.patch deleted file mode 100644 index a8e889a7b..000000000 --- a/target/linux/ar71xx/patches-2.6.34/201-ap83_spi_controller.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -11,6 +11,7 @@ endif - obj-$(CONFIG_SPI_MASTER) += spi.o - - # SPI master controller drivers (bus) -+obj-$(CONFIG_SPI_AP83) += ap83_spi.o - obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o - obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o - obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -53,6 +53,14 @@ if SPI_MASTER - - comment "SPI Master Controller Drivers" - -+config SPI_AP83 -+ tristate "Atheros AP83 specific SPI Controller" -+ depends on SPI_MASTER && AR71XX_MACH_AP83 -+ select SPI_BITBANG -+ help -+ This is a specific SPI controller driver for the Atheros AP83 -+ reference board. -+ - config SPI_AR71XX - tristate "Atheros AR71xx SPI Controller" - depends on SPI_MASTER && ATHEROS_AR71XX diff --git a/target/linux/ar71xx/patches-2.6.34/202-spi_vsc7385_driver.patch b/target/linux/ar71xx/patches-2.6.34/202-spi_vsc7385_driver.patch deleted file mode 100644 index 487785a94..000000000 --- a/target/linux/ar71xx/patches-2.6.34/202-spi_vsc7385_driver.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -365,6 +365,11 @@ config SPI_TLE62X0 - sysfs interface, with each line presented as a kind of GPIO - exposing both switch control and diagnostic feedback. - -+config SPI_VSC7385 -+ tristate "Vitesse VSC7385 ethernet switch driver" -+ help -+ SPI driver for the Vitesse VSC7385 ethernet switch. -+ - # - # Add new SPI protocol masters in alphabetical order above this line - # ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -54,6 +54,7 @@ spi_s3c24xx_hw-$(CONFIG_SPI_S3C24XX_FIQ) - - # SPI protocol drivers (device/link on bus) - obj-$(CONFIG_SPI_SPIDEV) += spidev.o -+obj-$(CONFIG_SPI_VSC7385) += spi_vsc7385.o - obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o - # ... add above this line ... - diff --git a/target/linux/ar71xx/patches-2.6.34/203-pb44_spi_controller.patch b/target/linux/ar71xx/patches-2.6.34/203-pb44_spi_controller.patch deleted file mode 100644 index 2a6edeb18..000000000 --- a/target/linux/ar71xx/patches-2.6.34/203-pb44_spi_controller.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -68,6 +68,14 @@ config SPI_AR71XX - help - This is the SPI contoller driver for Atheros AR71xx. - -+config SPI_PB44 -+ tristate "Atheros PB44 board specific SPI controller" -+ depends on SPI_MASTER && AR71XX_MACH_PB44 -+ select SPI_BITBANG -+ help -+ This is a specific SPI controller driver for the Atheros PB44 -+ reference board. -+ - config SPI_ATMEL - tristate "Atmel SPI Controller" - depends on (ARCH_AT91 || AVR32) ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_SPI_GPIO) += spi_gpio.o - obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o - obj-$(CONFIG_SPI_IMX) += spi_imx.o - obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o -+obj-$(CONFIG_SPI_PB44) += pb44_spi.o - obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o - obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o - obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o diff --git a/target/linux/ar71xx/patches-2.6.34/205-wndr3700-usb-led-driver.patch b/target/linux/ar71xx/patches-2.6.34/205-wndr3700-usb-led-driver.patch deleted file mode 100644 index d2fbc9c76..000000000 --- a/target/linux/ar71xx/patches-2.6.34/205-wndr3700-usb-led-driver.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -269,6 +269,13 @@ config LEDS_ADP5520 - To compile this driver as a module, choose M here: the module will - be called leds-adp5520. - -+config LEDS_WNDR3700_USB -+ tristate "NETGEAR WNDR3700 USB LED driver" -+ depends on LEDS_CLASS && AR71XX_MACH_WNDR3700 -+ help -+ This option enables support for the USB LED found on the -+ NETGEAR WNDR3700 board. -+ - comment "LED Triggers" - - config LEDS_TRIGGERS ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -29,6 +29,7 @@ obj-$(CONFIG_LEDS_DA903X) += leds-da903 - obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o - obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o - obj-$(CONFIG_LEDS_PWM) += leds-pwm.o -+obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o - obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o - obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o - obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o diff --git a/target/linux/ar71xx/patches-2.6.34/206-nxp-74hc153-gpio-chip-driver.patch b/target/linux/ar71xx/patches-2.6.34/206-nxp-74hc153-gpio-chip-driver.patch deleted file mode 100644 index 575f7bbd8..000000000 --- a/target/linux/ar71xx/patches-2.6.34/206-nxp-74hc153-gpio-chip-driver.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -255,4 +255,12 @@ config GPIO_UCB1400 - To compile this driver as a module, choose M here: the - module will be called ucb1400_gpio. - -+comment "Other GPIO expanders" -+ -+config GPIO_NXP_74HC153 -+ tristate "NXP 74HC153 Dual 4-input multiplexer" -+ help -+ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This -+ provides a GPIO interface supporting inputs. -+ - endif ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -11,6 +11,7 @@ obj-$(CONFIG_GPIO_MAX7301) += max7301.o - obj-$(CONFIG_GPIO_MAX732X) += max732x.o - obj-$(CONFIG_GPIO_MC33880) += mc33880.o - obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o -+obj-$(CONFIG_GPIO_NXP_74HC153) += nxp_74hc153.o - obj-$(CONFIG_GPIO_PCA953X) += pca953x.o - obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o - obj-$(CONFIG_GPIO_PL061) += pl061.o diff --git a/target/linux/ar71xx/patches-2.6.34/207-rb750-led-driver.patch b/target/linux/ar71xx/patches-2.6.34/207-rb750-led-driver.patch deleted file mode 100644 index 500604fe2..000000000 --- a/target/linux/ar71xx/patches-2.6.34/207-rb750-led-driver.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -276,6 +276,10 @@ config LEDS_WNDR3700_USB - This option enables support for the USB LED found on the - NETGEAR WNDR3700 board. - -+config LEDS_RB750 -+ tristate "LED driver for the Mikrotik RouterBOARD 750" -+ depends on LEDS_CLASS && AR71XX_MACH_RB750 -+ - comment "LED Triggers" - - config LEDS_TRIGGERS ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -34,6 +34,7 @@ obj-$(CONFIG_LEDS_REGULATOR) += leds-re - obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o - obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o - obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o -+obj-$(CONFIG_LEDS_RB750) += leds-rb750.o - - # LED SPI Drivers - obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o diff --git a/target/linux/ar71xx/patches-2.6.34/208-rb750-nand-driver.patch b/target/linux/ar71xx/patches-2.6.34/208-rb750-nand-driver.patch deleted file mode 100644 index 3766a1cd8..000000000 --- a/target/linux/ar71xx/patches-2.6.34/208-rb750-nand-driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -492,4 +492,8 @@ config MTD_NAND_RB4XX - tristate "NAND flash driver for RouterBoard 4xx series" - depends on MTD_NAND && AR71XX_MACH_RB4XX - -+config MTD_NAND_RB750 -+ tristate "NAND flash driver for the RouterBoard 750" -+ depends on MTD_NAND && AR71XX_MACH_RB750 -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -31,6 +31,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx - obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o - obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o -+obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o - obj-$(CONFIG_MTD_ALAUDA) += alauda.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o diff --git a/target/linux/ar71xx/patches-2.6.34/300-mips_fw_myloader.patch b/target/linux/ar71xx/patches-2.6.34/300-mips_fw_myloader.patch deleted file mode 100644 index 0d8f132dd..000000000 --- a/target/linux/ar71xx/patches-2.6.34/300-mips_fw_myloader.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -188,6 +188,7 @@ endif - # - libs-$(CONFIG_ARC) += arch/mips/fw/arc/ - libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ -+libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/ - libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ - libs-y += arch/mips/fw/lib/ - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -877,6 +877,9 @@ config MIPS_NILE4 - config MIPS_DISABLE_OBSOLETE_IDE - bool - -+config MYLOADER -+ bool -+ - config SYNC_R4K - bool - diff --git a/target/linux/ar71xx/patches-2.6.34/400-mips-multi-machine-update.patch b/target/linux/ar71xx/patches-2.6.34/400-mips-multi-machine-update.patch deleted file mode 100644 index d63587901..000000000 --- a/target/linux/ar71xx/patches-2.6.34/400-mips-multi-machine-update.patch +++ /dev/null @@ -1,134 +0,0 @@ ---- a/arch/mips/kernel/mips_machine.c -+++ b/arch/mips/kernel/mips_machine.c -@@ -7,12 +7,13 @@ - * - */ - #include -+#include - - #include --#include - - static struct list_head mips_machines __initdata = - LIST_HEAD_INIT(mips_machines); -+static char *mips_machid __initdata; - - char *mips_machine_name = "Unknown"; - -@@ -55,20 +56,65 @@ void __init mips_machine_set_name(char * - } - } - --void __init mips_machine_setup(unsigned long machtype) -+void __init mips_machine_setup(void) - { - struct mips_machine *mach; - -- mach = mips_machine_find(machtype); -+ mach = mips_machine_find(mips_machtype); - if (!mach) { -- printk(KERN_ALERT "MIPS: no machine registered for " -- "machtype %lu\n", machtype); -+ printk(KERN_WARNING "MIPS: no machine registered for " -+ "machtype %lu\n", mips_machtype); - return; - } - - mips_machine_set_name(mach->mach_name); -- printk(KERN_INFO "MIPS: machine is %s\n", mips_machine_name); -+ printk(KERN_NOTICE "MIPS: machine is %s\n", mips_machine_name); - - if (mach->mach_setup) - mach->mach_setup(); - } -+ -+int __init mips_machtype_setup(char *id) -+{ -+ if (mips_machid == NULL) -+ mips_machid = id; -+ -+ return 1; -+} -+ -+__setup("machtype=", mips_machtype_setup); -+ -+static int __init mips_machtype_init(void) -+{ -+ struct list_head *this; -+ struct mips_machine *mach; -+ -+ if (mips_machid == NULL) -+ return 0; -+ -+ list_for_each(this, &mips_machines) { -+ mach = list_entry(this, struct mips_machine, list); -+ if (mach->mach_id == NULL) -+ continue; -+ -+ if (strcmp(mach->mach_id, mips_machid) == 0) { -+ mips_machtype = mach->mach_type; -+ return 0; -+ } -+ } -+ -+ printk(KERN_WARNING -+ "MIPS: no machine found for id: '%s', registered machines:\n", -+ mips_machid); -+ printk(KERN_WARNING "%32s %s\n", "id", "name"); -+ -+ list_for_each(this, &mips_machines) { -+ mach = list_entry(this, struct mips_machine, list); -+ printk(KERN_WARNING "%32s %s\n", -+ mach->mach_id ? mach->mach_id : "", mach->mach_name); -+ } -+ -+ return 0; -+} -+ -+core_initcall(mips_machtype_init); ---- a/arch/mips/include/asm/mips_machine.h -+++ b/arch/mips/include/asm/mips_machine.h -@@ -13,25 +13,33 @@ - #include - #include - -+#include -+ - struct mips_machine { - unsigned long mach_type; -- void (*mach_setup)(void); -+ char *mach_id; - char *mach_name; -+ void (*mach_setup)(void); - struct list_head list; - }; - - void mips_machine_register(struct mips_machine *) __init; --void mips_machine_setup(unsigned long machtype) __init; -+void mips_machine_setup(void) __init; -+int mips_machtype_setup(char *id) __init; - void mips_machine_set_name(char *name) __init; - - extern char *mips_machine_name; - --#define MIPS_MACHINE(_type, _name, _setup) \ --static char machine_name_##_type[] __initdata = _name; \ -+#define MIPS_MACHINE(_type, _id, _name, _setup) \ -+static const char machine_name_##_type[] __initconst \ -+ __aligned(1) = _name; \ -+static const char machine_id_##_type[] __initconst \ -+ __aligned(1) = _id; \ - static struct mips_machine machine_##_type __initdata = \ - { \ - .mach_type = _type, \ -- .mach_name = machine_name_##_type, \ -+ .mach_id = (char *) machine_id_##_type, \ -+ .mach_name = (char *) machine_name_##_type, \ - .mach_setup = _setup, \ - }; \ - \ -@@ -44,4 +52,3 @@ static int __init register_machine_##_ty - pure_initcall(register_machine_##_type) - - #endif /* __ASM_MIPS_MACHINE_H */ -- diff --git a/target/linux/ar71xx/patches-2.6.34/901-get_c0_compare_irq_function.patch b/target/linux/ar71xx/patches-2.6.34/901-get_c0_compare_irq_function.patch deleted file mode 100644 index c10f4efb1..000000000 --- a/target/linux/ar71xx/patches-2.6.34/901-get_c0_compare_irq_function.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/mips/kernel/traps.c -+++ b/arch/mips/kernel/traps.c -@@ -51,6 +51,7 @@ - #include - #include - #include -+#include - - extern void check_wait(void); - extern asmlinkage void r4k_wait(void); -@@ -1501,6 +1502,8 @@ - if (cpu_has_mips_r2) { - cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; - cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; -+ if (get_c0_compare_irq) -+ cp0_compare_irq = get_c0_compare_irq(); - cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; ---- a/arch/mips/include/asm/time.h -+++ b/arch/mips/include/asm/time.h -@@ -52,6 +52,7 @@ extern int (*perf_irq)(void); - */ - #ifdef CONFIG_CEVT_R4K_LIB - extern unsigned int __weak get_c0_compare_int(void); -+extern unsigned int __weak get_c0_compare_irq(void); - extern int r4k_clockevent_init(void); - #endif - diff --git a/target/linux/ar71xx/profiles/00-default.mk b/target/linux/ar71xx/profiles/00-default.mk index d4044a6f4..aa46f22c5 100644 --- a/target/linux/ar71xx/profiles/00-default.mk +++ b/target/linux/ar71xx/profiles/00-default.mk @@ -6,8 +6,8 @@ # define Profile/Default - NAME:=Default Profile (no WiFi) - PACKAGES:= + NAME:=Default Profile (all drivers) + PACKAGES:=kmod-ath9k kmod-madwifi kmod-usb-core kmod-usb-ohci kmod-usb2 swconfig vsc7385-ucode-ap83 vsc7385-ucode-pb44 vsc7395-ucode-ap83 vsc7395-ucode-pb44 wpad-mini endef define Profile/Default/Description diff --git a/target/linux/ar71xx/profiles/01-minimal.mk b/target/linux/ar71xx/profiles/01-minimal.mk new file mode 100644 index 000000000..3651c88ab --- /dev/null +++ b/target/linux/ar71xx/profiles/01-minimal.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DefaultNoWifi + NAME:=Default Profile (no WiFi) + PACKAGES:= +endef + +define Profile/DefaultNoWifi/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,DefaultNoWifi)) diff --git a/target/linux/ar71xx/profiles/01-madwifi.mk b/target/linux/ar71xx/profiles/02-madwifi.mk similarity index 100% rename from target/linux/ar71xx/profiles/01-madwifi.mk rename to target/linux/ar71xx/profiles/02-madwifi.mk diff --git a/target/linux/ar71xx/profiles/tp-link.mk b/target/linux/ar71xx/profiles/tp-link.mk index ffb3b9e06..7efb1a376 100644 --- a/target/linux/ar71xx/profiles/tp-link.mk +++ b/target/linux/ar71xx/profiles/tp-link.mk @@ -60,6 +60,17 @@ endef $(eval $(call Profile,TLWR941NDV2)) +define Profile/TLWR941NDV3 + NAME:=TP-LINK TL-WR941ND v3 + PACKAGES:=kmod-ath9k wpad-mini +endef + +define Profile/TLWR941NDV3/Description + Package set optimized for the TP-LINK TL-WR941ND v3. +endef + +$(eval $(call Profile,TLWR941NDV3)) + define Profile/TLWR941NDV4 NAME:=TP-LINK TL-WR941ND v4 PACKAGES:=kmod-ath9k wpad-mini diff --git a/target/linux/at91/Makefile b/target/linux/at91/Makefile deleted file mode 100644 index 70a608262..000000000 --- a/target/linux/at91/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=arm -BOARD:=at91 -BOARDNAME:=Atmel AT91 -FEATURES:=squashfs usb broken - -LINUX_VERSION:=2.6.25.20 - -include $(INCLUDE_DIR)/target.mk - -KERNELNAME:="uImage" - -define Target/Description - Build fimware images for Figment Design Labs VersaLink board. -endef - -$(eval $(call BuildTarget)) diff --git a/target/linux/at91/base-files/etc/inittab b/target/linux/at91/base-files/etc/inittab deleted file mode 100644 index a627ce5ff..000000000 --- a/target/linux/at91/base-files/etc/inittab +++ /dev/null @@ -1,6 +0,0 @@ -::sysinit:/etc/init.d/rcS S boot -::shutdown:/etc/init.d/rcS K stop -tts/0::askfirst:/bin/ash --login -ttyS0::askfirst:/bin/ash --login - -ttyS2::respawn:/sbin/getty -L ttyS2 115200 vt100 diff --git a/target/linux/at91/base-files/etc/ipkg.conf b/target/linux/at91/base-files/etc/ipkg.conf deleted file mode 100644 index 10c4f67c6..000000000 --- a/target/linux/at91/base-files/etc/ipkg.conf +++ /dev/null @@ -1,3 +0,0 @@ -src snapshots http://vlink.guthrie.homedns.org/vlink3 -dest root / -dest ram /tmp diff --git a/target/linux/at91/config-2.6.25 b/target/linux/at91/config-2.6.25 deleted file mode 100644 index 593dd42a4..000000000 --- a/target/linux/at91/config-2.6.25 +++ /dev/null @@ -1,212 +0,0 @@ -# CONFIG_AEABI is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_ARCH_AT91CAP9 is not set -# CONFIG_ARCH_AT91RM9200DK is not set -CONFIG_ARCH_AT91RM9200=y -# CONFIG_ARCH_AT91SAM9260 is not set -# CONFIG_ARCH_AT91SAM9261 is not set -# CONFIG_ARCH_AT91SAM9263 is not set -# CONFIG_ARCH_AT91SAM9RL is not set -# CONFIG_ARCH_AT91X40 is not set -CONFIG_ARCH_AT91=y -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_AOUT=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM_AT91_ETHER=y -CONFIG_ARM_THUMB=y -CONFIG_ARM=y -# CONFIG_ARPD is not set -# CONFIG_ARTHUR is not set -CONFIG_AT91_EARLY_DBGU=y -# CONFIG_AT91_EARLY_USART0 is not set -# CONFIG_AT91_EARLY_USART1 is not set -# CONFIG_AT91_EARLY_USART2 is not set -# CONFIG_AT91_EARLY_USART3 is not set -# CONFIG_AT91_EARLY_USART4 is not set -# CONFIG_AT91_EARLY_USART5 is not set -CONFIG_AT91_PMC_UNIT=y -# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set -# CONFIG_AT91_SPIDEV is not set -CONFIG_AT91_SPI=y -CONFIG_AT91_TIMER_HZ=128 -CONFIG_AT91_VLIO=y -# CONFIG_ATMEL_PWM is not set -# CONFIG_ATMEL_SSC is not set -# CONFIG_BINFMT_AOUT is not set -CONFIG_BITREVERSE=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM=y -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_BONDING is not set -CONFIG_BOUNCE=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_CLASSIC_RCU=y -CONFIG_CPU_32v4T=y -CONFIG_CPU_32=y -CONFIG_CPU_ABRT_EV4T=y -CONFIG_CPU_ARM920T=y -CONFIG_CPU_CACHE_V4WT=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_CP15=y -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_TLB_V4WBI=y -# CONFIG_DATAFLASH_ALWAYS_ADD_DEVICE is not set -CONFIG_DAVICOM_PHY=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DM9000 is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_E1000E_ENABLED is not set -# CONFIG_FPE_FASTFPE is not set -# CONFIG_FPE_NWFPE_XP is not set -CONFIG_FPE_NWFPE=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_POSIX_ACL=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_GPIO=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -# CONFIG_HAVE_IDE is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HW_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_HZ=128 -# CONFIG_IEEE80211_CRYPT_CCMP is not set -# CONFIG_IEEE80211_CRYPT_TKIP is not set -# CONFIG_IEEE80211_SOFTMAC is not set -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_LEDS_CPU=y -CONFIG_LEDS=y -CONFIG_LEGACY_PTY_COUNT=32 -CONFIG_LEGACY_PTYS=y -# CONFIG_LLC2 is not set -# CONFIG_LZO_COMPRESS is not set -# CONFIG_LZO_DECOMPRESS is not set -# CONFIG_MACH_AT91RM9200EK is not set -# CONFIG_MACH_ATEB9200 is not set -# CONFIG_MACH_CARMEVA is not set -# CONFIG_MACH_CHUB is not set -# CONFIG_MACH_CSB337 is not set -# CONFIG_MACH_CSB637 is not set -# CONFIG_MACH_ECBAT91 is not set -# CONFIG_MACH_HOMEMATIC is not set -# CONFIG_MACH_KAFA is not set -# CONFIG_MACH_KB9200 is not set -# CONFIG_MACH_ONEARM is not set -# CONFIG_MACH_PICOTUX2XX is not set -# CONFIG_MACH_SWEDATMS is not set -# CONFIG_MACH_TT9200 is not set -CONFIG_MACH_VLINK=y -CONFIG_MTD_AT91_DATAFLASH=y -CONFIG_MTD_AT91_PARTS=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_ROOTFS_ROOT_DEV is not set -# CONFIG_MTD_ROOTFS_SPLIT is not set -# CONFIG_NET_IPGRE_BROADCAST is not set -# CONFIG_NET_PKTGEN is not set -# CONFIG_NF_CONNTRACK_AMANDA is not set -# CONFIG_NF_CONNTRACK_PPTP is not set -# CONFIG_NF_CONNTRACK_RTSP is not set -# CONFIG_NF_CONNTRACK_TFTP is not set -# CONFIG_NF_NAT_AMANDA is not set -# CONFIG_NF_NAT_PPTP is not set -# CONFIG_NF_NAT_RTSP is not set -# CONFIG_NF_NAT_TFTP is not set -# CONFIG_NO_IOPORT is not set -# CONFIG_OUTER_CACHE is not set -# CONFIG_PCI_SYSCALL is not set -CONFIG_PHYLIB=y -# CONFIG_SCSI_WAIT_SCAN is not set -# CONFIG_SDIO_UART is not set -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_ATMEL_CONSOLE=y -CONFIG_SERIAL_ATMEL_PDC=y -# CONFIG_SERIAL_ATMEL_TTYAT is not set -CONFIG_SERIAL_ATMEL=y -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO=y -CONFIG_SLABINFO=y -# CONFIG_SMC91X is not set -# CONFIG_SPI_AT91 is not set -# CONFIG_SPI_ATMEL is not set -CONFIG_SPLIT_PTLOCK_CPUS=4096 -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_UID16=y -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB is not set -CONFIG_USB_LIBUSUAL=y -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_SAFE_PADDED is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SPEEDTOUCH is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_USBAT is not set -CONFIG_USB_SUPPORT=y -# CONFIG_USB_UEAGLEATM is not set -CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VGA_CONSOLE is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_DEV is not set -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_VT=y -# CONFIG_W1 is not set -# CONFIG_WATCHDOG is not set -# CONFIG_WLAN_80211 is not set -# CONFIG_XIP_KERNEL is not set -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 diff --git a/target/linux/at91/files/drivers/mtd/at91part.c b/target/linux/at91/files/drivers/mtd/at91part.c deleted file mode 100644 index d9c55ed32..000000000 --- a/target/linux/at91/files/drivers/mtd/at91part.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * - * Copyright (C) 2007 OpenWrt.org - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Atmel AT91 flash partition table. (Modified by Hamish Guthrie). - * Based on ar7 map by Felix Fietkau. - * - */ - -#include -#include - -#include -#include -#include -#include - -static struct mtd_partition at91_parts[6]; - -static int create_mtd_partitions(struct mtd_info *master, - struct mtd_partition **pparts, - unsigned long origin) -{ - unsigned int offset, len; - unsigned int pre_size = 0x42000, root_max = 0x362400; - unsigned char buf[512]; - struct squashfs_super_block *sb = (struct squashfs_super_block *) buf; - - printk("Parsing AT91 partition map...\n"); - - at91_parts[0].name = "loaders"; - at91_parts[0].offset = 0; - at91_parts[0].size = 0x21000; - at91_parts[0].mask_flags = MTD_WRITEABLE; - - at91_parts[1].name = "ubparams"; - at91_parts[1].offset = 0x21000; - at91_parts[1].size = 0x8400; - at91_parts[1].mask_flags = 0; - - at91_parts[2].name = "kernel"; - at91_parts[2].offset = pre_size; - at91_parts[2].size = 0; - at91_parts[2].mask_flags = 0; - - at91_parts[3].name = "rootfs"; - at91_parts[3].offset = 0; - at91_parts[3].size = 0; - at91_parts[3].mask_flags = 0; - - for(offset = pre_size; offset < root_max; offset += master->erasesize) { - - memset(&buf, 0xe5, sizeof(buf)); - - if (master->read(master, offset, sizeof(buf), &len, buf) || len != sizeof(buf)) - break; - - if (*((__u32 *) buf) == SQUASHFS_MAGIC) { - printk(KERN_INFO "%s: Filesystem type: squashfs, size=0x%x\n", - master->name, (u32) sb->bytes_used); - - at91_parts[3].size = sb->bytes_used; - at91_parts[3].offset = offset; - len = at91_parts[3].offset + at91_parts[3].size; - len = ((len / (master->erasesize * 8)) + 1) * master->erasesize * 8; - at91_parts[3].size = len - at91_parts[3].offset; - at91_parts[2].size = offset - at91_parts[2].offset; - break; - } - } - - if (at91_parts[3].size == 0) { - printk(KERN_NOTICE "%s: Couldn't find root filesystem\n", master->name); - return -1; - } - - at91_parts[4].name = "rootfs_data"; - at91_parts[4].offset = root_max; - at91_parts[4].size = master->size - root_max; - at91_parts[4].mask_flags = 0; - - at91_parts[5].name = "complete"; - at91_parts[5].offset = 0; - at91_parts[5].size = master->size; - at91_parts[5].mask_flags = 0; - - *pparts = at91_parts; - return 6; -} - -static struct mtd_part_parser at91_parser = { - .owner = THIS_MODULE, - .parse_fn = create_mtd_partitions, - .name = "at91part", -}; - -static int __init at91_parser_init(void) -{ - return register_mtd_parser(&at91_parser); -} - -module_init(at91_parser_init); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Felix Fietkau, Eugene Konev, Hamish Guthrie"); -MODULE_DESCRIPTION("MTD partitioning for Atmel at91"); diff --git a/target/linux/at91/image/Config.in b/target/linux/at91/image/Config.in deleted file mode 100644 index b5a06f6bb..000000000 --- a/target/linux/at91/image/Config.in +++ /dev/null @@ -1,35 +0,0 @@ -config AT91_DFBOOT - bool "Build dataflashboot loader" - depends TARGET_at91 - default y - -config AT91_UBOOT - bool "Build U-Boot bootloader" - depends TARGET_at91 - default y - -config UBOOT_TARGET - string "U-Boot target board" - depends TARGET_at91 - depends AT91_UBOOT - default "vlink" - help - For all supported boards there are ready-to-use default - configurations available; just type "". - -config UBOOT_IPADDR - string "IP Address for U-Boot" - depends TARGET_at91 - depends AT91_UBOOT - default "192.168.0.178" - help - IP address of device to be used in U-Boot - -config UBOOT_SERVERIP - string "IP Address of TFTP server" - depends TARGET_at91 - depends AT91_UBOOT - default "192.168.0.232" - help - IP address of TFTP server for U-Boot - diff --git a/target/linux/at91/image/Makefile b/target/linux/at91/image/Makefile deleted file mode 100644 index 2ec0eb998..000000000 --- a/target/linux/at91/image/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright (C) 2006-2010 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -define Build/Clean - $(MAKE) -C dfboot clean - $(MAKE) -C u-boot clean -endef - -define Build/Compile - $(MAKE) -C dfboot compile - $(MAKE) -C u-boot compile - $(KDIR)/u-boot-1.1.4/tools/ubparams - cp params $(KDIR) -endef - -define Image/Prepare - cp $(LINUX_DIR)/arch/arm/boot/uImage $(KDIR)/uImage - cp $(KDIR)/dfboot/dfboot.bin $(KDIR)/dfboot.bin - cp $(KDIR)/dfboot/dfbptest.bin $(KDIR)/dfbptest.bin - cp $(KDIR)/u-boot-1.1.4/u-boot.bin $(KDIR)/u-boot.bin - dd if=$(KDIR)/u-boot.bin of=$(KDIR)/u-boot.block bs=100k count=1 conv=sync - cat $(KDIR)/u-boot.block $(KDIR)/params > $(KDIR)/u-boot.full -endef - -define Image/BuildKernel - cp $(KDIR)/uImage $(BIN_DIR)/$(IMG_PREFIX)-uImage -endef - -define Image/Build - dd if=$(KDIR)/uImage of=$(KDIR)/uImage.block bs=8448 conv=sync - dd if=$(KDIR)/root.squashfs of=$(KDIR)/root.block bs=8448 conv=sync - cat $(KDIR)/uImage.block $(KDIR)/root.block > $(KDIR)/knlroot.bin - $(STAGING_DIR_HOST)/bin/trx -o $(BIN_DIR)/$(IMG_PREFIX).trx -f $(KDIR)/dfboot.bin -f$(KDIR)/u-boot.full -f$(KDIR)/knlroot.bin - cp $(KDIR)/dfbptest.bin $(BIN_DIR) - $(call Image/Build/$(1),$(1)) -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/at91/image/dfboot/Makefile b/target/linux/at91/image/dfboot/Makefile deleted file mode 100644 index 91a603de4..000000000 --- a/target/linux/at91/image/dfboot/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=dfboot -PKG_VERSION:=0.1 -PKG_RELEASE:=1 - -PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME) - -include $(INCLUDE_DIR)/package.mk - -define Build/Prepare - mkdir -p $(PKG_BUILD_DIR) - $(CP) ./src/* $(PKG_BUILD_DIR)/ -endef - -define Build/Compile - $(MAKE) -C $(PKG_BUILD_DIR) \ - $(TARGET_CONFIGURE_OPTS) \ - CFLAGS="$(TARGET_CFLAGS)" \ - LDFLAGS="$(LIBGCC_S)" -endef - -define Build/InstallDev - dd if=$(PKG_BUILD_DIR)/binary/dfboot.bin of=$(PKG_BUILD_DIR)/binary/dfboot.block bs=32k count=1 conv=sync -endef - -$(eval $(call Build/DefaultTargets)) diff --git a/target/linux/at91/image/dfboot/src/Makefile b/target/linux/at91/image/dfboot/src/Makefile deleted file mode 100644 index ff92e0d49..000000000 --- a/target/linux/at91/image/dfboot/src/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -# Makefile for DataFlashBoot.bin -# Must use toolchain with H/W FLoating Point - -BASENAME=dfboot -BINNAME=$(BASENAME).bin -OUTNAME=$(BASENAME).out -LSSNAME=$(BASENAME).lss -MAPNAME=$(BASENAME).map - -BASENAME2=dfbptest -BINNAME2=$(BASENAME2).bin -OUTNAME2=$(BASENAME2).out -LSSNAME2=$(BASENAME2).lss -MAPNAME2=$(BASENAME2).map - -INCPATH=include - -CFLAGS_LOCAL=-Os -Wall -I$(INCPATH) -BUILD=$(CC) $(CFLAGS) $(CFLAGS_LOCAL) - -LDFLAGS+=-T elf32-littlearm.lds -Ttext 0 -LINK=$(LD) $(LDFLAGS) - -OBJS=objs/cstartup_ram.o objs/at45.o objs/com.o objs/dataflash.o\ - objs/div0.o objs/init.o objs/main.o objs/asm_isr.o objs/asm_mci_isr.o\ - objs/mci_device.o objs/jump.o objs/_udivsi3.o objs/_umodsi3.o - -OBJS2=objs/cstartup_ram.o objs/at45.o objs/com.o objs/dataflash.o\ - objs/div0.o objs/init.o objs/ptmain.o objs/asm_isr.o objs/asm_mci_isr.o\ - objs/mci_device.o objs/jump.o objs/_udivsi3.o objs/_umodsi3.o - -I=config.h com.h dataflash.h embedded_services.h main.h stdio.h include/AT91RM9200.h include/lib_AT91RM9200.h - -all:clean $(BASENAME) $(BASENAME2) - -$(BASENAME): $(OBJS) - $(LINK) -n -o $(OUTNAME) $(OBJS) - $(OBJCOPY) $(OUTNAME) -O binary $(BINNAME) - $(OBJDUMP) -h -s $(OUTNAME) > $(LSSNAME) - $(NM) -n $(OUTNAME) | grep -v '\( [aUw] \)\|\(__crc_\)\|\( \$[adt]\)' > $(MAPNAME) - cp $(BINNAME) binary - -$(BASENAME2): $(OBJS2) - $(LINK) -n -o $(OUTNAME2) $(OBJS2) - $(OBJCOPY) $(OUTNAME2) -O binary $(BINNAME2) - $(OBJDUMP) -h -s $(OUTNAME2) > $(LSSNAME2) - $(NM) -n $(OUTNAME2) | grep -v '\( [aUw] \)\|\(__crc_\)\|\( \$[adt]\)' > $(MAPNAME2) - cp $(BINNAME2) binary - -# C objects here -objs/at45.o: at45.c $(I) - $(BUILD) -c -o objs/at45.o at45.c -objs/com.o: com.c $(I) - $(BUILD) -c -o objs/com.o com.c -objs/dataflash.o: dataflash.c $(I) - $(BUILD) -c -o objs/dataflash.o dataflash.c -objs/mci_device.o: mci_device.c $(I) - $(BUILD) -c -o objs/mci_device.o mci_device.c -objs/div0.o: div0.c $(I) - $(BUILD) -c -o objs/div0.o div0.c -objs/init.o: init.c $(I) - $(BUILD) -c -o objs/init.o init.c -objs/main.o: main.c $(I) - $(BUILD) -c -o objs/main.o main.c -objs/ptmain.o: main.c $(I) - $(BUILD) -c -D PRODTEST -o objs/ptmain.o main.c - -# ASM objects here -objs/asm_isr.o: asm_isr.S - $(BUILD) -c -o objs/asm_isr.o asm_isr.S -objs/asm_mci_isr.o: asm_mci_isr.S - $(BUILD) -c -o objs/asm_mci_isr.o asm_mci_isr.S -objs/cstartup_ram.o: cstartup_ram.S - $(BUILD) -c -o objs/cstartup_ram.o cstartup_ram.S -objs/jump.o: jump.S - $(BUILD) -c -o objs/jump.o jump.S -objs/_udivsi3.o: _udivsi3.S - $(BUILD) -c -o objs/_udivsi3.o _udivsi3.S -objs/_umodsi3.o: _umodsi3.S - $(BUILD) -c -o objs/_umodsi3.o _umodsi3.S - -install: $(BINNAME) $(BINNAME2) - cp $(BINNAME) binary - cp $(BINNAME2) binary - -clean: - rm -f *~ - rm -f objs/* - rm -f *.out - rm -f *.bin - rm -f *.lss - rm -f *.map - rm -f .unpacked - mkdir -p objs diff --git a/target/linux/at91/image/dfboot/src/_udivsi3.S b/target/linux/at91/image/dfboot/src/_udivsi3.S deleted file mode 100644 index 2cdcd48b4..000000000 --- a/target/linux/at91/image/dfboot/src/_udivsi3.S +++ /dev/null @@ -1,77 +0,0 @@ -/* # 1 "libgcc1.S" */ -@ libgcc1 routines for ARM cpu. -@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) -dividend .req r0 -divisor .req r1 -result .req r2 -curbit .req r3 -/* ip .req r12 */ -/* sp .req r13 */ -/* lr .req r14 */ -/* pc .req r15 */ - .text - .globl __udivsi3 - .type __udivsi3 ,function - .align 0 - __udivsi3 : - cmp divisor, #0 - beq Ldiv0 - mov curbit, #1 - mov result, #0 - cmp dividend, divisor - bcc Lgot_result -Loop1: - @ Unless the divisor is very big, shift it up in multiples of - @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is - @ larger than the dividend. - cmp divisor, #0x10000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #4 - movcc curbit, curbit, lsl #4 - bcc Loop1 -Lbignum: - @ For very big divisors, we must shift it a bit at a time, or - @ we will be in danger of overflowing. - cmp divisor, #0x80000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #1 - movcc curbit, curbit, lsl #1 - bcc Lbignum -Loop3: - @ Test for possible subtractions, and note which bits - @ are done in the result. On the final pass, this may subtract - @ too much from the dividend, but the result will be ok, since the - @ "bit" will have been shifted out at the bottom. - cmp dividend, divisor - subcs dividend, dividend, divisor - orrcs result, result, curbit - cmp dividend, divisor, lsr #1 - subcs dividend, dividend, divisor, lsr #1 - orrcs result, result, curbit, lsr #1 - cmp dividend, divisor, lsr #2 - subcs dividend, dividend, divisor, lsr #2 - orrcs result, result, curbit, lsr #2 - cmp dividend, divisor, lsr #3 - subcs dividend, dividend, divisor, lsr #3 - orrcs result, result, curbit, lsr #3 - cmp dividend, #0 @ Early termination? - movnes curbit, curbit, lsr #4 @ No, any more bits to do? - movne divisor, divisor, lsr #4 - bne Loop3 -Lgot_result: - mov r0, result - mov pc, lr -Ldiv0: - str lr, [sp, #-4]! - bl __div0 (PLT) - mov r0, #0 @ about as wrong as it could be - ldmia sp!, {pc} - .size __udivsi3 , . - __udivsi3 -/* # 235 "libgcc1.S" */ -/* # 320 "libgcc1.S" */ -/* # 421 "libgcc1.S" */ -/* # 433 "libgcc1.S" */ -/* # 456 "libgcc1.S" */ -/* # 500 "libgcc1.S" */ -/* # 580 "libgcc1.S" */ diff --git a/target/linux/at91/image/dfboot/src/_umodsi3.S b/target/linux/at91/image/dfboot/src/_umodsi3.S deleted file mode 100644 index e4aebe84c..000000000 --- a/target/linux/at91/image/dfboot/src/_umodsi3.S +++ /dev/null @@ -1,88 +0,0 @@ -/* # 1 "libgcc1.S" */ -@ libgcc1 routines for ARM cpu. -@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) -/* # 145 "libgcc1.S" */ -dividend .req r0 -divisor .req r1 -overdone .req r2 -curbit .req r3 -/* ip .req r12 */ -/* sp .req r13 */ -/* lr .req r14 */ -/* pc .req r15 */ - .text - .globl __umodsi3 - .type __umodsi3 ,function - .align 0 - __umodsi3 : - cmp divisor, #0 - beq Ldiv0 - mov curbit, #1 - cmp dividend, divisor - movcc pc, lr -Loop1: - @ Unless the divisor is very big, shift it up in multiples of - @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is - @ larger than the dividend. - cmp divisor, #0x10000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #4 - movcc curbit, curbit, lsl #4 - bcc Loop1 -Lbignum: - @ For very big divisors, we must shift it a bit at a time, or - @ we will be in danger of overflowing. - cmp divisor, #0x80000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #1 - movcc curbit, curbit, lsl #1 - bcc Lbignum -Loop3: - @ Test for possible subtractions. On the final pass, this may - @ subtract too much from the dividend, so keep track of which - @ subtractions are done, we can fix them up afterwards... - mov overdone, #0 - cmp dividend, divisor - subcs dividend, dividend, divisor - cmp dividend, divisor, lsr #1 - subcs dividend, dividend, divisor, lsr #1 - orrcs overdone, overdone, curbit, ror #1 - cmp dividend, divisor, lsr #2 - subcs dividend, dividend, divisor, lsr #2 - orrcs overdone, overdone, curbit, ror #2 - cmp dividend, divisor, lsr #3 - subcs dividend, dividend, divisor, lsr #3 - orrcs overdone, overdone, curbit, ror #3 - mov ip, curbit - cmp dividend, #0 @ Early termination? - movnes curbit, curbit, lsr #4 @ No, any more bits to do? - movne divisor, divisor, lsr #4 - bne Loop3 - @ Any subtractions that we should not have done will be recorded in - @ the top three bits of "overdone". Exactly which were not needed - @ are governed by the position of the bit, stored in ip. - @ If we terminated early, because dividend became zero, - @ then none of the below will match, since the bit in ip will not be - @ in the bottom nibble. - ands overdone, overdone, #0xe0000000 - moveq pc, lr @ No fixups needed - tst overdone, ip, ror #3 - addne dividend, dividend, divisor, lsr #3 - tst overdone, ip, ror #2 - addne dividend, dividend, divisor, lsr #2 - tst overdone, ip, ror #1 - addne dividend, dividend, divisor, lsr #1 - mov pc, lr -Ldiv0: - str lr, [sp, #-4]! - bl __div0 (PLT) - mov r0, #0 @ about as wrong as it could be - ldmia sp!, {pc} - .size __umodsi3 , . - __umodsi3 -/* # 320 "libgcc1.S" */ -/* # 421 "libgcc1.S" */ -/* # 433 "libgcc1.S" */ -/* # 456 "libgcc1.S" */ -/* # 500 "libgcc1.S" */ -/* # 580 "libgcc1.S" */ diff --git a/target/linux/at91/image/dfboot/src/asm_isr.S b/target/linux/at91/image/dfboot/src/asm_isr.S deleted file mode 100644 index 8d1d52e19..000000000 --- a/target/linux/at91/image/dfboot/src/asm_isr.S +++ /dev/null @@ -1,75 +0,0 @@ -#include "AT91RM9200_inc.h" - -#define ARM_MODE_USER 0x10 -#define ARM_MODE_FIQ 0x11 -#define ARM_MODE_IRQ 0x12 -#define ARM_MODE_SVC 0x13 -#define ARM_MODE_ABORT 0x17 -#define ARM_MODE_UNDEF 0x1B -#define ARM_MODE_SYS 0x1F - -#define I_BIT 0x80 -#define F_BIT 0x40 -#define T_BIT 0x20 - - -/* ----------------------------------------------------------------------------- - AT91F_ASM_SPI_Handler - --------------------- - Handler called by the AIC - - Save context - Call C handler - Restore context - ----------------------------------------------------------------------------- */ - -.global AT91F_ST_ASM_HANDLER - -AT91F_ST_ASM_HANDLER: -/* Adjust and save LR_irq in IRQ stack */ - sub r14, r14, #4 - stmfd sp!, {r14} - -/* Write in the IVR to support Protect Mode - No effect in Normal Mode - De-assert the NIRQ and clear the source in Protect Mode */ - ldr r14, =AT91C_BASE_AIC - str r14, [r14, #AIC_IVR] - -/* Save SPSR and r0 in IRQ stack */ - mrs r14, SPSR - stmfd sp!, {r0, r14} - -/* Enable Interrupt and Switch in SYS Mode */ - mrs r0, CPSR - bic r0, r0, #I_BIT - orr r0, r0, #ARM_MODE_SYS - msr CPSR_c, r0 - -/* Save scratch/used registers and LR in User Stack */ - stmfd sp!, { r1-r3, r12, r14} - - ldr r1, =AT91F_ST_HANDLER - mov r14, pc - bx r1 - -/* Restore scratch/used registers and LR from User Stack */ - ldmia sp!, { r1-r3, r12, r14} - -/* Disable Interrupt and switch back in IRQ mode */ - mrs r0, CPSR - bic r0, r0, #ARM_MODE_SYS - orr r0, r0, #I_BIT | ARM_MODE_IRQ - msr CPSR_c, r0 - -/* Mark the End of Interrupt on the AIC */ - ldr r0, =AT91C_BASE_AIC - str r0, [r0, #AIC_EOICR] - -/* Restore SPSR_irq and r0 from IRQ stack */ - ldmia sp!, {r0, r14} - msr SPSR_cxsf, r14 - -/* Restore adjusted LR_irq from IRQ stack directly in the PC */ - ldmia sp!, {pc}^ - diff --git a/target/linux/at91/image/dfboot/src/asm_mci_isr.S b/target/linux/at91/image/dfboot/src/asm_mci_isr.S deleted file mode 100644 index 0f66fc0d6..000000000 --- a/target/linux/at91/image/dfboot/src/asm_mci_isr.S +++ /dev/null @@ -1,75 +0,0 @@ -#include - -#define ARM_MODE_USER 0x10 -#define ARM_MODE_FIQ 0x11 -#define ARM_MODE_IRQ 0x12 -#define ARM_MODE_SVC 0x13 -#define ARM_MODE_ABORT 0x17 -#define ARM_MODE_UNDEF 0x1B -#define ARM_MODE_SYS 0x1F - -#define I_BIT 0x80 -#define F_BIT 0x40 -#define T_BIT 0x20 - - -/* ----------------------------------------------------------------------------- - AT91F_ASM_MCI_Handler - --------------------- - Handler called by the AIC - - Save context - Call C handler - Restore context - ----------------------------------------------------------------------------- */ - -.global AT91F_ASM_MCI_Handler - -AT91F_ASM_MCI_Handler: -/* Adjust and save LR_irq in IRQ stack */ - sub r14, r14, #4 - stmfd sp!, {r14} - -/* Write in the IVR to support Protect Mode - No effect in Normal Mode - De-assert the NIRQ and clear the source in Protect Mode */ - ldr r14, =AT91C_BASE_AIC - str r14, [r14, #AIC_IVR] - -/* Save SPSR and r0 in IRQ stack */ - mrs r14, SPSR - stmfd sp!, {r0, r14} - -/* Enable Interrupt and Switch in SYS Mode */ - mrs r0, CPSR - bic r0, r0, #I_BIT - orr r0, r0, #ARM_MODE_SYS - msr CPSR_c, r0 - -/* Save scratch/used registers and LR in User Stack */ - stmfd sp!, { r1-r3, r12, r14} - - ldr r1, =AT91F_MCI_Handler - mov r14, pc - bx r1 - -/* Restore scratch/used registers and LR from User Stack */ - ldmia sp!, { r1-r3, r12, r14} - -/* Disable Interrupt and switch back in IRQ mode */ - mrs r0, CPSR - bic r0, r0, #ARM_MODE_SYS - orr r0, r0, #I_BIT | ARM_MODE_IRQ - msr CPSR_c, r0 - -/* Mark the End of Interrupt on the AIC */ - ldr r0, =AT91C_BASE_AIC - str r0, [r0, #AIC_EOICR] - -/* Restore SPSR_irq and r0 from IRQ stack */ - ldmia sp!, {r0, r14} - msr SPSR_cxsf, r14 - -/* Restore adjusted LR_irq from IRQ stack directly in the PC */ - ldmia sp!, {pc}^ - diff --git a/target/linux/at91/image/dfboot/src/at45.c b/target/linux/at91/image/dfboot/src/at45.c deleted file mode 100644 index 8830d7e9b..000000000 --- a/target/linux/at91/image/dfboot/src/at45.c +++ /dev/null @@ -1,595 +0,0 @@ -/*---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - *---------------------------------------------------------------------------- - * The software is delivered "AS IS" without warranty or condition of any - * kind, either express, implied or statutory. This includes without - * limitation any warranty or condition with respect to merchantability or - * fitness for any particular purpose, or against the infringements of - * intellectual property rights of others. - *---------------------------------------------------------------------------- - * File Name : at45c.h - * Object : - * - * 1.0 10/12/03 HIi : Creation. - * 1.01 03/05/04 HIi : Bug Fix in AT91F_DataFlashWaitReady() Function. - *---------------------------------------------------------------------------- - */ -#include "config.h" -#include "stdio.h" -#include "AT91RM9200.h" -#include "lib_AT91RM9200.h" -#include "dataflash.h" -#include "main.h" - - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiInit */ -/* \brief SPI Low level Init */ -/*----------------------------------------------------------------------------*/ -void AT91F_SpiInit(void) { - /* Configure PIOs */ - AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | - AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | - AT91C_PA2_SPCK; - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | - AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | - AT91C_PA2_SPCK; - /* Enable CLock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; - - /* Reset the SPI */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 and CS3 */ - *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); -} - - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiEnable */ -/* \brief Enable SPI chip select */ -/*----------------------------------------------------------------------------*/ -static void AT91F_SpiEnable(int cs) { - switch(cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH << 16) & AT91C_SPI_PCS); - break; - case 3: /* Configure SPI CS3 for Serial DataFlash Card */ - /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ - AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; - /* Configure PCS */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; -} - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiWrite */ -/* \brief Set the PDC registers for a transfert */ -/*----------------------------------------------------------------------------*/ -static unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) -{ - unsigned int timeout; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; - AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; - - if ( pDesc->tx_data_size != 0 ) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; - AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; - AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; - } - - /* ARM simple, non interrupt dependent timer */ - timeout = 0; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF)); - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - if (timeout >= AT91C_DATAFLASH_TIMEOUT){ - return AT91C_DATAFLASH_ERROR; - } - - return AT91C_DATAFLASH_OK; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashSendCommand */ -/* \brief Generic function to send a command to the dataflash */ -/*----------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress) -{ - unsigned int adr; - - /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) - << pDataFlash->pDevice->page_offset) + - (DataflashAddress % (pDataFlash->pDevice->pages_size)); - - /* fill the command buffer */ - pDataFlash->pDataFlashDesc->command[0] = OpCode; - if (pDataFlash->pDevice->pages_number >= 16384) - { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); - } - else - { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - } - pDataFlash->pDataFlashDesc->command[5] = 0; - pDataFlash->pDataFlashDesc->command[6] = 0; - pDataFlash->pDataFlashDesc->command[7] = 0; - - /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; - - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashGetStatus */ -/* \brief Read the status register of the dataflash */ -/*----------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) -{ - AT91S_DataFlashStatus status; - - /* first send the read status command (D7H) */ - pDesc->command[0] = DB_STATUS; - pDesc->command[1] = 0; - - pDesc->DataFlash_state = GET_STATUS; - pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ - pDesc->tx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_size = 2 ; - pDesc->tx_cmd_size = 2 ; - status = AT91F_SpiWrite (pDesc); - - pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); - return status; -} - -/*----------------------------------------------------------------------------- - * Function Name : AT91F_DataFlashWaitReady - * Object : wait for dataflash ready (bit7 of the status register == 1) - * Input Parameters : DataFlash Service and timeout - * Return value : DataFlash status "ready or not" - *----------------------------------------------------------------------------- - */ -static AT91S_DataFlashStatus AT91F_DataFlashWaitReady( - AT91PS_DataflashDesc pDataFlashDesc, - unsigned int timeout) -{ - pDataFlashDesc->DataFlash_state = IDLE; - do { - AT91F_DataFlashGetStatus(pDataFlashDesc); - timeout--; - } - while(((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0)); - - if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) - return AT91C_DATAFLASH_ERROR; - - return AT91C_DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashContinuousRead */ -/* Object : Continuous stream Read */ -/* Input Parameters : DataFlash Service */ -/* : = dataflash address */ -/* : <*dataBuffer> = data buffer pointer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_DataFlashContinuousRead( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ) -{ - AT91S_DataFlashStatus status; - /* Test the size to read in the device */ - if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return AT91C_DATAFLASH_MEMORY_OVERFLOW; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - - status = AT91F_DataFlashSendCommand(pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); - /* Send the command to the dataflash */ - return(status); -} - - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_MainMemoryToBufferTransfer */ -/* Object : Read a page in the SRAM Buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfer( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) - return AT91C_DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, cmdsize, - page*pDataFlash->pDevice->pages_size)); -} - - - -/*----------------------------------------------------------------------------- */ -/* Function Name : AT91F_DataFlashWriteBuffer */ -/* Object : Write data to the internal sram buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : = command to write buffer1 or buffer2 */ -/* : <*dataBuffer> = data buffer to write */ -/* : = address in the internal buffer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) - return AT91C_DATAFLASH_BAD_COMMAND; - - /* buffer address must be lower than page size */ - if (bufferAddress > pDataFlash->pDevice->pages_size) - return AT91C_DATAFLASH_BAD_ADDRESS; - - /* Send first Write Command */ - pDataFlash->pDataFlashDesc->command[0] = BufferCommand; - pDataFlash->pDataFlashDesc->command[1] = 0; - if (pDataFlash->pDevice->pages_number >= 16384) - { - pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - cmdsize = 5; - } - else - { - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - cmdsize = 4; - } - - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PageErase */ -/* Object : Read a page in the SRAM Buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand(pDataFlash, DB_PAGE_ERASE, cmdsize, - page*pDataFlash->pDevice->pages_size)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_WriteBufferToMain */ -/* Object : Write buffer to the main memory */ -/* Input Parameters : DataFlash Service */ -/* : = command to send to buf1 or buf2 */ -/* : = main memory address */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ) -{ - int cmdsize; - /* Test if the buffer command is correct */ - if ((BufferCommand != DB_BUF1_PAGE_PGM) && - (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && - (BufferCommand != DB_BUF2_PAGE_PGM) && - (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) - return AT91C_DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - /* Send the command to the dataflash */ - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PartialPageWrite */ -/* Object : Erase partially a page */ -/* Input Parameters : = page number */ -/* : = adr to begin the fading */ -/* : = Number of bytes to erase */ -/*------------------------------------------------------------------------------*/ -static AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size) -{ - unsigned int page; - unsigned int AdrInPage; - - page = dest / (pDataFlash->pDevice->pages_size); - AdrInPage = dest % (pDataFlash->pDevice->pages_size); - - /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfer(pDataFlash, DB_PAGE_2_BUF1_TRF, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - - /*Update the SRAM buffer */ - AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - - /* Erase page if a 128 Mbits device */ - if (pDataFlash->pDevice->pages_number >= 16384) - { - AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - } - - /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, - (page*pDataFlash->pDevice->pages_size))); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashWrite */ -/* Object : */ -/* Input Parameters : <*src> = Source buffer */ -/* : = dataflash adress */ -/* : = data buffer size */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ) -{ - unsigned int length; - unsigned int page; - unsigned int status; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return AT91C_DATAFLASH_MEMORY_OVERFLOW; - - /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { - length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); - - if (size < length) - length = size; - - if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) - return AT91C_DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - - /* Update size, source and destination pointers */ - size -= length; - dest += length; - src += length; - } - - while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) - { - /* program dataflash page */ - page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); - - status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, - 0, pDataFlash->pDevice->pages_size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - - status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - if (!status) - return AT91C_DATAFLASH_ERROR; - - status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); - if(!status) - return AT91C_DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - - /* Update size, source and destination pointers */ - size -= pDataFlash->pDevice->pages_size ; - dest += pDataFlash->pDevice->pages_size ; - src += pDataFlash->pDevice->pages_size ; - } - - /* If still some bytes to read */ - if ( size > 0 ) { - /* program dataflash page */ - if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) - return AT91C_DATAFLASH_ERROR; - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - } - return AT91C_DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashRead */ -/* Object : Read a block in dataflash */ -/* Input Parameters : */ -/* Return value : */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer) -{ - unsigned long SizeToRead; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT) != AT91C_DATAFLASH_OK) - return -1; - - while (size) - { - SizeToRead = (size < 0x8000)? size:0x8000; - - if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT) - != AT91C_DATAFLASH_OK) - return -1; - - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (unsigned char *)buffer, - SizeToRead) != AT91C_DATAFLASH_OK) - return -1; - - size -= SizeToRead; - addr += SizeToRead; - buffer += SizeToRead; - } - - return AT91C_DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataflashProbe */ -/* Object : */ -/* Input Parameters : */ -/* Return value : Dataflash status register */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) -{ - AT91F_SpiEnable(cs); - AT91F_DataFlashGetStatus(pDesc); - return ((pDesc->command[1] == 0xFF)? 0: (pDesc->command[1] & 0x3C)); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashErase */ -/* Object : */ -/* Input Parameters : <*pDataFlash> = Device info */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash) -{ - unsigned int page; - unsigned int status; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - for(page=0; page < pDataFlash->pDevice->pages_number; page++) - { - /* Erase dataflash page */ - if ((page & 0x00FF) == 0) - printf("\rERA %d/%d", page, pDataFlash->pDevice->pages_number); - status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - if (!status) - return AT91C_DATAFLASH_ERROR; - } - - return AT91C_DATAFLASH_OK; -} - diff --git a/target/linux/at91/image/dfboot/src/com.c b/target/linux/at91/image/dfboot/src/com.c deleted file mode 100644 index aacfb5555..000000000 --- a/target/linux/at91/image/dfboot/src/com.c +++ /dev/null @@ -1,368 +0,0 @@ -/*---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - *---------------------------------------------------------------------------- - * The software is delivered "AS IS" without warranty or condition of any - * kind, either express, implied or statutory. This includes without - * limitation any warranty or condition with respect to merchantability or - * fitness for any particular purpose, or against the infringements of - * intellectual property rights of others. - *---------------------------------------------------------------------------- - * File Name : com.c - * Object : - * Creation : HIi 03/27/2003 - * - *---------------------------------------------------------------------------- - */ -#include "AT91RM9200.h" -#include "lib_AT91RM9200.h" -#include "config.h" -#include "com.h" -#include "stdio.h" - -static char erase_seq[] = "\b \b"; /* erase sequence */ - -#define MAX_UARTS 1 - -//unsigned int usa[2] = {(unsigned int)AT91C_BASE_DBGU, (unsigned int)AT91C_ALTERNATE_USART}; -unsigned int usa[1] = {(unsigned int)AT91C_BASE_DBGU}; -unsigned int us; -int port_detected; - -void at91_init_uarts(void) -{ - int i; - - port_detected = 0; - AT91F_DBGU_CfgPIO(); - AT91F_US0_CfgPIO(); - AT91F_US0_CfgPMC(); - - for(i=0; i 16) - return 0; - c = (type & ZEROPAD) ? '0' : ' '; - sign = 0; - - if(type & SIGN && num < 0) - { - sign = '-'; - num = -num; - size--; - } - - i = 0; - if(num == 0) - tmp[i++] = digits[0]; - else while(num != 0) - tmp[i++] = digits[do_div(num, base)]; - - if(i > precision) - precision = i; - size -= precision; - - if(!(type&(ZEROPAD+LEFT))) - while(size-->0) - putc(' '); - - if(sign) - putc(sign); - - if (!(type & LEFT)) - while (size-- > 0) - putc(c); - - while (i < precision--) - putc('0'); - - while (i-- > 0) - putc(tmp[i]); - - while (size-- > 0) - putc(' ');; - - return 1; -} - -int hvfprintf(const char *fmt, va_list va) -{ - char *s; - - do { - if(*fmt == '%') { - bool done = false; - - int type = 0; - int precision = 0; - - do { - fmt++; - switch(*fmt) { - case '0' : - if(!precision) - type |= ZEROPAD; - case '1' : - case '2' : - case '3' : - case '4' : - case '5' : - case '6' : - case '7' : - case '8' : - case '9' : - precision = precision * 10 + (*fmt - '0'); - break; - case '.' : - break; - case 's' : - s = va_arg(va, char *); - if(!s) - puts(""); - else - puts(s); - done = true; - break; - case 'c' : - putc(va_arg(va, int)); - done = true; - break; - case 'd' : - number(va_arg(va, int), 10, 0, precision, type); - done = true; - break; - case 'x' : - case 'X' : - number(va_arg(va, int), 16, 0, precision, type); - done = true; - break; - case '%' : - putc(*fmt); - done = true; - default: - putc('%'); - putc(*fmt); - done = true; - break; - } - } while(!done); - } else if(*fmt == '\\') { - fmt++; - if(*fmt == 'r') { - putc('\r'); - } else if(*fmt == 'n') { - putc('\n'); - } - } else { - putc(*fmt); - } - fmt++; - } while(*fmt != 0); - - return 0; -} - -int printf(const char *fmt, ...) -{ - va_list ap; - int i; - - va_start(ap, fmt); - i = hvfprintf(fmt, ap); - va_end(ap); - - return i; -} diff --git a/target/linux/at91/image/dfboot/src/com.h b/target/linux/at91/image/dfboot/src/com.h deleted file mode 100644 index 7af09e4d6..000000000 --- a/target/linux/at91/image/dfboot/src/com.h +++ /dev/null @@ -1,28 +0,0 @@ -/*---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - *---------------------------------------------------------------------------- - * The software is delivered "AS IS" without warranty or condition of any - * kind, either express, implied or statutory. This includes without - * limitation any warranty or condition with respect to merchantability or - * fitness for any particular purpose, or against the infringements of - * intellectual property rights of others. - *---------------------------------------------------------------------------- - * File Name : com.h - * Object : - * - * 1.0 27/03/03 HIi : Creation - *---------------------------------------------------------------------------- - */ -#ifndef com_h -#define com_h - -#define AT91C_CB_SIZE 20 /* size of the console buffer */ - -/* Escape sequences */ -#define ESC \033 - -extern int AT91F_ReadLine (const char *const prompt, char *console_buffer); -extern void AT91F_WaitKeyPressed(void); - -#endif - diff --git a/target/linux/at91/image/dfboot/src/config.h b/target/linux/at91/image/dfboot/src/config.h deleted file mode 100644 index 3be8d499a..000000000 --- a/target/linux/at91/image/dfboot/src/config.h +++ /dev/null @@ -1,17 +0,0 @@ - -#ifndef _CONFIG_H -#define _CONFIG_H - -//#define PAGESZ_1056 1 -#undef PAGESZ_1056 -#define SPI_LOW_SPEED 1 -#define AT91C_DELAY_TO_BOOT 1500 - -#define CRC_RETRIES 0x100 - -#define AT91C_MASTER_CLOCK 59904000 -#define AT91C_BAUD_RATE 115200 - -#define AT91C_ALTERNATE_USART AT91C_BASE_US0 - -#endif diff --git a/target/linux/at91/image/dfboot/src/cstartup_ram.S b/target/linux/at91/image/dfboot/src/cstartup_ram.S deleted file mode 100644 index 223900098..000000000 --- a/target/linux/at91/image/dfboot/src/cstartup_ram.S +++ /dev/null @@ -1,144 +0,0 @@ -#include "AT91RM9200_inc.h" - -/*--------------------------- -ARM Core Mode and Status Bits ----------------------------*/ -.section start - .text - -#define ARM_MODE_USER 0x10 -#define ARM_MODE_FIQ 0x11 -#define ARM_MODE_IRQ 0x12 -#define ARM_MODE_SVC 0x13 -#define ARM_MODE_ABORT 0x17 -#define ARM_MODE_UNDEF 0x1B -#define ARM_MODE_SYS 0x1F - -#define I_BIT 0x80 -#define F_BIT 0x40 -#define T_BIT 0x20 - -/*---------------------------------------------------------------------------- - Area Definition ----------------- - Must be defined as function to put first in the code as it must be mapped - at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap. -_---------------------------------------------------------------------------*/ - - .align 4 - .globl _start -_start: - -/*---------------------------------------------------------------------------- - Exception vectors ( before Remap ) ------------------------------------- - These vectors are read at address 0. - They absolutely requires to be in relative addresssing mode in order to - guarantee a valid jump. For the moment, all are just looping (what may be - dangerous in a final system). If an exception occurs before remap, this - would result in an infinite loop. -----------------------------------------------------------------------------*/ - b reset /* reset */ - b undefvec /* Undefined Instruction */ - b swivec /* Software Interrupt */ - b pabtvec /* Prefetch Abort */ - b dabtvec /* Data Abort */ - b rsvdvec /* reserved */ - b aicvec /* IRQ : read the AIC */ - b fiqvec /* FIQ */ - -undefvec: -swivec: -pabtvec: -dabtvec: -rsvdvec: -aicvec: -fiqvec: - b undefvec - -reset: - -#define MEMEND 0x00004000 - -/* ---------------------------- - Setup the stack for each mode ----------------------------- */ - -#define IRQ_STACK_SIZE 0x10 -#define FIQ_STACK_SIZE 0x04 -#define ABT_STACK_SIZE 0x04 -#define UND_STACK_SIZE 0x04 -#define SVC_STACK_SIZE 0x10 -#define USER_STACK_SIZE 0x400 - - ldr r0,= MEMEND - -/*- Set up Supervisor Mode and set Supervisor Mode Stack*/ - msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT - mov r13, r0 /* Init stack Undef*/ - sub r0, r0, #SVC_STACK_SIZE - -/*- Set up Interrupt Mode and set IRQ Mode Stack*/ - msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT - mov r13, r0 /* Init stack IRQ*/ - sub r0, r0, #IRQ_STACK_SIZE - -/*- Set up Fast Interrupt Mode and set FIQ Mode Stack*/ - msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT - mov r13, r0 /* Init stack FIQ*/ - sub r0, r0, #FIQ_STACK_SIZE - -/*- Set up Abort Mode and set Abort Mode Stack*/ - msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT - mov r13, r0 /* Init stack Abort*/ - sub r0, r0, #ABT_STACK_SIZE - -/*- Set up Undefined Instruction Mode and set Undef Mode Stack*/ - msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT - mov r13, r0 /* Init stack Undef*/ - sub r0, r0, #UND_STACK_SIZE - -/*- Set up user Mode and set System Mode Stack*/ - msr CPSR_c, #ARM_MODE_SYS | I_BIT | F_BIT - bic r0, r0, #3 /* Insure word alignement */ - mov sp, r0 /* Init stack System */ - - - ldr r0, = AT91F_LowLevelInit - mov lr, pc - bx r0 - -/*---------------------------------------- - Read/modify/write CP15 control register -----------------------------------------*/ - mrc p15, 0, r0, c1, c0,0 /* read cp15 control registre (cp15 r1) in r0 */ - ldr r3,= 0xC0000080 /* Reset bit :Little Endian end fast bus mode */ - ldr r4,= 0xC0001000 /* Set bit :Asynchronous clock mode, Not Fast Bus, I-Cache enable */ - bic r0, r0, r3 - orr r0, r0, r4 - mcr p15, 0, r0, c1, c0,0 /* write r0 in cp15 control registre (cp15 r1) */ - -/* Enable interrupts */ - msr CPSR_c, #ARM_MODE_SYS | F_BIT - -/*------------------------------------------------------------------------------ -- Branch on C code Main function (with interworking) ----------------------------------------------------- -- Branch must be performed by an interworking call as either an ARM or Thumb -- _start function must be supported. This makes the code not position- -- independent. A Branch with link would generate errors -----------------------------------------------------------------------------*/ - -/*- Branch to _start by interworking*/ - ldr r4, = main - mov lr, pc - bx r4 - -/*----------------------------------------------------------------------------- -- Loop for ever ---------------- -- End of application. Normally, never occur. -- Could jump on Software Reset ( B 0x0 ). -------------------------------------------------------------------------------*/ -End: - b End diff --git a/target/linux/at91/image/dfboot/src/dataflash.c b/target/linux/at91/image/dfboot/src/dataflash.c deleted file mode 100644 index 5e54460b7..000000000 --- a/target/linux/at91/image/dfboot/src/dataflash.c +++ /dev/null @@ -1,208 +0,0 @@ -/*---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - *---------------------------------------------------------------------------- - * The software is delivered "AS IS" without warranty or condition of any - * kind, either express, implied or statutory. This includes without - * limitation any warranty or condition with respect to merchantability or - * fitness for any particular purpose, or against the infringements of - * intellectual property rights of others. - *---------------------------------------------------------------------------- - * File Name : dataflash.c - * Object : High level functions for the dataflash - * Creation : HIi 10/10/2003 - *---------------------------------------------------------------------------- - */ -#include "config.h" -#include "stdio.h" -#include "dataflash.h" - - -AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; -static AT91S_DataFlash DataFlashInst; - -int cs[][CFG_MAX_DATAFLASH_BANKS] = { - {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ - {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} -}; - -int AT91F_DataflashInit(void) -{ - int i; - int dfcode; - int Nb_device = 0; - - AT91F_SpiInit(); - - for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { - dataflash_info[i].id = 0; - dataflash_info[i].Device.pages_number = 0; - dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc); - - switch (dfcode) { - case AT45DB161: - dataflash_info[i].Device.pages_number = 4096; - dataflash_info[i].Device.pages_size = 528; - dataflash_info[i].Device.page_offset = 10; - dataflash_info[i].Device.byte_mask = 0x300; - dataflash_info[i].Device.cs = cs[i][1]; - dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; - dataflash_info[i].id = dfcode; - Nb_device++; - break; - - case AT45DB321: - dataflash_info[i].Device.pages_number = 8192; - dataflash_info[i].Device.pages_size = 528; - dataflash_info[i].Device.page_offset = 10; - dataflash_info[i].Device.byte_mask = 0x300; - dataflash_info[i].Device.cs = cs[i][1]; - dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; - dataflash_info[i].id = dfcode; - Nb_device++; - break; - - case AT45DB642: - dataflash_info[i].Device.pages_number = 8192; - dataflash_info[i].Device.pages_size = 1056; - dataflash_info[i].Device.page_offset = 11; - dataflash_info[i].Device.byte_mask = 0x700; - dataflash_info[i].Device.cs = cs[i][1]; - dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; - dataflash_info[i].id = dfcode; - Nb_device++; - break; - case AT45DB128: - dataflash_info[i].Device.pages_number = 16384; - dataflash_info[i].Device.pages_size = 1056; - dataflash_info[i].Device.page_offset = 11; - dataflash_info[i].Device.byte_mask = 0x700; - dataflash_info[i].Device.cs = cs[i][1]; - dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; - dataflash_info[i].id = dfcode; - Nb_device++; - break; - default: - break; - } - } - return (Nb_device); -} - - -void AT91F_DataflashPrintInfo(void) -{ - int i; - for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { - if (dataflash_info[i].id != 0) { - printf ("DF:AT45DB"); - switch (dataflash_info[i].id) { - case AT45DB161: - printf ("161"); - break; - - case AT45DB321: - printf ("321"); - break; - - case AT45DB642: - printf ("642"); - break; - case AT45DB128: - printf ("128"); - break; - } - - printf ("\n# PG: %6d\n" - "PG SZ: %6d\n" - "SZ=%8d bytes\n" - "ADDR: %08X\n", - (unsigned int) dataflash_info[i].Device.pages_number, - (unsigned int) dataflash_info[i].Device.pages_size, - (unsigned int) dataflash_info[i].Device.pages_number * - dataflash_info[i].Device.pages_size, - (unsigned int) dataflash_info[i].logical_address); - } - } -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataflashSelect */ -/* Object : Select the correct device */ -/*------------------------------------------------------------------------------*/ -static AT91PS_DataFlash AT91F_DataflashSelect(AT91PS_DataFlash pFlash, - unsigned int *addr) -{ - char addr_valid = 0; - int i; - - for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) - if ((*addr & 0xFF000000) == dataflash_info[i].logical_address) { - addr_valid = 1; - break; - } - if (!addr_valid) { - pFlash = (AT91PS_DataFlash) 0; - return pFlash; - } - pFlash->pDataFlashDesc = &(dataflash_info[i].Desc); - pFlash->pDevice = &(dataflash_info[i].Device); - *addr -= dataflash_info[i].logical_address; - return (pFlash); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : read_dataflash */ -/* Object : dataflash memory read */ -/*------------------------------------------------------------------------------*/ -int read_dataflash(unsigned long addr, unsigned long size, char *result) -{ - unsigned int AddrToRead = addr; - AT91PS_DataFlash pFlash = &DataFlashInst; - - pFlash = AT91F_DataflashSelect (pFlash, &AddrToRead); - if (pFlash == 0) - return -1; - - return (AT91F_DataFlashRead(pFlash, AddrToRead, size, result)); -} - - -/*-----------------------------------------------------------------------------*/ -/* Function Name : write_dataflash */ -/* Object : write a block in dataflash */ -/*-----------------------------------------------------------------------------*/ -int write_dataflash(unsigned long addr_dest, unsigned int addr_src, - unsigned int size) -{ - unsigned int AddrToWrite = addr_dest; - AT91PS_DataFlash pFlash = &DataFlashInst; - - pFlash = AT91F_DataflashSelect(pFlash, &AddrToWrite); - if (AddrToWrite == -1) - return -1; - - return AT91F_DataFlashWrite(pFlash, (unsigned char *) addr_src, AddrToWrite, size); -} - -/*-----------------------------------------------------------------------------*/ -/* Function Name : erase_dataflash */ -/* Object : Erase entire dataflash */ -/*-----------------------------------------------------------------------------*/ -int erase_dataflash(unsigned long addr_dest) -{ - unsigned int AddrToWrite = addr_dest; - AT91PS_DataFlash pFlash = &DataFlashInst; - - pFlash = AT91F_DataflashSelect (pFlash, &AddrToWrite); - if (AddrToWrite == -1) - return -1; - - return AT91F_DataFlashErase(pFlash); -} - diff --git a/target/linux/at91/image/dfboot/src/dataflash.h b/target/linux/at91/image/dfboot/src/dataflash.h deleted file mode 100644 index 8fab63fa9..000000000 --- a/target/linux/at91/image/dfboot/src/dataflash.h +++ /dev/null @@ -1,181 +0,0 @@ -//*--------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*--------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*--------------------------------------------------------------------------- -//* File Name : AT91_SpiDataFlash.h -//* Object : Data Flash Atmel Description File -//* Translator : -//* -//* 1.0 03/04/01 HI : Creation -//* -//*--------------------------------------------------------------------------- - -#ifndef _DataFlash_h -#define _DataFlash_h - -/* Max value = 15Mhz to be compliant with the Continuous array read function */ -#ifdef SPI_LOW_SPEED -#define AT91C_SPI_CLK 14976000/4 -#else -#define AT91C_SPI_CLK 14976000 -#endif - -/* AC characteristics */ -/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */ - -#define DATAFLASH_TCSS (0xf << 16) /* 250ns 15/60000000 */ -#define DATAFLASH_TCHS (0x1 << 24) /* 250ns 32*1/60000000 */ - - -#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ - -#define CFG_MAX_DATAFLASH_BANKS 2 -#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 -#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 - -typedef struct { - unsigned long base; /* logical base address for a bank */ - unsigned long size; /* total bank size */ - unsigned long page_count; - unsigned long page_size; - unsigned long id; /* device id */ -} dataflash_info_t; - -typedef unsigned int AT91S_DataFlashStatus; - -/*----------------------------------------------------------------------*/ -/* DataFlash Structures */ -/*----------------------------------------------------------------------*/ - -/*---------------------------------------------*/ -/* DataFlash Descriptor Structure Definition */ -/*---------------------------------------------*/ -typedef struct _AT91S_DataflashDesc { - unsigned char *tx_cmd_pt; - unsigned int tx_cmd_size; - unsigned char *rx_cmd_pt; - unsigned int rx_cmd_size; - unsigned char *tx_data_pt; - unsigned int tx_data_size; - unsigned char *rx_data_pt; - unsigned int rx_data_size; - volatile unsigned char DataFlash_state; - unsigned char command[8]; -} AT91S_DataflashDesc, *AT91PS_DataflashDesc; - -/*---------------------------------------------*/ -/* DataFlash device definition structure */ -/*---------------------------------------------*/ -typedef struct _AT91S_Dataflash { - int pages_number; /* dataflash page number */ - int pages_size; /* dataflash page size */ - int page_offset; /* page offset in command */ - int byte_mask; /* byte mask in command */ - int cs; -} AT91S_DataflashFeatures, *AT91PS_DataflashFeatures; - - -/*---------------------------------------------*/ -/* DataFlash Structure Definition */ -/*---------------------------------------------*/ -typedef struct _AT91S_DataFlash { - AT91PS_DataflashDesc pDataFlashDesc; /* dataflash descriptor */ - AT91PS_DataflashFeatures pDevice; /* Pointer on a dataflash features array */ -} AT91S_DataFlash, *AT91PS_DataFlash; - - -typedef struct _AT91S_DATAFLASH_INFO { - - AT91S_DataflashDesc Desc; - AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */ - unsigned long logical_address; - unsigned int id; /* device id */ -} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO; - - -/*-------------------------------------------------------------------------------------------------*/ - -#define AT45DB161 0x2c -#define AT45DB321 0x34 -#define AT45DB642 0x3c -#define AT45DB128 0x10 - -#define AT91C_DATAFLASH_TIMEOUT 20000 /* For AT91F_DataFlashWaitReady */ - -/* DataFlash return value */ -#define AT91C_DATAFLASH_BUSY 0x00 -#define AT91C_DATAFLASH_OK 0x01 -#define AT91C_DATAFLASH_ERROR 0x02 -#define AT91C_DATAFLASH_MEMORY_OVERFLOW 0x03 -#define AT91C_DATAFLASH_BAD_COMMAND 0x04 -#define AT91C_DATAFLASH_BAD_ADDRESS 0x05 - - -/* Driver State */ -#define IDLE 0x0 -#define BUSY 0x1 -#define ERROR 0x2 - -/* DataFlash Driver State */ -#define GET_STATUS 0x0F - -/*-------------------------------------------------------------------------------------------------*/ -/* Command Definition */ -/*-------------------------------------------------------------------------------------------------*/ - -/* READ COMMANDS */ -#define DB_CONTINUOUS_ARRAY_READ 0xE8 /* Continuous array read */ -#define DB_BURST_ARRAY_READ 0xE8 /* Burst array read */ -#define DB_PAGE_READ 0xD2 /* Main memory page read */ -#define DB_BUF1_READ 0xD4 /* Buffer 1 read */ -#define DB_BUF2_READ 0xD6 /* Buffer 2 read */ -#define DB_STATUS 0xD7 /* Status Register */ - -/* PROGRAM and ERASE COMMANDS */ -#define DB_BUF1_WRITE 0x84 /* Buffer 1 write */ -#define DB_BUF2_WRITE 0x87 /* Buffer 2 write */ -#define DB_BUF1_PAGE_ERASE_PGM 0x83 /* Buffer 1 to main memory page program with built-In erase */ -#define DB_BUF1_PAGE_ERASE_FASTPGM 0x93 /* Buffer 1 to main memory page program with built-In erase, Fast program */ -#define DB_BUF2_PAGE_ERASE_PGM 0x86 /* Buffer 2 to main memory page program with built-In erase */ -#define DB_BUF2_PAGE_ERASE_FASTPGM 0x96 /* Buffer 1 to main memory page program with built-In erase, Fast program */ -#define DB_BUF1_PAGE_PGM 0x88 /* Buffer 1 to main memory page program without built-In erase */ -#define DB_BUF1_PAGE_FASTPGM 0x98 /* Buffer 1 to main memory page program without built-In erase, Fast program */ -#define DB_BUF2_PAGE_PGM 0x89 /* Buffer 2 to main memory page program without built-In erase */ -#define DB_BUF2_PAGE_FASTPGM 0x99 /* Buffer 1 to main memory page program without built-In erase, Fast program */ -#define DB_PAGE_ERASE 0x81 /* Page Erase */ -#define DB_BLOCK_ERASE 0x50 /* Block Erase */ -#define DB_PAGE_PGM_BUF1 0x82 /* Main memory page through buffer 1 */ -#define DB_PAGE_FASTPGM_BUF1 0x92 /* Main memory page through buffer 1, Fast program */ -#define DB_PAGE_PGM_BUF2 0x85 /* Main memory page through buffer 2 */ -#define DB_PAGE_FastPGM_BUF2 0x95 /* Main memory page through buffer 2, Fast program */ - -/* ADDITIONAL COMMANDS */ -#define DB_PAGE_2_BUF1_TRF 0x53 /* Main memory page to buffer 1 transfert */ -#define DB_PAGE_2_BUF2_TRF 0x55 /* Main memory page to buffer 2 transfert */ -#define DB_PAGE_2_BUF1_CMP 0x60 /* Main memory page to buffer 1 compare */ -#define DB_PAGE_2_BUF2_CMP 0x61 /* Main memory page to buffer 2 compare */ -#define DB_AUTO_PAGE_PGM_BUF1 0x58 /* Auto page rewrite throught buffer 1 */ -#define DB_AUTO_PAGE_PGM_BUF2 0x59 /* Auto page rewrite throught buffer 2 */ - -/*-------------------------------------------------------------------------------------------------*/ - -extern AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; - -extern void AT91F_SpiInit(void); -extern int AT91F_DataflashProbe(int i, AT91PS_DataflashDesc pDesc); -extern int AT91F_DataFlashRead(AT91PS_DataFlash, unsigned long , unsigned long, char *); -extern AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash ,unsigned char *, int, int); -extern AT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash); -extern int AT91F_DataflashInit(void); -extern void AT91F_DataflashPrintInfo(void); -extern int read_dataflash(unsigned long addr, unsigned long size, char *result); -extern int write_dataflash(unsigned long addr_dest, unsigned int addr_src, unsigned int size); -extern int erase_dataflash(unsigned long addr_dest); - -#endif diff --git a/target/linux/at91/image/dfboot/src/div0.c b/target/linux/at91/image/dfboot/src/div0.c deleted file mode 100644 index d6fd90ec3..000000000 --- a/target/linux/at91/image/dfboot/src/div0.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Replacement (=dummy) for GNU/Linux division-by zero handler */ -void __div0 (void) -{ - while(-1); -} diff --git a/target/linux/at91/image/dfboot/src/elf32-littlearm.lds b/target/linux/at91/image/dfboot/src/elf32-littlearm.lds deleted file mode 100644 index 4d4efb6ad..000000000 --- a/target/linux/at91/image/dfboot/src/elf32-littlearm.lds +++ /dev/null @@ -1,19 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : { *(.text) } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .bss : { *(.bss) } -} \ No newline at end of file diff --git a/target/linux/at91/image/dfboot/src/embedded_services.h b/target/linux/at91/image/dfboot/src/embedded_services.h deleted file mode 100644 index 956b9edf0..000000000 --- a/target/linux/at91/image/dfboot/src/embedded_services.h +++ /dev/null @@ -1,500 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : embedded_sevices.h -//* Object : Header File with all the embedded software services definitions -//* -//* 1.0 24 Jan 2003 FB : Creation -//*---------------------------------------------------------------------------- -#ifndef embedded_sevices_h -#define embedded_sevices_h - -#include "AT91RM9200.h" - -#define AT91C_BASE_ROM (char *)0x00100000 - -/* Return values */ -#define AT91C_BUFFER_SUCCESS 0 -#define AT91C_BUFFER_ERROR_SHIFT 16 -#define AT91C_BUFFER_ERROR (0x0F << AT91C_BUFFER_ERROR_SHIFT) - -#define AT91C_BUFFER_OVERFLOW (0x01 << AT91C_BUFFER_ERROR_SHIFT) -#define AT91C_BUFFER_UNDERRUN (0x02 << AT91C_BUFFER_ERROR_SHIFT) - -typedef unsigned int AT91S_BufferStatus; - -struct _AT91S_Pipe; - -// This structure is a virtual object of a buffer -typedef struct _AT91S_Buffer -{ - struct _AT91S_Pipe *pPipe; - void *pChild; - - // Functions invoked by the pipe - AT91S_BufferStatus (*SetRdBuffer) (struct _AT91S_Buffer *pSBuffer, char *pBuffer, unsigned int Size); - AT91S_BufferStatus (*SetWrBuffer) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer, unsigned int Size); - AT91S_BufferStatus (*RstRdBuffer) (struct _AT91S_Buffer *pSBuffer); - AT91S_BufferStatus (*RstWrBuffer) (struct _AT91S_Buffer *pSBuffer); - char (*MsgWritten) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer); - char (*MsgRead) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer); - // Functions invoked by the peripheral - AT91S_BufferStatus (*GetWrBuffer) (struct _AT91S_Buffer *pSBuffer, char const **pData, unsigned int *pSize); - AT91S_BufferStatus (*GetRdBuffer) (struct _AT91S_Buffer *pSBuffer, char **pData, unsigned int *pSize); - AT91S_BufferStatus (*EmptyWrBuffer) (struct _AT91S_Buffer *pSBuffer, unsigned int size); - AT91S_BufferStatus (*FillRdBuffer) (struct _AT91S_Buffer *pSBuffer, unsigned int size); - char (*IsWrEmpty) (struct _AT91S_Buffer *pSBuffer); - char (*IsRdFull) (struct _AT91S_Buffer *pSBuffer); -} AT91S_Buffer, *AT91PS_Buffer; - -// =========================================================================================== -// SimpleBuffer definition -// -// This structure is pointed by pRealBuffer field in the SBuffer -// It contains usefull information for a real implementation of -// a SBuffer object. -// The application just create an instance of SSBUffer and SBuffer, -// call OpenSimpleBuffer, and continue using SBuffer instance - -typedef struct _AT91S_SBuffer -{ - AT91S_Buffer parent; - char *pRdBuffer; - char const *pWrBuffer; - unsigned int szRdBuffer; - unsigned int szWrBuffer; - unsigned int stRdBuffer; - unsigned int stWrBuffer; -} AT91S_SBuffer, *AT91PS_SBuffer; - -typedef AT91PS_Buffer (*AT91PF_OpenSBuffer) (AT91PS_SBuffer); - -// This function is called by the application -extern AT91PS_Buffer AT91F_OpenSBuffer(AT91PS_SBuffer pBuffer); - -// Functions invoked by the pipe -extern AT91S_BufferStatus AT91F_SbSetRdBuffer (AT91PS_Buffer pBuffer, char *pData, unsigned int Size); -extern AT91S_BufferStatus AT91F_SbSetWrBuffer (AT91PS_Buffer pBuffer, char const *pData, unsigned int Size); -extern AT91S_BufferStatus AT91F_SbRstRdBuffer (AT91PS_Buffer pBuffer); -extern AT91S_BufferStatus AT91F_SbRstWrBuffer (AT91PS_Buffer pBuffer); -extern char AT91F_SbMsgWritten (AT91PS_Buffer pBuffer, char const *pMsg); -extern char AT91F_SbMsgRead (AT91PS_Buffer pBuffer, char const *pMsg); -// Functions invoked by the peripheral -extern AT91S_BufferStatus AT91F_SbGetWrBuffer (AT91PS_Buffer pBuffer, char const **pData, unsigned int *pSize); -extern AT91S_BufferStatus AT91F_SbGetRdBuffer (AT91PS_Buffer pBuffer, char **pData, unsigned int *pSize); -extern AT91S_BufferStatus AT91F_SbEmptyWrBuffer(AT91PS_Buffer pBuffer, unsigned int size); -extern AT91S_BufferStatus AT91F_SbFillRdBuffer (AT91PS_Buffer pBuffer, unsigned int size); -extern char AT91F_SbIsWrEmpty (AT91PS_Buffer pBuffer); -extern char AT91F_SbIsRdFull (AT91PS_Buffer pBuffer); - -#ifdef DBG_DRV_BUFFER -extern char const *AT91F_SbGetError(AT91S_BufferStatus errorNumber); -#endif - - -#define AT91C_OPEN_CTRLTEMPO_SUCCESS 0 -#define AT91C_ERROR_OPEN_CTRLTEMPO 1 -#define AT91C_START_OK 2 -#define AT91C_STOP_OK 3 -#define AT91C_TIMEOUT_REACHED 4 - -typedef enum _AT91E_SvcTempo { - AT91E_SVCTEMPO_DIS, - AT91E_SVCTEMPO_EN -} AT91E_SvcTempo; - -typedef unsigned int AT91S_TempoStatus; - -// AT91S_SvcTempo -typedef struct _AT91S_SvcTempo -{ - - // Methods: - AT91S_TempoStatus (*Start) ( - struct _AT91S_SvcTempo *pSvc, - unsigned int timeout, - unsigned int reload, - void (*callback) (AT91S_TempoStatus, void *), - void *pData); - AT91S_TempoStatus (*Stop) (struct _AT91S_SvcTempo *pSvc); - - struct _AT91S_SvcTempo *pPreviousTempo; - struct _AT91S_SvcTempo *pNextTempo; - - // Data - unsigned int TickTempo; //* timeout value - unsigned int ReloadTempo;//* Reload value for periodic execution - void (*TempoCallback)(AT91S_TempoStatus, void *); - void *pPrivateData; - AT91E_SvcTempo flag; -} AT91S_SvcTempo, *AT91PS_SvcTempo; - - -// AT91S_CtrlTempo -typedef struct _AT91S_CtlTempo -{ - // Members: - - // Start and stop for Timer hardware - AT91S_TempoStatus (*CtlTempoStart) (void *pTimer); - AT91S_TempoStatus (*CtlTempoStop) (void *pTimer); - - // Start and stop for Tempo service - AT91S_TempoStatus (*SvcTempoStart) ( - struct _AT91S_SvcTempo *pSvc, - unsigned int timeout, - unsigned int reload, - void (*callback) (AT91S_TempoStatus, void *), - void *pData); - AT91S_TempoStatus (*SvcTempoStop) (struct _AT91S_SvcTempo *pSvc); - AT91S_TempoStatus (*CtlTempoSetTime)(struct _AT91S_CtlTempo *pCtrl, unsigned int NewTime); - AT91S_TempoStatus (*CtlTempoGetTime)(struct _AT91S_CtlTempo *pCtrl); - AT91S_TempoStatus (*CtlTempoIsStart)(struct _AT91S_CtlTempo *pCtrl); - AT91S_TempoStatus (*CtlTempoCreate) ( - struct _AT91S_CtlTempo *pCtrl, - struct _AT91S_SvcTempo *pTempo); - AT91S_TempoStatus (*CtlTempoRemove) ( - struct _AT91S_CtlTempo *pCtrl, - struct _AT91S_SvcTempo *pTempo); - AT91S_TempoStatus (*CtlTempoTick) (struct _AT91S_CtlTempo *pCtrl); - - // Data: - - void *pPrivateData; // Pointer to devived class - void const *pTimer; // hardware - AT91PS_SvcTempo pFirstTempo; - AT91PS_SvcTempo pNewTempo; -} AT91S_CtlTempo, *AT91PS_CtlTempo; -typedef AT91S_TempoStatus (*AT91PF_OpenCtlTempo) ( AT91PS_CtlTempo, void const *); - -// This function is called by the application. -extern AT91S_TempoStatus AT91F_OpenCtlTempo( AT91PS_CtlTempo pCtrlTempo, void const *pTempoTimer ); - -extern AT91S_TempoStatus AT91F_STStart (void *); -extern AT91S_TempoStatus AT91F_STStop (void *); -extern AT91S_TempoStatus AT91F_STSetTime (AT91PS_CtlTempo, unsigned int); -extern AT91S_TempoStatus AT91F_STGetTime (AT91PS_CtlTempo); -extern AT91S_TempoStatus AT91F_STIsStart (AT91PS_CtlTempo); -extern AT91S_TempoStatus AT91F_CtlTempoCreate (AT91PS_CtlTempo, AT91PS_SvcTempo); -extern AT91S_TempoStatus AT91F_CtlTempoRemove (AT91PS_CtlTempo, AT91PS_SvcTempo); -extern AT91S_TempoStatus AT91F_CtlTempoTick (AT91PS_CtlTempo); -extern AT91S_TempoStatus AT91F_SvcTempoStart ( - AT91PS_SvcTempo pSvc, - unsigned int timeout, - unsigned int reload, - void (*callback) (AT91S_TempoStatus, void *), - void *pData); -extern AT91S_TempoStatus AT91F_SvcTempoStop (AT91PS_SvcTempo); - - -// Following types are defined in another header files -struct _AT91S_Buffer; - -// Constants: -#define AT91C_COMMSVC_SUCCESS 0 -#define AT91C_COMMSVC_ERROR_SHIFT 8 -#define AT91C_COMMSVC_ERROR (0x0f << AT91C_COMMSVC_ERROR_SHIFT) - -typedef unsigned int AT91S_SvcCommStatus; - -// AT91S_Service definition -// This structure is an abstraction of a communication peripheral -typedef struct _AT91S_Service -{ - // Methods: - AT91S_SvcCommStatus (*Reset) (struct _AT91S_Service *pService); - AT91S_SvcCommStatus (*StartTx)(struct _AT91S_Service *pService); - AT91S_SvcCommStatus (*StartRx)(struct _AT91S_Service *pService); - AT91S_SvcCommStatus (*StopTx) (struct _AT91S_Service *pService); - AT91S_SvcCommStatus (*StopRx) (struct _AT91S_Service *pService); - char (*TxReady)(struct _AT91S_Service *pService); - char (*RxReady)(struct _AT91S_Service *pService); - // Data: - struct _AT91S_Buffer *pBuffer; // Link to a buffer object - void *pChild; -} AT91S_SvcComm, *AT91PS_SvcComm; - -// Constants: -#define AT91C_XMODEM_SOH 0x01 /* Start of Heading for 128 bytes */ -#define AT91C_XMODEM_STX 0x02 /* Start of heading for 1024 bytes */ -#define AT91C_XMODEM_EOT 0x04 /* End of transmission */ -#define AT91C_XMODEM_ACK 0x06 /* Acknowledge */ -#define AT91C_XMODEM_NAK 0x15 /* Negative Acknowledge */ -#define AT91C_XMODEM_CRCCHR 'C' - -#define AT91C_XMODEM_PACKET_SIZE 2 // packet + packetCRC -#define AT91C_XMODEM_CRC_SIZE 2 // crcLSB + crcMSB -#define AT91C_XMODEM_DATA_SIZE_SOH 128 // data 128 corresponding to SOH header -#define AT91C_XMODEM_DATA_SIZE_STX 1024 // data 1024 corresponding to STX header - -//* Following structure is used by SPipe to refer to the USB device peripheral endpoint -typedef struct _AT91PS_SvcXmodem { - - // Public Methods: - AT91S_SvcCommStatus (*Handler) (struct _AT91PS_SvcXmodem *, unsigned int); - AT91S_SvcCommStatus (*StartTx) (struct _AT91PS_SvcXmodem *, unsigned int); - AT91S_SvcCommStatus (*StopTx) (struct _AT91PS_SvcXmodem *, unsigned int); - - // Private Methods: - AT91S_SvcCommStatus (*ReadHandler) (struct _AT91PS_SvcXmodem *, unsigned int csr); - AT91S_SvcCommStatus (*WriteHandler) (struct _AT91PS_SvcXmodem *, unsigned int csr); - unsigned short (*GetCrc) (char *ptr, unsigned int count); - char (*CheckHeader) (unsigned char currentPacket, char *packet); - char (*CheckData) (struct _AT91PS_SvcXmodem *); - - AT91S_SvcComm parent; // Base class - AT91PS_USART pUsart; - - AT91S_SvcTempo tempo; // Link to a AT91S_Tempo object - - char *pData; - unsigned int dataSize; // = XMODEM_DATA_STX or XMODEM_DATA_SOH - char packetDesc[AT91C_XMODEM_PACKET_SIZE]; - unsigned char packetId; // Current packet - char packetStatus; - char isPacketDesc; - char eot; // end of transmition -} AT91S_SvcXmodem, *AT91PS_SvcXmodem; - -typedef AT91PS_SvcComm (*AT91PF_OpenSvcXmodem) ( AT91PS_SvcXmodem, AT91PS_USART, AT91PS_CtlTempo); - -// This function is called by the application. -extern AT91PS_SvcComm AT91F_OpenSvcXmodem( AT91PS_SvcXmodem, AT91PS_USART, AT91PS_CtlTempo); - -extern unsigned short AT91F_SvcXmodemGetCrc (char *ptr, unsigned int count); -extern char AT91F_SvcXmodemCheckHeader(unsigned char currentPacket, char *packet); -extern char AT91F_SvcXmodemCheckData (AT91PS_SvcXmodem pSvcXmodem); -extern AT91S_SvcCommStatus AT91F_SvcXmodemReadHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr); -extern AT91S_SvcCommStatus AT91F_SvcXmodemWriteHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr); -extern AT91S_SvcCommStatus AT91F_SvcXmodemStartTx(AT91PS_SvcComm pSvcComm); -extern AT91S_SvcCommStatus AT91F_SvcXmodemStopTx(AT91PS_SvcComm pSvcComm); -extern AT91S_SvcCommStatus AT91F_SvcXmodemStartRx(AT91PS_SvcComm pSvcComm); -extern AT91S_SvcCommStatus AT91F_SvcXmodemStopRx(AT91PS_SvcComm pSvcComm); -extern char AT91F_SvcXmodemTxReady(AT91PS_SvcComm pService); -extern char AT91F_SvcXmodemRxReady(AT91PS_SvcComm pSvcComm); - - -// Constants: -#define AT91C_PIPE_SUCCESS 0 -#define AT91C_PIPE_ERROR_SHIFT 8 -#define AT91C_PIPE_ERROR (0x0F << AT91C_PIPE_ERROR_SHIFT) - -#define AT91C_PIPE_OPEN_FAILED (1 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_WRITE_FAILED (2 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_WRITE_ABORTED (3 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_READ_FAILED (4 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_READ_ABORTED (5 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_ABORT_FAILED (6 << AT91C_PIPE_ERROR_SHIFT) -#define AT91C_PIPE_RESET_FAILED (7 << AT91C_PIPE_ERROR_SHIFT) - -/* _AT91S_Pipe stucture */ -typedef unsigned int AT91S_PipeStatus; - -typedef struct _AT91S_Pipe -{ - // A pipe is linked with a peripheral and a buffer - AT91PS_SvcComm pSvcComm; - AT91PS_Buffer pBuffer; - - // Callback functions with their arguments - void (*WriteCallback) (AT91S_PipeStatus, void *); - void (*ReadCallback) (AT91S_PipeStatus, void *); - void *pPrivateReadData; - void *pPrivateWriteData; - - // Pipe methods - AT91S_PipeStatus (*Write) ( - struct _AT91S_Pipe *pPipe, - char const * pData, - unsigned int size, - void (*callback) (AT91S_PipeStatus, void *), - void *privateData); - AT91S_PipeStatus (*Read) ( - struct _AT91S_Pipe *pPipe, - char *pData, - unsigned int size, - void (*callback) (AT91S_PipeStatus, void *), - void *privateData); - AT91S_PipeStatus (*AbortWrite) ( - struct _AT91S_Pipe *pPipe); - AT91S_PipeStatus (*AbortRead) ( - struct _AT91S_Pipe *pPipe); - AT91S_PipeStatus (*Reset) ( - struct _AT91S_Pipe *pPipe); - char (*IsWritten) ( - struct _AT91S_Pipe *pPipe, - char const *pVoid); - char (*IsReceived) ( - struct _AT91S_Pipe *pPipe, - char const *pVoid); -} AT91S_Pipe, *AT91PS_Pipe; - -// types used in AT91S_Pipe -typedef AT91PS_Pipe (*AT91PF_OpenPipe) (AT91PS_Pipe, AT91PS_SvcComm, AT91PS_Buffer); -typedef void (*AT91PF_PipeWriteCallBack) (AT91S_PipeStatus, void *); -typedef void (*AT91PF_PipeReadCallBack) (AT91S_PipeStatus, void *); -typedef AT91S_PipeStatus (*AT91PF_PipeWrite) (AT91PS_Pipe, char const *, unsigned int, void (*) (AT91S_PipeStatus, void *), void *); -typedef AT91S_PipeStatus (*AT91PF_PipeRead) (AT91PS_Pipe, char const *, unsigned int, void (*) (AT91S_PipeStatus, void *), void *); -typedef AT91S_PipeStatus (*AT91PF_PipeAbortWrite) (AT91PS_Pipe); -typedef AT91S_PipeStatus (*AT91PF_PipeAbortRead) (AT91PS_Pipe); -typedef AT91S_PipeStatus (*AT91PF_PipeReset) (AT91PS_Pipe); -typedef char (*AT91PF_PipeIsWritten) (AT91PS_Pipe, char const *); -typedef char (*AT91PF_PipeIsReceived) (AT91PS_Pipe, char const *); - -// This function is called by the application -extern AT91PS_Pipe AT91F_OpenPipe( - AT91PS_Pipe pPipe, - AT91PS_SvcComm pSvcComm, - AT91PS_Buffer pBuffer); - -// Following functions are called through AT91S_Pipe pointers - -extern AT91S_PipeStatus AT91F_PipeWrite( - AT91PS_Pipe pPipe, - char const *pVoid, - unsigned int size, - AT91PF_PipeWriteCallBack callback, - void *privateData); -extern AT91S_PipeStatus AT91F_PipeRead( - AT91PS_Pipe pPipe, - char *pVoid, - unsigned int Size, - AT91PF_PipeReadCallBack callback, - void *privateData); -extern AT91S_PipeStatus AT91F_PipeAbortWrite(AT91PS_Pipe pPipe); -extern AT91S_PipeStatus AT91F_PipeAbortRead(AT91PS_Pipe pPipe); -extern AT91S_PipeStatus AT91F_PipeReset(AT91PS_Pipe pPipe); -extern char AT91F_PipeMsgWritten(AT91PS_Pipe pPipe, char const *pVoid); -extern char AT91F_PipeMsgReceived(AT91PS_Pipe pPipe, char const *pVoid); - -#ifdef DBG_DRV_PIPE -// This function parse the error number and return a string -// describing the error message -extern char const *AT91F_PipeGetError(AT91S_PipeStatus msgId); -#endif - -extern const unsigned char bit_rev[256]; - -extern void CalculateCrc32(const unsigned char *,unsigned int, unsigned int *); -extern void CalculateCrc16(const unsigned char *, unsigned int , unsigned short *); -extern void CalculateCrcHdlc(const unsigned char *, unsigned int, unsigned short *); -extern void CalculateCrc16ccitt(const unsigned char *, unsigned int , unsigned short *); - -typedef const unsigned char* AT91PS_SVC_CRC_BIT_REV ; - -typedef void (*AT91PF_SVC_CRC32) (const unsigned char *, unsigned int, unsigned int *); -typedef void (*AT91PF_SVC_CRC16) (const unsigned char *, unsigned int, unsigned short *); -typedef void (*AT91PF_SVC_CRCHDLC) (const unsigned char *, unsigned int, unsigned short *); -typedef void (*AT91PF_SVC_CRCCCITT)(const unsigned char *, unsigned int , unsigned short *); - - -typedef short (*AT91PF_Sinus) (int angle); -typedef const short * AT91PS_SINE_TAB; - -extern short AT91F_Sinus(int angle); -extern const short AT91C_SINUS180_TAB[256]; - - -typedef void (TypeAICHandler) (void) ; - - -// ROM BOOT Structure Element Definition (liv v2) -typedef struct _AT91S_MEMCDesc -{ - AT91PS_MC memc_base ; /* Peripheral base */ - unsigned char periph_id ; /* MC Peripheral Identifier */ -} AT91S_MEMCDesc, *AT91PS_MEMCDesc ; - -typedef struct _AT91S_Pio2Desc -{ - AT91PS_PIO pio_base ; /* Base Address */ - unsigned char periph_id ; /* Peripheral Identifier */ - unsigned char pio_number ; /* Total Pin Number */ -} AT91S_Pio2Desc, *AT91PS_Pio2Desc ; - -typedef struct _AT91S_SPIDesc -{ - AT91PS_SPI spi_base ; - const AT91PS_PIO pio_base ; - unsigned char periph_id ; - unsigned char pin_spck ; - unsigned char pin_miso ; - unsigned char pin_mosi ; - unsigned char pin_npcs[4] ; -} AT91S_SPIDesc, *AT91PS_SPIDesc ; - -typedef struct _AT91S_USART2Desc -{ - AT91PS_USART usart_base ; /* Peripheral base */ - const AT91PS_PIO pio_base ; /* IO controller descriptor */ - unsigned int pin_rxd ; /* RXD pin number in the PIO */ - unsigned int pin_txd ; /* TXD pin number in the PIO */ - unsigned int pin_sck ; /* SCK pin number in the PIO */ - unsigned int pin_rts ; /* RTS pin number in the PIO */ - unsigned int pin_cts ; /* CTS pin number in the PIO */ - unsigned int pin_dtr ; /* DTR pin number in the PIO */ - unsigned int pin_ri ; /* RI pin number in the PIO */ - unsigned int pin_dsr ; /* DSR pin number in the PIO */ - unsigned int pin_dcd ; /* DCD pin number in the PIO */ - unsigned int periph_id ; /* USART Peripheral Identifier */ -} AT91S_USART2Desc, *AT91PS_USART2Desc ; - -typedef struct _AT91S_TWIDesc -{ - AT91PS_TWI TWI_base ; - const AT91PS_PIO pio_base ; - unsigned int pin_sck ; - unsigned int pin_sda ; - unsigned int periph_id; -}AT91S_TWIDesc, *AT91PS_TWIDesc; - -typedef struct _AT91S_STDesc -{ - AT91PS_ST st_base ; /* Peripheral base address */ - TypeAICHandler *AsmSTHandler ; /* Assembly interrupt handler */ - unsigned char PeriphId ; /* Peripheral Identifier */ -} AT91S_STDesc, *AT91PS_STDesc; - -typedef struct _AT91S_RomBoot { - const unsigned int version; - // Peripheral descriptors - const AT91S_MEMCDesc MEMC_DESC; - const AT91S_STDesc SYSTIMER_DESC; - const AT91S_Pio2Desc PIOA_DESC; - const AT91S_Pio2Desc PIOB_DESC; - const AT91S_USART2Desc DBGU_DESC; - const AT91S_USART2Desc USART0_DESC; - const AT91S_USART2Desc USART1_DESC; - const AT91S_USART2Desc USART2_DESC; - const AT91S_USART2Desc USART3_DESC; - const AT91S_TWIDesc TWI_DESC; - const AT91S_SPIDesc SPI_DESC; - - // Objects entry - const AT91PF_OpenPipe OpenPipe; - const AT91PF_OpenSBuffer OpenSBuffer; - const unsigned int reserved1; - const AT91PF_OpenSvcXmodem OpenSvcXmodem; - const AT91PF_OpenCtlTempo OpenCtlTempo; - const unsigned int reserved2; - const unsigned int reserved3; - const unsigned int reserved4; - const AT91PF_SVC_CRC16 CRC16; - const AT91PF_SVC_CRCCCITT CRCCCITT; - const AT91PF_SVC_CRCHDLC CRCHDLC; - const AT91PF_SVC_CRC32 CRC32; - const AT91PS_SVC_CRC_BIT_REV Bit_Reverse_Array; - const AT91PS_SINE_TAB SineTab; - const AT91PF_Sinus Sine; -} AT91S_RomBoot, *AT91PS_RomBoot; - -#define AT91C_ROM_BOOT_ADDRESS ((const AT91S_RomBoot *) ( *((unsigned int *) (AT91C_BASE_ROM + 0x20))) ) - -#endif - diff --git a/target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h b/target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h deleted file mode 100644 index 43d583523..000000000 --- a/target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h +++ /dev/null @@ -1,379 +0,0 @@ -//*--------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*--------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*--------------------------------------------------------------------------- -//* File Name : AT91C_MCI_Device.h -//* Object : Data Flash Atmel Description File -//* Translator : -//* -//* 1.0 26/11/02 FB : Creation -//*--------------------------------------------------------------------------- - -#ifndef AT91C_MCI_Device_h -#define AT91C_MCI_Device_h - -#include "AT91RM9200.h" -#include "lib_AT91RM9200.h" - -typedef unsigned int AT91S_MCIDeviceStatus; - -///////////////////////////////////////////////////////////////////////////////////////////////////// - -#define AT91C_CARD_REMOVED 0 -#define AT91C_MMC_CARD_INSERTED 1 -#define AT91C_SD_CARD_INSERTED 2 - -#define AT91C_NO_ARGUMENT 0x0 - -#define AT91C_FIRST_RCA 0xCAFE -#define AT91C_MAX_MCI_CARDS 10 - -#define AT91C_BUS_WIDTH_1BIT 0x00 -#define AT91C_BUS_WIDTH_4BITS 0x02 - -/* Driver State */ -#define AT91C_MCI_IDLE 0x0 -#define AT91C_MCI_TIMEOUT_ERROR 0x1 -#define AT91C_MCI_RX_SINGLE_BLOCK 0x2 -#define AT91C_MCI_RX_MULTIPLE_BLOCK 0x3 -#define AT91C_MCI_RX_STREAM 0x4 -#define AT91C_MCI_TX_SINGLE_BLOCK 0x5 -#define AT91C_MCI_TX_MULTIPLE_BLOCK 0x6 -#define AT91C_MCI_TX_STREAM 0x7 - -/* TimeOut */ -#define AT91C_TIMEOUT_CMDRDY 30 - -///////////////////////////////////////////////////////////////////////////////////////////////////// -// MMC & SDCard Structures -///////////////////////////////////////////////////////////////////////////////////////////////////// - -/*-----------------------------------------------*/ -/* SDCard Device Descriptor Structure Definition */ -/*-----------------------------------------------*/ -typedef struct _AT91S_MciDeviceDesc -{ - volatile unsigned char state; - unsigned char SDCard_bus_width; - -} AT91S_MciDeviceDesc, *AT91PS_MciDeviceDesc; - -/*---------------------------------------------*/ -/* MMC & SDCard Structure Device Features */ -/*---------------------------------------------*/ -typedef struct _AT91S_MciDeviceFeatures -{ - unsigned char Card_Inserted; // (0=AT91C_CARD_REMOVED) (1=AT91C_MMC_CARD_INSERTED) (2=AT91C_SD_CARD_INSERTED) - unsigned int Relative_Card_Address; // RCA - unsigned int Max_Read_DataBlock_Length; // 2^(READ_BL_LEN) in CSD - unsigned int Max_Write_DataBlock_Length; // 2^(WRITE_BL_LEN) in CSD - unsigned char Read_Partial; // READ_BL_PARTIAL - unsigned char Write_Partial; // WRITE_BL_PARTIAL - unsigned char Erase_Block_Enable; // ERASE_BLK_EN - unsigned char Read_Block_Misalignment; // READ_BLK_MISALIGN - unsigned char Write_Block_Misalignment; // WRITE_BLK_MISALIGN - unsigned char Sector_Size; // SECTOR_SIZE - unsigned int Memory_Capacity; // Size in bits of the device - -} AT91S_MciDeviceFeatures, *AT91PS_MciDeviceFeatures ; - -/*---------------------------------------------*/ -/* MCI Device Structure Definition */ -/*---------------------------------------------*/ -typedef struct _AT91S_MciDevice -{ - AT91PS_MciDeviceDesc pMCI_DeviceDesc; // MCI device descriptor - AT91PS_MciDeviceFeatures pMCI_DeviceFeatures;// Pointer on a MCI device features array -}AT91S_MciDevice, *AT91PS_MciDevice; - -///////////////////////////////////////////////////////////////////////////////////////////////////// -// MCI_CMD Register Value -///////////////////////////////////////////////////////////////////////////////////////////////////// -#define AT91C_POWER_ON_INIT (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_INIT | AT91C_MCI_OPDCMD) - -///////////////////////////////////////////////////////////////// -// Class 0 & 1 commands: Basic commands and Read Stream commands -///////////////////////////////////////////////////////////////// - -#define AT91C_GO_IDLE_STATE_CMD (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE ) -#define AT91C_MMC_GO_IDLE_STATE_CMD (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_OPDCMD) -#define AT91C_MMC_SEND_OP_COND_CMD (1 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD) -#define AT91C_ALL_SEND_CID_CMD (2 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 ) -#define AT91C_MMC_ALL_SEND_CID_CMD (2 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_OPDCMD) -#define AT91C_SET_RELATIVE_ADDR_CMD (3 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_MMC_SET_RELATIVE_ADDR_CMD (3 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT | AT91C_MCI_OPDCMD) - -#define AT91C_SET_DSR_CMD (4 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_NO | AT91C_MCI_MAXLAT ) // no tested - -#define AT91C_SEL_DESEL_CARD_CMD (7 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_SEND_CSD_CMD (9 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_MAXLAT ) -#define AT91C_SEND_CID_CMD (10 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_MAXLAT ) -#define AT91C_MMC_READ_DAT_UNTIL_STOP_CMD (11 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT ) - -#define AT91C_STOP_TRANSMISSION_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_STOP_TRANSMISSION_SYNC_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_SYNC | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_SEND_STATUS_CMD (13 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_GO_INACTIVE_STATE_CMD (15 | AT91C_MCI_RSPTYP_NO ) - -//*------------------------------------------------ -//* Class 2 commands: Block oriented Read commands -//*------------------------------------------------ - -#define AT91C_SET_BLOCKLEN_CMD (16 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) -#define AT91C_READ_SINGLE_BLOCK_CMD (17 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_BLOCK | AT91C_MCI_TRDIR | AT91C_MCI_MAXLAT) -#define AT91C_READ_MULTIPLE_BLOCK_CMD (18 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_MULTIPLE | AT91C_MCI_TRDIR | AT91C_MCI_MAXLAT) - -//*-------------------------------------------- -//* Class 3 commands: Sequential write commands -//*-------------------------------------------- - -#define AT91C_MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 & ~(AT91C_MCI_TRDIR) | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT ) // MMC - -//*------------------------------------------------ -//* Class 4 commands: Block oriented write commands -//*------------------------------------------------ - -#define AT91C_WRITE_BLOCK_CMD (24 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_BLOCK & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT) -#define AT91C_WRITE_MULTIPLE_BLOCK_CMD (25 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_MULTIPLE & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT) -#define AT91C_PROGRAM_CSD_CMD (27 | AT91C_MCI_RSPTYP_48 ) - - -//*---------------------------------------- -//* Class 6 commands: Group Write protect -//*---------------------------------------- - -#define AT91C_SET_WRITE_PROT_CMD (28 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_CLR_WRITE_PROT_CMD (29 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_SEND_WRITE_PROT_CMD (30 | AT91C_MCI_RSPTYP_48 ) - - -//*---------------------------------------- -//* Class 5 commands: Erase commands -//*---------------------------------------- - -#define AT91C_TAG_SECTOR_START_CMD (32 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_TAG_SECTOR_END_CMD (33 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_MMC_UNTAG_SECTOR_CMD (34 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_MMC_TAG_ERASE_GROUP_START_CMD (35 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_MMC_TAG_ERASE_GROUP_END_CMD (36 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_MMC_UNTAG_ERASE_GROUP_CMD (37 | AT91C_MCI_RSPTYP_48 ) -#define AT91C_ERASE_CMD (38 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT ) - -//*---------------------------------------- -//* Class 7 commands: Lock commands -//*---------------------------------------- - -#define AT91C_LOCK_UNLOCK (42 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) // no tested - -//*----------------------------------------------- -// Class 8 commands: Application specific commands -//*----------------------------------------------- - -#define AT91C_APP_CMD (55 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_GEN_CMD (56 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) // no tested - -#define AT91C_SDCARD_SET_BUS_WIDTH_CMD (6 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_SDCARD_STATUS_CMD (13 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_SDCARD_APP_OP_COND_CMD (41 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO ) -#define AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD (42 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) -#define AT91C_SDCARD_SEND_SCR_CMD (51 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) - -#define AT91C_SDCARD_APP_ALL_CMD (AT91C_SDCARD_SET_BUS_WIDTH_CMD +\ - AT91C_SDCARD_STATUS_CMD +\ - AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD +\ - AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\ - AT91C_SDCARD_APP_OP_COND_CMD +\ - AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD +\ - AT91C_SDCARD_SEND_SCR_CMD) - -//*---------------------------------------- -//* Class 9 commands: IO Mode commands -//*---------------------------------------- - -#define AT91C_MMC_FAST_IO_CMD (39 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT) -#define AT91C_MMC_GO_IRQ_STATE_CMD (40 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) - -///////////////////////////////////////////////////////////////////////////////////////////////////// -// Functions returnals -///////////////////////////////////////////////////////////////////////////////////////////////////// -#define AT91C_CMD_SEND_OK 0 // Command ok -#define AT91C_CMD_SEND_ERROR -1 // Command failed -#define AT91C_INIT_OK 2 // Init Successfull -#define AT91C_INIT_ERROR 3 // Init Failed -#define AT91C_READ_OK 4 // Read Successfull -#define AT91C_READ_ERROR 5 // Read Failed -#define AT91C_WRITE_OK 6 // Write Successfull -#define AT91C_WRITE_ERROR 7 // Write Failed -#define AT91C_ERASE_OK 8 // Erase Successfull -#define AT91C_ERASE_ERROR 9 // Erase Failed -#define AT91C_CARD_SELECTED_OK 10 // Card Selection Successfull -#define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed - -///////////////////////////////////////////////////////////////////////////////////////////////////// -// MCI_SR Errors -///////////////////////////////////////////////////////////////////////////////////////////////////// -#define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE |\ - AT91C_MCI_OVRE |\ - AT91C_MCI_DTOE |\ - AT91C_MCI_DCRCE |\ - AT91C_MCI_RTOE |\ - AT91C_MCI_RENDE |\ - AT91C_MCI_RCRCE |\ - AT91C_MCI_RDIRE |\ - AT91C_MCI_RINDE) - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// OCR Register -//////////////////////////////////////////////////////////////////////////////////////////////////// -#define AT91C_VDD_16_17 (1 << 4) -#define AT91C_VDD_17_18 (1 << 5) -#define AT91C_VDD_18_19 (1 << 6) -#define AT91C_VDD_19_20 (1 << 7) -#define AT91C_VDD_20_21 (1 << 8) -#define AT91C_VDD_21_22 (1 << 9) -#define AT91C_VDD_22_23 (1 << 10) -#define AT91C_VDD_23_24 (1 << 11) -#define AT91C_VDD_24_25 (1 << 12) -#define AT91C_VDD_25_26 (1 << 13) -#define AT91C_VDD_26_27 (1 << 14) -#define AT91C_VDD_27_28 (1 << 15) -#define AT91C_VDD_28_29 (1 << 16) -#define AT91C_VDD_29_30 (1 << 17) -#define AT91C_VDD_30_31 (1 << 18) -#define AT91C_VDD_31_32 (1 << 19) -#define AT91C_VDD_32_33 (1 << 20) -#define AT91C_VDD_33_34 (1 << 21) -#define AT91C_VDD_34_35 (1 << 22) -#define AT91C_VDD_35_36 (1 << 23) -#define AT91C_CARD_POWER_UP_BUSY (1 << 31) - -#define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 +\ - AT91C_VDD_28_29 +\ - AT91C_VDD_29_30 +\ - AT91C_VDD_30_31 +\ - AT91C_VDD_31_32 +\ - AT91C_VDD_32_33) - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1) -//////////////////////////////////////////////////////////////////////////////////////////////////// -#define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus -#define AT91C_SR_IDLE (0 << 9) -#define AT91C_SR_READY (1 << 9) -#define AT91C_SR_IDENT (2 << 9) -#define AT91C_SR_STBY (3 << 9) -#define AT91C_SR_TRAN (4 << 9) -#define AT91C_SR_DATA (5 << 9) -#define AT91C_SR_RCV (6 << 9) -#define AT91C_SR_PRG (7 << 9) -#define AT91C_SR_DIS (8 << 9) - -#define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN) - -///////////////////////////////////////////////////////////////////////////////////////////////////// -// MMC CSD register header File -// AT91C_CSD_xxx_S for shift value -// AT91C_CSD_xxx_M for mask value -///////////////////////////////////////////////////////////////////////////////////////////////////// - -// First Response INT <=> CSD[3] : bits 0 to 31 -#define AT91C_CSD_BIT0_S 0 // [0:0] -#define AT91C_CSD_BIT0_M 0x01 -#define AT91C_CSD_CRC_S 1 // [7:1] -#define AT91C_CSD_CRC_M 0x7F -#define AT91C_CSD_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility -#define AT91C_CSD_MMC_ECC_M 0x03 -#define AT91C_CSD_FILE_FMT_S 10 // [11:10] -#define AT91C_CSD_FILE_FMT_M 0x03 -#define AT91C_CSD_TMP_WP_S 12 // [12:12] -#define AT91C_CSD_TMP_WP_M 0x01 -#define AT91C_CSD_PERM_WP_S 13 // [13:13] -#define AT91C_CSD_PERM_WP_M 0x01 -#define AT91C_CSD_COPY_S 14 // [14:14] -#define AT91C_CSD_COPY_M 0x01 -#define AT91C_CSD_FILE_FMT_GRP_S 15 // [15:15] -#define AT91C_CSD_FILE_FMT_GRP_M 0x01 -// reserved 16 // [20:16] -// reserved 0x1F -#define AT91C_CSD_WBLOCK_P_S 21 // [21:21] -#define AT91C_CSD_WBLOCK_P_M 0x01 -#define AT91C_CSD_WBLEN_S 22 // [25:22] -#define AT91C_CSD_WBLEN_M 0x0F -#define AT91C_CSD_R2W_F_S 26 // [28:26] -#define AT91C_CSD_R2W_F_M 0x07 -#define AT91C_CSD_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility -#define AT91C_CSD_MMC_DEF_ECC_M 0x03 -#define AT91C_CSD_WP_GRP_EN_S 31 // [31:31] -#define AT91C_CSD_WP_GRP_EN_M 0x01 - -// Seconde Response INT <=> CSD[2] : bits 32 to 63 -#define AT91C_CSD_v21_WP_GRP_SIZE_S 0 // [38:32] -#define AT91C_CSD_v21_WP_GRP_SIZE_M 0x7F -#define AT91C_CSD_v21_SECT_SIZE_S 7 // [45:39] -#define AT91C_CSD_v21_SECT_SIZE_M 0x7F -#define AT91C_CSD_v21_ER_BLEN_EN_S 14 // [46:46] -#define AT91C_CSD_v21_ER_BLEN_EN_M 0x01 - -#define AT91C_CSD_v22_WP_GRP_SIZE_S 0 // [36:32] -#define AT91C_CSD_v22_WP_GRP_SIZE_M 0x1F -#define AT91C_CSD_v22_ER_GRP_SIZE_S 5 // [41:37] -#define AT91C_CSD_v22_ER_GRP_SIZE_M 0x1F -#define AT91C_CSD_v22_SECT_SIZE_S 10 // [46:42] -#define AT91C_CSD_v22_SECT_SIZE_M 0x1F - -#define AT91C_CSD_C_SIZE_M_S 15 // [49:47] -#define AT91C_CSD_C_SIZE_M_M 0x07 -#define AT91C_CSD_VDD_WMAX_S 18 // [52:50] -#define AT91C_CSD_VDD_WMAX_M 0x07 -#define AT91C_CSD_VDD_WMIN_S 21 // [55:53] -#define AT91C_CSD_VDD_WMIN_M 0x07 -#define AT91C_CSD_RCUR_MAX_S 24 // [58:56] -#define AT91C_CSD_RCUR_MAX_M 0x07 -#define AT91C_CSD_RCUR_MIN_S 27 // [61:59] -#define AT91C_CSD_RCUR_MIN_M 0x07 -#define AT91C_CSD_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE -#define AT91C_CSD_CSIZE_L_M 0x03 - -// Third Response INT <=> CSD[1] : bits 64 to 95 -#define AT91C_CSD_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE -#define AT91C_CSD_CSIZE_H_M 0x03FF -// reserved 10 // [75:74] -// reserved 0x03 -#define AT91C_CSD_DSR_I_S 12 // [76:76] -#define AT91C_CSD_DSR_I_M 0x01 -#define AT91C_CSD_RD_B_MIS_S 13 // [77:77] -#define AT91C_CSD_RD_B_MIS_M 0x01 -#define AT91C_CSD_WR_B_MIS_S 14 // [78:78] -#define AT91C_CSD_WR_B_MIS_M 0x01 -#define AT91C_CSD_RD_B_PAR_S 15 // [79:79] -#define AT91C_CSD_RD_B_PAR_M 0x01 -#define AT91C_CSD_RD_B_LEN_S 16 // [83:80] -#define AT91C_CSD_RD_B_LEN_M 0x0F -#define AT91C_CSD_CCC_S 20 // [95:84] -#define AT91C_CSD_CCC_M 0x0FFF - -// Fourth Response INT <=> CSD[0] : bits 96 to 127 -#define AT91C_CSD_TRANS_SPEED_S 0 // [103:96] -#define AT91C_CSD_TRANS_SPEED_M 0xFF -#define AT91C_CSD_NSAC_S 8 // [111:104] -#define AT91C_CSD_NSAC_M 0xFF -#define AT91C_CSD_TAAC_S 16 // [119:112] -#define AT91C_CSD_TAAC_M 0xFF -// reserved 24 // [121:120] -// reserved 0x03 -#define AT91C_CSD_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility -#define AT91C_CSD_MMC_SPEC_VERS_M 0x0F -#define AT91C_CSD_STRUCT_S 30 // [127:126] -#define AT91C_CSD_STRUCT_M 0x03 - -///////////////////////////////////////////////////////////////////////////////////////////////////// - -#endif - diff --git a/target/linux/at91/image/dfboot/src/include/AT91RM9200.h b/target/linux/at91/image/dfboot/src/include/AT91RM9200.h deleted file mode 100644 index 0cd153b42..000000000 --- a/target/linux/at91/image/dfboot/src/include/AT91RM9200.h +++ /dev/null @@ -1,2745 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// The software is delivered "AS IS" without warranty or condition of any -// kind, either express, implied or statutory. This includes without -// limitation any warranty or condition with respect to merchantability or -// fitness for any particular purpose, or against the infringements of -// intellectual property rights of others. -// ---------------------------------------------------------------------------- -// File Name : AT91RM9200.h -// Object : AT91RM9200 definitions -// Generated : AT91 SW Application Group 11/19/2003 (17:20:50) -// -// CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// -// CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// -// CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// -// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -// CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002// -// CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003// -// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// -// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002// -// CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002// -// CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002// -// CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002// -// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002// -// CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003// -// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003// -// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002// -// CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002// -// CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003// -// CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003// -// CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002// -// CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002// -// CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002// -// ---------------------------------------------------------------------------- - -#ifndef AT91RM9200_H -#define AT91RM9200_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_C1R; // Chip ID1 Register - AT91_REG DBGU_C2R; // Chip ID2 Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[85]; // - AT91_REG PIOC_PER; // PIO Enable Register - AT91_REG PIOC_PDR; // PIO Disable Register - AT91_REG PIOC_PSR; // PIO Status Register - AT91_REG Reserved20[1]; // - AT91_REG PIOC_OER; // Output Enable Register - AT91_REG PIOC_ODR; // Output Disable Registerr - AT91_REG PIOC_OSR; // Output Status Register - AT91_REG Reserved21[1]; // - AT91_REG PIOC_IFER; // Input Filter Enable Register - AT91_REG PIOC_IFDR; // Input Filter Disable Register - AT91_REG PIOC_IFSR; // Input Filter Status Register - AT91_REG Reserved22[1]; // - AT91_REG PIOC_SODR; // Set Output Data Register - AT91_REG PIOC_CODR; // Clear Output Data Register - AT91_REG PIOC_ODSR; // Output Data Status Register - AT91_REG PIOC_PDSR; // Pin Data Status Register - AT91_REG PIOC_IER; // Interrupt Enable Register - AT91_REG PIOC_IDR; // Interrupt Disable Register - AT91_REG PIOC_IMR; // Interrupt Mask Register - AT91_REG PIOC_ISR; // Interrupt Status Register - AT91_REG PIOC_MDER; // Multi-driver Enable Register - AT91_REG PIOC_MDDR; // Multi-driver Disable Register - AT91_REG PIOC_MDSR; // Multi-driver Status Register - AT91_REG Reserved23[1]; // - AT91_REG PIOC_PPUDR; // Pull-up Disable Register - AT91_REG PIOC_PPUER; // Pull-up Enable Register - AT91_REG PIOC_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved24[1]; // - AT91_REG PIOC_ASR; // Select A Register - AT91_REG PIOC_BSR; // Select B Register - AT91_REG PIOC_ABSR; // AB Select Status Register - AT91_REG Reserved25[9]; // - AT91_REG PIOC_OWER; // Output Write Enable Register - AT91_REG PIOC_OWDR; // Output Write Disable Register - AT91_REG PIOC_OWSR; // Output Write Status Register - AT91_REG Reserved26[85]; // - AT91_REG PIOD_PER; // PIO Enable Register - AT91_REG PIOD_PDR; // PIO Disable Register - AT91_REG PIOD_PSR; // PIO Status Register - AT91_REG Reserved27[1]; // - AT91_REG PIOD_OER; // Output Enable Register - AT91_REG PIOD_ODR; // Output Disable Registerr - AT91_REG PIOD_OSR; // Output Status Register - AT91_REG Reserved28[1]; // - AT91_REG PIOD_IFER; // Input Filter Enable Register - AT91_REG PIOD_IFDR; // Input Filter Disable Register - AT91_REG PIOD_IFSR; // Input Filter Status Register - AT91_REG Reserved29[1]; // - AT91_REG PIOD_SODR; // Set Output Data Register - AT91_REG PIOD_CODR; // Clear Output Data Register - AT91_REG PIOD_ODSR; // Output Data Status Register - AT91_REG PIOD_PDSR; // Pin Data Status Register - AT91_REG PIOD_IER; // Interrupt Enable Register - AT91_REG PIOD_IDR; // Interrupt Disable Register - AT91_REG PIOD_IMR; // Interrupt Mask Register - AT91_REG PIOD_ISR; // Interrupt Status Register - AT91_REG PIOD_MDER; // Multi-driver Enable Register - AT91_REG PIOD_MDDR; // Multi-driver Disable Register - AT91_REG PIOD_MDSR; // Multi-driver Status Register - AT91_REG Reserved30[1]; // - AT91_REG PIOD_PPUDR; // Pull-up Disable Register - AT91_REG PIOD_PPUER; // Pull-up Enable Register - AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved31[1]; // - AT91_REG PIOD_ASR; // Select A Register - AT91_REG PIOD_BSR; // Select B Register - AT91_REG PIOD_ABSR; // AB Select Status Register - AT91_REG Reserved32[9]; // - AT91_REG PIOD_OWER; // Output Write Enable Register - AT91_REG PIOD_OWDR; // Output Write Disable Register - AT91_REG PIOD_OWSR; // Output Write Status Register - AT91_REG Reserved33[85]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved34[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved35[1]; // - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG CKGR_PLLAR; // PLL A Register - AT91_REG CKGR_PLLBR; // PLL B Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved36[3]; // - AT91_REG PMC_PCKR[8]; // Programmable Clock Register - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved37[36]; // - AT91_REG ST_CR; // Control Register - AT91_REG ST_PIMR; // Period Interval Mode Register - AT91_REG ST_WDMR; // Watchdog Mode Register - AT91_REG ST_RTMR; // Real-time Mode Register - AT91_REG ST_SR; // Status Register - AT91_REG ST_IER; // Interrupt Enable Register - AT91_REG ST_IDR; // Interrupt Disable Register - AT91_REG ST_IMR; // Interrupt Mask Register - AT91_REG ST_RTAR; // Real-time Alarm Register - AT91_REG ST_CRTR; // Current Real-time Register - AT91_REG Reserved38[54]; // - AT91_REG RTC_CR; // Control Register - AT91_REG RTC_MR; // Mode Register - AT91_REG RTC_TIMR; // Time Register - AT91_REG RTC_CALR; // Calendar Register - AT91_REG RTC_TIMALR; // Time Alarm Register - AT91_REG RTC_CALALR; // Calendar Alarm Register - AT91_REG RTC_SR; // Status Register - AT91_REG RTC_SCCR; // Status Clear Command Register - AT91_REG RTC_IER; // Interrupt Enable Register - AT91_REG RTC_IDR; // Interrupt Disable Register - AT91_REG RTC_IMR; // Interrupt Mask Register - AT91_REG RTC_VER; // Valid Entry Register - AT91_REG Reserved39[52]; // - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved40[1]; // - AT91_REG MC_PUIA[16]; // MC Protection Unit Area - AT91_REG MC_PUP; // MC Protection Unit Peripherals - AT91_REG MC_PUER; // MC Protection Unit Enable Register - AT91_REG Reserved41[2]; // - AT91_REG EBI_CSA; // Chip Select Assignment Register - AT91_REG EBI_CFGR; // Configuration Register - AT91_REG Reserved42[2]; // - AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register - AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register - AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register - AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register - AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register - AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register - AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register - AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register - AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register - AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register - AT91_REG Reserved43[3]; // - AT91_REG EBI_BFC_MR; // BFC Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[1]; // - AT91_REG MC_PUIA[16]; // MC Protection Unit Area - AT91_REG MC_PUP; // MC Protection Unit Peripherals - AT91_REG MC_PUER; // MC Protection Unit Enable Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_MPU ((unsigned int) 0x1 << 2) // (MC) Memory protection Unit Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- -#define AT91C_MC_PROT ((unsigned int) 0x3 << 0) // (MC) Protection -#define AT91C_MC_PROT_PNAUNA ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access -#define AT91C_MC_PROT_PRWUNA ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access -#define AT91C_MC_PROT_PRWURO ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only -#define AT91C_MC_PROT_PRWURW ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write -#define AT91C_MC_SIZE ((unsigned int) 0xF << 4) // (MC) Internal Area Size -#define AT91C_MC_SIZE_1KB ((unsigned int) 0x0 << 4) // (MC) Area size 1KByte -#define AT91C_MC_SIZE_2KB ((unsigned int) 0x1 << 4) // (MC) Area size 2KByte -#define AT91C_MC_SIZE_4KB ((unsigned int) 0x2 << 4) // (MC) Area size 4KByte -#define AT91C_MC_SIZE_8KB ((unsigned int) 0x3 << 4) // (MC) Area size 8KByte -#define AT91C_MC_SIZE_16KB ((unsigned int) 0x4 << 4) // (MC) Area size 16KByte -#define AT91C_MC_SIZE_32KB ((unsigned int) 0x5 << 4) // (MC) Area size 32KByte -#define AT91C_MC_SIZE_64KB ((unsigned int) 0x6 << 4) // (MC) Area size 64KByte -#define AT91C_MC_SIZE_128KB ((unsigned int) 0x7 << 4) // (MC) Area size 128KByte -#define AT91C_MC_SIZE_256KB ((unsigned int) 0x8 << 4) // (MC) Area size 256KByte -#define AT91C_MC_SIZE_512KB ((unsigned int) 0x9 << 4) // (MC) Area size 512KByte -#define AT91C_MC_SIZE_1MB ((unsigned int) 0xA << 4) // (MC) Area size 1MByte -#define AT91C_MC_SIZE_2MB ((unsigned int) 0xB << 4) // (MC) Area size 2MByte -#define AT91C_MC_SIZE_4MB ((unsigned int) 0xC << 4) // (MC) Area size 4MByte -#define AT91C_MC_SIZE_8MB ((unsigned int) 0xD << 4) // (MC) Area size 8MByte -#define AT91C_MC_SIZE_16MB ((unsigned int) 0xE << 4) // (MC) Area size 16MByte -#define AT91C_MC_SIZE_64MB ((unsigned int) 0xF << 4) // (MC) Area size 64MByte -#define AT91C_MC_BA ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address -// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- -#define AT91C_MC_PUEB ((unsigned int) 0x1 << 0) // (MC) Protection Unit enable Bit - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface -// ***************************************************************************** -typedef struct _AT91S_RTC { - AT91_REG RTC_CR; // Control Register - AT91_REG RTC_MR; // Mode Register - AT91_REG RTC_TIMR; // Time Register - AT91_REG RTC_CALR; // Calendar Register - AT91_REG RTC_TIMALR; // Time Alarm Register - AT91_REG RTC_CALALR; // Calendar Alarm Register - AT91_REG RTC_SR; // Status Register - AT91_REG RTC_SCCR; // Status Clear Command Register - AT91_REG RTC_IER; // Interrupt Enable Register - AT91_REG RTC_IDR; // Interrupt Disable Register - AT91_REG RTC_IMR; // Interrupt Mask Register - AT91_REG RTC_VER; // Valid Entry Register -} AT91S_RTC, *AT91PS_RTC; - -// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- -#define AT91C_RTC_UPDTIM ((unsigned int) 0x1 << 0) // (RTC) Update Request Time Register -#define AT91C_RTC_UPDCAL ((unsigned int) 0x1 << 1) // (RTC) Update Request Calendar Register -#define AT91C_RTC_TIMEVSEL ((unsigned int) 0x3 << 8) // (RTC) Time Event Selection -#define AT91C_RTC_TIMEVSEL_MINUTE ((unsigned int) 0x0 << 8) // (RTC) Minute change. -#define AT91C_RTC_TIMEVSEL_HOUR ((unsigned int) 0x1 << 8) // (RTC) Hour change. -#define AT91C_RTC_TIMEVSEL_DAY24 ((unsigned int) 0x2 << 8) // (RTC) Every day at midnight. -#define AT91C_RTC_TIMEVSEL_DAY12 ((unsigned int) 0x3 << 8) // (RTC) Every day at noon. -#define AT91C_RTC_CALEVSEL ((unsigned int) 0x3 << 16) // (RTC) Calendar Event Selection -#define AT91C_RTC_CALEVSEL_WEEK ((unsigned int) 0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). -#define AT91C_RTC_CALEVSEL_MONTH ((unsigned int) 0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). -#define AT91C_RTC_CALEVSEL_YEAR ((unsigned int) 0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). -// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- -#define AT91C_RTC_HRMOD ((unsigned int) 0x1 << 0) // (RTC) 12-24 hour Mode -// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- -#define AT91C_RTC_SEC ((unsigned int) 0x7F << 0) // (RTC) Current Second -#define AT91C_RTC_MIN ((unsigned int) 0x7F << 8) // (RTC) Current Minute -#define AT91C_RTC_HOUR ((unsigned int) 0x1F << 16) // (RTC) Current Hour -#define AT91C_RTC_AMPM ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator -// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- -#define AT91C_RTC_CENT ((unsigned int) 0x3F << 0) // (RTC) Current Century -#define AT91C_RTC_YEAR ((unsigned int) 0xFF << 8) // (RTC) Current Year -#define AT91C_RTC_MONTH ((unsigned int) 0x1F << 16) // (RTC) Current Month -#define AT91C_RTC_DAY ((unsigned int) 0x7 << 21) // (RTC) Current Day -#define AT91C_RTC_DATE ((unsigned int) 0x3F << 24) // (RTC) Current Date -// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- -#define AT91C_RTC_SECEN ((unsigned int) 0x1 << 7) // (RTC) Second Alarm Enable -#define AT91C_RTC_MINEN ((unsigned int) 0x1 << 15) // (RTC) Minute Alarm -#define AT91C_RTC_HOUREN ((unsigned int) 0x1 << 23) // (RTC) Current Hour -// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- -#define AT91C_RTC_MONTHEN ((unsigned int) 0x1 << 23) // (RTC) Month Alarm Enable -#define AT91C_RTC_DATEEN ((unsigned int) 0x1 << 31) // (RTC) Date Alarm Enable -// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- -#define AT91C_RTC_ACKUPD ((unsigned int) 0x1 << 0) // (RTC) Acknowledge for Update -#define AT91C_RTC_ALARM ((unsigned int) 0x1 << 1) // (RTC) Alarm Flag -#define AT91C_RTC_SECEV ((unsigned int) 0x1 << 2) // (RTC) Second Event -#define AT91C_RTC_TIMEV ((unsigned int) 0x1 << 3) // (RTC) Time Event -#define AT91C_RTC_CALEV ((unsigned int) 0x1 << 4) // (RTC) Calendar event -// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- -// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- -// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- -// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- -// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- -#define AT91C_RTC_NVTIM ((unsigned int) 0x1 << 0) // (RTC) Non valid Time -#define AT91C_RTC_NVCAL ((unsigned int) 0x1 << 1) // (RTC) Non valid Calendar -#define AT91C_RTC_NVTIMALR ((unsigned int) 0x1 << 2) // (RTC) Non valid time Alarm -#define AT91C_RTC_NVCALALR ((unsigned int) 0x1 << 3) // (RTC) Nonvalid Calendar Alarm - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Timer Interface -// ***************************************************************************** -typedef struct _AT91S_ST { - AT91_REG ST_CR; // Control Register - AT91_REG ST_PIMR; // Period Interval Mode Register - AT91_REG ST_WDMR; // Watchdog Mode Register - AT91_REG ST_RTMR; // Real-time Mode Register - AT91_REG ST_SR; // Status Register - AT91_REG ST_IER; // Interrupt Enable Register - AT91_REG ST_IDR; // Interrupt Disable Register - AT91_REG ST_IMR; // Interrupt Mask Register - AT91_REG ST_RTAR; // Real-time Alarm Register - AT91_REG ST_CRTR; // Current Real-time Register -} AT91S_ST, *AT91PS_ST; - -// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- -#define AT91C_ST_WDRST ((unsigned int) 0x1 << 0) // (ST) Watchdog Timer Restart -// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- -#define AT91C_ST_PIV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart -// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- -#define AT91C_ST_WDV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart -#define AT91C_ST_RSTEN ((unsigned int) 0x1 << 16) // (ST) Reset Enable -#define AT91C_ST_EXTEN ((unsigned int) 0x1 << 17) // (ST) External Signal Assertion Enable -// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- -#define AT91C_ST_RTPRES ((unsigned int) 0xFFFF << 0) // (ST) Real-time Timer Prescaler Value -// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- -#define AT91C_ST_PITS ((unsigned int) 0x1 << 0) // (ST) Period Interval Timer Interrupt -#define AT91C_ST_WDOVF ((unsigned int) 0x1 << 1) // (ST) Watchdog Overflow -#define AT91C_ST_RTTINC ((unsigned int) 0x1 << 2) // (ST) Real-time Timer Increment -#define AT91C_ST_ALMS ((unsigned int) 0x1 << 3) // (ST) Alarm Status -// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- -// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- -// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- -// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- -#define AT91C_ST_ALMV ((unsigned int) 0xFFFFF << 0) // (ST) Alarm Value Value -// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- -#define AT91C_ST_CRTV ((unsigned int) 0xFFFFF << 0) // (ST) Current Real-time Value - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[5]; // - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved2[3]; // - AT91_REG PMC_PCKR[8]; // Programmable Clock Register - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) // (PMC) USB Device Port Clock -#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend -#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) // (PMC) USB Host Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected -#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division -#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same -#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock -#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is three times faster than the master clock -#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) // (PMC) The processor clock is four times faster than the master clock -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask -#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG CKGR_PLLAR; // PLL A Register - AT91_REG CKGR_PLLBR; // PLL B Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) // (CKGR) Oscillator Test -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- -#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL A Counter -#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) // (CKGR) PLL A Output Frequency Range -#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier -#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) // (CKGR) PLL A Source -// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL B Counter -#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) // (CKGR) PLL B Output Frequency Range -#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) // (CKGR) PLL B Multiplier -#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) // (CKGR) Divider for USB Ports -#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) // (CKGR) PLL Use - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_C1R; // Chip ID1 Register - AT91_REG DBGU_C2R; // Chip ID2 Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral Data Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive -#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG SSC_RC0R; // Receive Compare 0 Register - AT91_REG SSC_RC1R; // Receive Compare 1 Register - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved2[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG US_XXR; // XON_XOFF Register - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved1[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG TWI_SMR; // Slave Mode Register - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved0[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled -#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- -#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read -#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access -#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Multimedia Card Interface -// ***************************************************************************** -typedef struct _AT91S_MCI { - AT91_REG MCI_CR; // MCI Control Register - AT91_REG MCI_MR; // MCI Mode Register - AT91_REG MCI_DTOR; // MCI Data Timeout Register - AT91_REG MCI_SDCR; // MCI SD Card Register - AT91_REG MCI_ARGR; // MCI Argument Register - AT91_REG MCI_CMDR; // MCI Command Register - AT91_REG Reserved0[2]; // - AT91_REG MCI_RSPR[4]; // MCI Response Register - AT91_REG MCI_RDR; // MCI Receive Data Register - AT91_REG MCI_TDR; // MCI Transmit Data Register - AT91_REG Reserved1[2]; // - AT91_REG MCI_SR; // MCI Status Register - AT91_REG MCI_IER; // MCI Interrupt Enable Register - AT91_REG MCI_IDR; // MCI Interrupt Disable Register - AT91_REG MCI_IMR; // MCI Interrupt Mask Register - AT91_REG Reserved2[44]; // - AT91_REG MCI_RPR; // Receive Pointer Register - AT91_REG MCI_RCR; // Receive Counter Register - AT91_REG MCI_TPR; // Transmit Pointer Register - AT91_REG MCI_TCR; // Transmit Counter Register - AT91_REG MCI_RNPR; // Receive Next Pointer Register - AT91_REG MCI_RNCR; // Receive Next Counter Register - AT91_REG MCI_TNPR; // Transmit Next Pointer Register - AT91_REG MCI_TNCR; // Transmit Next Counter Register - AT91_REG MCI_PTCR; // PDC Transfer Control Register - AT91_REG MCI_PTSR; // PDC Transfer Status Register -} AT91S_MCI, *AT91PS_MCI; - -// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- -#define AT91C_MCI_MCIEN ((unsigned int) 0x1 << 0) // (MCI) Multimedia Interface Enable -#define AT91C_MCI_MCIDIS ((unsigned int) 0x1 << 1) // (MCI) Multimedia Interface Disable -#define AT91C_MCI_PWSEN ((unsigned int) 0x1 << 2) // (MCI) Power Save Mode Enable -#define AT91C_MCI_PWSDIS ((unsigned int) 0x1 << 3) // (MCI) Power Save Mode Disable -// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- -#define AT91C_MCI_CLKDIV ((unsigned int) 0x1 << 0) // (MCI) Clock Divider -#define AT91C_MCI_PWSDIV ((unsigned int) 0x1 << 8) // (MCI) Power Saving Divider -#define AT91C_MCI_PDCPADV ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value -#define AT91C_MCI_PDCMODE ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode -#define AT91C_MCI_BLKLEN ((unsigned int) 0x1 << 18) // (MCI) Data Block Length -// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- -#define AT91C_MCI_DTOCYC ((unsigned int) 0x1 << 0) // (MCI) Data Timeout Cycle Number -#define AT91C_MCI_DTOMUL ((unsigned int) 0x7 << 4) // (MCI) Data Timeout Multiplier -#define AT91C_MCI_DTOMUL_1 ((unsigned int) 0x0 << 4) // (MCI) DTOCYC x 1 -#define AT91C_MCI_DTOMUL_16 ((unsigned int) 0x1 << 4) // (MCI) DTOCYC x 16 -#define AT91C_MCI_DTOMUL_128 ((unsigned int) 0x2 << 4) // (MCI) DTOCYC x 128 -#define AT91C_MCI_DTOMUL_256 ((unsigned int) 0x3 << 4) // (MCI) DTOCYC x 256 -#define AT91C_MCI_DTOMUL_1024 ((unsigned int) 0x4 << 4) // (MCI) DTOCYC x 1024 -#define AT91C_MCI_DTOMUL_4096 ((unsigned int) 0x5 << 4) // (MCI) DTOCYC x 4096 -#define AT91C_MCI_DTOMUL_65536 ((unsigned int) 0x6 << 4) // (MCI) DTOCYC x 65536 -#define AT91C_MCI_DTOMUL_1048576 ((unsigned int) 0x7 << 4) // (MCI) DTOCYC x 1048576 -// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- -#define AT91C_MCI_SCDSEL ((unsigned int) 0x1 << 0) // (MCI) SD Card Selector -#define AT91C_MCI_SCDBUS ((unsigned int) 0x1 << 7) // (MCI) SD Card Bus Width -// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- -#define AT91C_MCI_CMDNB ((unsigned int) 0x1F << 0) // (MCI) Command Number -#define AT91C_MCI_RSPTYP ((unsigned int) 0x3 << 6) // (MCI) Response Type -#define AT91C_MCI_RSPTYP_NO ((unsigned int) 0x0 << 6) // (MCI) No response -#define AT91C_MCI_RSPTYP_48 ((unsigned int) 0x1 << 6) // (MCI) 48-bit response -#define AT91C_MCI_RSPTYP_136 ((unsigned int) 0x2 << 6) // (MCI) 136-bit response -#define AT91C_MCI_SPCMD ((unsigned int) 0x7 << 8) // (MCI) Special CMD -#define AT91C_MCI_SPCMD_NONE ((unsigned int) 0x0 << 8) // (MCI) Not a special CMD -#define AT91C_MCI_SPCMD_INIT ((unsigned int) 0x1 << 8) // (MCI) Initialization CMD -#define AT91C_MCI_SPCMD_SYNC ((unsigned int) 0x2 << 8) // (MCI) Synchronized CMD -#define AT91C_MCI_SPCMD_IT_CMD ((unsigned int) 0x4 << 8) // (MCI) Interrupt command -#define AT91C_MCI_SPCMD_IT_REP ((unsigned int) 0x5 << 8) // (MCI) Interrupt response -#define AT91C_MCI_OPDCMD ((unsigned int) 0x1 << 11) // (MCI) Open Drain Command -#define AT91C_MCI_MAXLAT ((unsigned int) 0x1 << 12) // (MCI) Maximum Latency for Command to respond -#define AT91C_MCI_TRCMD ((unsigned int) 0x3 << 16) // (MCI) Transfer CMD -#define AT91C_MCI_TRCMD_NO ((unsigned int) 0x0 << 16) // (MCI) No transfer -#define AT91C_MCI_TRCMD_START ((unsigned int) 0x1 << 16) // (MCI) Start transfer -#define AT91C_MCI_TRCMD_STOP ((unsigned int) 0x2 << 16) // (MCI) Stop transfer -#define AT91C_MCI_TRDIR ((unsigned int) 0x1 << 18) // (MCI) Transfer Direction -#define AT91C_MCI_TRTYP ((unsigned int) 0x3 << 19) // (MCI) Transfer Type -#define AT91C_MCI_TRTYP_BLOCK ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type -#define AT91C_MCI_TRTYP_MULTIPLE ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type -#define AT91C_MCI_TRTYP_STREAM ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type -// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- -#define AT91C_MCI_CMDRDY ((unsigned int) 0x1 << 0) // (MCI) Command Ready flag -#define AT91C_MCI_RXRDY ((unsigned int) 0x1 << 1) // (MCI) RX Ready flag -#define AT91C_MCI_TXRDY ((unsigned int) 0x1 << 2) // (MCI) TX Ready flag -#define AT91C_MCI_BLKE ((unsigned int) 0x1 << 3) // (MCI) Data Block Transfer Ended flag -#define AT91C_MCI_DTIP ((unsigned int) 0x1 << 4) // (MCI) Data Transfer in Progress flag -#define AT91C_MCI_NOTBUSY ((unsigned int) 0x1 << 5) // (MCI) Data Line Not Busy flag -#define AT91C_MCI_ENDRX ((unsigned int) 0x1 << 6) // (MCI) End of RX Buffer flag -#define AT91C_MCI_ENDTX ((unsigned int) 0x1 << 7) // (MCI) End of TX Buffer flag -#define AT91C_MCI_RXBUFF ((unsigned int) 0x1 << 14) // (MCI) RX Buffer Full flag -#define AT91C_MCI_TXBUFE ((unsigned int) 0x1 << 15) // (MCI) TX Buffer Empty flag -#define AT91C_MCI_RINDE ((unsigned int) 0x1 << 16) // (MCI) Response Index Error flag -#define AT91C_MCI_RDIRE ((unsigned int) 0x1 << 17) // (MCI) Response Direction Error flag -#define AT91C_MCI_RCRCE ((unsigned int) 0x1 << 18) // (MCI) Response CRC Error flag -#define AT91C_MCI_RENDE ((unsigned int) 0x1 << 19) // (MCI) Response End Bit Error flag -#define AT91C_MCI_RTOE ((unsigned int) 0x1 << 20) // (MCI) Response Time-out Error flag -#define AT91C_MCI_DCRCE ((unsigned int) 0x1 << 21) // (MCI) data CRC Error flag -#define AT91C_MCI_DTOE ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag -#define AT91C_MCI_OVRE ((unsigned int) 0x1 << 30) // (MCI) Overrun flag -#define AT91C_MCI_UNRE ((unsigned int) 0x1 << 31) // (MCI) Underrun flag -// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- -// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- -// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register - AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt -#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 -#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Host Interface -// ***************************************************************************** -typedef struct _AT91S_UHP { - AT91_REG UHP_HcRevision; // Revision - AT91_REG UHP_HcControl; // Operating modes for the Host Controller - AT91_REG UHP_HcCommandStatus; // Command & status Register - AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register - AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register - AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register - AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area - AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor - AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list - AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register - AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list - AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list - AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor - AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs - AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame - AT91_REG UHP_HcFmNumber; // Frame number - AT91_REG UHP_HcPeriodicStart; // Periodic Start - AT91_REG UHP_HcLSThreshold; // LS Threshold - AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A - AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B - AT91_REG UHP_HcRhStatus; // Root Hub Status register - AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register -} AT91S_UHP, *AT91PS_UHP; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_CTL; // Network Control Register - AT91_REG EMAC_CFG; // Network Configuration Register - AT91_REG EMAC_SR; // Network Status Register - AT91_REG EMAC_TAR; // Transmit Address Register - AT91_REG EMAC_TCR; // Transmit Control Register - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG Reserved0[1]; // - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG Reserved1[2]; // - AT91_REG EMAC_FRA; // Frames Transmitted OK Register - AT91_REG EMAC_SCOL; // Single Collision Frame Register - AT91_REG EMAC_MCOL; // Multiple Collision Frame Register - AT91_REG EMAC_OK; // Frames Received OK Register - AT91_REG EMAC_SEQE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTE; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_TUE; // Transmit Underrun Error Register - AT91_REG EMAC_CDE; // Code Error Register - AT91_REG EMAC_ELR; // Excessive Length Error Register - AT91_REG EMAC_RJB; // Receive Jabber Register - AT91_REG EMAC_USF; // Undersize Frame Register - AT91_REG EMAC_SQEE; // SQE Test Error Register - AT91_REG EMAC_DRFC; // Discarded RX Frame Register - AT91_REG Reserved2[3]; // - AT91_REG EMAC_HSH; // Hash Address High[63:32] - AT91_REG EMAC_HSL; // Hash Address Low[31:0] - AT91_REG EMAC_SA1L; // Specific Address 1 Low, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 High, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Low, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 High, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Low, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 High, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Low, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 High, Last 2 bytesr -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_CTL : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) // (EMAC) Bit rate. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- -#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) // (EMAC) -#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) // (EMAC) -#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR External Bus Interface -// ***************************************************************************** -typedef struct _AT91S_EBI { - AT91_REG EBI_CSA; // Chip Select Assignment Register - AT91_REG EBI_CFGR; // Configuration Register -} AT91S_EBI, *AT91PS_EBI; - -// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- -#define AT91C_EBI_CS0A ((unsigned int) 0x1 << 0) // (EBI) Chip Select 0 Assignment -#define AT91C_EBI_CS0A_SMC ((unsigned int) 0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller. -#define AT91C_EBI_CS0A_BFC ((unsigned int) 0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. -#define AT91C_EBI_CS1A ((unsigned int) 0x1 << 1) // (EBI) Chip Select 1 Assignment -#define AT91C_EBI_CS1A_SMC ((unsigned int) 0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. -#define AT91C_EBI_CS1A_SDRAMC ((unsigned int) 0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. -#define AT91C_EBI_CS3A ((unsigned int) 0x1 << 3) // (EBI) Chip Select 3 Assignment -#define AT91C_EBI_CS3A_SMC ((unsigned int) 0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. -#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. -#define AT91C_EBI_CS4A ((unsigned int) 0x1 << 4) // (EBI) Chip Select 4 Assignment -#define AT91C_EBI_CS4A_SMC ((unsigned int) 0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. -#define AT91C_EBI_CS4A_SMC_CompactFlash ((unsigned int) 0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. -// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- -#define AT91C_EBI_DBPUC ((unsigned int) 0x1 << 0) // (EBI) Data Bus Pull-Up Configuration -#define AT91C_EBI_EBSEN ((unsigned int) 0x1 << 1) // (EBI) Bus Sharing Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface -// ***************************************************************************** -typedef struct _AT91S_SMC2 { - AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register -} AT91S_SMC2, *AT91PS_SMC2; - -// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- -#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) // (SMC2) Number of Wait States -#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) // (SMC2) Wait State Enable -#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) // (SMC2) Data Float Time -#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) // (SMC2) Byte Access Type -#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) // (SMC2) Data Bus Width -#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) // (SMC2) 16-bit. -#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) // (SMC2) 8-bit. -#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) // (SMC2) Data Read Protocol -#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) // (SMC2) Address to Chip Select Setup -#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. -#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access. -#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access. -#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access. -#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) // (SMC2) Read and Write Signal Setup Time -#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) // (SMC2) Read and Write Signal Hold Time - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR SDRAM Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SDRC { - AT91_REG SDRC_MR; // SDRAM Controller Mode Register - AT91_REG SDRC_TR; // SDRAM Controller Refresh Timer Register - AT91_REG SDRC_CR; // SDRAM Controller Configuration Register - AT91_REG SDRC_SRR; // SDRAM Controller Self Refresh Register - AT91_REG SDRC_LPR; // SDRAM Controller Low Power Register - AT91_REG SDRC_IER; // SDRAM Controller Interrupt Enable Register - AT91_REG SDRC_IDR; // SDRAM Controller Interrupt Disable Register - AT91_REG SDRC_IMR; // SDRAM Controller Interrupt Mask Register - AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register -} AT91S_SDRC, *AT91PS_SDRC; - -// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- -#define AT91C_SDRC_MODE ((unsigned int) 0xF << 0) // (SDRC) Mode -#define AT91C_SDRC_MODE_NORMAL_CMD ((unsigned int) 0x0) // (SDRC) Normal Mode -#define AT91C_SDRC_MODE_NOP_CMD ((unsigned int) 0x1) // (SDRC) NOP Command -#define AT91C_SDRC_MODE_PRCGALL_CMD ((unsigned int) 0x2) // (SDRC) All Banks Precharge Command -#define AT91C_SDRC_MODE_LMR_CMD ((unsigned int) 0x3) // (SDRC) Load Mode Register Command -#define AT91C_SDRC_MODE_RFSH_CMD ((unsigned int) 0x4) // (SDRC) Refresh Command -#define AT91C_SDRC_DBW ((unsigned int) 0x1 << 4) // (SDRC) Data Bus Width -#define AT91C_SDRC_DBW_32_BITS ((unsigned int) 0x0 << 4) // (SDRC) 32 Bits datas bus -#define AT91C_SDRC_DBW_16_BITS ((unsigned int) 0x1 << 4) // (SDRC) 16 Bits datas bus -// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- -#define AT91C_SDRC_COUNT ((unsigned int) 0xFFF << 0) // (SDRC) Refresh Counter -// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- -#define AT91C_SDRC_NC ((unsigned int) 0x3 << 0) // (SDRC) Number of Column Bits -#define AT91C_SDRC_NC_8 ((unsigned int) 0x0) // (SDRC) 8 Bits -#define AT91C_SDRC_NC_9 ((unsigned int) 0x1) // (SDRC) 9 Bits -#define AT91C_SDRC_NC_10 ((unsigned int) 0x2) // (SDRC) 10 Bits -#define AT91C_SDRC_NC_11 ((unsigned int) 0x3) // (SDRC) 11 Bits -#define AT91C_SDRC_NR ((unsigned int) 0x3 << 2) // (SDRC) Number of Row Bits -#define AT91C_SDRC_NR_11 ((unsigned int) 0x0 << 2) // (SDRC) 11 Bits -#define AT91C_SDRC_NR_12 ((unsigned int) 0x1 << 2) // (SDRC) 12 Bits -#define AT91C_SDRC_NR_13 ((unsigned int) 0x2 << 2) // (SDRC) 13 Bits -#define AT91C_SDRC_NB ((unsigned int) 0x1 << 4) // (SDRC) Number of Banks -#define AT91C_SDRC_NB_2_BANKS ((unsigned int) 0x0 << 4) // (SDRC) 2 banks -#define AT91C_SDRC_NB_4_BANKS ((unsigned int) 0x1 << 4) // (SDRC) 4 banks -#define AT91C_SDRC_CAS ((unsigned int) 0x3 << 5) // (SDRC) CAS Latency -#define AT91C_SDRC_CAS_2 ((unsigned int) 0x2 << 5) // (SDRC) 2 cycles -#define AT91C_SDRC_TWR ((unsigned int) 0xF << 7) // (SDRC) Number of Write Recovery Time Cycles -#define AT91C_SDRC_TRC ((unsigned int) 0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles -#define AT91C_SDRC_TRP ((unsigned int) 0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles -#define AT91C_SDRC_TRCD ((unsigned int) 0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles -#define AT91C_SDRC_TRAS ((unsigned int) 0xF << 23) // (SDRC) Number of RAS Active Time Cycles -#define AT91C_SDRC_TXSR ((unsigned int) 0xF << 27) // (SDRC) Number of Command Recovery Time Cycles -// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- -#define AT91C_SDRC_SRCB ((unsigned int) 0x1 << 0) // (SDRC) Self-refresh Command Bit -// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- -#define AT91C_SDRC_LPCB ((unsigned int) 0x1 << 0) // (SDRC) Low-power Command Bit -// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- -#define AT91C_SDRC_RES ((unsigned int) 0x1 << 0) // (SDRC) Refresh Error Status -// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- -// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- -// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Burst Flash Controller Interface -// ***************************************************************************** -typedef struct _AT91S_BFC { - AT91_REG BFC_MR; // BFC Mode Register -} AT91S_BFC, *AT91PS_BFC; - -// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- -#define AT91C_BFC_BFCOM ((unsigned int) 0x3 << 0) // (BFC) Burst Flash Controller Operating Mode -#define AT91C_BFC_BFCOM_DISABLED ((unsigned int) 0x0) // (BFC) NPCS0 is driven by the SMC or remains high. -#define AT91C_BFC_BFCOM_ASYNC ((unsigned int) 0x1) // (BFC) Asynchronous -#define AT91C_BFC_BFCOM_BURST_READ ((unsigned int) 0x2) // (BFC) Burst Read -#define AT91C_BFC_BFCC ((unsigned int) 0x3 << 2) // (BFC) Burst Flash Controller Operating Mode -#define AT91C_BFC_BFCC_MCK ((unsigned int) 0x1 << 2) // (BFC) Master Clock. -#define AT91C_BFC_BFCC_MCK_DIV_2 ((unsigned int) 0x2 << 2) // (BFC) Master Clock divided by 2. -#define AT91C_BFC_BFCC_MCK_DIV_4 ((unsigned int) 0x3 << 2) // (BFC) Master Clock divided by 4. -#define AT91C_BFC_AVL ((unsigned int) 0xF << 4) // (BFC) Address Valid Latency -#define AT91C_BFC_PAGES ((unsigned int) 0x7 << 8) // (BFC) Page Size -#define AT91C_BFC_PAGES_NO_PAGE ((unsigned int) 0x0 << 8) // (BFC) No page handling. -#define AT91C_BFC_PAGES_16 ((unsigned int) 0x1 << 8) // (BFC) 16 bytes page size. -#define AT91C_BFC_PAGES_32 ((unsigned int) 0x2 << 8) // (BFC) 32 bytes page size. -#define AT91C_BFC_PAGES_64 ((unsigned int) 0x3 << 8) // (BFC) 64 bytes page size. -#define AT91C_BFC_PAGES_128 ((unsigned int) 0x4 << 8) // (BFC) 128 bytes page size. -#define AT91C_BFC_PAGES_256 ((unsigned int) 0x5 << 8) // (BFC) 256 bytes page size. -#define AT91C_BFC_PAGES_512 ((unsigned int) 0x6 << 8) // (BFC) 512 bytes page size. -#define AT91C_BFC_PAGES_1024 ((unsigned int) 0x7 << 8) // (BFC) 1024 bytes page size. -#define AT91C_BFC_OEL ((unsigned int) 0x3 << 12) // (BFC) Output Enable Latency -#define AT91C_BFC_BAAEN ((unsigned int) 0x1 << 16) // (BFC) Burst Address Advance Enable -#define AT91C_BFC_BFOEH ((unsigned int) 0x1 << 17) // (BFC) Burst Flash Output Enable Handling -#define AT91C_BFC_MUXEN ((unsigned int) 0x1 << 18) // (BFC) Multiplexed Bus Enable -#define AT91C_BFC_RDYEN ((unsigned int) 0x1 << 19) // (BFC) Ready Enable Mode - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91RM9200 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_PUER ((AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_PUP ((AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals -#define AT91C_MC_PUIA ((AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for RTC peripheral ========== -#define AT91C_RTC_IMR ((AT91_REG *) 0xFFFFFE28) // (RTC) Interrupt Mask Register -#define AT91C_RTC_IER ((AT91_REG *) 0xFFFFFE20) // (RTC) Interrupt Enable Register -#define AT91C_RTC_SR ((AT91_REG *) 0xFFFFFE18) // (RTC) Status Register -#define AT91C_RTC_TIMALR ((AT91_REG *) 0xFFFFFE10) // (RTC) Time Alarm Register -#define AT91C_RTC_TIMR ((AT91_REG *) 0xFFFFFE08) // (RTC) Time Register -#define AT91C_RTC_CR ((AT91_REG *) 0xFFFFFE00) // (RTC) Control Register -#define AT91C_RTC_VER ((AT91_REG *) 0xFFFFFE2C) // (RTC) Valid Entry Register -#define AT91C_RTC_IDR ((AT91_REG *) 0xFFFFFE24) // (RTC) Interrupt Disable Register -#define AT91C_RTC_SCCR ((AT91_REG *) 0xFFFFFE1C) // (RTC) Status Clear Command Register -#define AT91C_RTC_CALALR ((AT91_REG *) 0xFFFFFE14) // (RTC) Calendar Alarm Register -#define AT91C_RTC_CALR ((AT91_REG *) 0xFFFFFE0C) // (RTC) Calendar Register -#define AT91C_RTC_MR ((AT91_REG *) 0xFFFFFE04) // (RTC) Mode Register -// ========== Register definition for ST peripheral ========== -#define AT91C_ST_CRTR ((AT91_REG *) 0xFFFFFD24) // (ST) Current Real-time Register -#define AT91C_ST_IMR ((AT91_REG *) 0xFFFFFD1C) // (ST) Interrupt Mask Register -#define AT91C_ST_IER ((AT91_REG *) 0xFFFFFD14) // (ST) Interrupt Enable Register -#define AT91C_ST_RTMR ((AT91_REG *) 0xFFFFFD0C) // (ST) Real-time Mode Register -#define AT91C_ST_PIMR ((AT91_REG *) 0xFFFFFD04) // (ST) Period Interval Mode Register -#define AT91C_ST_RTAR ((AT91_REG *) 0xFFFFFD20) // (ST) Real-time Alarm Register -#define AT91C_ST_IDR ((AT91_REG *) 0xFFFFFD18) // (ST) Interrupt Disable Register -#define AT91C_ST_SR ((AT91_REG *) 0xFFFFFD10) // (ST) Status Register -#define AT91C_ST_WDMR ((AT91_REG *) 0xFFFFFD08) // (ST) Watchdog Mode Register -#define AT91C_ST_CR ((AT91_REG *) 0xFFFFFD00) // (ST) Control Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_PLLAR ((AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PIOD peripheral ========== -#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) // (PIOD) Pin Data Status Register -#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) // (PIOD) Clear Output Data Register -#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) // (PIOD) Output Write Enable Register -#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) // (PIOD) Multi-driver Enable Register -#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) // (PIOD) Interrupt Mask Register -#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) // (PIOD) Interrupt Enable Register -#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) // (PIOD) Output Data Status Register -#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) // (PIOD) Set Output Data Register -#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) // (PIOD) PIO Enable Register -#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) // (PIOD) Output Write Disable Register -#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) // (PIOD) Pull-up Enable Register -#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) // (PIOD) Multi-driver Disable Register -#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) // (PIOD) Interrupt Status Register -#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) // (PIOD) Interrupt Disable Register -#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) // (PIOD) PIO Disable Register -#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) // (PIOD) Output Disable Registerr -#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) // (PIOD) Output Write Status Register -#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) // (PIOD) AB Select Status Register -#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) // (PIOD) Select A Register -#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) // (PIOD) Pad Pull-up Status Register -#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) // (PIOD) Pull-up Disable Register -#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) // (PIOD) Multi-driver Status Register -#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) // (PIOD) PIO Status Register -#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) // (PIOD) Output Enable Register -#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) // (PIOD) Output Status Register -#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) // (PIOD) Input Filter Enable Register -#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) // (PIOD) Select B Register -#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) // (PIOD) Input Filter Disable Register -#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) // (PIOD) Input Filter Status Register -// ========== Register definition for PIOC peripheral ========== -#define AT91C_PIOC_IFDR ((AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register -#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr -#define AT91C_PIOC_ABSR ((AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register -#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register -#define AT91C_PIOC_IFSR ((AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register -#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register -#define AT91C_PIOC_ODSR ((AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register -#define AT91C_PIOC_IER ((AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register -#define AT91C_PIOC_IMR ((AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register -#define AT91C_PIOC_OWDR ((AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register -#define AT91C_PIOC_MDDR ((AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register -#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register -#define AT91C_PIOC_IDR ((AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register -#define AT91C_PIOC_ISR ((AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register -#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register -#define AT91C_PIOC_OWSR ((AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register -#define AT91C_PIOC_OWER ((AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register -#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register -#define AT91C_PIOC_PPUSR ((AT91_REG *) 0xFFFFF868) // (PIOC) Pad Pull-up Status Register -#define AT91C_PIOC_PPUDR ((AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register -#define AT91C_PIOC_MDSR ((AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register -#define AT91C_PIOC_MDER ((AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register -#define AT91C_PIOC_IFER ((AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register -#define AT91C_PIOC_OSR ((AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register -#define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register -#define AT91C_PIOC_PSR ((AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register -#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register -#define AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register -#define AT91C_PIOC_PPUER ((AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pad Pull-up Status Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_SSC2 peripheral ========== -#define AT91C_SSC2_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register -#define AT91C_SSC2_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register -#define AT91C_SSC2_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register -#define AT91C_SSC2_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register -#define AT91C_SSC2_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_SSC2) Receive Pointer Register -#define AT91C_SSC2_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register -#define AT91C_SSC2_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register -#define AT91C_SSC2_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register -#define AT91C_SSC2_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_SSC2) Transmit Counter Register -#define AT91C_SSC2_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_SSC2) Receive Counter Register -// ========== Register definition for SSC2 peripheral ========== -#define AT91C_SSC2_IMR ((AT91_REG *) 0xFFFD804C) // (SSC2) Interrupt Mask Register -#define AT91C_SSC2_IER ((AT91_REG *) 0xFFFD8044) // (SSC2) Interrupt Enable Register -#define AT91C_SSC2_RC1R ((AT91_REG *) 0xFFFD803C) // (SSC2) Receive Compare 1 Register -#define AT91C_SSC2_TSHR ((AT91_REG *) 0xFFFD8034) // (SSC2) Transmit Sync Holding Register -#define AT91C_SSC2_CMR ((AT91_REG *) 0xFFFD8004) // (SSC2) Clock Mode Register -#define AT91C_SSC2_IDR ((AT91_REG *) 0xFFFD8048) // (SSC2) Interrupt Disable Register -#define AT91C_SSC2_TCMR ((AT91_REG *) 0xFFFD8018) // (SSC2) Transmit Clock Mode Register -#define AT91C_SSC2_RCMR ((AT91_REG *) 0xFFFD8010) // (SSC2) Receive Clock ModeRegister -#define AT91C_SSC2_CR ((AT91_REG *) 0xFFFD8000) // (SSC2) Control Register -#define AT91C_SSC2_RFMR ((AT91_REG *) 0xFFFD8014) // (SSC2) Receive Frame Mode Register -#define AT91C_SSC2_TFMR ((AT91_REG *) 0xFFFD801C) // (SSC2) Transmit Frame Mode Register -#define AT91C_SSC2_THR ((AT91_REG *) 0xFFFD8024) // (SSC2) Transmit Holding Register -#define AT91C_SSC2_SR ((AT91_REG *) 0xFFFD8040) // (SSC2) Status Register -#define AT91C_SSC2_RC0R ((AT91_REG *) 0xFFFD8038) // (SSC2) Receive Compare 0 Register -#define AT91C_SSC2_RSHR ((AT91_REG *) 0xFFFD8030) // (SSC2) Receive Sync Holding Register -#define AT91C_SSC2_RHR ((AT91_REG *) 0xFFFD8020) // (SSC2) Receive Holding Register -// ========== Register definition for PDC_SSC1 peripheral ========== -#define AT91C_SSC1_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register -#define AT91C_SSC1_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register -#define AT91C_SSC1_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register -#define AT91C_SSC1_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register -#define AT91C_SSC1_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC1) Receive Pointer Register -#define AT91C_SSC1_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register -#define AT91C_SSC1_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register -#define AT91C_SSC1_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register -#define AT91C_SSC1_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register -#define AT91C_SSC1_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register -// ========== Register definition for SSC1 peripheral ========== -#define AT91C_SSC1_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register -#define AT91C_SSC1_CMR ((AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register -#define AT91C_SSC1_IDR ((AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register -#define AT91C_SSC1_SR ((AT91_REG *) 0xFFFD4040) // (SSC1) Status Register -#define AT91C_SSC1_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC1) Receive Compare 0 Register -#define AT91C_SSC1_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC1) Receive Sync Holding Register -#define AT91C_SSC1_RHR ((AT91_REG *) 0xFFFD4020) // (SSC1) Receive Holding Register -#define AT91C_SSC1_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC1) Transmit Clock Mode Register -#define AT91C_SSC1_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC1) Receive Clock ModeRegister -#define AT91C_SSC1_CR ((AT91_REG *) 0xFFFD4000) // (SSC1) Control Register -#define AT91C_SSC1_IMR ((AT91_REG *) 0xFFFD404C) // (SSC1) Interrupt Mask Register -#define AT91C_SSC1_IER ((AT91_REG *) 0xFFFD4044) // (SSC1) Interrupt Enable Register -#define AT91C_SSC1_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC1) Receive Compare 1 Register -#define AT91C_SSC1_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register -#define AT91C_SSC1_THR ((AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register -#define AT91C_SSC1_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register -// ========== Register definition for PDC_SSC0 peripheral ========== -#define AT91C_SSC0_PTCR ((AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register -#define AT91C_SSC0_TNPR ((AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register -#define AT91C_SSC0_RNPR ((AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register -#define AT91C_SSC0_TPR ((AT91_REG *) 0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register -#define AT91C_SSC0_RPR ((AT91_REG *) 0xFFFD0100) // (PDC_SSC0) Receive Pointer Register -#define AT91C_SSC0_PTSR ((AT91_REG *) 0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register -#define AT91C_SSC0_TNCR ((AT91_REG *) 0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register -#define AT91C_SSC0_RNCR ((AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register -#define AT91C_SSC0_TCR ((AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register -#define AT91C_SSC0_RCR ((AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register -// ========== Register definition for SSC0 peripheral ========== -#define AT91C_SSC0_IMR ((AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register -#define AT91C_SSC0_IER ((AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register -#define AT91C_SSC0_RC1R ((AT91_REG *) 0xFFFD003C) // (SSC0) Receive Compare 1 Register -#define AT91C_SSC0_TSHR ((AT91_REG *) 0xFFFD0034) // (SSC0) Transmit Sync Holding Register -#define AT91C_SSC0_THR ((AT91_REG *) 0xFFFD0024) // (SSC0) Transmit Holding Register -#define AT91C_SSC0_TFMR ((AT91_REG *) 0xFFFD001C) // (SSC0) Transmit Frame Mode Register -#define AT91C_SSC0_RFMR ((AT91_REG *) 0xFFFD0014) // (SSC0) Receive Frame Mode Register -#define AT91C_SSC0_CMR ((AT91_REG *) 0xFFFD0004) // (SSC0) Clock Mode Register -#define AT91C_SSC0_IDR ((AT91_REG *) 0xFFFD0048) // (SSC0) Interrupt Disable Register -#define AT91C_SSC0_SR ((AT91_REG *) 0xFFFD0040) // (SSC0) Status Register -#define AT91C_SSC0_RC0R ((AT91_REG *) 0xFFFD0038) // (SSC0) Receive Compare 0 Register -#define AT91C_SSC0_RSHR ((AT91_REG *) 0xFFFD0030) // (SSC0) Receive Sync Holding Register -#define AT91C_SSC0_RHR ((AT91_REG *) 0xFFFD0020) // (SSC0) Receive Holding Register -#define AT91C_SSC0_TCMR ((AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register -#define AT91C_SSC0_RCMR ((AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister -#define AT91C_SSC0_CR ((AT91_REG *) 0xFFFD0000) // (SSC0) Control Register -// ========== Register definition for PDC_US3 peripheral ========== -#define AT91C_US3_PTSR ((AT91_REG *) 0xFFFCC124) // (PDC_US3) PDC Transfer Status Register -#define AT91C_US3_TNCR ((AT91_REG *) 0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register -#define AT91C_US3_RNCR ((AT91_REG *) 0xFFFCC114) // (PDC_US3) Receive Next Counter Register -#define AT91C_US3_TCR ((AT91_REG *) 0xFFFCC10C) // (PDC_US3) Transmit Counter Register -#define AT91C_US3_RCR ((AT91_REG *) 0xFFFCC104) // (PDC_US3) Receive Counter Register -#define AT91C_US3_PTCR ((AT91_REG *) 0xFFFCC120) // (PDC_US3) PDC Transfer Control Register -#define AT91C_US3_TNPR ((AT91_REG *) 0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register -#define AT91C_US3_RNPR ((AT91_REG *) 0xFFFCC110) // (PDC_US3) Receive Next Pointer Register -#define AT91C_US3_TPR ((AT91_REG *) 0xFFFCC108) // (PDC_US3) Transmit Pointer Register -#define AT91C_US3_RPR ((AT91_REG *) 0xFFFCC100) // (PDC_US3) Receive Pointer Register -// ========== Register definition for US3 peripheral ========== -#define AT91C_US3_IF ((AT91_REG *) 0xFFFCC04C) // (US3) IRDA_FILTER Register -#define AT91C_US3_NER ((AT91_REG *) 0xFFFCC044) // (US3) Nb Errors Register -#define AT91C_US3_RTOR ((AT91_REG *) 0xFFFCC024) // (US3) Receiver Time-out Register -#define AT91C_US3_THR ((AT91_REG *) 0xFFFCC01C) // (US3) Transmitter Holding Register -#define AT91C_US3_CSR ((AT91_REG *) 0xFFFCC014) // (US3) Channel Status Register -#define AT91C_US3_IDR ((AT91_REG *) 0xFFFCC00C) // (US3) Interrupt Disable Register -#define AT91C_US3_MR ((AT91_REG *) 0xFFFCC004) // (US3) Mode Register -#define AT91C_US3_XXR ((AT91_REG *) 0xFFFCC048) // (US3) XON_XOFF Register -#define AT91C_US3_FIDI ((AT91_REG *) 0xFFFCC040) // (US3) FI_DI_Ratio Register -#define AT91C_US3_TTGR ((AT91_REG *) 0xFFFCC028) // (US3) Transmitter Time-guard Register -#define AT91C_US3_BRGR ((AT91_REG *) 0xFFFCC020) // (US3) Baud Rate Generator Register -#define AT91C_US3_RHR ((AT91_REG *) 0xFFFCC018) // (US3) Receiver Holding Register -#define AT91C_US3_IMR ((AT91_REG *) 0xFFFCC010) // (US3) Interrupt Mask Register -#define AT91C_US3_IER ((AT91_REG *) 0xFFFCC008) // (US3) Interrupt Enable Register -#define AT91C_US3_CR ((AT91_REG *) 0xFFFCC000) // (US3) Control Register -// ========== Register definition for PDC_US2 peripheral ========== -#define AT91C_US2_PTSR ((AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register -#define AT91C_US2_TNCR ((AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register -#define AT91C_US2_RNCR ((AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register -#define AT91C_US2_TCR ((AT91_REG *) 0xFFFC810C) // (PDC_US2) Transmit Counter Register -#define AT91C_US2_PTCR ((AT91_REG *) 0xFFFC8120) // (PDC_US2) PDC Transfer Control Register -#define AT91C_US2_RCR ((AT91_REG *) 0xFFFC8104) // (PDC_US2) Receive Counter Register -#define AT91C_US2_TNPR ((AT91_REG *) 0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register -#define AT91C_US2_RPR ((AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register -#define AT91C_US2_TPR ((AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register -#define AT91C_US2_RNPR ((AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register -// ========== Register definition for US2 peripheral ========== -#define AT91C_US2_XXR ((AT91_REG *) 0xFFFC8048) // (US2) XON_XOFF Register -#define AT91C_US2_FIDI ((AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register -#define AT91C_US2_TTGR ((AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register -#define AT91C_US2_BRGR ((AT91_REG *) 0xFFFC8020) // (US2) Baud Rate Generator Register -#define AT91C_US2_RHR ((AT91_REG *) 0xFFFC8018) // (US2) Receiver Holding Register -#define AT91C_US2_IMR ((AT91_REG *) 0xFFFC8010) // (US2) Interrupt Mask Register -#define AT91C_US2_IER ((AT91_REG *) 0xFFFC8008) // (US2) Interrupt Enable Register -#define AT91C_US2_CR ((AT91_REG *) 0xFFFC8000) // (US2) Control Register -#define AT91C_US2_IF ((AT91_REG *) 0xFFFC804C) // (US2) IRDA_FILTER Register -#define AT91C_US2_NER ((AT91_REG *) 0xFFFC8044) // (US2) Nb Errors Register -#define AT91C_US2_RTOR ((AT91_REG *) 0xFFFC8024) // (US2) Receiver Time-out Register -#define AT91C_US2_THR ((AT91_REG *) 0xFFFC801C) // (US2) Transmitter Holding Register -#define AT91C_US2_CSR ((AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register -#define AT91C_US2_IDR ((AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register -#define AT91C_US2_MR ((AT91_REG *) 0xFFFC8004) // (US2) Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for PDC_MCI peripheral ========== -#define AT91C_MCI_PTCR ((AT91_REG *) 0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register -#define AT91C_MCI_TNPR ((AT91_REG *) 0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register -#define AT91C_MCI_RNPR ((AT91_REG *) 0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register -#define AT91C_MCI_TPR ((AT91_REG *) 0xFFFB4108) // (PDC_MCI) Transmit Pointer Register -#define AT91C_MCI_RPR ((AT91_REG *) 0xFFFB4100) // (PDC_MCI) Receive Pointer Register -#define AT91C_MCI_PTSR ((AT91_REG *) 0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register -#define AT91C_MCI_TNCR ((AT91_REG *) 0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register -#define AT91C_MCI_RNCR ((AT91_REG *) 0xFFFB4114) // (PDC_MCI) Receive Next Counter Register -#define AT91C_MCI_TCR ((AT91_REG *) 0xFFFB410C) // (PDC_MCI) Transmit Counter Register -#define AT91C_MCI_RCR ((AT91_REG *) 0xFFFB4104) // (PDC_MCI) Receive Counter Register -// ========== Register definition for MCI peripheral ========== -#define AT91C_MCI_IDR ((AT91_REG *) 0xFFFB4048) // (MCI) MCI Interrupt Disable Register -#define AT91C_MCI_SR ((AT91_REG *) 0xFFFB4040) // (MCI) MCI Status Register -#define AT91C_MCI_RDR ((AT91_REG *) 0xFFFB4030) // (MCI) MCI Receive Data Register -#define AT91C_MCI_RSPR ((AT91_REG *) 0xFFFB4020) // (MCI) MCI Response Register -#define AT91C_MCI_ARGR ((AT91_REG *) 0xFFFB4010) // (MCI) MCI Argument Register -#define AT91C_MCI_DTOR ((AT91_REG *) 0xFFFB4008) // (MCI) MCI Data Timeout Register -#define AT91C_MCI_CR ((AT91_REG *) 0xFFFB4000) // (MCI) MCI Control Register -#define AT91C_MCI_IMR ((AT91_REG *) 0xFFFB404C) // (MCI) MCI Interrupt Mask Register -#define AT91C_MCI_IER ((AT91_REG *) 0xFFFB4044) // (MCI) MCI Interrupt Enable Register -#define AT91C_MCI_TDR ((AT91_REG *) 0xFFFB4034) // (MCI) MCI Transmit Data Register -#define AT91C_MCI_CMDR ((AT91_REG *) 0xFFFB4014) // (MCI) MCI Command Register -#define AT91C_MCI_SDCR ((AT91_REG *) 0xFFFB400C) // (MCI) MCI SD Card Register -#define AT91C_MCI_MR ((AT91_REG *) 0xFFFB4004) // (MCI) MCI Mode Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -// ========== Register definition for TC5 peripheral ========== -#define AT91C_TC5_CMR ((AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register -#define AT91C_TC5_IDR ((AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register -#define AT91C_TC5_SR ((AT91_REG *) 0xFFFA40A0) // (TC5) Status Register -#define AT91C_TC5_RB ((AT91_REG *) 0xFFFA4098) // (TC5) Register B -#define AT91C_TC5_CV ((AT91_REG *) 0xFFFA4090) // (TC5) Counter Value -#define AT91C_TC5_CCR ((AT91_REG *) 0xFFFA4080) // (TC5) Channel Control Register -#define AT91C_TC5_IMR ((AT91_REG *) 0xFFFA40AC) // (TC5) Interrupt Mask Register -#define AT91C_TC5_IER ((AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register -#define AT91C_TC5_RC ((AT91_REG *) 0xFFFA409C) // (TC5) Register C -#define AT91C_TC5_RA ((AT91_REG *) 0xFFFA4094) // (TC5) Register A -// ========== Register definition for TC4 peripheral ========== -#define AT91C_TC4_IMR ((AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register -#define AT91C_TC4_IER ((AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register -#define AT91C_TC4_RC ((AT91_REG *) 0xFFFA405C) // (TC4) Register C -#define AT91C_TC4_RA ((AT91_REG *) 0xFFFA4054) // (TC4) Register A -#define AT91C_TC4_CMR ((AT91_REG *) 0xFFFA4044) // (TC4) Channel Mode Register -#define AT91C_TC4_IDR ((AT91_REG *) 0xFFFA4068) // (TC4) Interrupt Disable Register -#define AT91C_TC4_SR ((AT91_REG *) 0xFFFA4060) // (TC4) Status Register -#define AT91C_TC4_RB ((AT91_REG *) 0xFFFA4058) // (TC4) Register B -#define AT91C_TC4_CV ((AT91_REG *) 0xFFFA4050) // (TC4) Counter Value -#define AT91C_TC4_CCR ((AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register -// ========== Register definition for TC3 peripheral ========== -#define AT91C_TC3_IMR ((AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register -#define AT91C_TC3_CV ((AT91_REG *) 0xFFFA4010) // (TC3) Counter Value -#define AT91C_TC3_CCR ((AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register -#define AT91C_TC3_IER ((AT91_REG *) 0xFFFA4024) // (TC3) Interrupt Enable Register -#define AT91C_TC3_CMR ((AT91_REG *) 0xFFFA4004) // (TC3) Channel Mode Register -#define AT91C_TC3_RA ((AT91_REG *) 0xFFFA4014) // (TC3) Register A -#define AT91C_TC3_RC ((AT91_REG *) 0xFFFA401C) // (TC3) Register C -#define AT91C_TC3_IDR ((AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register -#define AT91C_TC3_RB ((AT91_REG *) 0xFFFA4018) // (TC3) Register B -#define AT91C_TC3_SR ((AT91_REG *) 0xFFFA4020) // (TC3) Status Register -// ========== Register definition for TCB1 peripheral ========== -#define AT91C_TCB1_BCR ((AT91_REG *) 0xFFFA4140) // (TCB1) TC Block Control Register -#define AT91C_TCB1_BMR ((AT91_REG *) 0xFFFA4144) // (TCB1) TC Block Mode Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TCB0 peripheral ========== -#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register -#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register -// ========== Register definition for UHP peripheral ========== -#define AT91C_UHP_HcRhDescriptorA ((AT91_REG *) 0x00300048) // (UHP) Root Hub characteristics A -#define AT91C_UHP_HcRhPortStatus ((AT91_REG *) 0x00300054) // (UHP) Root Hub Port Status Register -#define AT91C_UHP_HcRhDescriptorB ((AT91_REG *) 0x0030004C) // (UHP) Root Hub characteristics B -#define AT91C_UHP_HcControl ((AT91_REG *) 0x00300004) // (UHP) Operating modes for the Host Controller -#define AT91C_UHP_HcInterruptStatus ((AT91_REG *) 0x0030000C) // (UHP) Interrupt Status Register -#define AT91C_UHP_HcRhStatus ((AT91_REG *) 0x00300050) // (UHP) Root Hub Status register -#define AT91C_UHP_HcRevision ((AT91_REG *) 0x00300000) // (UHP) Revision -#define AT91C_UHP_HcCommandStatus ((AT91_REG *) 0x00300008) // (UHP) Command & status Register -#define AT91C_UHP_HcInterruptEnable ((AT91_REG *) 0x00300010) // (UHP) Interrupt Enable Register -#define AT91C_UHP_HcHCCA ((AT91_REG *) 0x00300018) // (UHP) Pointer to the Host Controller Communication Area -#define AT91C_UHP_HcControlHeadED ((AT91_REG *) 0x00300020) // (UHP) First Endpoint Descriptor of the Control list -#define AT91C_UHP_HcInterruptDisable ((AT91_REG *) 0x00300014) // (UHP) Interrupt Disable Register -#define AT91C_UHP_HcPeriodCurrentED ((AT91_REG *) 0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor -#define AT91C_UHP_HcControlCurrentED ((AT91_REG *) 0x00300024) // (UHP) Endpoint Control and Status Register -#define AT91C_UHP_HcBulkCurrentED ((AT91_REG *) 0x0030002C) // (UHP) Current endpoint of the Bulk list -#define AT91C_UHP_HcFmInterval ((AT91_REG *) 0x00300034) // (UHP) Bit time between 2 consecutive SOFs -#define AT91C_UHP_HcBulkHeadED ((AT91_REG *) 0x00300028) // (UHP) First endpoint register of the Bulk list -#define AT91C_UHP_HcBulkDoneHead ((AT91_REG *) 0x00300030) // (UHP) Last completed transfer descriptor -#define AT91C_UHP_HcFmRemaining ((AT91_REG *) 0x00300038) // (UHP) Bit time remaining in the current Frame -#define AT91C_UHP_HcPeriodicStart ((AT91_REG *) 0x00300040) // (UHP) Periodic Start -#define AT91C_UHP_HcLSThreshold ((AT91_REG *) 0x00300044) // (UHP) LS Threshold -#define AT91C_UHP_HcFmNumber ((AT91_REG *) 0x0030003C) // (UHP) Frame number -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFBC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFBC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_HSH ((AT91_REG *) 0xFFFBC090) // (EMAC) Hash Address High[63:32] -#define AT91C_EMAC_MCOL ((AT91_REG *) 0xFFFBC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFBC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes -#define AT91C_EMAC_HSL ((AT91_REG *) 0xFFFBC094) // (EMAC) Hash Address Low[31:0] -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFBC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_OK ((AT91_REG *) 0xFFFBC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_CFG ((AT91_REG *) 0xFFFBC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes -#define AT91C_EMAC_SEQE ((AT91_REG *) 0xFFFBC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFBC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_ELR ((AT91_REG *) 0xFFFBC070) // (EMAC) Excessive Length Error Register -#define AT91C_EMAC_SR ((AT91_REG *) 0xFFFBC008) // (EMAC) Network Status Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFBC064) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_RJB ((AT91_REG *) 0xFFFBC074) // (EMAC) Receive Jabber Register -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFBC078) // (EMAC) Undersize Frame Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFBC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFBC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_FRA ((AT91_REG *) 0xFFFBC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes -#define AT91C_EMAC_SCOL ((AT91_REG *) 0xFFFBC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFBC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_TAR ((AT91_REG *) 0xFFFBC00C) // (EMAC) Transmit Address Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes -#define AT91C_EMAC_TUE ((AT91_REG *) 0xFFFBC068) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_DTE ((AT91_REG *) 0xFFFBC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TCR ((AT91_REG *) 0xFFFBC010) // (EMAC) Transmit Control Register -#define AT91C_EMAC_CTL ((AT91_REG *) 0xFFFBC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr -#define AT91C_EMAC_CDE ((AT91_REG *) 0xFFFBC06C) // (EMAC) Code Error Register -#define AT91C_EMAC_SQEE ((AT91_REG *) 0xFFFBC07C) // (EMAC) SQE Test Error Register -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFBC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_DRFC ((AT91_REG *) 0xFFFBC080) // (EMAC) Discarded RX Frame Register -// ========== Register definition for EBI peripheral ========== -#define AT91C_EBI_CFGR ((AT91_REG *) 0xFFFFFF64) // (EBI) Configuration Register -#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) // (EBI) Chip Select Assignment Register -// ========== Register definition for SMC2 peripheral ========== -#define AT91C_SMC2_CSR ((AT91_REG *) 0xFFFFFF70) // (SMC2) SMC2 Chip Select Register -// ========== Register definition for SDRC peripheral ========== -#define AT91C_SDRC_IMR ((AT91_REG *) 0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register -#define AT91C_SDRC_IER ((AT91_REG *) 0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register -#define AT91C_SDRC_SRR ((AT91_REG *) 0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register -#define AT91C_SDRC_TR ((AT91_REG *) 0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register -#define AT91C_SDRC_ISR ((AT91_REG *) 0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register -#define AT91C_SDRC_IDR ((AT91_REG *) 0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register -#define AT91C_SDRC_LPR ((AT91_REG *) 0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register -#define AT91C_SDRC_CR ((AT91_REG *) 0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register -#define AT91C_SDRC_MR ((AT91_REG *) 0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register -// ========== Register definition for BFC peripheral ========== -#define AT91C_BFC_MR ((AT91_REG *) 0xFFFFFFC0) // (BFC) BFC Mode Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) // SPI Master In Slave -#define AT91C_PA0_PCK3 ((unsigned int) AT91C_PIO_PA0) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) // SPI Master Out Slave -#define AT91C_PA1_PCK0 ((unsigned int) AT91C_PIO_PA1) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) // Ethernet MAC Transmit Data 1 -#define AT91C_PA10_MCDB1 ((unsigned int) AT91C_PIO_PA10) // Multimedia Card B Data 1 -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PA11_MCDB2 ((unsigned int) AT91C_PIO_PA11) // Multimedia Card B Data 2 -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) // Ethernet MAC Receive Data 0 -#define AT91C_PA12_MCDB3 ((unsigned int) AT91C_PIO_PA12) // Multimedia Card B Data 3 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) // Ethernet MAC Receive Data 1 -#define AT91C_PA13_TCLK0 ((unsigned int) AT91C_PIO_PA13) // Timer Counter 0 external clock input -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) // Ethernet MAC Receive Error -#define AT91C_PA14_TCLK1 ((unsigned int) AT91C_PIO_PA14) // Timer Counter 1 external clock input -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) // Ethernet MAC Management Data Clock -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) // Ethernet MAC Management Data Input/Output -#define AT91C_PA16_IRQ6 ((unsigned int) AT91C_PIO_PA16) // AIC Interrupt input 6 -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TXD0 ((unsigned int) AT91C_PIO_PA17) // USART 0 Transmit Data -#define AT91C_PA17_TIOA0 ((unsigned int) AT91C_PIO_PA17) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RXD0 ((unsigned int) AT91C_PIO_PA18) // USART 0 Receive Data -#define AT91C_PA18_TIOB0 ((unsigned int) AT91C_PIO_PA18) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_SCK0 ((unsigned int) AT91C_PIO_PA19) // USART 0 Serial Clock -#define AT91C_PA19_TIOA1 ((unsigned int) AT91C_PIO_PA19) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) // SPI Serial Clock -#define AT91C_PA2_IRQ4 ((unsigned int) AT91C_PIO_PA2) // AIC Interrupt Input 4 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CTS0 ((unsigned int) AT91C_PIO_PA20) // USART 0 Clear To Send -#define AT91C_PA20_TIOB1 ((unsigned int) AT91C_PIO_PA20) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RTS0 ((unsigned int) AT91C_PIO_PA21) // Usart 0 Ready To Send -#define AT91C_PA21_TIOA2 ((unsigned int) AT91C_PIO_PA21) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) // USART 2 Receive Data -#define AT91C_PA22_TIOB2 ((unsigned int) AT91C_PIO_PA22) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) // USART 2 Transmit Data -#define AT91C_PA23_IRQ3 ((unsigned int) AT91C_PIO_PA23) // Interrupt input 3 -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_SCK2 ((unsigned int) AT91C_PIO_PA24) // USART2 Serial Clock -#define AT91C_PA24_PCK1 ((unsigned int) AT91C_PIO_PA24) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_TWD ((unsigned int) AT91C_PIO_PA25) // TWI Two-wire Serial Data -#define AT91C_PA25_IRQ2 ((unsigned int) AT91C_PIO_PA25) // Interrupt input 2 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_TWCK ((unsigned int) AT91C_PIO_PA26) // TWI Two-wire Serial Clock -#define AT91C_PA26_IRQ1 ((unsigned int) AT91C_PIO_PA26) // Interrupt input 1 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_MCCK ((unsigned int) AT91C_PIO_PA27) // Multimedia Card Clock -#define AT91C_PA27_TCLK3 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 3 External Clock Input -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_MCCDA ((unsigned int) AT91C_PIO_PA28) // Multimedia Card A Command -#define AT91C_PA28_TCLK4 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 4 external Clock Input -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_MCDA0 ((unsigned int) AT91C_PIO_PA29) // Multimedia Card A Data 0 -#define AT91C_PA29_TCLK5 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 5 external clock input -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 0 -#define AT91C_PA3_IRQ5 ((unsigned int) AT91C_PIO_PA3) // AIC Interrupt Input 5 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) // DBGU Debug Receive Data -#define AT91C_PA30_CTS2 ((unsigned int) AT91C_PIO_PA30) // Usart 2 Clear To Send -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) // DBGU Debug Transmit Data -#define AT91C_PA31_RTS2 ((unsigned int) AT91C_PIO_PA31) // USART 2 Ready To Send -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) // SPI Peripheral Chip Select 1 -#define AT91C_PA4_PCK1 ((unsigned int) AT91C_PIO_PA4) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 2 -#define AT91C_PA5_TXD3 ((unsigned int) AT91C_PIO_PA5) // USART 3 Transmit Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) // SPI Peripheral Chip Select 3 -#define AT91C_PA6_RXD3 ((unsigned int) AT91C_PIO_PA6) // USART 3 Receive Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PA7_PCK2 ((unsigned int) AT91C_PIO_PA7) // PMC Programmable Clock 2 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) // Ethernet MAC Transmit Enable -#define AT91C_PA8_MCCDB ((unsigned int) AT91C_PIO_PA8) // Multimedia Card B Command -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) // Ethernet MAC Transmit Data 0 -#define AT91C_PA9_MCDB0 ((unsigned int) AT91C_PIO_PA9) // Multimedia Card B Data 0 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_TF0 ((unsigned int) AT91C_PIO_PB0) // SSC Transmit Frame Sync 0 -#define AT91C_PB0_TIOB3 ((unsigned int) AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_TK0 ((unsigned int) AT91C_PIO_PB1) // SSC Transmit Clock 0 -#define AT91C_PB1_CTS3 ((unsigned int) AT91C_PIO_PB1) // USART 3 Clear To Send -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_RK1 ((unsigned int) AT91C_PIO_PB10) // SSC Receive Clock 1 -#define AT91C_PB10_TIOA5 ((unsigned int) AT91C_PIO_PB10) // Timer Counter 5 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_RF1 ((unsigned int) AT91C_PIO_PB11) // SSC Receive Frame Sync 1 -#define AT91C_PB11_TIOB5 ((unsigned int) AT91C_PIO_PB11) // Timer Counter 5 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) // SSC Transmit Frame Sync 2 -#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmit Data 2 -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) // SSC Transmit Clock 2 -#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Transmit Data 3 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) // SSC Transmit Data 2 -#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Transmikt Coding Error -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) // SSC Receive Data 2 -#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data 2 -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) // SSC Receive Clock 2 -#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Receive Data 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) // SSC Receive Frame Sync 2 -#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) // USART 1 Ring Indicator -#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Collision Detected -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) // USART 1 Data Terminal ready -#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) // Ethernet MAC Receive Clock -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_TD0 ((unsigned int) AT91C_PIO_PB2) // SSC Transmit data -#define AT91C_PB2_SCK3 ((unsigned int) AT91C_PIO_PB2) // USART 3 Serial Clock -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_TXD1 ((unsigned int) AT91C_PIO_PB20) // USART 1 Transmit Data -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_RXD1 ((unsigned int) AT91C_PIO_PB21) // USART 1 Receive Data -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_SCK1 ((unsigned int) AT91C_PIO_PB22) // USART1 Serial Clock -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_CTS1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Clear To Send -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Set ready -#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_RTS1 ((unsigned int) AT91C_PIO_PB26) // Usart 0 Ready To Send -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_PCK0 ((unsigned int) AT91C_PIO_PB27) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_FIQ ((unsigned int) AT91C_PIO_PB28) // AIC Fast Interrupt Input -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_IRQ0 ((unsigned int) AT91C_PIO_PB29) // Interrupt input 0 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_RD0 ((unsigned int) AT91C_PIO_PB3) // SSC Receive Data -#define AT91C_PB3_MCDA1 ((unsigned int) AT91C_PIO_PB3) // Multimedia Card A Data 1 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_RK0 ((unsigned int) AT91C_PIO_PB4) // SSC Receive Clock -#define AT91C_PB4_MCDA2 ((unsigned int) AT91C_PIO_PB4) // Multimedia Card A Data 2 -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_RF0 ((unsigned int) AT91C_PIO_PB5) // SSC Receive Frame Sync 0 -#define AT91C_PB5_MCDA3 ((unsigned int) AT91C_PIO_PB5) // Multimedia Card A Data 3 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_TF1 ((unsigned int) AT91C_PIO_PB6) // SSC Transmit Frame Sync 1 -#define AT91C_PB6_TIOA3 ((unsigned int) AT91C_PIO_PB6) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_TK1 ((unsigned int) AT91C_PIO_PB7) // SSC Transmit Clock 1 -#define AT91C_PB7_TIOB3 ((unsigned int) AT91C_PIO_PB7) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_TD1 ((unsigned int) AT91C_PIO_PB8) // SSC Transmit Data 1 -#define AT91C_PB8_TIOA4 ((unsigned int) AT91C_PIO_PB8) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_RD1 ((unsigned int) AT91C_PIO_PB9) // SSC Receive Data 1 -#define AT91C_PB9_TIOB4 ((unsigned int) AT91C_PIO_PB9) // Timer Counter 4 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) // Pin Controlled by PC0 -#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) // Burst Flash Clock -#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) // Pin Controlled by PC1 -#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) // Burst Flash Ready -#define AT91C_PIO_PC10 ((unsigned int) 1 << 10) // Pin Controlled by PC10 -#define AT91C_PC10_NCS4_CFCS ((unsigned int) AT91C_PIO_PC10) // Compact Flash Chip Select -#define AT91C_PIO_PC11 ((unsigned int) 1 << 11) // Pin Controlled by PC11 -#define AT91C_PC11_NCS5_CFCE1 ((unsigned int) AT91C_PIO_PC11) // Chip Select 5 / Compact Flash Chip Enable 1 -#define AT91C_PIO_PC12 ((unsigned int) 1 << 12) // Pin Controlled by PC12 -#define AT91C_PC12_NCS6_CFCE2 ((unsigned int) AT91C_PIO_PC12) // Chip Select 6 / Compact Flash Chip Enable 2 -#define AT91C_PIO_PC13 ((unsigned int) 1 << 13) // Pin Controlled by PC13 -#define AT91C_PC13_NCS7 ((unsigned int) AT91C_PIO_PC13) // Chip Select 7 -#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) // Pin Controlled by PC14 -#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) // Pin Controlled by PC15 -#define AT91C_PIO_PC16 ((unsigned int) 1 << 16) // Pin Controlled by PC16 -#define AT91C_PC16_D16 ((unsigned int) AT91C_PIO_PC16) // Data Bus [16] -#define AT91C_PIO_PC17 ((unsigned int) 1 << 17) // Pin Controlled by PC17 -#define AT91C_PC17_D17 ((unsigned int) AT91C_PIO_PC17) // Data Bus [17] -#define AT91C_PIO_PC18 ((unsigned int) 1 << 18) // Pin Controlled by PC18 -#define AT91C_PC18_D18 ((unsigned int) AT91C_PIO_PC18) // Data Bus [18] -#define AT91C_PIO_PC19 ((unsigned int) 1 << 19) // Pin Controlled by PC19 -#define AT91C_PC19_D19 ((unsigned int) AT91C_PIO_PC19) // Data Bus [19] -#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) // Pin Controlled by PC2 -#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) // Burst Flash Address Valid -#define AT91C_PIO_PC20 ((unsigned int) 1 << 20) // Pin Controlled by PC20 -#define AT91C_PC20_D20 ((unsigned int) AT91C_PIO_PC20) // Data Bus [20] -#define AT91C_PIO_PC21 ((unsigned int) 1 << 21) // Pin Controlled by PC21 -#define AT91C_PC21_D21 ((unsigned int) AT91C_PIO_PC21) // Data Bus [21] -#define AT91C_PIO_PC22 ((unsigned int) 1 << 22) // Pin Controlled by PC22 -#define AT91C_PC22_D22 ((unsigned int) AT91C_PIO_PC22) // Data Bus [22] -#define AT91C_PIO_PC23 ((unsigned int) 1 << 23) // Pin Controlled by PC23 -#define AT91C_PC23_D23 ((unsigned int) AT91C_PIO_PC23) // Data Bus [23] -#define AT91C_PIO_PC24 ((unsigned int) 1 << 24) // Pin Controlled by PC24 -#define AT91C_PC24_D24 ((unsigned int) AT91C_PIO_PC24) // Data Bus [24] -#define AT91C_PIO_PC25 ((unsigned int) 1 << 25) // Pin Controlled by PC25 -#define AT91C_PC25_D25 ((unsigned int) AT91C_PIO_PC25) // Data Bus [25] -#define AT91C_PIO_PC26 ((unsigned int) 1 << 26) // Pin Controlled by PC26 -#define AT91C_PC26_D26 ((unsigned int) AT91C_PIO_PC26) // Data Bus [26] -#define AT91C_PIO_PC27 ((unsigned int) 1 << 27) // Pin Controlled by PC27 -#define AT91C_PC27_D27 ((unsigned int) AT91C_PIO_PC27) // Data Bus [27] -#define AT91C_PIO_PC28 ((unsigned int) 1 << 28) // Pin Controlled by PC28 -#define AT91C_PC28_D28 ((unsigned int) AT91C_PIO_PC28) // Data Bus [28] -#define AT91C_PIO_PC29 ((unsigned int) 1 << 29) // Pin Controlled by PC29 -#define AT91C_PC29_D29 ((unsigned int) AT91C_PIO_PC29) // Data Bus [29] -#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) // Pin Controlled by PC3 -#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) // Burst Flash Address Advance / SmartMedia Write Enable -#define AT91C_PIO_PC30 ((unsigned int) 1 << 30) // Pin Controlled by PC30 -#define AT91C_PC30_D30 ((unsigned int) AT91C_PIO_PC30) // Data Bus [30] -#define AT91C_PIO_PC31 ((unsigned int) 1 << 31) // Pin Controlled by PC31 -#define AT91C_PC31_D31 ((unsigned int) AT91C_PIO_PC31) // Data Bus [31] -#define AT91C_PIO_PC4 ((unsigned int) 1 << 4) // Pin Controlled by PC4 -#define AT91C_PC4_BFOE ((unsigned int) AT91C_PIO_PC4) // Burst Flash Output Enable -#define AT91C_PIO_PC5 ((unsigned int) 1 << 5) // Pin Controlled by PC5 -#define AT91C_PC5_BFWE ((unsigned int) AT91C_PIO_PC5) // Burst Flash Write Enable -#define AT91C_PIO_PC6 ((unsigned int) 1 << 6) // Pin Controlled by PC6 -#define AT91C_PC6_NWAIT ((unsigned int) AT91C_PIO_PC6) // NWAIT -#define AT91C_PIO_PC7 ((unsigned int) 1 << 7) // Pin Controlled by PC7 -#define AT91C_PC7_A23 ((unsigned int) AT91C_PIO_PC7) // Address Bus[23] -#define AT91C_PIO_PC8 ((unsigned int) 1 << 8) // Pin Controlled by PC8 -#define AT91C_PC8_A24 ((unsigned int) AT91C_PIO_PC8) // Address Bus[24] -#define AT91C_PIO_PC9 ((unsigned int) 1 << 9) // Pin Controlled by PC9 -#define AT91C_PC9_A25_CFRNW ((unsigned int) AT91C_PIO_PC9) // Address Bus[25] / Compact Flash Read Not Write -#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) // Pin Controlled by PD0 -#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) // Pin Controlled by PD1 -#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) // Pin Controlled by PD10 -#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) // PMC Programmable Clock Output 3 -#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) // ETM ARM9 pipeline status 1 -#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) // Pin Controlled by PD11 -#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) // -#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) // ETM ARM9 pipeline status 2 -#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) // Pin Controlled by PD12 -#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) // -#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) // ETM Trace Packet 0 -#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) // Pin Controlled by PD13 -#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) // -#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) // ETM Trace Packet 1 -#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) // Pin Controlled by PD14 -#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) // -#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) // ETM Trace Packet 2 -#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) // Pin Controlled by PD15 -#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) // SSC Transmit data -#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) // ETM Trace Packet 3 -#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) // Pin Controlled by PD16 -#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) // SSC Transmit Data 1 -#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) // ETM Trace Packet 4 -#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) // Pin Controlled by PD17 -#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) // SSC Transmit Data 2 -#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) // ETM Trace Packet 5 -#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) // Pin Controlled by PD18 -#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) // SPI Peripheral Chip Select 1 -#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) // ETM Trace Packet 6 -#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) // Pin Controlled by PD19 -#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) // SPI Peripheral Chip Select 2 -#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) // ETM Trace Packet 7 -#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) // Pin Controlled by PD2 -#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) // Ethernet MAC Transmit Data 2 -#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) // Pin Controlled by PD20 -#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) // SPI Peripheral Chip Select 3 -#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) // ETM Trace Packet 8 -#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) // Pin Controlled by PD21 -#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) // Usart 0 Ready To Send -#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) // ETM Trace Packet 9 -#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) // Pin Controlled by PD22 -#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) // Usart 0 Ready To Send -#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) // ETM Trace Packet 10 -#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) // Pin Controlled by PD23 -#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) // USART 2 Ready To Send -#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) // ETM Trace Packet 11 -#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) // Pin Controlled by PD24 -#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) // USART 3 Ready To Send -#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) // ETM Trace Packet 12 -#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) // Pin Controlled by PD25 -#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) // USART 1 Data Terminal ready -#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) // ETM Trace Packet 13 -#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) // Pin Controlled by PD26 -#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) // ETM Trace Packet 14 -#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) // Pin Controlled by PD27 -#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) // ETM Trace Packet 15 -#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) // Pin Controlled by PD3 -#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) // Ethernet MAC Transmit Data 3 -#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) // Pin Controlled by PD4 -#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) // Pin Controlled by PD5 -#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) // Ethernet MAC Transmikt Coding Error -#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) // Pin Controlled by PD6 -#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) // DBGU Debug Transmit Data -#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) // Pin Controlled by PD7 -#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) // PMC Programmable Clock Output 0 -#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) // ETM Synchronization signal -#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) // Pin Controlled by PD8 -#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) // PMC Programmable Clock Output 1 -#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) // ETM Trace Clock signal -#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) // Pin Controlled by PD9 -#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) // PMC Programmable Clock 2 -#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) // ETM ARM9 pipeline status 0 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_PIOC ((unsigned int) 4) // Parallel IO Controller C -#define AT91C_ID_PIOD ((unsigned int) 5) // Parallel IO Controller D -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_US2 ((unsigned int) 8) // USART 2 -#define AT91C_ID_US3 ((unsigned int) 9) // USART 3 -#define AT91C_ID_MCI ((unsigned int) 10) // Multimedia Card Interface -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TWI ((unsigned int) 12) // Two-Wire Interface -#define AT91C_ID_SPI ((unsigned int) 13) // Serial Peripheral Interface -#define AT91C_ID_SSC0 ((unsigned int) 14) // Serial Synchronous Controller 0 -#define AT91C_ID_SSC1 ((unsigned int) 15) // Serial Synchronous Controller 1 -#define AT91C_ID_SSC2 ((unsigned int) 16) // Serial Synchronous Controller 2 -#define AT91C_ID_TC0 ((unsigned int) 17) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 18) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 19) // Timer Counter 2 -#define AT91C_ID_TC3 ((unsigned int) 20) // Timer Counter 3 -#define AT91C_ID_TC4 ((unsigned int) 21) // Timer Counter 4 -#define AT91C_ID_TC5 ((unsigned int) 22) // Timer Counter 5 -#define AT91C_ID_UHP ((unsigned int) 23) // USB Host port -#define AT91C_ID_EMAC ((unsigned int) 24) // Ethernet MAC -#define AT91C_ID_IRQ0 ((unsigned int) 25) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 26) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ID_IRQ2 ((unsigned int) 27) // Advanced Interrupt Controller (IRQ2) -#define AT91C_ID_IRQ3 ((unsigned int) 28) // Advanced Interrupt Controller (IRQ3) -#define AT91C_ID_IRQ4 ((unsigned int) 29) // Advanced Interrupt Controller (IRQ4) -#define AT91C_ID_IRQ5 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ5) -#define AT91C_ID_IRQ6 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ6) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) // (RTC) Base Address -#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) // (ST) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) // (PIOD) Base Address -#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_SSC2 ((AT91PS_PDC) 0xFFFD8100) // (PDC_SSC2) Base Address -#define AT91C_BASE_SSC2 ((AT91PS_SSC) 0xFFFD8000) // (SSC2) Base Address -#define AT91C_BASE_PDC_SSC1 ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC1) Base Address -#define AT91C_BASE_SSC1 ((AT91PS_SSC) 0xFFFD4000) // (SSC1) Base Address -#define AT91C_BASE_PDC_SSC0 ((AT91PS_PDC) 0xFFFD0100) // (PDC_SSC0) Base Address -#define AT91C_BASE_SSC0 ((AT91PS_SSC) 0xFFFD0000) // (SSC0) Base Address -#define AT91C_BASE_PDC_US3 ((AT91PS_PDC) 0xFFFCC100) // (PDC_US3) Base Address -#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) // (US3) Base Address -#define AT91C_BASE_PDC_US2 ((AT91PS_PDC) 0xFFFC8100) // (PDC_US2) Base Address -#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) // (US2) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PDC_MCI ((AT91PS_PDC) 0xFFFB4100) // (PDC_MCI) Base Address -#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) // (MCI) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC5 ((AT91PS_TC) 0xFFFA4080) // (TC5) Base Address -#define AT91C_BASE_TC4 ((AT91PS_TC) 0xFFFA4040) // (TC4) Base Address -#define AT91C_BASE_TC3 ((AT91PS_TC) 0xFFFA4000) // (TC3) Base Address -#define AT91C_BASE_TCB1 ((AT91PS_TCB) 0xFFFA4080) // (TCB1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address -#define AT91C_BASE_UHP ((AT91PS_UHP) 0x00300000) // (UHP) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) // (EMAC) Base Address -#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFFFFF60) // (EBI) Base Address -#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) // (SMC2) Base Address -#define AT91C_BASE_SDRC ((AT91PS_SDRC) 0xFFFFFF90) // (SDRC) Base Address -#define AT91C_BASE_BFC ((AT91PS_BFC) 0xFFFFFFC0) // (BFC) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte) -#define AT91C_IROM ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IROM_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte) - -#endif diff --git a/target/linux/at91/image/dfboot/src/include/AT91RM9200.inc b/target/linux/at91/image/dfboot/src/include/AT91RM9200.inc deleted file mode 100644 index 670e023fb..000000000 --- a/target/linux/at91/image/dfboot/src/include/AT91RM9200.inc +++ /dev/null @@ -1,2437 +0,0 @@ -;- ---------------------------------------------------------------------------- -;- ATMEL Microcontroller Software Support - ROUSSET - -;- ---------------------------------------------------------------------------- -;- The software is delivered "AS IS" without warranty or condition of any -;- kind, either express, implied or statutory. This includes without -;- limitation any warranty or condition with respect to merchantability or -;- fitness for any particular purpose, or against the infringements of -;- intellectual property rights of others. -;- ---------------------------------------------------------------------------- -;- File Name : AT91RM9200.h -;- Object : AT91RM9200 definitions -;- Generated : AT91 SW Application Group 11/19/2003 (17:20:51) -;- -;- CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// -;- CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// -;- CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// -;- CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -;- CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -;- CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002// -;- CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003// -;- CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -;- CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// -;- CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002// -;- CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002// -;- CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002// -;- CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002// -;- CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002// -;- CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003// -;- CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003// -;- CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002// -;- CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002// -;- CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003// -;- CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003// -;- CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002// -;- CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002// -;- CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002// -;- ---------------------------------------------------------------------------- - -;- Hardware register definition - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR System Peripherals -;- ***************************************************************************** - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Memory Controller Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_MC -MC_RCR # 4 ;- MC Remap Control Register -MC_ASR # 4 ;- MC Abort Status Register -MC_AASR # 4 ;- MC Abort Address Status Register - # 4 ;- Reserved -MC_PUIA # 64 ;- MC Protection Unit Area -MC_PUP # 4 ;- MC Protection Unit Peripherals -MC_PUER # 4 ;- MC Protection Unit Enable Register -;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -AT91C_MC_RCB EQU (0x1:SHL:0) ;- (MC) Remap Command Bit -;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -AT91C_MC_UNDADD EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status -AT91C_MC_MISADD EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status -AT91C_MC_MPU EQU (0x1:SHL:2) ;- (MC) Memory protection Unit Abort Status -AT91C_MC_ABTSZ EQU (0x3:SHL:8) ;- (MC) Abort Size Status -AT91C_MC_ABTSZ_BYTE EQU (0x0:SHL:8) ;- (MC) Byte -AT91C_MC_ABTSZ_HWORD EQU (0x1:SHL:8) ;- (MC) Half-word -AT91C_MC_ABTSZ_WORD EQU (0x2:SHL:8) ;- (MC) Word -AT91C_MC_ABTTYP EQU (0x3:SHL:10) ;- (MC) Abort Type Status -AT91C_MC_ABTTYP_DATAR EQU (0x0:SHL:10) ;- (MC) Data Read -AT91C_MC_ABTTYP_DATAW EQU (0x1:SHL:10) ;- (MC) Data Write -AT91C_MC_ABTTYP_FETCH EQU (0x2:SHL:10) ;- (MC) Code Fetch -AT91C_MC_MST0 EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source -AT91C_MC_MST1 EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source -AT91C_MC_SVMST0 EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source -AT91C_MC_SVMST1 EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source -;- -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- -AT91C_MC_PROT EQU (0x3:SHL:0) ;- (MC) Protection -AT91C_MC_PROT_PNAUNA EQU (0x0) ;- (MC) Privilege: No Access, User: No Access -AT91C_MC_PROT_PRWUNA EQU (0x1) ;- (MC) Privilege: Read/Write, User: No Access -AT91C_MC_PROT_PRWURO EQU (0x2) ;- (MC) Privilege: Read/Write, User: Read Only -AT91C_MC_PROT_PRWURW EQU (0x3) ;- (MC) Privilege: Read/Write, User: Read/Write -AT91C_MC_SIZE EQU (0xF:SHL:4) ;- (MC) Internal Area Size -AT91C_MC_SIZE_1KB EQU (0x0:SHL:4) ;- (MC) Area size 1KByte -AT91C_MC_SIZE_2KB EQU (0x1:SHL:4) ;- (MC) Area size 2KByte -AT91C_MC_SIZE_4KB EQU (0x2:SHL:4) ;- (MC) Area size 4KByte -AT91C_MC_SIZE_8KB EQU (0x3:SHL:4) ;- (MC) Area size 8KByte -AT91C_MC_SIZE_16KB EQU (0x4:SHL:4) ;- (MC) Area size 16KByte -AT91C_MC_SIZE_32KB EQU (0x5:SHL:4) ;- (MC) Area size 32KByte -AT91C_MC_SIZE_64KB EQU (0x6:SHL:4) ;- (MC) Area size 64KByte -AT91C_MC_SIZE_128KB EQU (0x7:SHL:4) ;- (MC) Area size 128KByte -AT91C_MC_SIZE_256KB EQU (0x8:SHL:4) ;- (MC) Area size 256KByte -AT91C_MC_SIZE_512KB EQU (0x9:SHL:4) ;- (MC) Area size 512KByte -AT91C_MC_SIZE_1MB EQU (0xA:SHL:4) ;- (MC) Area size 1MByte -AT91C_MC_SIZE_2MB EQU (0xB:SHL:4) ;- (MC) Area size 2MByte -AT91C_MC_SIZE_4MB EQU (0xC:SHL:4) ;- (MC) Area size 4MByte -AT91C_MC_SIZE_8MB EQU (0xD:SHL:4) ;- (MC) Area size 8MByte -AT91C_MC_SIZE_16MB EQU (0xE:SHL:4) ;- (MC) Area size 16MByte -AT91C_MC_SIZE_64MB EQU (0xF:SHL:4) ;- (MC) Area size 64MByte -AT91C_MC_BA EQU (0x3FFFF:SHL:10) ;- (MC) Internal Area Base Address -;- -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -;- -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- -AT91C_MC_PUEB EQU (0x1:SHL:0) ;- (MC) Protection Unit enable Bit - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_RTC -RTC_CR # 4 ;- Control Register -RTC_MR # 4 ;- Mode Register -RTC_TIMR # 4 ;- Time Register -RTC_CALR # 4 ;- Calendar Register -RTC_TIMALR # 4 ;- Time Alarm Register -RTC_CALALR # 4 ;- Calendar Alarm Register -RTC_SR # 4 ;- Status Register -RTC_SCCR # 4 ;- Status Clear Command Register -RTC_IER # 4 ;- Interrupt Enable Register -RTC_IDR # 4 ;- Interrupt Disable Register -RTC_IMR # 4 ;- Interrupt Mask Register -RTC_VER # 4 ;- Valid Entry Register -;- -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- -AT91C_RTC_UPDTIM EQU (0x1:SHL:0) ;- (RTC) Update Request Time Register -AT91C_RTC_UPDCAL EQU (0x1:SHL:1) ;- (RTC) Update Request Calendar Register -AT91C_RTC_TIMEVSEL EQU (0x3:SHL:8) ;- (RTC) Time Event Selection -AT91C_RTC_TIMEVSEL_MINUTE EQU (0x0:SHL:8) ;- (RTC) Minute change. -AT91C_RTC_TIMEVSEL_HOUR EQU (0x1:SHL:8) ;- (RTC) Hour change. -AT91C_RTC_TIMEVSEL_DAY24 EQU (0x2:SHL:8) ;- (RTC) Every day at midnight. -AT91C_RTC_TIMEVSEL_DAY12 EQU (0x3:SHL:8) ;- (RTC) Every day at noon. -AT91C_RTC_CALEVSEL EQU (0x3:SHL:16) ;- (RTC) Calendar Event Selection -AT91C_RTC_CALEVSEL_WEEK EQU (0x0:SHL:16) ;- (RTC) Week change (every Monday at time 00:00:00). -AT91C_RTC_CALEVSEL_MONTH EQU (0x1:SHL:16) ;- (RTC) Month change (every 01 of each month at time 00:00:00). -AT91C_RTC_CALEVSEL_YEAR EQU (0x2:SHL:16) ;- (RTC) Year change (every January 1 at time 00:00:00). -;- -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- -AT91C_RTC_HRMOD EQU (0x1:SHL:0) ;- (RTC) 12-24 hour Mode -;- -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- -AT91C_RTC_SEC EQU (0x7F:SHL:0) ;- (RTC) Current Second -AT91C_RTC_MIN EQU (0x7F:SHL:8) ;- (RTC) Current Minute -AT91C_RTC_HOUR EQU (0x1F:SHL:16) ;- (RTC) Current Hour -AT91C_RTC_AMPM EQU (0x1:SHL:22) ;- (RTC) Ante Meridiem, Post Meridiem Indicator -;- -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- -AT91C_RTC_CENT EQU (0x3F:SHL:0) ;- (RTC) Current Century -AT91C_RTC_YEAR EQU (0xFF:SHL:8) ;- (RTC) Current Year -AT91C_RTC_MONTH EQU (0x1F:SHL:16) ;- (RTC) Current Month -AT91C_RTC_DAY EQU (0x7:SHL:21) ;- (RTC) Current Day -AT91C_RTC_DATE EQU (0x3F:SHL:24) ;- (RTC) Current Date -;- -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- -AT91C_RTC_SECEN EQU (0x1:SHL:7) ;- (RTC) Second Alarm Enable -AT91C_RTC_MINEN EQU (0x1:SHL:15) ;- (RTC) Minute Alarm -AT91C_RTC_HOUREN EQU (0x1:SHL:23) ;- (RTC) Current Hour -;- -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- -AT91C_RTC_MONTHEN EQU (0x1:SHL:23) ;- (RTC) Month Alarm Enable -AT91C_RTC_DATEEN EQU (0x1:SHL:31) ;- (RTC) Date Alarm Enable -;- -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- -AT91C_RTC_ACKUPD EQU (0x1:SHL:0) ;- (RTC) Acknowledge for Update -AT91C_RTC_ALARM EQU (0x1:SHL:1) ;- (RTC) Alarm Flag -AT91C_RTC_SECEV EQU (0x1:SHL:2) ;- (RTC) Second Event -AT91C_RTC_TIMEV EQU (0x1:SHL:3) ;- (RTC) Time Event -AT91C_RTC_CALEV EQU (0x1:SHL:4) ;- (RTC) Calendar event -;- -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- -;- -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- -;- -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- -;- -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- -;- -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- -AT91C_RTC_NVTIM EQU (0x1:SHL:0) ;- (RTC) Non valid Time -AT91C_RTC_NVCAL EQU (0x1:SHL:1) ;- (RTC) Non valid Calendar -AT91C_RTC_NVTIMALR EQU (0x1:SHL:2) ;- (RTC) Non valid time Alarm -AT91C_RTC_NVCALALR EQU (0x1:SHL:3) ;- (RTC) Nonvalid Calendar Alarm - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR System Timer Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_ST -ST_CR # 4 ;- Control Register -ST_PIMR # 4 ;- Period Interval Mode Register -ST_WDMR # 4 ;- Watchdog Mode Register -ST_RTMR # 4 ;- Real-time Mode Register -ST_SR # 4 ;- Status Register -ST_IER # 4 ;- Interrupt Enable Register -ST_IDR # 4 ;- Interrupt Disable Register -ST_IMR # 4 ;- Interrupt Mask Register -ST_RTAR # 4 ;- Real-time Alarm Register -ST_CRTR # 4 ;- Current Real-time Register -;- -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- -AT91C_ST_WDRST EQU (0x1:SHL:0) ;- (ST) Watchdog Timer Restart -;- -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- -AT91C_ST_PIV EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart -;- -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- -AT91C_ST_WDV EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart -AT91C_ST_RSTEN EQU (0x1:SHL:16) ;- (ST) Reset Enable -AT91C_ST_EXTEN EQU (0x1:SHL:17) ;- (ST) External Signal Assertion Enable -;- -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- -AT91C_ST_RTPRES EQU (0xFFFF:SHL:0) ;- (ST) Real-time Timer Prescaler Value -;- -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- -AT91C_ST_PITS EQU (0x1:SHL:0) ;- (ST) Period Interval Timer Interrupt -AT91C_ST_WDOVF EQU (0x1:SHL:1) ;- (ST) Watchdog Overflow -AT91C_ST_RTTINC EQU (0x1:SHL:2) ;- (ST) Real-time Timer Increment -AT91C_ST_ALMS EQU (0x1:SHL:3) ;- (ST) Alarm Status -;- -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- -;- -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- -;- -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- -;- -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- -AT91C_ST_ALMV EQU (0xFFFFF:SHL:0) ;- (ST) Alarm Value Value -;- -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- -AT91C_ST_CRTV EQU (0xFFFFF:SHL:0) ;- (ST) Current Real-time Value - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Power Management Controler -;- ***************************************************************************** - ^ 0 ;- AT91S_PMC -PMC_SCER # 4 ;- System Clock Enable Register -PMC_SCDR # 4 ;- System Clock Disable Register -PMC_SCSR # 4 ;- System Clock Status Register - # 4 ;- Reserved -PMC_PCER # 4 ;- Peripheral Clock Enable Register -PMC_PCDR # 4 ;- Peripheral Clock Disable Register -PMC_PCSR # 4 ;- Peripheral Clock Status Register - # 20 ;- Reserved -PMC_MCKR # 4 ;- Master Clock Register - # 12 ;- Reserved -PMC_PCKR # 32 ;- Programmable Clock Register -PMC_IER # 4 ;- Interrupt Enable Register -PMC_IDR # 4 ;- Interrupt Disable Register -PMC_SR # 4 ;- Status Register -PMC_IMR # 4 ;- Interrupt Mask Register -;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -AT91C_PMC_PCK EQU (0x1:SHL:0) ;- (PMC) Processor Clock -AT91C_PMC_UDP EQU (0x1:SHL:1) ;- (PMC) USB Device Port Clock -AT91C_PMC_MCKUDP EQU (0x1:SHL:2) ;- (PMC) USB Device Port Master Clock Automatic Disable on Suspend -AT91C_PMC_UHP EQU (0x1:SHL:4) ;- (PMC) USB Host Port Clock -AT91C_PMC_PCK0 EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK1 EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK2 EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK3 EQU (0x1:SHL:11) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK4 EQU (0x1:SHL:12) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK5 EQU (0x1:SHL:13) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK6 EQU (0x1:SHL:14) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK7 EQU (0x1:SHL:15) ;- (PMC) Programmable Clock Output -;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -AT91C_PMC_CSS EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection -AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected -AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected -AT91C_PMC_CSS_PLLA_CLK EQU (0x2) ;- (PMC) Clock from PLL A is selected -AT91C_PMC_CSS_PLLB_CLK EQU (0x3) ;- (PMC) Clock from PLL B is selected -AT91C_PMC_PRES EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler -AT91C_PMC_PRES_CLK EQU (0x0:SHL:2) ;- (PMC) Selected clock -AT91C_PMC_PRES_CLK_2 EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2 -AT91C_PMC_PRES_CLK_4 EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4 -AT91C_PMC_PRES_CLK_8 EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8 -AT91C_PMC_PRES_CLK_16 EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16 -AT91C_PMC_PRES_CLK_32 EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32 -AT91C_PMC_PRES_CLK_64 EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64 -AT91C_PMC_MDIV EQU (0x3:SHL:8) ;- (PMC) Master Clock Division -AT91C_PMC_MDIV_1 EQU (0x0:SHL:8) ;- (PMC) The master clock and the processor clock are the same -AT91C_PMC_MDIV_2 EQU (0x1:SHL:8) ;- (PMC) The processor clock is twice as fast as the master clock -AT91C_PMC_MDIV_3 EQU (0x2:SHL:8) ;- (PMC) The processor clock is three times faster than the master clock -AT91C_PMC_MDIV_4 EQU (0x3:SHL:8) ;- (PMC) The processor clock is four times faster than the master clock -;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -AT91C_PMC_MOSCS EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask -AT91C_PMC_LOCKA EQU (0x1:SHL:1) ;- (PMC) PLL A Status/Enable/Disable/Mask -AT91C_PMC_LOCKB EQU (0x1:SHL:2) ;- (PMC) PLL B Status/Enable/Disable/Mask -AT91C_PMC_MCKRDY EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK0RDY EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK1RDY EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK2RDY EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK3RDY EQU (0x1:SHL:11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK4RDY EQU (0x1:SHL:12) ;- (PMC) PCK4_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK5RDY EQU (0x1:SHL:13) ;- (PMC) PCK5_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK6RDY EQU (0x1:SHL:14) ;- (PMC) PCK6_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK7RDY EQU (0x1:SHL:15) ;- (PMC) PCK7_RDY Status/Enable/Disable/Mask -;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Clock Generator Controler -;- ***************************************************************************** - ^ 0 ;- AT91S_CKGR -CKGR_MOR # 4 ;- Main Oscillator Register -CKGR_MCFR # 4 ;- Main Clock Frequency Register -CKGR_PLLAR # 4 ;- PLL A Register -CKGR_PLLBR # 4 ;- PLL B Register -;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -AT91C_CKGR_MOSCEN EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator Enable -AT91C_CKGR_OSCTEST EQU (0x1:SHL:1) ;- (CKGR) Oscillator Test -AT91C_CKGR_OSCOUNT EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time -;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -AT91C_CKGR_MAINF EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock Frequency -AT91C_CKGR_MAINRDY EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready -;- -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- -AT91C_CKGR_DIVA EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected -AT91C_CKGR_DIVA_0 EQU (0x0) ;- (CKGR) Divider output is 0 -AT91C_CKGR_DIVA_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed -AT91C_CKGR_PLLACOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL A Counter -AT91C_CKGR_OUTA EQU (0x3:SHL:14) ;- (CKGR) PLL A Output Frequency Range -AT91C_CKGR_OUTA_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet -AT91C_CKGR_OUTA_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet -AT91C_CKGR_OUTA_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet -AT91C_CKGR_OUTA_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet -AT91C_CKGR_MULA EQU (0x7FF:SHL:16) ;- (CKGR) PLL A Multiplier -AT91C_CKGR_SRCA EQU (0x1:SHL:29) ;- (CKGR) PLL A Source -;- -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- -AT91C_CKGR_DIVB EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected -AT91C_CKGR_DIVB_0 EQU (0x0) ;- (CKGR) Divider output is 0 -AT91C_CKGR_DIVB_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed -AT91C_CKGR_PLLBCOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL B Counter -AT91C_CKGR_OUTB EQU (0x3:SHL:14) ;- (CKGR) PLL B Output Frequency Range -AT91C_CKGR_OUTB_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet -AT91C_CKGR_OUTB_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet -AT91C_CKGR_OUTB_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet -AT91C_CKGR_OUTB_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet -AT91C_CKGR_MULB EQU (0x7FF:SHL:16) ;- (CKGR) PLL B Multiplier -AT91C_CKGR_USB_96M EQU (0x1:SHL:28) ;- (CKGR) Divider for USB Ports -AT91C_CKGR_USB_PLL EQU (0x1:SHL:29) ;- (CKGR) PLL Use - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler -;- ***************************************************************************** - ^ 0 ;- AT91S_PIO -PIO_PER # 4 ;- PIO Enable Register -PIO_PDR # 4 ;- PIO Disable Register -PIO_PSR # 4 ;- PIO Status Register - # 4 ;- Reserved -PIO_OER # 4 ;- Output Enable Register -PIO_ODR # 4 ;- Output Disable Registerr -PIO_OSR # 4 ;- Output Status Register - # 4 ;- Reserved -PIO_IFER # 4 ;- Input Filter Enable Register -PIO_IFDR # 4 ;- Input Filter Disable Register -PIO_IFSR # 4 ;- Input Filter Status Register - # 4 ;- Reserved -PIO_SODR # 4 ;- Set Output Data Register -PIO_CODR # 4 ;- Clear Output Data Register -PIO_ODSR # 4 ;- Output Data Status Register -PIO_PDSR # 4 ;- Pin Data Status Register -PIO_IER # 4 ;- Interrupt Enable Register -PIO_IDR # 4 ;- Interrupt Disable Register -PIO_IMR # 4 ;- Interrupt Mask Register -PIO_ISR # 4 ;- Interrupt Status Register -PIO_MDER # 4 ;- Multi-driver Enable Register -PIO_MDDR # 4 ;- Multi-driver Disable Register -PIO_MDSR # 4 ;- Multi-driver Status Register - # 4 ;- Reserved -PIO_PPUDR # 4 ;- Pull-up Disable Register -PIO_PPUER # 4 ;- Pull-up Enable Register -PIO_PPUSR # 4 ;- Pad Pull-up Status Register - # 4 ;- Reserved -PIO_ASR # 4 ;- Select A Register -PIO_BSR # 4 ;- Select B Register -PIO_ABSR # 4 ;- AB Select Status Register - # 36 ;- Reserved -PIO_OWER # 4 ;- Output Write Enable Register -PIO_OWDR # 4 ;- Output Write Disable Register -PIO_OWSR # 4 ;- Output Write Status Register - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Debug Unit -;- ***************************************************************************** - ^ 0 ;- AT91S_DBGU -DBGU_CR # 4 ;- Control Register -DBGU_MR # 4 ;- Mode Register -DBGU_IER # 4 ;- Interrupt Enable Register -DBGU_IDR # 4 ;- Interrupt Disable Register -DBGU_IMR # 4 ;- Interrupt Mask Register -DBGU_CSR # 4 ;- Channel Status Register -DBGU_RHR # 4 ;- Receiver Holding Register -DBGU_THR # 4 ;- Transmitter Holding Register -DBGU_BRGR # 4 ;- Baud Rate Generator Register - # 28 ;- Reserved -DBGU_C1R # 4 ;- Chip ID1 Register -DBGU_C2R # 4 ;- Chip ID2 Register -DBGU_FNTR # 4 ;- Force NTRST Register - # 180 ;- Reserved -DBGU_RPR # 4 ;- Receive Pointer Register -DBGU_RCR # 4 ;- Receive Counter Register -DBGU_TPR # 4 ;- Transmit Pointer Register -DBGU_TCR # 4 ;- Transmit Counter Register -DBGU_RNPR # 4 ;- Receive Next Pointer Register -DBGU_RNCR # 4 ;- Receive Next Counter Register -DBGU_TNPR # 4 ;- Transmit Next Pointer Register -DBGU_TNCR # 4 ;- Transmit Next Counter Register -DBGU_PTCR # 4 ;- PDC Transfer Control Register -DBGU_PTSR # 4 ;- PDC Transfer Status Register -;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver -AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter -AT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable -AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable -AT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable -AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable -;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity type -AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even Parity -AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd Parity -AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space) -AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark) -AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity -AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode -AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel Mode -AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt -AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt -AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt -AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt -AT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt -AT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt -AT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt -AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt -AT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt -AT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt -AT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt -AT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt -;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Peripheral Data Controller -;- ***************************************************************************** - ^ 0 ;- AT91S_PDC -PDC_RPR # 4 ;- Receive Pointer Register -PDC_RCR # 4 ;- Receive Counter Register -PDC_TPR # 4 ;- Transmit Pointer Register -PDC_TCR # 4 ;- Transmit Counter Register -PDC_RNPR # 4 ;- Receive Next Pointer Register -PDC_RNCR # 4 ;- Receive Next Counter Register -PDC_TNPR # 4 ;- Transmit Next Pointer Register -PDC_TNCR # 4 ;- Transmit Next Counter Register -PDC_PTCR # 4 ;- PDC Transfer Control Register -PDC_PTSR # 4 ;- PDC Transfer Status Register -;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable -AT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable -AT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable -AT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable -;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -;- ***************************************************************************** - ^ 0 ;- AT91S_AIC -AIC_SMR # 128 ;- Source Mode Register -AIC_SVR # 128 ;- Source Vector Register -AIC_IVR # 4 ;- IRQ Vector Register -AIC_FVR # 4 ;- FIQ Vector Register -AIC_ISR # 4 ;- Interrupt Status Register -AIC_IPR # 4 ;- Interrupt Pending Register -AIC_IMR # 4 ;- Interrupt Mask Register -AIC_CISR # 4 ;- Core Interrupt Status Register - # 8 ;- Reserved -AIC_IECR # 4 ;- Interrupt Enable Command Register -AIC_IDCR # 4 ;- Interrupt Disable Command Register -AIC_ICCR # 4 ;- Interrupt Clear Command Register -AIC_ISCR # 4 ;- Interrupt Set Command Register -AIC_EOICR # 4 ;- End of Interrupt Command Register -AIC_SPU # 4 ;- Spurious Vector Register -AIC_DCR # 4 ;- Debug Control Register (Protect) - # 4 ;- Reserved -AIC_FFER # 4 ;- Fast Forcing Enable Register -AIC_FFDR # 4 ;- Fast Forcing Disable Register -AIC_FFSR # 4 ;- Fast Forcing Status Register -;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority Level -AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level -AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level -AT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type -AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level Sensitive -AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggered -AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered -;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ Status -AT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status -;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -AT91C_AIC_DCR_PROT EQU (0x1:SHL:0) ;- (AIC) Protection Mode -AT91C_AIC_DCR_GMSK EQU (0x1:SHL:1) ;- (AIC) General Mask - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Serial Parallel Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_SPI -SPI_CR # 4 ;- Control Register -SPI_MR # 4 ;- Mode Register -SPI_RDR # 4 ;- Receive Data Register -SPI_TDR # 4 ;- Transmit Data Register -SPI_SR # 4 ;- Status Register -SPI_IER # 4 ;- Interrupt Enable Register -SPI_IDR # 4 ;- Interrupt Disable Register -SPI_IMR # 4 ;- Interrupt Mask Register - # 16 ;- Reserved -SPI_CSR # 16 ;- Chip Select Register - # 192 ;- Reserved -SPI_RPR # 4 ;- Receive Pointer Register -SPI_RCR # 4 ;- Receive Counter Register -SPI_TPR # 4 ;- Transmit Pointer Register -SPI_TCR # 4 ;- Transmit Counter Register -SPI_RNPR # 4 ;- Receive Next Pointer Register -SPI_RNCR # 4 ;- Receive Next Counter Register -SPI_TNPR # 4 ;- Transmit Next Pointer Register -SPI_TNCR # 4 ;- Transmit Next Counter Register -SPI_PTCR # 4 ;- PDC Transfer Control Register -SPI_PTSR # 4 ;- PDC Transfer Status Register -;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -AT91C_SPI_SPIEN EQU (0x1:SHL:0) ;- (SPI) SPI Enable -AT91C_SPI_SPIDIS EQU (0x1:SHL:1) ;- (SPI) SPI Disable -AT91C_SPI_SWRST EQU (0x1:SHL:7) ;- (SPI) SPI Software reset -;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -AT91C_SPI_MSTR EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode -AT91C_SPI_PS EQU (0x1:SHL:1) ;- (SPI) Peripheral Select -AT91C_SPI_PS_FIXED EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select -AT91C_SPI_PS_VARIABLE EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select -AT91C_SPI_PCSDEC EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode -AT91C_SPI_DIV32 EQU (0x1:SHL:3) ;- (SPI) Clock Selection -AT91C_SPI_MODFDIS EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection -AT91C_SPI_LLB EQU (0x1:SHL:7) ;- (SPI) Clock Selection -AT91C_SPI_PCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select -AT91C_SPI_DLYBCS EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects -;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -AT91C_SPI_RD EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data -AT91C_SPI_RPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status -;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -AT91C_SPI_TD EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data -AT91C_SPI_TPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status -;- -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -AT91C_SPI_RDRF EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full -AT91C_SPI_TDRE EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty -AT91C_SPI_MODF EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error -AT91C_SPI_OVRES EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status -AT91C_SPI_SPENDRX EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer -AT91C_SPI_SPENDTX EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer -AT91C_SPI_RXBUFF EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt -AT91C_SPI_TXBUFE EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt -AT91C_SPI_SPIENS EQU (0x1:SHL:16) ;- (SPI) Enable Status -;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -AT91C_SPI_CPOL EQU (0x1:SHL:0) ;- (SPI) Clock Polarity -AT91C_SPI_NCPHA EQU (0x1:SHL:1) ;- (SPI) Clock Phase -AT91C_SPI_BITS EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer -AT91C_SPI_BITS_8 EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer -AT91C_SPI_BITS_9 EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer -AT91C_SPI_BITS_10 EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer -AT91C_SPI_BITS_11 EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer -AT91C_SPI_BITS_12 EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer -AT91C_SPI_BITS_13 EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer -AT91C_SPI_BITS_14 EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer -AT91C_SPI_BITS_15 EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer -AT91C_SPI_BITS_16 EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer -AT91C_SPI_SCBR EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate -AT91C_SPI_DLYBS EQU (0xFF:SHL:16) ;- (SPI) Serial Clock Baud Rate -AT91C_SPI_DLYBCT EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_SSC -SSC_CR # 4 ;- Control Register -SSC_CMR # 4 ;- Clock Mode Register - # 8 ;- Reserved -SSC_RCMR # 4 ;- Receive Clock ModeRegister -SSC_RFMR # 4 ;- Receive Frame Mode Register -SSC_TCMR # 4 ;- Transmit Clock Mode Register -SSC_TFMR # 4 ;- Transmit Frame Mode Register -SSC_RHR # 4 ;- Receive Holding Register -SSC_THR # 4 ;- Transmit Holding Register - # 8 ;- Reserved -SSC_RSHR # 4 ;- Receive Sync Holding Register -SSC_TSHR # 4 ;- Transmit Sync Holding Register -SSC_RC0R # 4 ;- Receive Compare 0 Register -SSC_RC1R # 4 ;- Receive Compare 1 Register -SSC_SR # 4 ;- Status Register -SSC_IER # 4 ;- Interrupt Enable Register -SSC_IDR # 4 ;- Interrupt Disable Register -SSC_IMR # 4 ;- Interrupt Mask Register - # 176 ;- Reserved -SSC_RPR # 4 ;- Receive Pointer Register -SSC_RCR # 4 ;- Receive Counter Register -SSC_TPR # 4 ;- Transmit Pointer Register -SSC_TCR # 4 ;- Transmit Counter Register -SSC_RNPR # 4 ;- Receive Next Pointer Register -SSC_RNCR # 4 ;- Receive Next Counter Register -SSC_TNPR # 4 ;- Transmit Next Pointer Register -SSC_TNCR # 4 ;- Transmit Next Counter Register -SSC_PTCR # 4 ;- PDC Transfer Control Register -SSC_PTSR # 4 ;- PDC Transfer Status Register -;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -AT91C_SSC_RXEN EQU (0x1:SHL:0) ;- (SSC) Receive Enable -AT91C_SSC_RXDIS EQU (0x1:SHL:1) ;- (SSC) Receive Disable -AT91C_SSC_TXEN EQU (0x1:SHL:8) ;- (SSC) Transmit Enable -AT91C_SSC_TXDIS EQU (0x1:SHL:9) ;- (SSC) Transmit Disable -AT91C_SSC_SWRST EQU (0x1:SHL:15) ;- (SSC) Software Reset -;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -AT91C_SSC_CKS EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection -AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock -AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal -AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin -AT91C_SSC_CKO EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection -AT91C_SSC_CKO_NONE EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -AT91C_SSC_CKO_CONTINOUS EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output -AT91C_SSC_CKO_DATA_TX EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -AT91C_SSC_CKI EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion -AT91C_SSC_CKG EQU (0x3:SHL:6) ;- (SSC) Receive/Transmit Clock Gating Selection -AT91C_SSC_CKG_NONE EQU (0x0:SHL:6) ;- (SSC) Receive/Transmit Clock Gating: None, continuous clock -AT91C_SSC_CKG_LOW EQU (0x1:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF Low -AT91C_SSC_CKG_HIGH EQU (0x2:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF High -AT91C_SSC_START EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection -AT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -AT91C_SSC_START_TX EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start -AT91C_SSC_START_LOW_RF EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input -AT91C_SSC_START_HIGH_RF EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input -AT91C_SSC_START_FALL_RF EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input -AT91C_SSC_START_RISE_RF EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input -AT91C_SSC_START_LEVEL_RF EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input -AT91C_SSC_START_EDGE_RF EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input -AT91C_SSC_START_0 EQU (0x8:SHL:8) ;- (SSC) Compare 0 -AT91C_SSC_STOP EQU (0x1:SHL:12) ;- (SSC) Receive Stop Selection -AT91C_SSC_STTOUT EQU (0x1:SHL:15) ;- (SSC) Receive/Transmit Start Output Selection -AT91C_SSC_STTDLY EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay -AT91C_SSC_PERIOD EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection -;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -AT91C_SSC_DATLEN EQU (0x1F:SHL:0) ;- (SSC) Data Length -AT91C_SSC_LOOP EQU (0x1:SHL:5) ;- (SSC) Loop Mode -AT91C_SSC_MSBF EQU (0x1:SHL:7) ;- (SSC) Most Significant Bit First -AT91C_SSC_DATNB EQU (0xF:SHL:8) ;- (SSC) Data Number per Frame -AT91C_SSC_FSLEN EQU (0xF:SHL:16) ;- (SSC) Receive/Transmit Frame Sync length -AT91C_SSC_FSOS EQU (0x7:SHL:20) ;- (SSC) Receive/Transmit Frame Sync Output Selection -AT91C_SSC_FSOS_NONE EQU (0x0:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -AT91C_SSC_FSOS_NEGATIVE EQU (0x1:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -AT91C_SSC_FSOS_POSITIVE EQU (0x2:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -AT91C_SSC_FSOS_LOW EQU (0x3:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -AT91C_SSC_FSOS_HIGH EQU (0x4:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -AT91C_SSC_FSOS_TOGGLE EQU (0x5:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -AT91C_SSC_FSEDGE EQU (0x1:SHL:24) ;- (SSC) Frame Sync Edge Detection -;- -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -;- -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -AT91C_SSC_DATDEF EQU (0x1:SHL:5) ;- (SSC) Data Default Value -AT91C_SSC_FSDEN EQU (0x1:SHL:23) ;- (SSC) Frame Sync Data Enable -;- -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -AT91C_SSC_TXRDY EQU (0x1:SHL:0) ;- (SSC) Transmit Ready -AT91C_SSC_TXEMPTY EQU (0x1:SHL:1) ;- (SSC) Transmit Empty -AT91C_SSC_ENDTX EQU (0x1:SHL:2) ;- (SSC) End Of Transmission -AT91C_SSC_TXBUFE EQU (0x1:SHL:3) ;- (SSC) Transmit Buffer Empty -AT91C_SSC_RXRDY EQU (0x1:SHL:4) ;- (SSC) Receive Ready -AT91C_SSC_OVRUN EQU (0x1:SHL:5) ;- (SSC) Receive Overrun -AT91C_SSC_ENDRX EQU (0x1:SHL:6) ;- (SSC) End of Reception -AT91C_SSC_RXBUFF EQU (0x1:SHL:7) ;- (SSC) Receive Buffer Full -AT91C_SSC_CP0 EQU (0x1:SHL:8) ;- (SSC) Compare 0 -AT91C_SSC_CP1 EQU (0x1:SHL:9) ;- (SSC) Compare 1 -AT91C_SSC_TXSYN EQU (0x1:SHL:10) ;- (SSC) Transmit Sync -AT91C_SSC_RXSYN EQU (0x1:SHL:11) ;- (SSC) Receive Sync -AT91C_SSC_TXENA EQU (0x1:SHL:16) ;- (SSC) Transmit Enable -AT91C_SSC_RXENA EQU (0x1:SHL:17) ;- (SSC) Receive Enable -;- -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -;- -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -;- -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Usart -;- ***************************************************************************** - ^ 0 ;- AT91S_USART -US_CR # 4 ;- Control Register -US_MR # 4 ;- Mode Register -US_IER # 4 ;- Interrupt Enable Register -US_IDR # 4 ;- Interrupt Disable Register -US_IMR # 4 ;- Interrupt Mask Register -US_CSR # 4 ;- Channel Status Register -US_RHR # 4 ;- Receiver Holding Register -US_THR # 4 ;- Transmitter Holding Register -US_BRGR # 4 ;- Baud Rate Generator Register -US_RTOR # 4 ;- Receiver Time-out Register -US_TTGR # 4 ;- Transmitter Time-guard Register - # 20 ;- Reserved -US_FIDI # 4 ;- FI_DI_Ratio Register -US_NER # 4 ;- Nb Errors Register -US_XXR # 4 ;- XON_XOFF Register -US_IF # 4 ;- IRDA_FILTER Register - # 176 ;- Reserved -US_RPR # 4 ;- Receive Pointer Register -US_RCR # 4 ;- Receive Counter Register -US_TPR # 4 ;- Transmit Pointer Register -US_TCR # 4 ;- Transmit Counter Register -US_RNPR # 4 ;- Receive Next Pointer Register -US_RNCR # 4 ;- Receive Next Counter Register -US_TNPR # 4 ;- Transmit Next Pointer Register -US_TNCR # 4 ;- Transmit Next Counter Register -US_PTCR # 4 ;- PDC Transfer Control Register -US_PTSR # 4 ;- PDC Transfer Status Register -;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (USART) Reset Status Bits -AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break -AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break -AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out -AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address -AT91C_US_RSTIT EQU (0x1:SHL:13) ;- (USART) Reset Iterations -AT91C_US_RSTNACK EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge -AT91C_US_RETTO EQU (0x1:SHL:15) ;- (USART) Rearm Time-out -AT91C_US_DTREN EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable -AT91C_US_DTRDIS EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable -AT91C_US_RTSEN EQU (0x1:SHL:18) ;- (USART) Request to Send enable -AT91C_US_RTSDIS EQU (0x1:SHL:19) ;- (USART) Request to Send Disable -;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_USMODE EQU (0xF:SHL:0) ;- (USART) Usart mode -AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal -AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 -AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking -AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem -AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 -AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 -AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA -AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking -AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock -AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1 -AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM) -AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK) -AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits -AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits -AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits -AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits -AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select -AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits -AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit -AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits -AT91C_US_MSBF EQU (0x1:SHL:16) ;- (USART) Bit Order -AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length -AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select -AT91C_US_OVER EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode -AT91C_US_INACK EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge -AT91C_US_DSNACK EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK -AT91C_US_MAX_ITER EQU (0x1:SHL:24) ;- (USART) Number of Repetitions -AT91C_US_FILTER EQU (0x1:SHL:28) ;- (USART) Receive Line Filter -;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break -AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out -AT91C_US_ITERATION EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached -AT91C_US_NACK EQU (0x1:SHL:13) ;- (USART) Non Acknowledge -AT91C_US_RIIC EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag -AT91C_US_DSRIC EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag -AT91C_US_DCDIC EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag -AT91C_US_CTSIC EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag -;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -AT91C_US_RI EQU (0x1:SHL:20) ;- (USART) Image of RI Input -AT91C_US_DSR EQU (0x1:SHL:21) ;- (USART) Image of DSR Input -AT91C_US_DCD EQU (0x1:SHL:22) ;- (USART) Image of DCD Input -AT91C_US_CTS EQU (0x1:SHL:23) ;- (USART) Image of CTS Input - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Two-wire Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_TWI -TWI_CR # 4 ;- Control Register -TWI_MMR # 4 ;- Master Mode Register -TWI_SMR # 4 ;- Slave Mode Register -TWI_IADR # 4 ;- Internal Address Register -TWI_CWGR # 4 ;- Clock Waveform Generator Register - # 12 ;- Reserved -TWI_SR # 4 ;- Status Register -TWI_IER # 4 ;- Interrupt Enable Register -TWI_IDR # 4 ;- Interrupt Disable Register -TWI_IMR # 4 ;- Interrupt Mask Register -TWI_RHR # 4 ;- Receive Holding Register -TWI_THR # 4 ;- Transmit Holding Register -;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -AT91C_TWI_START EQU (0x1:SHL:0) ;- (TWI) Send a START Condition -AT91C_TWI_STOP EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition -AT91C_TWI_MSEN EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled -AT91C_TWI_MSDIS EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled -AT91C_TWI_SVEN EQU (0x1:SHL:4) ;- (TWI) TWI Slave Transfer Enabled -AT91C_TWI_SVDIS EQU (0x1:SHL:5) ;- (TWI) TWI Slave Transfer Disabled -AT91C_TWI_SWRST EQU (0x1:SHL:7) ;- (TWI) Software Reset -;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -AT91C_TWI_IADRSZ EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size -AT91C_TWI_IADRSZ_NO EQU (0x0:SHL:8) ;- (TWI) No internal device address -AT91C_TWI_IADRSZ_1_BYTE EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address -AT91C_TWI_IADRSZ_2_BYTE EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address -AT91C_TWI_IADRSZ_3_BYTE EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address -AT91C_TWI_MREAD EQU (0x1:SHL:12) ;- (TWI) Master Read Direction -AT91C_TWI_DADR EQU (0x7F:SHL:16) ;- (TWI) Device Address -;- -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- -AT91C_TWI_SADR EQU (0x7F:SHL:16) ;- (TWI) Slave Device Address -;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -AT91C_TWI_CLDIV EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider -AT91C_TWI_CHDIV EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider -AT91C_TWI_CKDIV EQU (0x7:SHL:16) ;- (TWI) Clock Divider -;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -AT91C_TWI_TXCOMP EQU (0x1:SHL:0) ;- (TWI) Transmission Completed -AT91C_TWI_RXRDY EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY -AT91C_TWI_TXRDY EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY -AT91C_TWI_SVREAD EQU (0x1:SHL:3) ;- (TWI) Slave Read -AT91C_TWI_SVACC EQU (0x1:SHL:4) ;- (TWI) Slave Access -AT91C_TWI_GCACC EQU (0x1:SHL:5) ;- (TWI) General Call Access -AT91C_TWI_OVRE EQU (0x1:SHL:6) ;- (TWI) Overrun Error -AT91C_TWI_UNRE EQU (0x1:SHL:7) ;- (TWI) Underrun Error -AT91C_TWI_NACK EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged -AT91C_TWI_ARBLST EQU (0x1:SHL:9) ;- (TWI) Arbitration Lost -;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Multimedia Card Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_MCI -MCI_CR # 4 ;- MCI Control Register -MCI_MR # 4 ;- MCI Mode Register -MCI_DTOR # 4 ;- MCI Data Timeout Register -MCI_SDCR # 4 ;- MCI SD Card Register -MCI_ARGR # 4 ;- MCI Argument Register -MCI_CMDR # 4 ;- MCI Command Register - # 8 ;- Reserved -MCI_RSPR # 16 ;- MCI Response Register -MCI_RDR # 4 ;- MCI Receive Data Register -MCI_TDR # 4 ;- MCI Transmit Data Register - # 8 ;- Reserved -MCI_SR # 4 ;- MCI Status Register -MCI_IER # 4 ;- MCI Interrupt Enable Register -MCI_IDR # 4 ;- MCI Interrupt Disable Register -MCI_IMR # 4 ;- MCI Interrupt Mask Register - # 176 ;- Reserved -MCI_RPR # 4 ;- Receive Pointer Register -MCI_RCR # 4 ;- Receive Counter Register -MCI_TPR # 4 ;- Transmit Pointer Register -MCI_TCR # 4 ;- Transmit Counter Register -MCI_RNPR # 4 ;- Receive Next Pointer Register -MCI_RNCR # 4 ;- Receive Next Counter Register -MCI_TNPR # 4 ;- Transmit Next Pointer Register -MCI_TNCR # 4 ;- Transmit Next Counter Register -MCI_PTCR # 4 ;- PDC Transfer Control Register -MCI_PTSR # 4 ;- PDC Transfer Status Register -;- -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- -AT91C_MCI_MCIEN EQU (0x1:SHL:0) ;- (MCI) Multimedia Interface Enable -AT91C_MCI_MCIDIS EQU (0x1:SHL:1) ;- (MCI) Multimedia Interface Disable -AT91C_MCI_PWSEN EQU (0x1:SHL:2) ;- (MCI) Power Save Mode Enable -AT91C_MCI_PWSDIS EQU (0x1:SHL:3) ;- (MCI) Power Save Mode Disable -;- -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- -AT91C_MCI_CLKDIV EQU (0x1:SHL:0) ;- (MCI) Clock Divider -AT91C_MCI_PWSDIV EQU (0x1:SHL:8) ;- (MCI) Power Saving Divider -AT91C_MCI_PDCPADV EQU (0x1:SHL:14) ;- (MCI) PDC Padding Value -AT91C_MCI_PDCMODE EQU (0x1:SHL:15) ;- (MCI) PDC Oriented Mode -AT91C_MCI_BLKLEN EQU (0x1:SHL:18) ;- (MCI) Data Block Length -;- -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- -AT91C_MCI_DTOCYC EQU (0x1:SHL:0) ;- (MCI) Data Timeout Cycle Number -AT91C_MCI_DTOMUL EQU (0x7:SHL:4) ;- (MCI) Data Timeout Multiplier -AT91C_MCI_DTOMUL_1 EQU (0x0:SHL:4) ;- (MCI) DTOCYC x 1 -AT91C_MCI_DTOMUL_16 EQU (0x1:SHL:4) ;- (MCI) DTOCYC x 16 -AT91C_MCI_DTOMUL_128 EQU (0x2:SHL:4) ;- (MCI) DTOCYC x 128 -AT91C_MCI_DTOMUL_256 EQU (0x3:SHL:4) ;- (MCI) DTOCYC x 256 -AT91C_MCI_DTOMUL_1024 EQU (0x4:SHL:4) ;- (MCI) DTOCYC x 1024 -AT91C_MCI_DTOMUL_4096 EQU (0x5:SHL:4) ;- (MCI) DTOCYC x 4096 -AT91C_MCI_DTOMUL_65536 EQU (0x6:SHL:4) ;- (MCI) DTOCYC x 65536 -AT91C_MCI_DTOMUL_1048576 EQU (0x7:SHL:4) ;- (MCI) DTOCYC x 1048576 -;- -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- -AT91C_MCI_SCDSEL EQU (0x1:SHL:0) ;- (MCI) SD Card Selector -AT91C_MCI_SCDBUS EQU (0x1:SHL:7) ;- (MCI) SD Card Bus Width -;- -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- -AT91C_MCI_CMDNB EQU (0x1F:SHL:0) ;- (MCI) Command Number -AT91C_MCI_RSPTYP EQU (0x3:SHL:6) ;- (MCI) Response Type -AT91C_MCI_RSPTYP_NO EQU (0x0:SHL:6) ;- (MCI) No response -AT91C_MCI_RSPTYP_48 EQU (0x1:SHL:6) ;- (MCI) 48-bit response -AT91C_MCI_RSPTYP_136 EQU (0x2:SHL:6) ;- (MCI) 136-bit response -AT91C_MCI_SPCMD EQU (0x7:SHL:8) ;- (MCI) Special CMD -AT91C_MCI_SPCMD_NONE EQU (0x0:SHL:8) ;- (MCI) Not a special CMD -AT91C_MCI_SPCMD_INIT EQU (0x1:SHL:8) ;- (MCI) Initialization CMD -AT91C_MCI_SPCMD_SYNC EQU (0x2:SHL:8) ;- (MCI) Synchronized CMD -AT91C_MCI_SPCMD_IT_CMD EQU (0x4:SHL:8) ;- (MCI) Interrupt command -AT91C_MCI_SPCMD_IT_REP EQU (0x5:SHL:8) ;- (MCI) Interrupt response -AT91C_MCI_OPDCMD EQU (0x1:SHL:11) ;- (MCI) Open Drain Command -AT91C_MCI_MAXLAT EQU (0x1:SHL:12) ;- (MCI) Maximum Latency for Command to respond -AT91C_MCI_TRCMD EQU (0x3:SHL:16) ;- (MCI) Transfer CMD -AT91C_MCI_TRCMD_NO EQU (0x0:SHL:16) ;- (MCI) No transfer -AT91C_MCI_TRCMD_START EQU (0x1:SHL:16) ;- (MCI) Start transfer -AT91C_MCI_TRCMD_STOP EQU (0x2:SHL:16) ;- (MCI) Stop transfer -AT91C_MCI_TRDIR EQU (0x1:SHL:18) ;- (MCI) Transfer Direction -AT91C_MCI_TRTYP EQU (0x3:SHL:19) ;- (MCI) Transfer Type -AT91C_MCI_TRTYP_BLOCK EQU (0x0:SHL:19) ;- (MCI) Block Transfer type -AT91C_MCI_TRTYP_MULTIPLE EQU (0x1:SHL:19) ;- (MCI) Multiple Block transfer type -AT91C_MCI_TRTYP_STREAM EQU (0x2:SHL:19) ;- (MCI) Stream transfer type -;- -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- -AT91C_MCI_CMDRDY EQU (0x1:SHL:0) ;- (MCI) Command Ready flag -AT91C_MCI_RXRDY EQU (0x1:SHL:1) ;- (MCI) RX Ready flag -AT91C_MCI_TXRDY EQU (0x1:SHL:2) ;- (MCI) TX Ready flag -AT91C_MCI_BLKE EQU (0x1:SHL:3) ;- (MCI) Data Block Transfer Ended flag -AT91C_MCI_DTIP EQU (0x1:SHL:4) ;- (MCI) Data Transfer in Progress flag -AT91C_MCI_NOTBUSY EQU (0x1:SHL:5) ;- (MCI) Data Line Not Busy flag -AT91C_MCI_ENDRX EQU (0x1:SHL:6) ;- (MCI) End of RX Buffer flag -AT91C_MCI_ENDTX EQU (0x1:SHL:7) ;- (MCI) End of TX Buffer flag -AT91C_MCI_RXBUFF EQU (0x1:SHL:14) ;- (MCI) RX Buffer Full flag -AT91C_MCI_TXBUFE EQU (0x1:SHL:15) ;- (MCI) TX Buffer Empty flag -AT91C_MCI_RINDE EQU (0x1:SHL:16) ;- (MCI) Response Index Error flag -AT91C_MCI_RDIRE EQU (0x1:SHL:17) ;- (MCI) Response Direction Error flag -AT91C_MCI_RCRCE EQU (0x1:SHL:18) ;- (MCI) Response CRC Error flag -AT91C_MCI_RENDE EQU (0x1:SHL:19) ;- (MCI) Response End Bit Error flag -AT91C_MCI_RTOE EQU (0x1:SHL:20) ;- (MCI) Response Time-out Error flag -AT91C_MCI_DCRCE EQU (0x1:SHL:21) ;- (MCI) data CRC Error flag -AT91C_MCI_DTOE EQU (0x1:SHL:22) ;- (MCI) Data timeout Error flag -AT91C_MCI_OVRE EQU (0x1:SHL:30) ;- (MCI) Overrun flag -AT91C_MCI_UNRE EQU (0x1:SHL:31) ;- (MCI) Underrun flag -;- -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- -;- -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- -;- -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR USB Device Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_UDP -UDP_NUM # 4 ;- Frame Number Register -UDP_GLBSTATE # 4 ;- Global State Register -UDP_FADDR # 4 ;- Function Address Register - # 4 ;- Reserved -UDP_IER # 4 ;- Interrupt Enable Register -UDP_IDR # 4 ;- Interrupt Disable Register -UDP_IMR # 4 ;- Interrupt Mask Register -UDP_ISR # 4 ;- Interrupt Status Register -UDP_ICR # 4 ;- Interrupt Clear Register - # 4 ;- Reserved -UDP_RSTEP # 4 ;- Reset Endpoint Register - # 4 ;- Reserved -UDP_CSR # 32 ;- Endpoint Control and Status Register -UDP_FDR # 32 ;- Endpoint FIFO Data Register -;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -AT91C_UDP_FRM_NUM EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field Formats -AT91C_UDP_FRM_ERR EQU (0x1:SHL:16) ;- (UDP) Frame Error -AT91C_UDP_FRM_OK EQU (0x1:SHL:17) ;- (UDP) Frame OK -;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -AT91C_UDP_FADDEN EQU (0x1:SHL:0) ;- (UDP) Function Address Enable -AT91C_UDP_CONFG EQU (0x1:SHL:1) ;- (UDP) Configured -AT91C_UDP_RMWUPE EQU (0x1:SHL:2) ;- (UDP) Remote Wake Up Enable -AT91C_UDP_RSMINPR EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host -;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -AT91C_UDP_FADD EQU (0xFF:SHL:0) ;- (UDP) Function Address Value -AT91C_UDP_FEN EQU (0x1:SHL:8) ;- (UDP) Function Enable -;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -AT91C_UDP_EPINT0 EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT1 EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT2 EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 Interrupt -AT91C_UDP_EPINT3 EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 Interrupt -AT91C_UDP_EPINT4 EQU (0x1:SHL:4) ;- (UDP) Endpoint 4 Interrupt -AT91C_UDP_EPINT5 EQU (0x1:SHL:5) ;- (UDP) Endpoint 5 Interrupt -AT91C_UDP_EPINT6 EQU (0x1:SHL:6) ;- (UDP) Endpoint 6 Interrupt -AT91C_UDP_EPINT7 EQU (0x1:SHL:7) ;- (UDP) Endpoint 7 Interrupt -AT91C_UDP_RXSUSP EQU (0x1:SHL:8) ;- (UDP) USB Suspend Interrupt -AT91C_UDP_RXRSM EQU (0x1:SHL:9) ;- (UDP) USB Resume Interrupt -AT91C_UDP_EXTRSM EQU (0x1:SHL:10) ;- (UDP) USB External Resume Interrupt -AT91C_UDP_SOFINT EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame Interrupt -AT91C_UDP_WAKEUP EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt -;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -AT91C_UDP_ENDBUSRES EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt -;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -AT91C_UDP_EP0 EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0 -AT91C_UDP_EP1 EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1 -AT91C_UDP_EP2 EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2 -AT91C_UDP_EP3 EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3 -AT91C_UDP_EP4 EQU (0x1:SHL:4) ;- (UDP) Reset Endpoint 4 -AT91C_UDP_EP5 EQU (0x1:SHL:5) ;- (UDP) Reset Endpoint 5 -AT91C_UDP_EP6 EQU (0x1:SHL:6) ;- (UDP) Reset Endpoint 6 -AT91C_UDP_EP7 EQU (0x1:SHL:7) ;- (UDP) Reset Endpoint 7 -;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -AT91C_UDP_TXCOMP EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPR -AT91C_UDP_RX_DATA_BK0 EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0 -AT91C_UDP_RXSETUP EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints) -AT91C_UDP_ISOERROR EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints) -AT91C_UDP_TXPKTRDY EQU (0x1:SHL:4) ;- (UDP) Transmit Packet Ready -AT91C_UDP_FORCESTALL EQU (0x1:SHL:5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -AT91C_UDP_RX_DATA_BK1 EQU (0x1:SHL:6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -AT91C_UDP_DIR EQU (0x1:SHL:7) ;- (UDP) Transfer Direction -AT91C_UDP_EPTYPE EQU (0x7:SHL:8) ;- (UDP) Endpoint type -AT91C_UDP_EPTYPE_CTRL EQU (0x0:SHL:8) ;- (UDP) Control -AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1:SHL:8) ;- (UDP) Isochronous OUT -AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2:SHL:8) ;- (UDP) Bulk OUT -AT91C_UDP_EPTYPE_INT_OUT EQU (0x3:SHL:8) ;- (UDP) Interrupt OUT -AT91C_UDP_EPTYPE_ISO_IN EQU (0x5:SHL:8) ;- (UDP) Isochronous IN -AT91C_UDP_EPTYPE_BULK_IN EQU (0x6:SHL:8) ;- (UDP) Bulk IN -AT91C_UDP_EPTYPE_INT_IN EQU (0x7:SHL:8) ;- (UDP) Interrupt IN -AT91C_UDP_DTGLE EQU (0x1:SHL:11) ;- (UDP) Data Toggle -AT91C_UDP_EPEDS EQU (0x1:SHL:15) ;- (UDP) Endpoint Enable Disable -AT91C_UDP_RXBYTECNT EQU (0x7FF:SHL:16) ;- (UDP) Number Of Bytes Available in the FIFO - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_TC -TC_CCR # 4 ;- Channel Control Register -TC_CMR # 4 ;- Channel Mode Register - # 8 ;- Reserved -TC_CV # 4 ;- Counter Value -TC_RA # 4 ;- Register A -TC_RB # 4 ;- Register B -TC_RC # 4 ;- Register C -TC_SR # 4 ;- Status Register -TC_IER # 4 ;- Interrupt Enable Register -TC_IDR # 4 ;- Interrupt Disable Register -TC_IMR # 4 ;- Interrupt Mask Register -;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -AT91C_TC_CLKEN EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command -AT91C_TC_CLKDIS EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command -AT91C_TC_SWTRG EQU (0x1:SHL:2) ;- (TC) Software Trigger Command -;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -AT91C_TC_CPCSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare -AT91C_TC_CPCDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare -AT91C_TC_EEVTEDG EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection -AT91C_TC_EEVTEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None -AT91C_TC_EEVTEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge -AT91C_TC_EEVTEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge -AT91C_TC_EEVTEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge -AT91C_TC_EEVT EQU (0x3:SHL:10) ;- (TC) External Event Selection -AT91C_TC_EEVT_NONE EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input -AT91C_TC_EEVT_RISING EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output -AT91C_TC_EEVT_FALLING EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output -AT91C_TC_EEVT_BOTH EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output -AT91C_TC_ENETRG EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable -AT91C_TC_WAVESEL EQU (0x3:SHL:13) ;- (TC) Waveform Selection -AT91C_TC_WAVESEL_UP EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN EQU (0x1:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare -AT91C_TC_WAVESEL_UP_AUTO EQU (0x2:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare -AT91C_TC_CPCTRG EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable -AT91C_TC_WAVE EQU (0x1:SHL:15) ;- (TC) -AT91C_TC_ACPA EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA -AT91C_TC_ACPA_NONE EQU (0x0:SHL:16) ;- (TC) Effect: none -AT91C_TC_ACPA_SET EQU (0x1:SHL:16) ;- (TC) Effect: set -AT91C_TC_ACPA_CLEAR EQU (0x2:SHL:16) ;- (TC) Effect: clear -AT91C_TC_ACPA_TOGGLE EQU (0x3:SHL:16) ;- (TC) Effect: toggle -AT91C_TC_ACPC EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA -AT91C_TC_ACPC_NONE EQU (0x0:SHL:18) ;- (TC) Effect: none -AT91C_TC_ACPC_SET EQU (0x1:SHL:18) ;- (TC) Effect: set -AT91C_TC_ACPC_CLEAR EQU (0x2:SHL:18) ;- (TC) Effect: clear -AT91C_TC_ACPC_TOGGLE EQU (0x3:SHL:18) ;- (TC) Effect: toggle -AT91C_TC_AEEVT EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA -AT91C_TC_AEEVT_NONE EQU (0x0:SHL:20) ;- (TC) Effect: none -AT91C_TC_AEEVT_SET EQU (0x1:SHL:20) ;- (TC) Effect: set -AT91C_TC_AEEVT_CLEAR EQU (0x2:SHL:20) ;- (TC) Effect: clear -AT91C_TC_AEEVT_TOGGLE EQU (0x3:SHL:20) ;- (TC) Effect: toggle -AT91C_TC_ASWTRG EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA -AT91C_TC_ASWTRG_NONE EQU (0x0:SHL:22) ;- (TC) Effect: none -AT91C_TC_ASWTRG_SET EQU (0x1:SHL:22) ;- (TC) Effect: set -AT91C_TC_ASWTRG_CLEAR EQU (0x2:SHL:22) ;- (TC) Effect: clear -AT91C_TC_ASWTRG_TOGGLE EQU (0x3:SHL:22) ;- (TC) Effect: toggle -AT91C_TC_BCPB EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB -AT91C_TC_BCPB_NONE EQU (0x0:SHL:24) ;- (TC) Effect: none -AT91C_TC_BCPB_SET EQU (0x1:SHL:24) ;- (TC) Effect: set -AT91C_TC_BCPB_CLEAR EQU (0x2:SHL:24) ;- (TC) Effect: clear -AT91C_TC_BCPB_TOGGLE EQU (0x3:SHL:24) ;- (TC) Effect: toggle -AT91C_TC_BCPC EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB -AT91C_TC_BCPC_NONE EQU (0x0:SHL:26) ;- (TC) Effect: none -AT91C_TC_BCPC_SET EQU (0x1:SHL:26) ;- (TC) Effect: set -AT91C_TC_BCPC_CLEAR EQU (0x2:SHL:26) ;- (TC) Effect: clear -AT91C_TC_BCPC_TOGGLE EQU (0x3:SHL:26) ;- (TC) Effect: toggle -AT91C_TC_BEEVT EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB -AT91C_TC_BEEVT_NONE EQU (0x0:SHL:28) ;- (TC) Effect: none -AT91C_TC_BEEVT_SET EQU (0x1:SHL:28) ;- (TC) Effect: set -AT91C_TC_BEEVT_CLEAR EQU (0x2:SHL:28) ;- (TC) Effect: clear -AT91C_TC_BEEVT_TOGGLE EQU (0x3:SHL:28) ;- (TC) Effect: toggle -AT91C_TC_BSWTRG EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB -AT91C_TC_BSWTRG_NONE EQU (0x0:SHL:30) ;- (TC) Effect: none -AT91C_TC_BSWTRG_SET EQU (0x1:SHL:30) ;- (TC) Effect: set -AT91C_TC_BSWTRG_CLEAR EQU (0x2:SHL:30) ;- (TC) Effect: clear -AT91C_TC_BSWTRG_TOGGLE EQU (0x3:SHL:30) ;- (TC) Effect: toggle -;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -AT91C_TC_COVFS EQU (0x1:SHL:0) ;- (TC) Counter Overflow -AT91C_TC_LOVRS EQU (0x1:SHL:1) ;- (TC) Load Overrun -AT91C_TC_CPAS EQU (0x1:SHL:2) ;- (TC) RA Compare -AT91C_TC_CPBS EQU (0x1:SHL:3) ;- (TC) RB Compare -AT91C_TC_CPCS EQU (0x1:SHL:4) ;- (TC) RC Compare -AT91C_TC_LDRAS EQU (0x1:SHL:5) ;- (TC) RA Loading -AT91C_TC_LDRBS EQU (0x1:SHL:6) ;- (TC) RB Loading -AT91C_TC_ETRCS EQU (0x1:SHL:7) ;- (TC) External Trigger -AT91C_TC_ETRGS EQU (0x1:SHL:16) ;- (TC) Clock Enabling -AT91C_TC_MTIOA EQU (0x1:SHL:17) ;- (TC) TIOA Mirror -AT91C_TC_MTIOB EQU (0x1:SHL:18) ;- (TC) TIOA Mirror -;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Timer Counter Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_TCB -TCB_TC0 # 48 ;- TC Channel 0 - # 16 ;- Reserved -TCB_TC1 # 48 ;- TC Channel 1 - # 16 ;- Reserved -TCB_TC2 # 48 ;- TC Channel 2 - # 16 ;- Reserved -TCB_BCR # 4 ;- TC Block Control Register -TCB_BMR # 4 ;- TC Block Mode Register -;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -AT91C_TCB_SYNC EQU (0x1:SHL:0) ;- (TCB) Synchro Command -;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -AT91C_TCB_TC0XC0S EQU (0x1:SHL:0) ;- (TCB) External Clock Signal 0 Selection -AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 -AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 -AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 -AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 -AT91C_TCB_TC1XC1S EQU (0x1:SHL:2) ;- (TCB) External Clock Signal 1 Selection -AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1 -AT91C_TCB_TC1XC1S_NONE EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1 -AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1 -AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1 -AT91C_TCB_TC2XC2S EQU (0x1:SHL:4) ;- (TCB) External Clock Signal 2 Selection -AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2 -AT91C_TCB_TC2XC2S_NONE EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2 -AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2 -AT91C_TCB_TC2XC2S_TIOA2 EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2 - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR USB Host Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_UHP -UHP_HcRevision # 4 ;- Revision -UHP_HcControl # 4 ;- Operating modes for the Host Controller -UHP_HcCommandStatus # 4 ;- Command & status Register -UHP_HcInterruptStatus # 4 ;- Interrupt Status Register -UHP_HcInterruptEnable # 4 ;- Interrupt Enable Register -UHP_HcInterruptDisable # 4 ;- Interrupt Disable Register -UHP_HcHCCA # 4 ;- Pointer to the Host Controller Communication Area -UHP_HcPeriodCurrentED # 4 ;- Current Isochronous or Interrupt Endpoint Descriptor -UHP_HcControlHeadED # 4 ;- First Endpoint Descriptor of the Control list -UHP_HcControlCurrentED # 4 ;- Endpoint Control and Status Register -UHP_HcBulkHeadED # 4 ;- First endpoint register of the Bulk list -UHP_HcBulkCurrentED # 4 ;- Current endpoint of the Bulk list -UHP_HcBulkDoneHead # 4 ;- Last completed transfer descriptor -UHP_HcFmInterval # 4 ;- Bit time between 2 consecutive SOFs -UHP_HcFmRemaining # 4 ;- Bit time remaining in the current Frame -UHP_HcFmNumber # 4 ;- Frame number -UHP_HcPeriodicStart # 4 ;- Periodic Start -UHP_HcLSThreshold # 4 ;- LS Threshold -UHP_HcRhDescriptorA # 4 ;- Root Hub characteristics A -UHP_HcRhDescriptorB # 4 ;- Root Hub characteristics B -UHP_HcRhStatus # 4 ;- Root Hub Status register -UHP_HcRhPortStatus # 8 ;- Root Hub Port Status Register - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Ethernet MAC -;- ***************************************************************************** - ^ 0 ;- AT91S_EMAC -EMAC_CTL # 4 ;- Network Control Register -EMAC_CFG # 4 ;- Network Configuration Register -EMAC_SR # 4 ;- Network Status Register -EMAC_TAR # 4 ;- Transmit Address Register -EMAC_TCR # 4 ;- Transmit Control Register -EMAC_TSR # 4 ;- Transmit Status Register -EMAC_RBQP # 4 ;- Receive Buffer Queue Pointer - # 4 ;- Reserved -EMAC_RSR # 4 ;- Receive Status Register -EMAC_ISR # 4 ;- Interrupt Status Register -EMAC_IER # 4 ;- Interrupt Enable Register -EMAC_IDR # 4 ;- Interrupt Disable Register -EMAC_IMR # 4 ;- Interrupt Mask Register -EMAC_MAN # 4 ;- PHY Maintenance Register - # 8 ;- Reserved -EMAC_FRA # 4 ;- Frames Transmitted OK Register -EMAC_SCOL # 4 ;- Single Collision Frame Register -EMAC_MCOL # 4 ;- Multiple Collision Frame Register -EMAC_OK # 4 ;- Frames Received OK Register -EMAC_SEQE # 4 ;- Frame Check Sequence Error Register -EMAC_ALE # 4 ;- Alignment Error Register -EMAC_DTE # 4 ;- Deferred Transmission Frame Register -EMAC_LCOL # 4 ;- Late Collision Register -EMAC_ECOL # 4 ;- Excessive Collision Register -EMAC_CSE # 4 ;- Carrier Sense Error Register -EMAC_TUE # 4 ;- Transmit Underrun Error Register -EMAC_CDE # 4 ;- Code Error Register -EMAC_ELR # 4 ;- Excessive Length Error Register -EMAC_RJB # 4 ;- Receive Jabber Register -EMAC_USF # 4 ;- Undersize Frame Register -EMAC_SQEE # 4 ;- SQE Test Error Register -EMAC_DRFC # 4 ;- Discarded RX Frame Register - # 12 ;- Reserved -EMAC_HSH # 4 ;- Hash Address High[63:32] -EMAC_HSL # 4 ;- Hash Address Low[31:0] -EMAC_SA1L # 4 ;- Specific Address 1 Low, First 4 bytes -EMAC_SA1H # 4 ;- Specific Address 1 High, Last 2 bytes -EMAC_SA2L # 4 ;- Specific Address 2 Low, First 4 bytes -EMAC_SA2H # 4 ;- Specific Address 2 High, Last 2 bytes -EMAC_SA3L # 4 ;- Specific Address 3 Low, First 4 bytes -EMAC_SA3H # 4 ;- Specific Address 3 High, Last 2 bytes -EMAC_SA4L # 4 ;- Specific Address 4 Low, First 4 bytes -EMAC_SA4H # 4 ;- Specific Address 4 High, Last 2 bytesr -;- -------- EMAC_CTL : (EMAC Offset: 0x0) -------- -AT91C_EMAC_LB EQU (0x1:SHL:0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. -AT91C_EMAC_LBL EQU (0x1:SHL:1) ;- (EMAC) Loopback local. -AT91C_EMAC_RE EQU (0x1:SHL:2) ;- (EMAC) Receive enable. -AT91C_EMAC_TE EQU (0x1:SHL:3) ;- (EMAC) Transmit enable. -AT91C_EMAC_MPE EQU (0x1:SHL:4) ;- (EMAC) Management port enable. -AT91C_EMAC_CSR EQU (0x1:SHL:5) ;- (EMAC) Clear statistics registers. -AT91C_EMAC_ISR EQU (0x1:SHL:6) ;- (EMAC) Increment statistics registers. -AT91C_EMAC_WES EQU (0x1:SHL:7) ;- (EMAC) Write enable for statistics registers. -AT91C_EMAC_BP EQU (0x1:SHL:8) ;- (EMAC) Back pressure. -;- -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- -AT91C_EMAC_SPD EQU (0x1:SHL:0) ;- (EMAC) Speed. -AT91C_EMAC_FD EQU (0x1:SHL:1) ;- (EMAC) Full duplex. -AT91C_EMAC_BR EQU (0x1:SHL:2) ;- (EMAC) Bit rate. -AT91C_EMAC_CAF EQU (0x1:SHL:4) ;- (EMAC) Copy all frames. -AT91C_EMAC_NBC EQU (0x1:SHL:5) ;- (EMAC) No broadcast. -AT91C_EMAC_MTI EQU (0x1:SHL:6) ;- (EMAC) Multicast hash enable -AT91C_EMAC_UNI EQU (0x1:SHL:7) ;- (EMAC) Unicast hash enable. -AT91C_EMAC_BIG EQU (0x1:SHL:8) ;- (EMAC) Receive 1522 bytes. -AT91C_EMAC_EAE EQU (0x1:SHL:9) ;- (EMAC) External address match enable. -AT91C_EMAC_CLK EQU (0x3:SHL:10) ;- (EMAC) -AT91C_EMAC_CLK_HCLK_8 EQU (0x0:SHL:10) ;- (EMAC) HCLK divided by 8 -AT91C_EMAC_CLK_HCLK_16 EQU (0x1:SHL:10) ;- (EMAC) HCLK divided by 16 -AT91C_EMAC_CLK_HCLK_32 EQU (0x2:SHL:10) ;- (EMAC) HCLK divided by 32 -AT91C_EMAC_CLK_HCLK_64 EQU (0x3:SHL:10) ;- (EMAC) HCLK divided by 64 -AT91C_EMAC_RTY EQU (0x1:SHL:12) ;- (EMAC) -AT91C_EMAC_RMII EQU (0x1:SHL:13) ;- (EMAC) -;- -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- -AT91C_EMAC_MDIO EQU (0x1:SHL:1) ;- (EMAC) -AT91C_EMAC_IDLE EQU (0x1:SHL:2) ;- (EMAC) -;- -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- -AT91C_EMAC_LEN EQU (0x7FF:SHL:0) ;- (EMAC) -AT91C_EMAC_NCRC EQU (0x1:SHL:15) ;- (EMAC) -;- -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- -AT91C_EMAC_OVR EQU (0x1:SHL:0) ;- (EMAC) -AT91C_EMAC_COL EQU (0x1:SHL:1) ;- (EMAC) -AT91C_EMAC_RLE EQU (0x1:SHL:2) ;- (EMAC) -AT91C_EMAC_TXIDLE EQU (0x1:SHL:3) ;- (EMAC) -AT91C_EMAC_BNQ EQU (0x1:SHL:4) ;- (EMAC) -AT91C_EMAC_COMP EQU (0x1:SHL:5) ;- (EMAC) -AT91C_EMAC_UND EQU (0x1:SHL:6) ;- (EMAC) -;- -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -AT91C_EMAC_BNA EQU (0x1:SHL:0) ;- (EMAC) -AT91C_EMAC_REC EQU (0x1:SHL:1) ;- (EMAC) -;- -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -AT91C_EMAC_DONE EQU (0x1:SHL:0) ;- (EMAC) -AT91C_EMAC_RCOM EQU (0x1:SHL:1) ;- (EMAC) -AT91C_EMAC_RBNA EQU (0x1:SHL:2) ;- (EMAC) -AT91C_EMAC_TOVR EQU (0x1:SHL:3) ;- (EMAC) -AT91C_EMAC_TUND EQU (0x1:SHL:4) ;- (EMAC) -AT91C_EMAC_RTRY EQU (0x1:SHL:5) ;- (EMAC) -AT91C_EMAC_TBRE EQU (0x1:SHL:6) ;- (EMAC) -AT91C_EMAC_TCOM EQU (0x1:SHL:7) ;- (EMAC) -AT91C_EMAC_TIDLE EQU (0x1:SHL:8) ;- (EMAC) -AT91C_EMAC_LINK EQU (0x1:SHL:9) ;- (EMAC) -AT91C_EMAC_ROVR EQU (0x1:SHL:10) ;- (EMAC) -AT91C_EMAC_HRESP EQU (0x1:SHL:11) ;- (EMAC) -;- -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -;- -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -;- -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -;- -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -AT91C_EMAC_DATA EQU (0xFFFF:SHL:0) ;- (EMAC) -AT91C_EMAC_CODE EQU (0x3:SHL:16) ;- (EMAC) -AT91C_EMAC_REGA EQU (0x1F:SHL:18) ;- (EMAC) -AT91C_EMAC_PHYA EQU (0x1F:SHL:23) ;- (EMAC) -AT91C_EMAC_RW EQU (0x3:SHL:28) ;- (EMAC) -AT91C_EMAC_HIGH EQU (0x1:SHL:30) ;- (EMAC) -AT91C_EMAC_LOW EQU (0x1:SHL:31) ;- (EMAC) - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR External Bus Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_EBI -EBI_CSA # 4 ;- Chip Select Assignment Register -EBI_CFGR # 4 ;- Configuration Register -;- -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- -AT91C_EBI_CS0A EQU (0x1:SHL:0) ;- (EBI) Chip Select 0 Assignment -AT91C_EBI_CS0A_SMC EQU (0x0) ;- (EBI) Chip Select 0 is assigned to the Static Memory Controller. -AT91C_EBI_CS0A_BFC EQU (0x1) ;- (EBI) Chip Select 0 is assigned to the Burst Flash Controller. -AT91C_EBI_CS1A EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 Assignment -AT91C_EBI_CS1A_SMC EQU (0x0:SHL:1) ;- (EBI) Chip Select 1 is assigned to the Static Memory Controller. -AT91C_EBI_CS1A_SDRAMC EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 is assigned to the SDRAM Controller. -AT91C_EBI_CS3A EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 Assignment -AT91C_EBI_CS3A_SMC EQU (0x0:SHL:3) ;- (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. -AT91C_EBI_CS3A_SMC_SmartMedia EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. -AT91C_EBI_CS4A EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 Assignment -AT91C_EBI_CS4A_SMC EQU (0x0:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. -AT91C_EBI_CS4A_SMC_CompactFlash EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. -;- -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- -AT91C_EBI_DBPUC EQU (0x1:SHL:0) ;- (EBI) Data Bus Pull-Up Configuration -AT91C_EBI_EBSEN EQU (0x1:SHL:1) ;- (EBI) Bus Sharing Enable - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_SMC2 -SMC2_CSR # 32 ;- SMC2 Chip Select Register -;- -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- -AT91C_SMC2_NWS EQU (0x7F:SHL:0) ;- (SMC2) Number of Wait States -AT91C_SMC2_WSEN EQU (0x1:SHL:7) ;- (SMC2) Wait State Enable -AT91C_SMC2_TDF EQU (0xF:SHL:8) ;- (SMC2) Data Float Time -AT91C_SMC2_BAT EQU (0x1:SHL:12) ;- (SMC2) Byte Access Type -AT91C_SMC2_DBW EQU (0x1:SHL:13) ;- (SMC2) Data Bus Width -AT91C_SMC2_DBW_16 EQU (0x1:SHL:13) ;- (SMC2) 16-bit. -AT91C_SMC2_DBW_8 EQU (0x2:SHL:13) ;- (SMC2) 8-bit. -AT91C_SMC2_DRP EQU (0x1:SHL:15) ;- (SMC2) Data Read Protocol -AT91C_SMC2_ACSS EQU (0x3:SHL:16) ;- (SMC2) Address to Chip Select Setup -AT91C_SMC2_ACSS_STANDARD EQU (0x0:SHL:16) ;- (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. -AT91C_SMC2_ACSS_1_CYCLE EQU (0x1:SHL:16) ;- (SMC2) One cycle less at the beginning and the end of the access. -AT91C_SMC2_ACSS_2_CYCLES EQU (0x2:SHL:16) ;- (SMC2) Two cycles less at the beginning and the end of the access. -AT91C_SMC2_ACSS_3_CYCLES EQU (0x3:SHL:16) ;- (SMC2) Three cycles less at the beginning and the end of the access. -AT91C_SMC2_RWSETUP EQU (0x7:SHL:24) ;- (SMC2) Read and Write Signal Setup Time -AT91C_SMC2_RWHOLD EQU (0x7:SHL:29) ;- (SMC2) Read and Write Signal Hold Time - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR SDRAM Controller Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_SDRC -SDRC_MR # 4 ;- SDRAM Controller Mode Register -SDRC_TR # 4 ;- SDRAM Controller Refresh Timer Register -SDRC_CR # 4 ;- SDRAM Controller Configuration Register -SDRC_SRR # 4 ;- SDRAM Controller Self Refresh Register -SDRC_LPR # 4 ;- SDRAM Controller Low Power Register -SDRC_IER # 4 ;- SDRAM Controller Interrupt Enable Register -SDRC_IDR # 4 ;- SDRAM Controller Interrupt Disable Register -SDRC_IMR # 4 ;- SDRAM Controller Interrupt Mask Register -SDRC_ISR # 4 ;- SDRAM Controller Interrupt Mask Register -;- -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- -AT91C_SDRC_MODE EQU (0xF:SHL:0) ;- (SDRC) Mode -AT91C_SDRC_MODE_NORMAL_CMD EQU (0x0) ;- (SDRC) Normal Mode -AT91C_SDRC_MODE_NOP_CMD EQU (0x1) ;- (SDRC) NOP Command -AT91C_SDRC_MODE_PRCGALL_CMD EQU (0x2) ;- (SDRC) All Banks Precharge Command -AT91C_SDRC_MODE_LMR_CMD EQU (0x3) ;- (SDRC) Load Mode Register Command -AT91C_SDRC_MODE_RFSH_CMD EQU (0x4) ;- (SDRC) Refresh Command -AT91C_SDRC_DBW EQU (0x1:SHL:4) ;- (SDRC) Data Bus Width -AT91C_SDRC_DBW_32_BITS EQU (0x0:SHL:4) ;- (SDRC) 32 Bits datas bus -AT91C_SDRC_DBW_16_BITS EQU (0x1:SHL:4) ;- (SDRC) 16 Bits datas bus -;- -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- -AT91C_SDRC_COUNT EQU (0xFFF:SHL:0) ;- (SDRC) Refresh Counter -;- -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- -AT91C_SDRC_NC EQU (0x3:SHL:0) ;- (SDRC) Number of Column Bits -AT91C_SDRC_NC_8 EQU (0x0) ;- (SDRC) 8 Bits -AT91C_SDRC_NC_9 EQU (0x1) ;- (SDRC) 9 Bits -AT91C_SDRC_NC_10 EQU (0x2) ;- (SDRC) 10 Bits -AT91C_SDRC_NC_11 EQU (0x3) ;- (SDRC) 11 Bits -AT91C_SDRC_NR EQU (0x3:SHL:2) ;- (SDRC) Number of Row Bits -AT91C_SDRC_NR_11 EQU (0x0:SHL:2) ;- (SDRC) 11 Bits -AT91C_SDRC_NR_12 EQU (0x1:SHL:2) ;- (SDRC) 12 Bits -AT91C_SDRC_NR_13 EQU (0x2:SHL:2) ;- (SDRC) 13 Bits -AT91C_SDRC_NB EQU (0x1:SHL:4) ;- (SDRC) Number of Banks -AT91C_SDRC_NB_2_BANKS EQU (0x0:SHL:4) ;- (SDRC) 2 banks -AT91C_SDRC_NB_4_BANKS EQU (0x1:SHL:4) ;- (SDRC) 4 banks -AT91C_SDRC_CAS EQU (0x3:SHL:5) ;- (SDRC) CAS Latency -AT91C_SDRC_CAS_2 EQU (0x2:SHL:5) ;- (SDRC) 2 cycles -AT91C_SDRC_TWR EQU (0xF:SHL:7) ;- (SDRC) Number of Write Recovery Time Cycles -AT91C_SDRC_TRC EQU (0xF:SHL:11) ;- (SDRC) Number of RAS Cycle Time Cycles -AT91C_SDRC_TRP EQU (0xF:SHL:15) ;- (SDRC) Number of RAS Precharge Time Cycles -AT91C_SDRC_TRCD EQU (0xF:SHL:19) ;- (SDRC) Number of RAS to CAS Delay Cycles -AT91C_SDRC_TRAS EQU (0xF:SHL:23) ;- (SDRC) Number of RAS Active Time Cycles -AT91C_SDRC_TXSR EQU (0xF:SHL:27) ;- (SDRC) Number of Command Recovery Time Cycles -;- -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- -AT91C_SDRC_SRCB EQU (0x1:SHL:0) ;- (SDRC) Self-refresh Command Bit -;- -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- -AT91C_SDRC_LPCB EQU (0x1:SHL:0) ;- (SDRC) Low-power Command Bit -;- -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- -AT91C_SDRC_RES EQU (0x1:SHL:0) ;- (SDRC) Refresh Error Status -;- -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- -;- -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- -;- -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- - -;- ***************************************************************************** -;- SOFTWARE API DEFINITION FOR Burst Flash Controller Interface -;- ***************************************************************************** - ^ 0 ;- AT91S_BFC -BFC_MR # 4 ;- BFC Mode Register -;- -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- -AT91C_BFC_BFCOM EQU (0x3:SHL:0) ;- (BFC) Burst Flash Controller Operating Mode -AT91C_BFC_BFCOM_DISABLED EQU (0x0) ;- (BFC) NPCS0 is driven by the SMC or remains high. -AT91C_BFC_BFCOM_ASYNC EQU (0x1) ;- (BFC) Asynchronous -AT91C_BFC_BFCOM_BURST_READ EQU (0x2) ;- (BFC) Burst Read -AT91C_BFC_BFCC EQU (0x3:SHL:2) ;- (BFC) Burst Flash Controller Operating Mode -AT91C_BFC_BFCC_MCK EQU (0x1:SHL:2) ;- (BFC) Master Clock. -AT91C_BFC_BFCC_MCK_DIV_2 EQU (0x2:SHL:2) ;- (BFC) Master Clock divided by 2. -AT91C_BFC_BFCC_MCK_DIV_4 EQU (0x3:SHL:2) ;- (BFC) Master Clock divided by 4. -AT91C_BFC_AVL EQU (0xF:SHL:4) ;- (BFC) Address Valid Latency -AT91C_BFC_PAGES EQU (0x7:SHL:8) ;- (BFC) Page Size -AT91C_BFC_PAGES_NO_PAGE EQU (0x0:SHL:8) ;- (BFC) No page handling. -AT91C_BFC_PAGES_16 EQU (0x1:SHL:8) ;- (BFC) 16 bytes page size. -AT91C_BFC_PAGES_32 EQU (0x2:SHL:8) ;- (BFC) 32 bytes page size. -AT91C_BFC_PAGES_64 EQU (0x3:SHL:8) ;- (BFC) 64 bytes page size. -AT91C_BFC_PAGES_128 EQU (0x4:SHL:8) ;- (BFC) 128 bytes page size. -AT91C_BFC_PAGES_256 EQU (0x5:SHL:8) ;- (BFC) 256 bytes page size. -AT91C_BFC_PAGES_512 EQU (0x6:SHL:8) ;- (BFC) 512 bytes page size. -AT91C_BFC_PAGES_1024 EQU (0x7:SHL:8) ;- (BFC) 1024 bytes page size. -AT91C_BFC_OEL EQU (0x3:SHL:12) ;- (BFC) Output Enable Latency -AT91C_BFC_BAAEN EQU (0x1:SHL:16) ;- (BFC) Burst Address Advance Enable -AT91C_BFC_BFOEH EQU (0x1:SHL:17) ;- (BFC) Burst Flash Output Enable Handling -AT91C_BFC_MUXEN EQU (0x1:SHL:18) ;- (BFC) Multiplexed Bus Enable -AT91C_BFC_RDYEN EQU (0x1:SHL:19) ;- (BFC) Ready Enable Mode - -;- ***************************************************************************** -;- REGISTER ADDRESS DEFINITION FOR AT91RM9200 -;- ***************************************************************************** -;- ========== Register definition for SYS peripheral ========== -;- ========== Register definition for MC peripheral ========== -AT91C_MC_PUER EQU (0xFFFFFF54) ;- (MC) MC Protection Unit Enable Register -AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register -AT91C_MC_PUP EQU (0xFFFFFF50) ;- (MC) MC Protection Unit Peripherals -AT91C_MC_PUIA EQU (0xFFFFFF10) ;- (MC) MC Protection Unit Area -AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register -AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register -;- ========== Register definition for RTC peripheral ========== -AT91C_RTC_IMR EQU (0xFFFFFE28) ;- (RTC) Interrupt Mask Register -AT91C_RTC_IER EQU (0xFFFFFE20) ;- (RTC) Interrupt Enable Register -AT91C_RTC_SR EQU (0xFFFFFE18) ;- (RTC) Status Register -AT91C_RTC_TIMALR EQU (0xFFFFFE10) ;- (RTC) Time Alarm Register -AT91C_RTC_TIMR EQU (0xFFFFFE08) ;- (RTC) Time Register -AT91C_RTC_CR EQU (0xFFFFFE00) ;- (RTC) Control Register -AT91C_RTC_VER EQU (0xFFFFFE2C) ;- (RTC) Valid Entry Register -AT91C_RTC_IDR EQU (0xFFFFFE24) ;- (RTC) Interrupt Disable Register -AT91C_RTC_SCCR EQU (0xFFFFFE1C) ;- (RTC) Status Clear Command Register -AT91C_RTC_CALALR EQU (0xFFFFFE14) ;- (RTC) Calendar Alarm Register -AT91C_RTC_CALR EQU (0xFFFFFE0C) ;- (RTC) Calendar Register -AT91C_RTC_MR EQU (0xFFFFFE04) ;- (RTC) Mode Register -;- ========== Register definition for ST peripheral ========== -AT91C_ST_CRTR EQU (0xFFFFFD24) ;- (ST) Current Real-time Register -AT91C_ST_IMR EQU (0xFFFFFD1C) ;- (ST) Interrupt Mask Register -AT91C_ST_IER EQU (0xFFFFFD14) ;- (ST) Interrupt Enable Register -AT91C_ST_RTMR EQU (0xFFFFFD0C) ;- (ST) Real-time Mode Register -AT91C_ST_PIMR EQU (0xFFFFFD04) ;- (ST) Period Interval Mode Register -AT91C_ST_RTAR EQU (0xFFFFFD20) ;- (ST) Real-time Alarm Register -AT91C_ST_IDR EQU (0xFFFFFD18) ;- (ST) Interrupt Disable Register -AT91C_ST_SR EQU (0xFFFFFD10) ;- (ST) Status Register -AT91C_ST_WDMR EQU (0xFFFFFD08) ;- (ST) Watchdog Mode Register -AT91C_ST_CR EQU (0xFFFFFD00) ;- (ST) Control Register -;- ========== Register definition for PMC peripheral ========== -AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register -AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register -AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register -AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register -AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register -AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register -AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register -AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register -AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register -AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register -AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register -AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register -;- ========== Register definition for CKGR peripheral ========== -AT91C_CKGR_PLLBR EQU (0xFFFFFC2C) ;- (CKGR) PLL B Register -AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register -AT91C_CKGR_PLLAR EQU (0xFFFFFC28) ;- (CKGR) PLL A Register -AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register -;- ========== Register definition for PIOD peripheral ========== -AT91C_PIOD_PDSR EQU (0xFFFFFA3C) ;- (PIOD) Pin Data Status Register -AT91C_PIOD_CODR EQU (0xFFFFFA34) ;- (PIOD) Clear Output Data Register -AT91C_PIOD_OWER EQU (0xFFFFFAA0) ;- (PIOD) Output Write Enable Register -AT91C_PIOD_MDER EQU (0xFFFFFA50) ;- (PIOD) Multi-driver Enable Register -AT91C_PIOD_IMR EQU (0xFFFFFA48) ;- (PIOD) Interrupt Mask Register -AT91C_PIOD_IER EQU (0xFFFFFA40) ;- (PIOD) Interrupt Enable Register -AT91C_PIOD_ODSR EQU (0xFFFFFA38) ;- (PIOD) Output Data Status Register -AT91C_PIOD_SODR EQU (0xFFFFFA30) ;- (PIOD) Set Output Data Register -AT91C_PIOD_PER EQU (0xFFFFFA00) ;- (PIOD) PIO Enable Register -AT91C_PIOD_OWDR EQU (0xFFFFFAA4) ;- (PIOD) Output Write Disable Register -AT91C_PIOD_PPUER EQU (0xFFFFFA64) ;- (PIOD) Pull-up Enable Register -AT91C_PIOD_MDDR EQU (0xFFFFFA54) ;- (PIOD) Multi-driver Disable Register -AT91C_PIOD_ISR EQU (0xFFFFFA4C) ;- (PIOD) Interrupt Status Register -AT91C_PIOD_IDR EQU (0xFFFFFA44) ;- (PIOD) Interrupt Disable Register -AT91C_PIOD_PDR EQU (0xFFFFFA04) ;- (PIOD) PIO Disable Register -AT91C_PIOD_ODR EQU (0xFFFFFA14) ;- (PIOD) Output Disable Registerr -AT91C_PIOD_OWSR EQU (0xFFFFFAA8) ;- (PIOD) Output Write Status Register -AT91C_PIOD_ABSR EQU (0xFFFFFA78) ;- (PIOD) AB Select Status Register -AT91C_PIOD_ASR EQU (0xFFFFFA70) ;- (PIOD) Select A Register -AT91C_PIOD_PPUSR EQU (0xFFFFFA68) ;- (PIOD) Pad Pull-up Status Register -AT91C_PIOD_PPUDR EQU (0xFFFFFA60) ;- (PIOD) Pull-up Disable Register -AT91C_PIOD_MDSR EQU (0xFFFFFA58) ;- (PIOD) Multi-driver Status Register -AT91C_PIOD_PSR EQU (0xFFFFFA08) ;- (PIOD) PIO Status Register -AT91C_PIOD_OER EQU (0xFFFFFA10) ;- (PIOD) Output Enable Register -AT91C_PIOD_OSR EQU (0xFFFFFA18) ;- (PIOD) Output Status Register -AT91C_PIOD_IFER EQU (0xFFFFFA20) ;- (PIOD) Input Filter Enable Register -AT91C_PIOD_BSR EQU (0xFFFFFA74) ;- (PIOD) Select B Register -AT91C_PIOD_IFDR EQU (0xFFFFFA24) ;- (PIOD) Input Filter Disable Register -AT91C_PIOD_IFSR EQU (0xFFFFFA28) ;- (PIOD) Input Filter Status Register -;- ========== Register definition for PIOC peripheral ========== -AT91C_PIOC_IFDR EQU (0xFFFFF824) ;- (PIOC) Input Filter Disable Register -AT91C_PIOC_ODR EQU (0xFFFFF814) ;- (PIOC) Output Disable Registerr -AT91C_PIOC_ABSR EQU (0xFFFFF878) ;- (PIOC) AB Select Status Register -AT91C_PIOC_SODR EQU (0xFFFFF830) ;- (PIOC) Set Output Data Register -AT91C_PIOC_IFSR EQU (0xFFFFF828) ;- (PIOC) Input Filter Status Register -AT91C_PIOC_CODR EQU (0xFFFFF834) ;- (PIOC) Clear Output Data Register -AT91C_PIOC_ODSR EQU (0xFFFFF838) ;- (PIOC) Output Data Status Register -AT91C_PIOC_IER EQU (0xFFFFF840) ;- (PIOC) Interrupt Enable Register -AT91C_PIOC_IMR EQU (0xFFFFF848) ;- (PIOC) Interrupt Mask Register -AT91C_PIOC_OWDR EQU (0xFFFFF8A4) ;- (PIOC) Output Write Disable Register -AT91C_PIOC_MDDR EQU (0xFFFFF854) ;- (PIOC) Multi-driver Disable Register -AT91C_PIOC_PDSR EQU (0xFFFFF83C) ;- (PIOC) Pin Data Status Register -AT91C_PIOC_IDR EQU (0xFFFFF844) ;- (PIOC) Interrupt Disable Register -AT91C_PIOC_ISR EQU (0xFFFFF84C) ;- (PIOC) Interrupt Status Register -AT91C_PIOC_PDR EQU (0xFFFFF804) ;- (PIOC) PIO Disable Register -AT91C_PIOC_OWSR EQU (0xFFFFF8A8) ;- (PIOC) Output Write Status Register -AT91C_PIOC_OWER EQU (0xFFFFF8A0) ;- (PIOC) Output Write Enable Register -AT91C_PIOC_ASR EQU (0xFFFFF870) ;- (PIOC) Select A Register -AT91C_PIOC_PPUSR EQU (0xFFFFF868) ;- (PIOC) Pad Pull-up Status Register -AT91C_PIOC_PPUDR EQU (0xFFFFF860) ;- (PIOC) Pull-up Disable Register -AT91C_PIOC_MDSR EQU (0xFFFFF858) ;- (PIOC) Multi-driver Status Register -AT91C_PIOC_MDER EQU (0xFFFFF850) ;- (PIOC) Multi-driver Enable Register -AT91C_PIOC_IFER EQU (0xFFFFF820) ;- (PIOC) Input Filter Enable Register -AT91C_PIOC_OSR EQU (0xFFFFF818) ;- (PIOC) Output Status Register -AT91C_PIOC_OER EQU (0xFFFFF810) ;- (PIOC) Output Enable Register -AT91C_PIOC_PSR EQU (0xFFFFF808) ;- (PIOC) PIO Status Register -AT91C_PIOC_PER EQU (0xFFFFF800) ;- (PIOC) PIO Enable Register -AT91C_PIOC_BSR EQU (0xFFFFF874) ;- (PIOC) Select B Register -AT91C_PIOC_PPUER EQU (0xFFFFF864) ;- (PIOC) Pull-up Enable Register -;- ========== Register definition for PIOB peripheral ========== -AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register -AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pad Pull-up Status Register -AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register -AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register -AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register -AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register -AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register -AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register -AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register -AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register -AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register -AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register -AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register -AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr -AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register -AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register -AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register -AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register -AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register -AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register -AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register -AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register -AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register -AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register -AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register -AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register -AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register -AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register -AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register -;- ========== Register definition for PIOA peripheral ========== -AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register -AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register -AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register -AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register -AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register -AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register -AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register -AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register -AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register -AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register -AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register -AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register -AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register -AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register -AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr -AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register -AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register -AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register -AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pad Pull-up Status Register -AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register -AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register -AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register -AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register -AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register -AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register -AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register -AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register -AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register -AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register -;- ========== Register definition for DBGU peripheral ========== -AT91C_DBGU_C2R EQU (0xFFFFF244) ;- (DBGU) Chip ID2 Register -AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register -AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register -AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register -AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register -AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register -AT91C_DBGU_C1R EQU (0xFFFFF240) ;- (DBGU) Chip ID1 Register -AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register -AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register -AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register -AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register -AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register -;- ========== Register definition for PDC_DBGU peripheral ========== -AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register -AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register -AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register -AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register -AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register -AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register -AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register -AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register -AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register -AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register -;- ========== Register definition for AIC peripheral ========== -AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register -AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register -AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register -AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register -AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register -AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) -AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register -AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register -AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register -AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register -AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register -AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register -AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register -AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register -AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register -AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register -AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register -AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register -;- ========== Register definition for PDC_SPI peripheral ========== -AT91C_SPI_PTCR EQU (0xFFFE0120) ;- (PDC_SPI) PDC Transfer Control Register -AT91C_SPI_TNPR EQU (0xFFFE0118) ;- (PDC_SPI) Transmit Next Pointer Register -AT91C_SPI_RNPR EQU (0xFFFE0110) ;- (PDC_SPI) Receive Next Pointer Register -AT91C_SPI_TPR EQU (0xFFFE0108) ;- (PDC_SPI) Transmit Pointer Register -AT91C_SPI_RPR EQU (0xFFFE0100) ;- (PDC_SPI) Receive Pointer Register -AT91C_SPI_PTSR EQU (0xFFFE0124) ;- (PDC_SPI) PDC Transfer Status Register -AT91C_SPI_TNCR EQU (0xFFFE011C) ;- (PDC_SPI) Transmit Next Counter Register -AT91C_SPI_RNCR EQU (0xFFFE0114) ;- (PDC_SPI) Receive Next Counter Register -AT91C_SPI_TCR EQU (0xFFFE010C) ;- (PDC_SPI) Transmit Counter Register -AT91C_SPI_RCR EQU (0xFFFE0104) ;- (PDC_SPI) Receive Counter Register -;- ========== Register definition for SPI peripheral ========== -AT91C_SPI_CSR EQU (0xFFFE0030) ;- (SPI) Chip Select Register -AT91C_SPI_IDR EQU (0xFFFE0018) ;- (SPI) Interrupt Disable Register -AT91C_SPI_SR EQU (0xFFFE0010) ;- (SPI) Status Register -AT91C_SPI_RDR EQU (0xFFFE0008) ;- (SPI) Receive Data Register -AT91C_SPI_CR EQU (0xFFFE0000) ;- (SPI) Control Register -AT91C_SPI_IMR EQU (0xFFFE001C) ;- (SPI) Interrupt Mask Register -AT91C_SPI_IER EQU (0xFFFE0014) ;- (SPI) Interrupt Enable Register -AT91C_SPI_TDR EQU (0xFFFE000C) ;- (SPI) Transmit Data Register -AT91C_SPI_MR EQU (0xFFFE0004) ;- (SPI) Mode Register -;- ========== Register definition for PDC_SSC2 peripheral ========== -AT91C_SSC2_PTCR EQU (0xFFFD8120) ;- (PDC_SSC2) PDC Transfer Control Register -AT91C_SSC2_TNPR EQU (0xFFFD8118) ;- (PDC_SSC2) Transmit Next Pointer Register -AT91C_SSC2_RNPR EQU (0xFFFD8110) ;- (PDC_SSC2) Receive Next Pointer Register -AT91C_SSC2_TPR EQU (0xFFFD8108) ;- (PDC_SSC2) Transmit Pointer Register -AT91C_SSC2_RPR EQU (0xFFFD8100) ;- (PDC_SSC2) Receive Pointer Register -AT91C_SSC2_PTSR EQU (0xFFFD8124) ;- (PDC_SSC2) PDC Transfer Status Register -AT91C_SSC2_TNCR EQU (0xFFFD811C) ;- (PDC_SSC2) Transmit Next Counter Register -AT91C_SSC2_RNCR EQU (0xFFFD8114) ;- (PDC_SSC2) Receive Next Counter Register -AT91C_SSC2_TCR EQU (0xFFFD810C) ;- (PDC_SSC2) Transmit Counter Register -AT91C_SSC2_RCR EQU (0xFFFD8104) ;- (PDC_SSC2) Receive Counter Register -;- ========== Register definition for SSC2 peripheral ========== -AT91C_SSC2_IMR EQU (0xFFFD804C) ;- (SSC2) Interrupt Mask Register -AT91C_SSC2_IER EQU (0xFFFD8044) ;- (SSC2) Interrupt Enable Register -AT91C_SSC2_RC1R EQU (0xFFFD803C) ;- (SSC2) Receive Compare 1 Register -AT91C_SSC2_TSHR EQU (0xFFFD8034) ;- (SSC2) Transmit Sync Holding Register -AT91C_SSC2_CMR EQU (0xFFFD8004) ;- (SSC2) Clock Mode Register -AT91C_SSC2_IDR EQU (0xFFFD8048) ;- (SSC2) Interrupt Disable Register -AT91C_SSC2_TCMR EQU (0xFFFD8018) ;- (SSC2) Transmit Clock Mode Register -AT91C_SSC2_RCMR EQU (0xFFFD8010) ;- (SSC2) Receive Clock ModeRegister -AT91C_SSC2_CR EQU (0xFFFD8000) ;- (SSC2) Control Register -AT91C_SSC2_RFMR EQU (0xFFFD8014) ;- (SSC2) Receive Frame Mode Register -AT91C_SSC2_TFMR EQU (0xFFFD801C) ;- (SSC2) Transmit Frame Mode Register -AT91C_SSC2_THR EQU (0xFFFD8024) ;- (SSC2) Transmit Holding Register -AT91C_SSC2_SR EQU (0xFFFD8040) ;- (SSC2) Status Register -AT91C_SSC2_RC0R EQU (0xFFFD8038) ;- (SSC2) Receive Compare 0 Register -AT91C_SSC2_RSHR EQU (0xFFFD8030) ;- (SSC2) Receive Sync Holding Register -AT91C_SSC2_RHR EQU (0xFFFD8020) ;- (SSC2) Receive Holding Register -;- ========== Register definition for PDC_SSC1 peripheral ========== -AT91C_SSC1_PTCR EQU (0xFFFD4120) ;- (PDC_SSC1) PDC Transfer Control Register -AT91C_SSC1_TNPR EQU (0xFFFD4118) ;- (PDC_SSC1) Transmit Next Pointer Register -AT91C_SSC1_RNPR EQU (0xFFFD4110) ;- (PDC_SSC1) Receive Next Pointer Register -AT91C_SSC1_TPR EQU (0xFFFD4108) ;- (PDC_SSC1) Transmit Pointer Register -AT91C_SSC1_RPR EQU (0xFFFD4100) ;- (PDC_SSC1) Receive Pointer Register -AT91C_SSC1_PTSR EQU (0xFFFD4124) ;- (PDC_SSC1) PDC Transfer Status Register -AT91C_SSC1_TNCR EQU (0xFFFD411C) ;- (PDC_SSC1) Transmit Next Counter Register -AT91C_SSC1_RNCR EQU (0xFFFD4114) ;- (PDC_SSC1) Receive Next Counter Register -AT91C_SSC1_TCR EQU (0xFFFD410C) ;- (PDC_SSC1) Transmit Counter Register -AT91C_SSC1_RCR EQU (0xFFFD4104) ;- (PDC_SSC1) Receive Counter Register -;- ========== Register definition for SSC1 peripheral ========== -AT91C_SSC1_RFMR EQU (0xFFFD4014) ;- (SSC1) Receive Frame Mode Register -AT91C_SSC1_CMR EQU (0xFFFD4004) ;- (SSC1) Clock Mode Register -AT91C_SSC1_IDR EQU (0xFFFD4048) ;- (SSC1) Interrupt Disable Register -AT91C_SSC1_SR EQU (0xFFFD4040) ;- (SSC1) Status Register -AT91C_SSC1_RC0R EQU (0xFFFD4038) ;- (SSC1) Receive Compare 0 Register -AT91C_SSC1_RSHR EQU (0xFFFD4030) ;- (SSC1) Receive Sync Holding Register -AT91C_SSC1_RHR EQU (0xFFFD4020) ;- (SSC1) Receive Holding Register -AT91C_SSC1_TCMR EQU (0xFFFD4018) ;- (SSC1) Transmit Clock Mode Register -AT91C_SSC1_RCMR EQU (0xFFFD4010) ;- (SSC1) Receive Clock ModeRegister -AT91C_SSC1_CR EQU (0xFFFD4000) ;- (SSC1) Control Register -AT91C_SSC1_IMR EQU (0xFFFD404C) ;- (SSC1) Interrupt Mask Register -AT91C_SSC1_IER EQU (0xFFFD4044) ;- (SSC1) Interrupt Enable Register -AT91C_SSC1_RC1R EQU (0xFFFD403C) ;- (SSC1) Receive Compare 1 Register -AT91C_SSC1_TSHR EQU (0xFFFD4034) ;- (SSC1) Transmit Sync Holding Register -AT91C_SSC1_THR EQU (0xFFFD4024) ;- (SSC1) Transmit Holding Register -AT91C_SSC1_TFMR EQU (0xFFFD401C) ;- (SSC1) Transmit Frame Mode Register -;- ========== Register definition for PDC_SSC0 peripheral ========== -AT91C_SSC0_PTCR EQU (0xFFFD0120) ;- (PDC_SSC0) PDC Transfer Control Register -AT91C_SSC0_TNPR EQU (0xFFFD0118) ;- (PDC_SSC0) Transmit Next Pointer Register -AT91C_SSC0_RNPR EQU (0xFFFD0110) ;- (PDC_SSC0) Receive Next Pointer Register -AT91C_SSC0_TPR EQU (0xFFFD0108) ;- (PDC_SSC0) Transmit Pointer Register -AT91C_SSC0_RPR EQU (0xFFFD0100) ;- (PDC_SSC0) Receive Pointer Register -AT91C_SSC0_PTSR EQU (0xFFFD0124) ;- (PDC_SSC0) PDC Transfer Status Register -AT91C_SSC0_TNCR EQU (0xFFFD011C) ;- (PDC_SSC0) Transmit Next Counter Register -AT91C_SSC0_RNCR EQU (0xFFFD0114) ;- (PDC_SSC0) Receive Next Counter Register -AT91C_SSC0_TCR EQU (0xFFFD010C) ;- (PDC_SSC0) Transmit Counter Register -AT91C_SSC0_RCR EQU (0xFFFD0104) ;- (PDC_SSC0) Receive Counter Register -;- ========== Register definition for SSC0 peripheral ========== -AT91C_SSC0_IMR EQU (0xFFFD004C) ;- (SSC0) Interrupt Mask Register -AT91C_SSC0_IER EQU (0xFFFD0044) ;- (SSC0) Interrupt Enable Register -AT91C_SSC0_RC1R EQU (0xFFFD003C) ;- (SSC0) Receive Compare 1 Register -AT91C_SSC0_TSHR EQU (0xFFFD0034) ;- (SSC0) Transmit Sync Holding Register -AT91C_SSC0_THR EQU (0xFFFD0024) ;- (SSC0) Transmit Holding Register -AT91C_SSC0_TFMR EQU (0xFFFD001C) ;- (SSC0) Transmit Frame Mode Register -AT91C_SSC0_RFMR EQU (0xFFFD0014) ;- (SSC0) Receive Frame Mode Register -AT91C_SSC0_CMR EQU (0xFFFD0004) ;- (SSC0) Clock Mode Register -AT91C_SSC0_IDR EQU (0xFFFD0048) ;- (SSC0) Interrupt Disable Register -AT91C_SSC0_SR EQU (0xFFFD0040) ;- (SSC0) Status Register -AT91C_SSC0_RC0R EQU (0xFFFD0038) ;- (SSC0) Receive Compare 0 Register -AT91C_SSC0_RSHR EQU (0xFFFD0030) ;- (SSC0) Receive Sync Holding Register -AT91C_SSC0_RHR EQU (0xFFFD0020) ;- (SSC0) Receive Holding Register -AT91C_SSC0_TCMR EQU (0xFFFD0018) ;- (SSC0) Transmit Clock Mode Register -AT91C_SSC0_RCMR EQU (0xFFFD0010) ;- (SSC0) Receive Clock ModeRegister -AT91C_SSC0_CR EQU (0xFFFD0000) ;- (SSC0) Control Register -;- ========== Register definition for PDC_US3 peripheral ========== -AT91C_US3_PTSR EQU (0xFFFCC124) ;- (PDC_US3) PDC Transfer Status Register -AT91C_US3_TNCR EQU (0xFFFCC11C) ;- (PDC_US3) Transmit Next Counter Register -AT91C_US3_RNCR EQU (0xFFFCC114) ;- (PDC_US3) Receive Next Counter Register -AT91C_US3_TCR EQU (0xFFFCC10C) ;- (PDC_US3) Transmit Counter Register -AT91C_US3_RCR EQU (0xFFFCC104) ;- (PDC_US3) Receive Counter Register -AT91C_US3_PTCR EQU (0xFFFCC120) ;- (PDC_US3) PDC Transfer Control Register -AT91C_US3_TNPR EQU (0xFFFCC118) ;- (PDC_US3) Transmit Next Pointer Register -AT91C_US3_RNPR EQU (0xFFFCC110) ;- (PDC_US3) Receive Next Pointer Register -AT91C_US3_TPR EQU (0xFFFCC108) ;- (PDC_US3) Transmit Pointer Register -AT91C_US3_RPR EQU (0xFFFCC100) ;- (PDC_US3) Receive Pointer Register -;- ========== Register definition for US3 peripheral ========== -AT91C_US3_IF EQU (0xFFFCC04C) ;- (US3) IRDA_FILTER Register -AT91C_US3_NER EQU (0xFFFCC044) ;- (US3) Nb Errors Register -AT91C_US3_RTOR EQU (0xFFFCC024) ;- (US3) Receiver Time-out Register -AT91C_US3_THR EQU (0xFFFCC01C) ;- (US3) Transmitter Holding Register -AT91C_US3_CSR EQU (0xFFFCC014) ;- (US3) Channel Status Register -AT91C_US3_IDR EQU (0xFFFCC00C) ;- (US3) Interrupt Disable Register -AT91C_US3_MR EQU (0xFFFCC004) ;- (US3) Mode Register -AT91C_US3_XXR EQU (0xFFFCC048) ;- (US3) XON_XOFF Register -AT91C_US3_FIDI EQU (0xFFFCC040) ;- (US3) FI_DI_Ratio Register -AT91C_US3_TTGR EQU (0xFFFCC028) ;- (US3) Transmitter Time-guard Register -AT91C_US3_BRGR EQU (0xFFFCC020) ;- (US3) Baud Rate Generator Register -AT91C_US3_RHR EQU (0xFFFCC018) ;- (US3) Receiver Holding Register -AT91C_US3_IMR EQU (0xFFFCC010) ;- (US3) Interrupt Mask Register -AT91C_US3_IER EQU (0xFFFCC008) ;- (US3) Interrupt Enable Register -AT91C_US3_CR EQU (0xFFFCC000) ;- (US3) Control Register -;- ========== Register definition for PDC_US2 peripheral ========== -AT91C_US2_PTSR EQU (0xFFFC8124) ;- (PDC_US2) PDC Transfer Status Register -AT91C_US2_TNCR EQU (0xFFFC811C) ;- (PDC_US2) Transmit Next Counter Register -AT91C_US2_RNCR EQU (0xFFFC8114) ;- (PDC_US2) Receive Next Counter Register -AT91C_US2_TCR EQU (0xFFFC810C) ;- (PDC_US2) Transmit Counter Register -AT91C_US2_PTCR EQU (0xFFFC8120) ;- (PDC_US2) PDC Transfer Control Register -AT91C_US2_RCR EQU (0xFFFC8104) ;- (PDC_US2) Receive Counter Register -AT91C_US2_TNPR EQU (0xFFFC8118) ;- (PDC_US2) Transmit Next Pointer Register -AT91C_US2_RPR EQU (0xFFFC8100) ;- (PDC_US2) Receive Pointer Register -AT91C_US2_TPR EQU (0xFFFC8108) ;- (PDC_US2) Transmit Pointer Register -AT91C_US2_RNPR EQU (0xFFFC8110) ;- (PDC_US2) Receive Next Pointer Register -;- ========== Register definition for US2 peripheral ========== -AT91C_US2_XXR EQU (0xFFFC8048) ;- (US2) XON_XOFF Register -AT91C_US2_FIDI EQU (0xFFFC8040) ;- (US2) FI_DI_Ratio Register -AT91C_US2_TTGR EQU (0xFFFC8028) ;- (US2) Transmitter Time-guard Register -AT91C_US2_BRGR EQU (0xFFFC8020) ;- (US2) Baud Rate Generator Register -AT91C_US2_RHR EQU (0xFFFC8018) ;- (US2) Receiver Holding Register -AT91C_US2_IMR EQU (0xFFFC8010) ;- (US2) Interrupt Mask Register -AT91C_US2_IER EQU (0xFFFC8008) ;- (US2) Interrupt Enable Register -AT91C_US2_CR EQU (0xFFFC8000) ;- (US2) Control Register -AT91C_US2_IF EQU (0xFFFC804C) ;- (US2) IRDA_FILTER Register -AT91C_US2_NER EQU (0xFFFC8044) ;- (US2) Nb Errors Register -AT91C_US2_RTOR EQU (0xFFFC8024) ;- (US2) Receiver Time-out Register -AT91C_US2_THR EQU (0xFFFC801C) ;- (US2) Transmitter Holding Register -AT91C_US2_CSR EQU (0xFFFC8014) ;- (US2) Channel Status Register -AT91C_US2_IDR EQU (0xFFFC800C) ;- (US2) Interrupt Disable Register -AT91C_US2_MR EQU (0xFFFC8004) ;- (US2) Mode Register -;- ========== Register definition for PDC_US1 peripheral ========== -AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register -AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register -AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register -AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register -AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register -AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register -AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register -AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register -AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register -AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register -;- ========== Register definition for US1 peripheral ========== -AT91C_US1_XXR EQU (0xFFFC4048) ;- (US1) XON_XOFF Register -AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register -AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register -AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register -AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register -AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register -AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register -AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register -AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register -AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register -AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register -AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register -AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register -AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register -AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register -;- ========== Register definition for PDC_US0 peripheral ========== -AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register -AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register -AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register -AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register -AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register -AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register -AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register -AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register -AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register -AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register -;- ========== Register definition for US0 peripheral ========== -AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register -AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register -AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register -AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register -AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register -AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register -AT91C_US0_XXR EQU (0xFFFC0048) ;- (US0) XON_XOFF Register -AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register -AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register -AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register -AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register -AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register -AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register -AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register -AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register -;- ========== Register definition for TWI peripheral ========== -AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register -AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register -AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register -AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register -AT91C_TWI_SMR EQU (0xFFFB8008) ;- (TWI) Slave Mode Register -AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register -AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register -AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register -AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register -AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register -AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register -;- ========== Register definition for PDC_MCI peripheral ========== -AT91C_MCI_PTCR EQU (0xFFFB4120) ;- (PDC_MCI) PDC Transfer Control Register -AT91C_MCI_TNPR EQU (0xFFFB4118) ;- (PDC_MCI) Transmit Next Pointer Register -AT91C_MCI_RNPR EQU (0xFFFB4110) ;- (PDC_MCI) Receive Next Pointer Register -AT91C_MCI_TPR EQU (0xFFFB4108) ;- (PDC_MCI) Transmit Pointer Register -AT91C_MCI_RPR EQU (0xFFFB4100) ;- (PDC_MCI) Receive Pointer Register -AT91C_MCI_PTSR EQU (0xFFFB4124) ;- (PDC_MCI) PDC Transfer Status Register -AT91C_MCI_TNCR EQU (0xFFFB411C) ;- (PDC_MCI) Transmit Next Counter Register -AT91C_MCI_RNCR EQU (0xFFFB4114) ;- (PDC_MCI) Receive Next Counter Register -AT91C_MCI_TCR EQU (0xFFFB410C) ;- (PDC_MCI) Transmit Counter Register -AT91C_MCI_RCR EQU (0xFFFB4104) ;- (PDC_MCI) Receive Counter Register -;- ========== Register definition for MCI peripheral ========== -AT91C_MCI_IDR EQU (0xFFFB4048) ;- (MCI) MCI Interrupt Disable Register -AT91C_MCI_SR EQU (0xFFFB4040) ;- (MCI) MCI Status Register -AT91C_MCI_RDR EQU (0xFFFB4030) ;- (MCI) MCI Receive Data Register -AT91C_MCI_RSPR EQU (0xFFFB4020) ;- (MCI) MCI Response Register -AT91C_MCI_ARGR EQU (0xFFFB4010) ;- (MCI) MCI Argument Register -AT91C_MCI_DTOR EQU (0xFFFB4008) ;- (MCI) MCI Data Timeout Register -AT91C_MCI_CR EQU (0xFFFB4000) ;- (MCI) MCI Control Register -AT91C_MCI_IMR EQU (0xFFFB404C) ;- (MCI) MCI Interrupt Mask Register -AT91C_MCI_IER EQU (0xFFFB4044) ;- (MCI) MCI Interrupt Enable Register -AT91C_MCI_TDR EQU (0xFFFB4034) ;- (MCI) MCI Transmit Data Register -AT91C_MCI_CMDR EQU (0xFFFB4014) ;- (MCI) MCI Command Register -AT91C_MCI_SDCR EQU (0xFFFB400C) ;- (MCI) MCI SD Card Register -AT91C_MCI_MR EQU (0xFFFB4004) ;- (MCI) MCI Mode Register -;- ========== Register definition for UDP peripheral ========== -AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register -AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register -AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register -AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register -AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register -AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register -AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register -AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register -AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register -AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register -AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register -;- ========== Register definition for TC5 peripheral ========== -AT91C_TC5_CMR EQU (0xFFFA4084) ;- (TC5) Channel Mode Register -AT91C_TC5_IDR EQU (0xFFFA40A8) ;- (TC5) Interrupt Disable Register -AT91C_TC5_SR EQU (0xFFFA40A0) ;- (TC5) Status Register -AT91C_TC5_RB EQU (0xFFFA4098) ;- (TC5) Register B -AT91C_TC5_CV EQU (0xFFFA4090) ;- (TC5) Counter Value -AT91C_TC5_CCR EQU (0xFFFA4080) ;- (TC5) Channel Control Register -AT91C_TC5_IMR EQU (0xFFFA40AC) ;- (TC5) Interrupt Mask Register -AT91C_TC5_IER EQU (0xFFFA40A4) ;- (TC5) Interrupt Enable Register -AT91C_TC5_RC EQU (0xFFFA409C) ;- (TC5) Register C -AT91C_TC5_RA EQU (0xFFFA4094) ;- (TC5) Register A -;- ========== Register definition for TC4 peripheral ========== -AT91C_TC4_IMR EQU (0xFFFA406C) ;- (TC4) Interrupt Mask Register -AT91C_TC4_IER EQU (0xFFFA4064) ;- (TC4) Interrupt Enable Register -AT91C_TC4_RC EQU (0xFFFA405C) ;- (TC4) Register C -AT91C_TC4_RA EQU (0xFFFA4054) ;- (TC4) Register A -AT91C_TC4_CMR EQU (0xFFFA4044) ;- (TC4) Channel Mode Register -AT91C_TC4_IDR EQU (0xFFFA4068) ;- (TC4) Interrupt Disable Register -AT91C_TC4_SR EQU (0xFFFA4060) ;- (TC4) Status Register -AT91C_TC4_RB EQU (0xFFFA4058) ;- (TC4) Register B -AT91C_TC4_CV EQU (0xFFFA4050) ;- (TC4) Counter Value -AT91C_TC4_CCR EQU (0xFFFA4040) ;- (TC4) Channel Control Register -;- ========== Register definition for TC3 peripheral ========== -AT91C_TC3_IMR EQU (0xFFFA402C) ;- (TC3) Interrupt Mask Register -AT91C_TC3_CV EQU (0xFFFA4010) ;- (TC3) Counter Value -AT91C_TC3_CCR EQU (0xFFFA4000) ;- (TC3) Channel Control Register -AT91C_TC3_IER EQU (0xFFFA4024) ;- (TC3) Interrupt Enable Register -AT91C_TC3_CMR EQU (0xFFFA4004) ;- (TC3) Channel Mode Register -AT91C_TC3_RA EQU (0xFFFA4014) ;- (TC3) Register A -AT91C_TC3_RC EQU (0xFFFA401C) ;- (TC3) Register C -AT91C_TC3_IDR EQU (0xFFFA4028) ;- (TC3) Interrupt Disable Register -AT91C_TC3_RB EQU (0xFFFA4018) ;- (TC3) Register B -AT91C_TC3_SR EQU (0xFFFA4020) ;- (TC3) Status Register -;- ========== Register definition for TCB1 peripheral ========== -AT91C_TCB1_BCR EQU (0xFFFA4140) ;- (TCB1) TC Block Control Register -AT91C_TCB1_BMR EQU (0xFFFA4144) ;- (TCB1) TC Block Mode Register -;- ========== Register definition for TC2 peripheral ========== -AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register -AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register -AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C -AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A -AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register -AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register -AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register -AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B -AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value -AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register -;- ========== Register definition for TC1 peripheral ========== -AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register -AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register -AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C -AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A -AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register -AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register -AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register -AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B -AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value -AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register -;- ========== Register definition for TC0 peripheral ========== -AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register -AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register -AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C -AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A -AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register -AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register -AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register -AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B -AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value -AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register -;- ========== Register definition for TCB0 peripheral ========== -AT91C_TCB0_BMR EQU (0xFFFA00C4) ;- (TCB0) TC Block Mode Register -AT91C_TCB0_BCR EQU (0xFFFA00C0) ;- (TCB0) TC Block Control Register -;- ========== Register definition for UHP peripheral ========== -AT91C_UHP_HcRhDescriptorA EQU (0x00300048) ;- (UHP) Root Hub characteristics A -AT91C_UHP_HcRhPortStatus EQU (0x00300054) ;- (UHP) Root Hub Port Status Register -AT91C_UHP_HcRhDescriptorB EQU (0x0030004C) ;- (UHP) Root Hub characteristics B -AT91C_UHP_HcControl EQU (0x00300004) ;- (UHP) Operating modes for the Host Controller -AT91C_UHP_HcInterruptStatus EQU (0x0030000C) ;- (UHP) Interrupt Status Register -AT91C_UHP_HcRhStatus EQU (0x00300050) ;- (UHP) Root Hub Status register -AT91C_UHP_HcRevision EQU (0x00300000) ;- (UHP) Revision -AT91C_UHP_HcCommandStatus EQU (0x00300008) ;- (UHP) Command & status Register -AT91C_UHP_HcInterruptEnable EQU (0x00300010) ;- (UHP) Interrupt Enable Register -AT91C_UHP_HcHCCA EQU (0x00300018) ;- (UHP) Pointer to the Host Controller Communication Area -AT91C_UHP_HcControlHeadED EQU (0x00300020) ;- (UHP) First Endpoint Descriptor of the Control list -AT91C_UHP_HcInterruptDisable EQU (0x00300014) ;- (UHP) Interrupt Disable Register -AT91C_UHP_HcPeriodCurrentED EQU (0x0030001C) ;- (UHP) Current Isochronous or Interrupt Endpoint Descriptor -AT91C_UHP_HcControlCurrentED EQU (0x00300024) ;- (UHP) Endpoint Control and Status Register -AT91C_UHP_HcBulkCurrentED EQU (0x0030002C) ;- (UHP) Current endpoint of the Bulk list -AT91C_UHP_HcFmInterval EQU (0x00300034) ;- (UHP) Bit time between 2 consecutive SOFs -AT91C_UHP_HcBulkHeadED EQU (0x00300028) ;- (UHP) First endpoint register of the Bulk list -AT91C_UHP_HcBulkDoneHead EQU (0x00300030) ;- (UHP) Last completed transfer descriptor -AT91C_UHP_HcFmRemaining EQU (0x00300038) ;- (UHP) Bit time remaining in the current Frame -AT91C_UHP_HcPeriodicStart EQU (0x00300040) ;- (UHP) Periodic Start -AT91C_UHP_HcLSThreshold EQU (0x00300044) ;- (UHP) LS Threshold -AT91C_UHP_HcFmNumber EQU (0x0030003C) ;- (UHP) Frame number -;- ========== Register definition for EMAC peripheral ========== -AT91C_EMAC_RSR EQU (0xFFFBC020) ;- (EMAC) Receive Status Register -AT91C_EMAC_MAN EQU (0xFFFBC034) ;- (EMAC) PHY Maintenance Register -AT91C_EMAC_HSH EQU (0xFFFBC090) ;- (EMAC) Hash Address High[63:32] -AT91C_EMAC_MCOL EQU (0xFFFBC048) ;- (EMAC) Multiple Collision Frame Register -AT91C_EMAC_IER EQU (0xFFFBC028) ;- (EMAC) Interrupt Enable Register -AT91C_EMAC_SA2H EQU (0xFFFBC0A4) ;- (EMAC) Specific Address 2 High, Last 2 bytes -AT91C_EMAC_HSL EQU (0xFFFBC094) ;- (EMAC) Hash Address Low[31:0] -AT91C_EMAC_LCOL EQU (0xFFFBC05C) ;- (EMAC) Late Collision Register -AT91C_EMAC_OK EQU (0xFFFBC04C) ;- (EMAC) Frames Received OK Register -AT91C_EMAC_CFG EQU (0xFFFBC004) ;- (EMAC) Network Configuration Register -AT91C_EMAC_SA3L EQU (0xFFFBC0A8) ;- (EMAC) Specific Address 3 Low, First 4 bytes -AT91C_EMAC_SEQE EQU (0xFFFBC050) ;- (EMAC) Frame Check Sequence Error Register -AT91C_EMAC_ECOL EQU (0xFFFBC060) ;- (EMAC) Excessive Collision Register -AT91C_EMAC_ELR EQU (0xFFFBC070) ;- (EMAC) Excessive Length Error Register -AT91C_EMAC_SR EQU (0xFFFBC008) ;- (EMAC) Network Status Register -AT91C_EMAC_RBQP EQU (0xFFFBC018) ;- (EMAC) Receive Buffer Queue Pointer -AT91C_EMAC_CSE EQU (0xFFFBC064) ;- (EMAC) Carrier Sense Error Register -AT91C_EMAC_RJB EQU (0xFFFBC074) ;- (EMAC) Receive Jabber Register -AT91C_EMAC_USF EQU (0xFFFBC078) ;- (EMAC) Undersize Frame Register -AT91C_EMAC_IDR EQU (0xFFFBC02C) ;- (EMAC) Interrupt Disable Register -AT91C_EMAC_SA1L EQU (0xFFFBC098) ;- (EMAC) Specific Address 1 Low, First 4 bytes -AT91C_EMAC_IMR EQU (0xFFFBC030) ;- (EMAC) Interrupt Mask Register -AT91C_EMAC_FRA EQU (0xFFFBC040) ;- (EMAC) Frames Transmitted OK Register -AT91C_EMAC_SA3H EQU (0xFFFBC0AC) ;- (EMAC) Specific Address 3 High, Last 2 bytes -AT91C_EMAC_SA1H EQU (0xFFFBC09C) ;- (EMAC) Specific Address 1 High, Last 2 bytes -AT91C_EMAC_SCOL EQU (0xFFFBC044) ;- (EMAC) Single Collision Frame Register -AT91C_EMAC_ALE EQU (0xFFFBC054) ;- (EMAC) Alignment Error Register -AT91C_EMAC_TAR EQU (0xFFFBC00C) ;- (EMAC) Transmit Address Register -AT91C_EMAC_SA4L EQU (0xFFFBC0B0) ;- (EMAC) Specific Address 4 Low, First 4 bytes -AT91C_EMAC_SA2L EQU (0xFFFBC0A0) ;- (EMAC) Specific Address 2 Low, First 4 bytes -AT91C_EMAC_TUE EQU (0xFFFBC068) ;- (EMAC) Transmit Underrun Error Register -AT91C_EMAC_DTE EQU (0xFFFBC058) ;- (EMAC) Deferred Transmission Frame Register -AT91C_EMAC_TCR EQU (0xFFFBC010) ;- (EMAC) Transmit Control Register -AT91C_EMAC_CTL EQU (0xFFFBC000) ;- (EMAC) Network Control Register -AT91C_EMAC_SA4H EQU (0xFFFBC0B4) ;- (EMAC) Specific Address 4 High, Last 2 bytesr -AT91C_EMAC_CDE EQU (0xFFFBC06C) ;- (EMAC) Code Error Register -AT91C_EMAC_SQEE EQU (0xFFFBC07C) ;- (EMAC) SQE Test Error Register -AT91C_EMAC_TSR EQU (0xFFFBC014) ;- (EMAC) Transmit Status Register -AT91C_EMAC_DRFC EQU (0xFFFBC080) ;- (EMAC) Discarded RX Frame Register -;- ========== Register definition for EBI peripheral ========== -AT91C_EBI_CFGR EQU (0xFFFFFF64) ;- (EBI) Configuration Register -AT91C_EBI_CSA EQU (0xFFFFFF60) ;- (EBI) Chip Select Assignment Register -;- ========== Register definition for SMC2 peripheral ========== -AT91C_SMC2_CSR EQU (0xFFFFFF70) ;- (SMC2) SMC2 Chip Select Register -;- ========== Register definition for SDRC peripheral ========== -AT91C_SDRC_IMR EQU (0xFFFFFFAC) ;- (SDRC) SDRAM Controller Interrupt Mask Register -AT91C_SDRC_IER EQU (0xFFFFFFA4) ;- (SDRC) SDRAM Controller Interrupt Enable Register -AT91C_SDRC_SRR EQU (0xFFFFFF9C) ;- (SDRC) SDRAM Controller Self Refresh Register -AT91C_SDRC_TR EQU (0xFFFFFF94) ;- (SDRC) SDRAM Controller Refresh Timer Register -AT91C_SDRC_ISR EQU (0xFFFFFFB0) ;- (SDRC) SDRAM Controller Interrupt Mask Register -AT91C_SDRC_IDR EQU (0xFFFFFFA8) ;- (SDRC) SDRAM Controller Interrupt Disable Register -AT91C_SDRC_LPR EQU (0xFFFFFFA0) ;- (SDRC) SDRAM Controller Low Power Register -AT91C_SDRC_CR EQU (0xFFFFFF98) ;- (SDRC) SDRAM Controller Configuration Register -AT91C_SDRC_MR EQU (0xFFFFFF90) ;- (SDRC) SDRAM Controller Mode Register -;- ========== Register definition for BFC peripheral ========== -AT91C_BFC_MR EQU (0xFFFFFFC0) ;- (BFC) BFC Mode Register - -;- ***************************************************************************** -;- PIO DEFINITIONS FOR AT91RM9200 -;- ***************************************************************************** -AT91C_PIO_PA0 EQU (1:SHL:0) ;- Pin Controlled by PA0 -AT91C_PA0_MISO EQU (AT91C_PIO_PA0) ;- SPI Master In Slave -AT91C_PA0_PCK3 EQU (AT91C_PIO_PA0) ;- PMC Programmable Clock Output 3 -AT91C_PIO_PA1 EQU (1:SHL:1) ;- Pin Controlled by PA1 -AT91C_PA1_MOSI EQU (AT91C_PIO_PA1) ;- SPI Master Out Slave -AT91C_PA1_PCK0 EQU (AT91C_PIO_PA1) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PA10 EQU (1:SHL:10) ;- Pin Controlled by PA10 -AT91C_PA10_ETX1 EQU (AT91C_PIO_PA10) ;- Ethernet MAC Transmit Data 1 -AT91C_PA10_MCDB1 EQU (AT91C_PIO_PA10) ;- Multimedia Card B Data 1 -AT91C_PIO_PA11 EQU (1:SHL:11) ;- Pin Controlled by PA11 -AT91C_PA11_ECRS_ECRSDV EQU (AT91C_PIO_PA11) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -AT91C_PA11_MCDB2 EQU (AT91C_PIO_PA11) ;- Multimedia Card B Data 2 -AT91C_PIO_PA12 EQU (1:SHL:12) ;- Pin Controlled by PA12 -AT91C_PA12_ERX0 EQU (AT91C_PIO_PA12) ;- Ethernet MAC Receive Data 0 -AT91C_PA12_MCDB3 EQU (AT91C_PIO_PA12) ;- Multimedia Card B Data 3 -AT91C_PIO_PA13 EQU (1:SHL:13) ;- Pin Controlled by PA13 -AT91C_PA13_ERX1 EQU (AT91C_PIO_PA13) ;- Ethernet MAC Receive Data 1 -AT91C_PA13_TCLK0 EQU (AT91C_PIO_PA13) ;- Timer Counter 0 external clock input -AT91C_PIO_PA14 EQU (1:SHL:14) ;- Pin Controlled by PA14 -AT91C_PA14_ERXER EQU (AT91C_PIO_PA14) ;- Ethernet MAC Receive Error -AT91C_PA14_TCLK1 EQU (AT91C_PIO_PA14) ;- Timer Counter 1 external clock input -AT91C_PIO_PA15 EQU (1:SHL:15) ;- Pin Controlled by PA15 -AT91C_PA15_EMDC EQU (AT91C_PIO_PA15) ;- Ethernet MAC Management Data Clock -AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input -AT91C_PIO_PA16 EQU (1:SHL:16) ;- Pin Controlled by PA16 -AT91C_PA16_EMDIO EQU (AT91C_PIO_PA16) ;- Ethernet MAC Management Data Input/Output -AT91C_PA16_IRQ6 EQU (AT91C_PIO_PA16) ;- AIC Interrupt input 6 -AT91C_PIO_PA17 EQU (1:SHL:17) ;- Pin Controlled by PA17 -AT91C_PA17_TXD0 EQU (AT91C_PIO_PA17) ;- USART 0 Transmit Data -AT91C_PA17_TIOA0 EQU (AT91C_PIO_PA17) ;- Timer Counter 0 Multipurpose Timer I/O Pin A -AT91C_PIO_PA18 EQU (1:SHL:18) ;- Pin Controlled by PA18 -AT91C_PA18_RXD0 EQU (AT91C_PIO_PA18) ;- USART 0 Receive Data -AT91C_PA18_TIOB0 EQU (AT91C_PIO_PA18) ;- Timer Counter 0 Multipurpose Timer I/O Pin B -AT91C_PIO_PA19 EQU (1:SHL:19) ;- Pin Controlled by PA19 -AT91C_PA19_SCK0 EQU (AT91C_PIO_PA19) ;- USART 0 Serial Clock -AT91C_PA19_TIOA1 EQU (AT91C_PIO_PA19) ;- Timer Counter 1 Multipurpose Timer I/O Pin A -AT91C_PIO_PA2 EQU (1:SHL:2) ;- Pin Controlled by PA2 -AT91C_PA2_SPCK EQU (AT91C_PIO_PA2) ;- SPI Serial Clock -AT91C_PA2_IRQ4 EQU (AT91C_PIO_PA2) ;- AIC Interrupt Input 4 -AT91C_PIO_PA20 EQU (1:SHL:20) ;- Pin Controlled by PA20 -AT91C_PA20_CTS0 EQU (AT91C_PIO_PA20) ;- USART 0 Clear To Send -AT91C_PA20_TIOB1 EQU (AT91C_PIO_PA20) ;- Timer Counter 1 Multipurpose Timer I/O Pin B -AT91C_PIO_PA21 EQU (1:SHL:21) ;- Pin Controlled by PA21 -AT91C_PA21_RTS0 EQU (AT91C_PIO_PA21) ;- Usart 0 Ready To Send -AT91C_PA21_TIOA2 EQU (AT91C_PIO_PA21) ;- Timer Counter 2 Multipurpose Timer I/O Pin A -AT91C_PIO_PA22 EQU (1:SHL:22) ;- Pin Controlled by PA22 -AT91C_PA22_RXD2 EQU (AT91C_PIO_PA22) ;- USART 2 Receive Data -AT91C_PA22_TIOB2 EQU (AT91C_PIO_PA22) ;- Timer Counter 2 Multipurpose Timer I/O Pin B -AT91C_PIO_PA23 EQU (1:SHL:23) ;- Pin Controlled by PA23 -AT91C_PA23_TXD2 EQU (AT91C_PIO_PA23) ;- USART 2 Transmit Data -AT91C_PA23_IRQ3 EQU (AT91C_PIO_PA23) ;- Interrupt input 3 -AT91C_PIO_PA24 EQU (1:SHL:24) ;- Pin Controlled by PA24 -AT91C_PA24_SCK2 EQU (AT91C_PIO_PA24) ;- USART2 Serial Clock -AT91C_PA24_PCK1 EQU (AT91C_PIO_PA24) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA25 EQU (1:SHL:25) ;- Pin Controlled by PA25 -AT91C_PA25_TWD EQU (AT91C_PIO_PA25) ;- TWI Two-wire Serial Data -AT91C_PA25_IRQ2 EQU (AT91C_PIO_PA25) ;- Interrupt input 2 -AT91C_PIO_PA26 EQU (1:SHL:26) ;- Pin Controlled by PA26 -AT91C_PA26_TWCK EQU (AT91C_PIO_PA26) ;- TWI Two-wire Serial Clock -AT91C_PA26_IRQ1 EQU (AT91C_PIO_PA26) ;- Interrupt input 1 -AT91C_PIO_PA27 EQU (1:SHL:27) ;- Pin Controlled by PA27 -AT91C_PA27_MCCK EQU (AT91C_PIO_PA27) ;- Multimedia Card Clock -AT91C_PA27_TCLK3 EQU (AT91C_PIO_PA27) ;- Timer Counter 3 External Clock Input -AT91C_PIO_PA28 EQU (1:SHL:28) ;- Pin Controlled by PA28 -AT91C_PA28_MCCDA EQU (AT91C_PIO_PA28) ;- Multimedia Card A Command -AT91C_PA28_TCLK4 EQU (AT91C_PIO_PA28) ;- Timer Counter 4 external Clock Input -AT91C_PIO_PA29 EQU (1:SHL:29) ;- Pin Controlled by PA29 -AT91C_PA29_MCDA0 EQU (AT91C_PIO_PA29) ;- Multimedia Card A Data 0 -AT91C_PA29_TCLK5 EQU (AT91C_PIO_PA29) ;- Timer Counter 5 external clock input -AT91C_PIO_PA3 EQU (1:SHL:3) ;- Pin Controlled by PA3 -AT91C_PA3_NPCS0 EQU (AT91C_PIO_PA3) ;- SPI Peripheral Chip Select 0 -AT91C_PA3_IRQ5 EQU (AT91C_PIO_PA3) ;- AIC Interrupt Input 5 -AT91C_PIO_PA30 EQU (1:SHL:30) ;- Pin Controlled by PA30 -AT91C_PA30_DRXD EQU (AT91C_PIO_PA30) ;- DBGU Debug Receive Data -AT91C_PA30_CTS2 EQU (AT91C_PIO_PA30) ;- Usart 2 Clear To Send -AT91C_PIO_PA31 EQU (1:SHL:31) ;- Pin Controlled by PA31 -AT91C_PA31_DTXD EQU (AT91C_PIO_PA31) ;- DBGU Debug Transmit Data -AT91C_PA31_RTS2 EQU (AT91C_PIO_PA31) ;- USART 2 Ready To Send -AT91C_PIO_PA4 EQU (1:SHL:4) ;- Pin Controlled by PA4 -AT91C_PA4_NPCS1 EQU (AT91C_PIO_PA4) ;- SPI Peripheral Chip Select 1 -AT91C_PA4_PCK1 EQU (AT91C_PIO_PA4) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA5 EQU (1:SHL:5) ;- Pin Controlled by PA5 -AT91C_PA5_NPCS2 EQU (AT91C_PIO_PA5) ;- SPI Peripheral Chip Select 2 -AT91C_PA5_TXD3 EQU (AT91C_PIO_PA5) ;- USART 3 Transmit Data -AT91C_PIO_PA6 EQU (1:SHL:6) ;- Pin Controlled by PA6 -AT91C_PA6_NPCS3 EQU (AT91C_PIO_PA6) ;- SPI Peripheral Chip Select 3 -AT91C_PA6_RXD3 EQU (AT91C_PIO_PA6) ;- USART 3 Receive Data -AT91C_PIO_PA7 EQU (1:SHL:7) ;- Pin Controlled by PA7 -AT91C_PA7_ETXCK_EREFCK EQU (AT91C_PIO_PA7) ;- Ethernet MAC Transmit Clock/Reference Clock -AT91C_PA7_PCK2 EQU (AT91C_PIO_PA7) ;- PMC Programmable Clock 2 -AT91C_PIO_PA8 EQU (1:SHL:8) ;- Pin Controlled by PA8 -AT91C_PA8_ETXEN EQU (AT91C_PIO_PA8) ;- Ethernet MAC Transmit Enable -AT91C_PA8_MCCDB EQU (AT91C_PIO_PA8) ;- Multimedia Card B Command -AT91C_PIO_PA9 EQU (1:SHL:9) ;- Pin Controlled by PA9 -AT91C_PA9_ETX0 EQU (AT91C_PIO_PA9) ;- Ethernet MAC Transmit Data 0 -AT91C_PA9_MCDB0 EQU (AT91C_PIO_PA9) ;- Multimedia Card B Data 0 -AT91C_PIO_PB0 EQU (1:SHL:0) ;- Pin Controlled by PB0 -AT91C_PB0_TF0 EQU (AT91C_PIO_PB0) ;- SSC Transmit Frame Sync 0 -AT91C_PB0_TIOB3 EQU (AT91C_PIO_PB0) ;- Timer Counter 3 Multipurpose Timer I/O Pin B -AT91C_PIO_PB1 EQU (1:SHL:1) ;- Pin Controlled by PB1 -AT91C_PB1_TK0 EQU (AT91C_PIO_PB1) ;- SSC Transmit Clock 0 -AT91C_PB1_CTS3 EQU (AT91C_PIO_PB1) ;- USART 3 Clear To Send -AT91C_PIO_PB10 EQU (1:SHL:10) ;- Pin Controlled by PB10 -AT91C_PB10_RK1 EQU (AT91C_PIO_PB10) ;- SSC Receive Clock 1 -AT91C_PB10_TIOA5 EQU (AT91C_PIO_PB10) ;- Timer Counter 5 Multipurpose Timer I/O Pin A -AT91C_PIO_PB11 EQU (1:SHL:11) ;- Pin Controlled by PB11 -AT91C_PB11_RF1 EQU (AT91C_PIO_PB11) ;- SSC Receive Frame Sync 1 -AT91C_PB11_TIOB5 EQU (AT91C_PIO_PB11) ;- Timer Counter 5 Multipurpose Timer I/O Pin B -AT91C_PIO_PB12 EQU (1:SHL:12) ;- Pin Controlled by PB12 -AT91C_PB12_TF2 EQU (AT91C_PIO_PB12) ;- SSC Transmit Frame Sync 2 -AT91C_PB12_ETX2 EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmit Data 2 -AT91C_PIO_PB13 EQU (1:SHL:13) ;- Pin Controlled by PB13 -AT91C_PB13_TK2 EQU (AT91C_PIO_PB13) ;- SSC Transmit Clock 2 -AT91C_PB13_ETX3 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Transmit Data 3 -AT91C_PIO_PB14 EQU (1:SHL:14) ;- Pin Controlled by PB14 -AT91C_PB14_TD2 EQU (AT91C_PIO_PB14) ;- SSC Transmit Data 2 -AT91C_PB14_ETXER EQU (AT91C_PIO_PB14) ;- Ethernet MAC Transmikt Coding Error -AT91C_PIO_PB15 EQU (1:SHL:15) ;- Pin Controlled by PB15 -AT91C_PB15_RD2 EQU (AT91C_PIO_PB15) ;- SSC Receive Data 2 -AT91C_PB15_ERX2 EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data 2 -AT91C_PIO_PB16 EQU (1:SHL:16) ;- Pin Controlled by PB16 -AT91C_PB16_RK2 EQU (AT91C_PIO_PB16) ;- SSC Receive Clock 2 -AT91C_PB16_ERX3 EQU (AT91C_PIO_PB16) ;- Ethernet MAC Receive Data 3 -AT91C_PIO_PB17 EQU (1:SHL:17) ;- Pin Controlled by PB17 -AT91C_PB17_RF2 EQU (AT91C_PIO_PB17) ;- SSC Receive Frame Sync 2 -AT91C_PB17_ERXDV EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Data Valid -AT91C_PIO_PB18 EQU (1:SHL:18) ;- Pin Controlled by PB18 -AT91C_PB18_RI1 EQU (AT91C_PIO_PB18) ;- USART 1 Ring Indicator -AT91C_PB18_ECOL EQU (AT91C_PIO_PB18) ;- Ethernet MAC Collision Detected -AT91C_PIO_PB19 EQU (1:SHL:19) ;- Pin Controlled by PB19 -AT91C_PB19_DTR1 EQU (AT91C_PIO_PB19) ;- USART 1 Data Terminal ready -AT91C_PB19_ERXCK EQU (AT91C_PIO_PB19) ;- Ethernet MAC Receive Clock -AT91C_PIO_PB2 EQU (1:SHL:2) ;- Pin Controlled by PB2 -AT91C_PB2_TD0 EQU (AT91C_PIO_PB2) ;- SSC Transmit data -AT91C_PB2_SCK3 EQU (AT91C_PIO_PB2) ;- USART 3 Serial Clock -AT91C_PIO_PB20 EQU (1:SHL:20) ;- Pin Controlled by PB20 -AT91C_PB20_TXD1 EQU (AT91C_PIO_PB20) ;- USART 1 Transmit Data -AT91C_PIO_PB21 EQU (1:SHL:21) ;- Pin Controlled by PB21 -AT91C_PB21_RXD1 EQU (AT91C_PIO_PB21) ;- USART 1 Receive Data -AT91C_PIO_PB22 EQU (1:SHL:22) ;- Pin Controlled by PB22 -AT91C_PB22_SCK1 EQU (AT91C_PIO_PB22) ;- USART1 Serial Clock -AT91C_PIO_PB23 EQU (1:SHL:23) ;- Pin Controlled by PB23 -AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect -AT91C_PIO_PB24 EQU (1:SHL:24) ;- Pin Controlled by PB24 -AT91C_PB24_CTS1 EQU (AT91C_PIO_PB24) ;- USART 1 Clear To Send -AT91C_PIO_PB25 EQU (1:SHL:25) ;- Pin Controlled by PB25 -AT91C_PB25_DSR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Set ready -AT91C_PB25_EF100 EQU (AT91C_PIO_PB25) ;- Ethernet MAC Force 100 Mbits/sec -AT91C_PIO_PB26 EQU (1:SHL:26) ;- Pin Controlled by PB26 -AT91C_PB26_RTS1 EQU (AT91C_PIO_PB26) ;- Usart 0 Ready To Send -AT91C_PIO_PB27 EQU (1:SHL:27) ;- Pin Controlled by PB27 -AT91C_PB27_PCK0 EQU (AT91C_PIO_PB27) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB28 EQU (1:SHL:28) ;- Pin Controlled by PB28 -AT91C_PB28_FIQ EQU (AT91C_PIO_PB28) ;- AIC Fast Interrupt Input -AT91C_PIO_PB29 EQU (1:SHL:29) ;- Pin Controlled by PB29 -AT91C_PB29_IRQ0 EQU (AT91C_PIO_PB29) ;- Interrupt input 0 -AT91C_PIO_PB3 EQU (1:SHL:3) ;- Pin Controlled by PB3 -AT91C_PB3_RD0 EQU (AT91C_PIO_PB3) ;- SSC Receive Data -AT91C_PB3_MCDA1 EQU (AT91C_PIO_PB3) ;- Multimedia Card A Data 1 -AT91C_PIO_PB4 EQU (1:SHL:4) ;- Pin Controlled by PB4 -AT91C_PB4_RK0 EQU (AT91C_PIO_PB4) ;- SSC Receive Clock -AT91C_PB4_MCDA2 EQU (AT91C_PIO_PB4) ;- Multimedia Card A Data 2 -AT91C_PIO_PB5 EQU (1:SHL:5) ;- Pin Controlled by PB5 -AT91C_PB5_RF0 EQU (AT91C_PIO_PB5) ;- SSC Receive Frame Sync 0 -AT91C_PB5_MCDA3 EQU (AT91C_PIO_PB5) ;- Multimedia Card A Data 3 -AT91C_PIO_PB6 EQU (1:SHL:6) ;- Pin Controlled by PB6 -AT91C_PB6_TF1 EQU (AT91C_PIO_PB6) ;- SSC Transmit Frame Sync 1 -AT91C_PB6_TIOA3 EQU (AT91C_PIO_PB6) ;- Timer Counter 4 Multipurpose Timer I/O Pin A -AT91C_PIO_PB7 EQU (1:SHL:7) ;- Pin Controlled by PB7 -AT91C_PB7_TK1 EQU (AT91C_PIO_PB7) ;- SSC Transmit Clock 1 -AT91C_PB7_TIOB3 EQU (AT91C_PIO_PB7) ;- Timer Counter 3 Multipurpose Timer I/O Pin B -AT91C_PIO_PB8 EQU (1:SHL:8) ;- Pin Controlled by PB8 -AT91C_PB8_TD1 EQU (AT91C_PIO_PB8) ;- SSC Transmit Data 1 -AT91C_PB8_TIOA4 EQU (AT91C_PIO_PB8) ;- Timer Counter 4 Multipurpose Timer I/O Pin A -AT91C_PIO_PB9 EQU (1:SHL:9) ;- Pin Controlled by PB9 -AT91C_PB9_RD1 EQU (AT91C_PIO_PB9) ;- SSC Receive Data 1 -AT91C_PB9_TIOB4 EQU (AT91C_PIO_PB9) ;- Timer Counter 4 Multipurpose Timer I/O Pin B -AT91C_PIO_PC0 EQU (1:SHL:0) ;- Pin Controlled by PC0 -AT91C_PC0_BFCK EQU (AT91C_PIO_PC0) ;- Burst Flash Clock -AT91C_PIO_PC1 EQU (1:SHL:1) ;- Pin Controlled by PC1 -AT91C_PC1_BFRDY_SMOE EQU (AT91C_PIO_PC1) ;- Burst Flash Ready -AT91C_PIO_PC10 EQU (1:SHL:10) ;- Pin Controlled by PC10 -AT91C_PC10_NCS4_CFCS EQU (AT91C_PIO_PC10) ;- Compact Flash Chip Select -AT91C_PIO_PC11 EQU (1:SHL:11) ;- Pin Controlled by PC11 -AT91C_PC11_NCS5_CFCE1 EQU (AT91C_PIO_PC11) ;- Chip Select 5 / Compact Flash Chip Enable 1 -AT91C_PIO_PC12 EQU (1:SHL:12) ;- Pin Controlled by PC12 -AT91C_PC12_NCS6_CFCE2 EQU (AT91C_PIO_PC12) ;- Chip Select 6 / Compact Flash Chip Enable 2 -AT91C_PIO_PC13 EQU (1:SHL:13) ;- Pin Controlled by PC13 -AT91C_PC13_NCS7 EQU (AT91C_PIO_PC13) ;- Chip Select 7 -AT91C_PIO_PC14 EQU (1:SHL:14) ;- Pin Controlled by PC14 -AT91C_PIO_PC15 EQU (1:SHL:15) ;- Pin Controlled by PC15 -AT91C_PIO_PC16 EQU (1:SHL:16) ;- Pin Controlled by PC16 -AT91C_PC16_D16 EQU (AT91C_PIO_PC16) ;- Data Bus [16] -AT91C_PIO_PC17 EQU (1:SHL:17) ;- Pin Controlled by PC17 -AT91C_PC17_D17 EQU (AT91C_PIO_PC17) ;- Data Bus [17] -AT91C_PIO_PC18 EQU (1:SHL:18) ;- Pin Controlled by PC18 -AT91C_PC18_D18 EQU (AT91C_PIO_PC18) ;- Data Bus [18] -AT91C_PIO_PC19 EQU (1:SHL:19) ;- Pin Controlled by PC19 -AT91C_PC19_D19 EQU (AT91C_PIO_PC19) ;- Data Bus [19] -AT91C_PIO_PC2 EQU (1:SHL:2) ;- Pin Controlled by PC2 -AT91C_PC2_BFAVD EQU (AT91C_PIO_PC2) ;- Burst Flash Address Valid -AT91C_PIO_PC20 EQU (1:SHL:20) ;- Pin Controlled by PC20 -AT91C_PC20_D20 EQU (AT91C_PIO_PC20) ;- Data Bus [20] -AT91C_PIO_PC21 EQU (1:SHL:21) ;- Pin Controlled by PC21 -AT91C_PC21_D21 EQU (AT91C_PIO_PC21) ;- Data Bus [21] -AT91C_PIO_PC22 EQU (1:SHL:22) ;- Pin Controlled by PC22 -AT91C_PC22_D22 EQU (AT91C_PIO_PC22) ;- Data Bus [22] -AT91C_PIO_PC23 EQU (1:SHL:23) ;- Pin Controlled by PC23 -AT91C_PC23_D23 EQU (AT91C_PIO_PC23) ;- Data Bus [23] -AT91C_PIO_PC24 EQU (1:SHL:24) ;- Pin Controlled by PC24 -AT91C_PC24_D24 EQU (AT91C_PIO_PC24) ;- Data Bus [24] -AT91C_PIO_PC25 EQU (1:SHL:25) ;- Pin Controlled by PC25 -AT91C_PC25_D25 EQU (AT91C_PIO_PC25) ;- Data Bus [25] -AT91C_PIO_PC26 EQU (1:SHL:26) ;- Pin Controlled by PC26 -AT91C_PC26_D26 EQU (AT91C_PIO_PC26) ;- Data Bus [26] -AT91C_PIO_PC27 EQU (1:SHL:27) ;- Pin Controlled by PC27 -AT91C_PC27_D27 EQU (AT91C_PIO_PC27) ;- Data Bus [27] -AT91C_PIO_PC28 EQU (1:SHL:28) ;- Pin Controlled by PC28 -AT91C_PC28_D28 EQU (AT91C_PIO_PC28) ;- Data Bus [28] -AT91C_PIO_PC29 EQU (1:SHL:29) ;- Pin Controlled by PC29 -AT91C_PC29_D29 EQU (AT91C_PIO_PC29) ;- Data Bus [29] -AT91C_PIO_PC3 EQU (1:SHL:3) ;- Pin Controlled by PC3 -AT91C_PC3_BFBAA_SMWE EQU (AT91C_PIO_PC3) ;- Burst Flash Address Advance / SmartMedia Write Enable -AT91C_PIO_PC30 EQU (1:SHL:30) ;- Pin Controlled by PC30 -AT91C_PC30_D30 EQU (AT91C_PIO_PC30) ;- Data Bus [30] -AT91C_PIO_PC31 EQU (1:SHL:31) ;- Pin Controlled by PC31 -AT91C_PC31_D31 EQU (AT91C_PIO_PC31) ;- Data Bus [31] -AT91C_PIO_PC4 EQU (1:SHL:4) ;- Pin Controlled by PC4 -AT91C_PC4_BFOE EQU (AT91C_PIO_PC4) ;- Burst Flash Output Enable -AT91C_PIO_PC5 EQU (1:SHL:5) ;- Pin Controlled by PC5 -AT91C_PC5_BFWE EQU (AT91C_PIO_PC5) ;- Burst Flash Write Enable -AT91C_PIO_PC6 EQU (1:SHL:6) ;- Pin Controlled by PC6 -AT91C_PC6_NWAIT EQU (AT91C_PIO_PC6) ;- NWAIT -AT91C_PIO_PC7 EQU (1:SHL:7) ;- Pin Controlled by PC7 -AT91C_PC7_A23 EQU (AT91C_PIO_PC7) ;- Address Bus[23] -AT91C_PIO_PC8 EQU (1:SHL:8) ;- Pin Controlled by PC8 -AT91C_PC8_A24 EQU (AT91C_PIO_PC8) ;- Address Bus[24] -AT91C_PIO_PC9 EQU (1:SHL:9) ;- Pin Controlled by PC9 -AT91C_PC9_A25_CFRNW EQU (AT91C_PIO_PC9) ;- Address Bus[25] / Compact Flash Read Not Write -AT91C_PIO_PD0 EQU (1:SHL:0) ;- Pin Controlled by PD0 -AT91C_PD0_ETX0 EQU (AT91C_PIO_PD0) ;- Ethernet MAC Transmit Data 0 -AT91C_PIO_PD1 EQU (1:SHL:1) ;- Pin Controlled by PD1 -AT91C_PD1_ETX1 EQU (AT91C_PIO_PD1) ;- Ethernet MAC Transmit Data 1 -AT91C_PIO_PD10 EQU (1:SHL:10) ;- Pin Controlled by PD10 -AT91C_PD10_PCK3 EQU (AT91C_PIO_PD10) ;- PMC Programmable Clock Output 3 -AT91C_PD10_TPS1 EQU (AT91C_PIO_PD10) ;- ETM ARM9 pipeline status 1 -AT91C_PIO_PD11 EQU (1:SHL:11) ;- Pin Controlled by PD11 -AT91C_PD11_ EQU (AT91C_PIO_PD11) ;- -AT91C_PD11_TPS2 EQU (AT91C_PIO_PD11) ;- ETM ARM9 pipeline status 2 -AT91C_PIO_PD12 EQU (1:SHL:12) ;- Pin Controlled by PD12 -AT91C_PD12_ EQU (AT91C_PIO_PD12) ;- -AT91C_PD12_TPK0 EQU (AT91C_PIO_PD12) ;- ETM Trace Packet 0 -AT91C_PIO_PD13 EQU (1:SHL:13) ;- Pin Controlled by PD13 -AT91C_PD13_ EQU (AT91C_PIO_PD13) ;- -AT91C_PD13_TPK1 EQU (AT91C_PIO_PD13) ;- ETM Trace Packet 1 -AT91C_PIO_PD14 EQU (1:SHL:14) ;- Pin Controlled by PD14 -AT91C_PD14_ EQU (AT91C_PIO_PD14) ;- -AT91C_PD14_TPK2 EQU (AT91C_PIO_PD14) ;- ETM Trace Packet 2 -AT91C_PIO_PD15 EQU (1:SHL:15) ;- Pin Controlled by PD15 -AT91C_PD15_TD0 EQU (AT91C_PIO_PD15) ;- SSC Transmit data -AT91C_PD15_TPK3 EQU (AT91C_PIO_PD15) ;- ETM Trace Packet 3 -AT91C_PIO_PD16 EQU (1:SHL:16) ;- Pin Controlled by PD16 -AT91C_PD16_TD1 EQU (AT91C_PIO_PD16) ;- SSC Transmit Data 1 -AT91C_PD16_TPK4 EQU (AT91C_PIO_PD16) ;- ETM Trace Packet 4 -AT91C_PIO_PD17 EQU (1:SHL:17) ;- Pin Controlled by PD17 -AT91C_PD17_TD2 EQU (AT91C_PIO_PD17) ;- SSC Transmit Data 2 -AT91C_PD17_TPK5 EQU (AT91C_PIO_PD17) ;- ETM Trace Packet 5 -AT91C_PIO_PD18 EQU (1:SHL:18) ;- Pin Controlled by PD18 -AT91C_PD18_NPCS1 EQU (AT91C_PIO_PD18) ;- SPI Peripheral Chip Select 1 -AT91C_PD18_TPK6 EQU (AT91C_PIO_PD18) ;- ETM Trace Packet 6 -AT91C_PIO_PD19 EQU (1:SHL:19) ;- Pin Controlled by PD19 -AT91C_PD19_NPCS2 EQU (AT91C_PIO_PD19) ;- SPI Peripheral Chip Select 2 -AT91C_PD19_TPK7 EQU (AT91C_PIO_PD19) ;- ETM Trace Packet 7 -AT91C_PIO_PD2 EQU (1:SHL:2) ;- Pin Controlled by PD2 -AT91C_PD2_ETX2 EQU (AT91C_PIO_PD2) ;- Ethernet MAC Transmit Data 2 -AT91C_PIO_PD20 EQU (1:SHL:20) ;- Pin Controlled by PD20 -AT91C_PD20_NPCS3 EQU (AT91C_PIO_PD20) ;- SPI Peripheral Chip Select 3 -AT91C_PD20_TPK8 EQU (AT91C_PIO_PD20) ;- ETM Trace Packet 8 -AT91C_PIO_PD21 EQU (1:SHL:21) ;- Pin Controlled by PD21 -AT91C_PD21_RTS0 EQU (AT91C_PIO_PD21) ;- Usart 0 Ready To Send -AT91C_PD21_TPK9 EQU (AT91C_PIO_PD21) ;- ETM Trace Packet 9 -AT91C_PIO_PD22 EQU (1:SHL:22) ;- Pin Controlled by PD22 -AT91C_PD22_RTS1 EQU (AT91C_PIO_PD22) ;- Usart 0 Ready To Send -AT91C_PD22_TPK10 EQU (AT91C_PIO_PD22) ;- ETM Trace Packet 10 -AT91C_PIO_PD23 EQU (1:SHL:23) ;- Pin Controlled by PD23 -AT91C_PD23_RTS2 EQU (AT91C_PIO_PD23) ;- USART 2 Ready To Send -AT91C_PD23_TPK11 EQU (AT91C_PIO_PD23) ;- ETM Trace Packet 11 -AT91C_PIO_PD24 EQU (1:SHL:24) ;- Pin Controlled by PD24 -AT91C_PD24_RTS3 EQU (AT91C_PIO_PD24) ;- USART 3 Ready To Send -AT91C_PD24_TPK12 EQU (AT91C_PIO_PD24) ;- ETM Trace Packet 12 -AT91C_PIO_PD25 EQU (1:SHL:25) ;- Pin Controlled by PD25 -AT91C_PD25_DTR1 EQU (AT91C_PIO_PD25) ;- USART 1 Data Terminal ready -AT91C_PD25_TPK13 EQU (AT91C_PIO_PD25) ;- ETM Trace Packet 13 -AT91C_PIO_PD26 EQU (1:SHL:26) ;- Pin Controlled by PD26 -AT91C_PD26_TPK14 EQU (AT91C_PIO_PD26) ;- ETM Trace Packet 14 -AT91C_PIO_PD27 EQU (1:SHL:27) ;- Pin Controlled by PD27 -AT91C_PD27_TPK15 EQU (AT91C_PIO_PD27) ;- ETM Trace Packet 15 -AT91C_PIO_PD3 EQU (1:SHL:3) ;- Pin Controlled by PD3 -AT91C_PD3_ETX3 EQU (AT91C_PIO_PD3) ;- Ethernet MAC Transmit Data 3 -AT91C_PIO_PD4 EQU (1:SHL:4) ;- Pin Controlled by PD4 -AT91C_PD4_ETXEN EQU (AT91C_PIO_PD4) ;- Ethernet MAC Transmit Enable -AT91C_PIO_PD5 EQU (1:SHL:5) ;- Pin Controlled by PD5 -AT91C_PD5_ETXER EQU (AT91C_PIO_PD5) ;- Ethernet MAC Transmikt Coding Error -AT91C_PIO_PD6 EQU (1:SHL:6) ;- Pin Controlled by PD6 -AT91C_PD6_DTXD EQU (AT91C_PIO_PD6) ;- DBGU Debug Transmit Data -AT91C_PIO_PD7 EQU (1:SHL:7) ;- Pin Controlled by PD7 -AT91C_PD7_PCK0 EQU (AT91C_PIO_PD7) ;- PMC Programmable Clock Output 0 -AT91C_PD7_TSYNC EQU (AT91C_PIO_PD7) ;- ETM Synchronization signal -AT91C_PIO_PD8 EQU (1:SHL:8) ;- Pin Controlled by PD8 -AT91C_PD8_PCK1 EQU (AT91C_PIO_PD8) ;- PMC Programmable Clock Output 1 -AT91C_PD8_TCLK EQU (AT91C_PIO_PD8) ;- ETM Trace Clock signal -AT91C_PIO_PD9 EQU (1:SHL:9) ;- Pin Controlled by PD9 -AT91C_PD9_PCK2 EQU (AT91C_PIO_PD9) ;- PMC Programmable Clock 2 -AT91C_PD9_TPS0 EQU (AT91C_PIO_PD9) ;- ETM ARM9 pipeline status 0 - -;- ***************************************************************************** -;- PERIPHERAL ID DEFINITIONS FOR AT91RM9200 -;- ***************************************************************************** -AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) -AT91C_ID_SYS EQU ( 1) ;- System Peripheral -AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A -AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B -AT91C_ID_PIOC EQU ( 4) ;- Parallel IO Controller C -AT91C_ID_PIOD EQU ( 5) ;- Parallel IO Controller D -AT91C_ID_US0 EQU ( 6) ;- USART 0 -AT91C_ID_US1 EQU ( 7) ;- USART 1 -AT91C_ID_US2 EQU ( 8) ;- USART 2 -AT91C_ID_US3 EQU ( 9) ;- USART 3 -AT91C_ID_MCI EQU (10) ;- Multimedia Card Interface -AT91C_ID_UDP EQU (11) ;- USB Device Port -AT91C_ID_TWI EQU (12) ;- Two-Wire Interface -AT91C_ID_SPI EQU (13) ;- Serial Peripheral Interface -AT91C_ID_SSC0 EQU (14) ;- Serial Synchronous Controller 0 -AT91C_ID_SSC1 EQU (15) ;- Serial Synchronous Controller 1 -AT91C_ID_SSC2 EQU (16) ;- Serial Synchronous Controller 2 -AT91C_ID_TC0 EQU (17) ;- Timer Counter 0 -AT91C_ID_TC1 EQU (18) ;- Timer Counter 1 -AT91C_ID_TC2 EQU (19) ;- Timer Counter 2 -AT91C_ID_TC3 EQU (20) ;- Timer Counter 3 -AT91C_ID_TC4 EQU (21) ;- Timer Counter 4 -AT91C_ID_TC5 EQU (22) ;- Timer Counter 5 -AT91C_ID_UHP EQU (23) ;- USB Host port -AT91C_ID_EMAC EQU (24) ;- Ethernet MAC -AT91C_ID_IRQ0 EQU (25) ;- Advanced Interrupt Controller (IRQ0) -AT91C_ID_IRQ1 EQU (26) ;- Advanced Interrupt Controller (IRQ1) -AT91C_ID_IRQ2 EQU (27) ;- Advanced Interrupt Controller (IRQ2) -AT91C_ID_IRQ3 EQU (28) ;- Advanced Interrupt Controller (IRQ3) -AT91C_ID_IRQ4 EQU (29) ;- Advanced Interrupt Controller (IRQ4) -AT91C_ID_IRQ5 EQU (30) ;- Advanced Interrupt Controller (IRQ5) -AT91C_ID_IRQ6 EQU (31) ;- Advanced Interrupt Controller (IRQ6) - -;- ***************************************************************************** -;- BASE ADDRESS DEFINITIONS FOR AT91RM9200 -;- ***************************************************************************** -AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address -AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address -AT91C_BASE_RTC EQU (0xFFFFFE00) ;- (RTC) Base Address -AT91C_BASE_ST EQU (0xFFFFFD00) ;- (ST) Base Address -AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address -AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address -AT91C_BASE_PIOD EQU (0xFFFFFA00) ;- (PIOD) Base Address -AT91C_BASE_PIOC EQU (0xFFFFF800) ;- (PIOC) Base Address -AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address -AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address -AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address -AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address -AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address -AT91C_BASE_PDC_SPI EQU (0xFFFE0100) ;- (PDC_SPI) Base Address -AT91C_BASE_SPI EQU (0xFFFE0000) ;- (SPI) Base Address -AT91C_BASE_PDC_SSC2 EQU (0xFFFD8100) ;- (PDC_SSC2) Base Address -AT91C_BASE_SSC2 EQU (0xFFFD8000) ;- (SSC2) Base Address -AT91C_BASE_PDC_SSC1 EQU (0xFFFD4100) ;- (PDC_SSC1) Base Address -AT91C_BASE_SSC1 EQU (0xFFFD4000) ;- (SSC1) Base Address -AT91C_BASE_PDC_SSC0 EQU (0xFFFD0100) ;- (PDC_SSC0) Base Address -AT91C_BASE_SSC0 EQU (0xFFFD0000) ;- (SSC0) Base Address -AT91C_BASE_PDC_US3 EQU (0xFFFCC100) ;- (PDC_US3) Base Address -AT91C_BASE_US3 EQU (0xFFFCC000) ;- (US3) Base Address -AT91C_BASE_PDC_US2 EQU (0xFFFC8100) ;- (PDC_US2) Base Address -AT91C_BASE_US2 EQU (0xFFFC8000) ;- (US2) Base Address -AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address -AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address -AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address -AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address -AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address -AT91C_BASE_PDC_MCI EQU (0xFFFB4100) ;- (PDC_MCI) Base Address -AT91C_BASE_MCI EQU (0xFFFB4000) ;- (MCI) Base Address -AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address -AT91C_BASE_TC5 EQU (0xFFFA4080) ;- (TC5) Base Address -AT91C_BASE_TC4 EQU (0xFFFA4040) ;- (TC4) Base Address -AT91C_BASE_TC3 EQU (0xFFFA4000) ;- (TC3) Base Address -AT91C_BASE_TCB1 EQU (0xFFFA4080) ;- (TCB1) Base Address -AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address -AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address -AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address -AT91C_BASE_TCB0 EQU (0xFFFA0000) ;- (TCB0) Base Address -AT91C_BASE_UHP EQU (0x00300000) ;- (UHP) Base Address -AT91C_BASE_EMAC EQU (0xFFFBC000) ;- (EMAC) Base Address -AT91C_BASE_EBI EQU (0xFFFFFF60) ;- (EBI) Base Address -AT91C_BASE_SMC2 EQU (0xFFFFFF70) ;- (SMC2) Base Address -AT91C_BASE_SDRC EQU (0xFFFFFF90) ;- (SDRC) Base Address -AT91C_BASE_BFC EQU (0xFFFFFFC0) ;- (BFC) Base Address - -;- ***************************************************************************** -;- MEMORY MAPPING DEFINITIONS FOR AT91RM9200 -;- ***************************************************************************** -AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address -AT91C_ISRAM_SIZE EQU (0x00004000) ;- Internal SRAM size in byte (16 Kbyte) -AT91C_IROM EQU (0x00100000) ;- Internal ROM base address -AT91C_IROM_SIZE EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte) - - - END diff --git a/target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h b/target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h deleted file mode 100644 index dabab01c7..000000000 --- a/target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h +++ /dev/null @@ -1,2401 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// The software is delivered "AS IS" without warranty or condition of any -// kind, either express, implied or statutory. This includes without -// limitation any warranty or condition with respect to merchantability or -// fitness for any particular purpose, or against the infringements of -// intellectual property rights of others. -// ---------------------------------------------------------------------------- -// File Name : AT91RM9200.h -// Object : AT91RM9200 definitions -// Generated : AT91 SW Application Group 11/19/2003 (17:20:51) -// -// CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// -// CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// -// CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// -// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -// CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002// -// CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003// -// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// -// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// -// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002// -// CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002// -// CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002// -// CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002// -// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002// -// CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003// -// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003// -// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002// -// CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002// -// CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003// -// CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003// -// CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002// -// CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002// -// CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002// -// ---------------------------------------------------------------------------- - -// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_MC structure *** -#define MC_RCR ( 0) // MC Remap Control Register -#define MC_ASR ( 4) // MC Abort Status Register -#define MC_AASR ( 8) // MC Abort Address Status Register -#define MC_PUIA (16) // MC Protection Unit Area -#define MC_PUP (80) // MC Protection Unit Peripherals -#define MC_PUER (84) // MC Protection Unit Enable Register -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- -#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection -#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access -#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access -#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only -#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write -#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size -#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte -#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte -#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte -#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte -#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte -#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte -#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte -#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte -#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte -#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte -#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte -#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte -#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte -#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte -#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte -#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte -#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address -// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- -#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface -// ***************************************************************************** -// *** Register offset in AT91S_RTC structure *** -#define RTC_CR ( 0) // Control Register -#define RTC_MR ( 4) // Mode Register -#define RTC_TIMR ( 8) // Time Register -#define RTC_CALR (12) // Calendar Register -#define RTC_TIMALR (16) // Time Alarm Register -#define RTC_CALALR (20) // Calendar Alarm Register -#define RTC_SR (24) // Status Register -#define RTC_SCCR (28) // Status Clear Command Register -#define RTC_IER (32) // Interrupt Enable Register -#define RTC_IDR (36) // Interrupt Disable Register -#define RTC_IMR (40) // Interrupt Mask Register -#define RTC_VER (44) // Valid Entry Register -// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- -#define AT91C_RTC_UPDTIM (0x1 << 0) // (RTC) Update Request Time Register -#define AT91C_RTC_UPDCAL (0x1 << 1) // (RTC) Update Request Calendar Register -#define AT91C_RTC_TIMEVSEL (0x3 << 8) // (RTC) Time Event Selection -#define AT91C_RTC_TIMEVSEL_MINUTE (0x0 << 8) // (RTC) Minute change. -#define AT91C_RTC_TIMEVSEL_HOUR (0x1 << 8) // (RTC) Hour change. -#define AT91C_RTC_TIMEVSEL_DAY24 (0x2 << 8) // (RTC) Every day at midnight. -#define AT91C_RTC_TIMEVSEL_DAY12 (0x3 << 8) // (RTC) Every day at noon. -#define AT91C_RTC_CALEVSEL (0x3 << 16) // (RTC) Calendar Event Selection -#define AT91C_RTC_CALEVSEL_WEEK (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). -#define AT91C_RTC_CALEVSEL_MONTH (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). -#define AT91C_RTC_CALEVSEL_YEAR (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). -// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- -#define AT91C_RTC_HRMOD (0x1 << 0) // (RTC) 12-24 hour Mode -// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- -#define AT91C_RTC_SEC (0x7F << 0) // (RTC) Current Second -#define AT91C_RTC_MIN (0x7F << 8) // (RTC) Current Minute -#define AT91C_RTC_HOUR (0x1F << 16) // (RTC) Current Hour -#define AT91C_RTC_AMPM (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator -// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- -#define AT91C_RTC_CENT (0x3F << 0) // (RTC) Current Century -#define AT91C_RTC_YEAR (0xFF << 8) // (RTC) Current Year -#define AT91C_RTC_MONTH (0x1F << 16) // (RTC) Current Month -#define AT91C_RTC_DAY (0x7 << 21) // (RTC) Current Day -#define AT91C_RTC_DATE (0x3F << 24) // (RTC) Current Date -// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- -#define AT91C_RTC_SECEN (0x1 << 7) // (RTC) Second Alarm Enable -#define AT91C_RTC_MINEN (0x1 << 15) // (RTC) Minute Alarm -#define AT91C_RTC_HOUREN (0x1 << 23) // (RTC) Current Hour -// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- -#define AT91C_RTC_MONTHEN (0x1 << 23) // (RTC) Month Alarm Enable -#define AT91C_RTC_DATEEN (0x1 << 31) // (RTC) Date Alarm Enable -// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- -#define AT91C_RTC_ACKUPD (0x1 << 0) // (RTC) Acknowledge for Update -#define AT91C_RTC_ALARM (0x1 << 1) // (RTC) Alarm Flag -#define AT91C_RTC_SECEV (0x1 << 2) // (RTC) Second Event -#define AT91C_RTC_TIMEV (0x1 << 3) // (RTC) Time Event -#define AT91C_RTC_CALEV (0x1 << 4) // (RTC) Calendar event -// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- -// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- -// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- -// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- -// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- -#define AT91C_RTC_NVTIM (0x1 << 0) // (RTC) Non valid Time -#define AT91C_RTC_NVCAL (0x1 << 1) // (RTC) Non valid Calendar -#define AT91C_RTC_NVTIMALR (0x1 << 2) // (RTC) Non valid time Alarm -#define AT91C_RTC_NVCALALR (0x1 << 3) // (RTC) Nonvalid Calendar Alarm - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Timer Interface -// ***************************************************************************** -// *** Register offset in AT91S_ST structure *** -#define ST_CR ( 0) // Control Register -#define ST_PIMR ( 4) // Period Interval Mode Register -#define ST_WDMR ( 8) // Watchdog Mode Register -#define ST_RTMR (12) // Real-time Mode Register -#define ST_SR (16) // Status Register -#define ST_IER (20) // Interrupt Enable Register -#define ST_IDR (24) // Interrupt Disable Register -#define ST_IMR (28) // Interrupt Mask Register -#define ST_RTAR (32) // Real-time Alarm Register -#define ST_CRTR (36) // Current Real-time Register -// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- -#define AT91C_ST_WDRST (0x1 << 0) // (ST) Watchdog Timer Restart -// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- -#define AT91C_ST_PIV (0xFFFF << 0) // (ST) Watchdog Timer Restart -// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- -#define AT91C_ST_WDV (0xFFFF << 0) // (ST) Watchdog Timer Restart -#define AT91C_ST_RSTEN (0x1 << 16) // (ST) Reset Enable -#define AT91C_ST_EXTEN (0x1 << 17) // (ST) External Signal Assertion Enable -// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- -#define AT91C_ST_RTPRES (0xFFFF << 0) // (ST) Real-time Timer Prescaler Value -// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- -#define AT91C_ST_PITS (0x1 << 0) // (ST) Period Interval Timer Interrupt -#define AT91C_ST_WDOVF (0x1 << 1) // (ST) Watchdog Overflow -#define AT91C_ST_RTTINC (0x1 << 2) // (ST) Real-time Timer Increment -#define AT91C_ST_ALMS (0x1 << 3) // (ST) Alarm Status -// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- -// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- -// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- -// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- -#define AT91C_ST_ALMV (0xFFFFF << 0) // (ST) Alarm Value Value -// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- -#define AT91C_ST_CRTV (0xFFFFF << 0) // (ST) Current Real-time Value - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -// *** Register offset in AT91S_PMC structure *** -#define PMC_SCER ( 0) // System Clock Enable Register -#define PMC_SCDR ( 4) // System Clock Disable Register -#define PMC_SCSR ( 8) // System Clock Status Register -#define PMC_PCER (16) // Peripheral Clock Enable Register -#define PMC_PCDR (20) // Peripheral Clock Disable Register -#define PMC_PCSR (24) // Peripheral Clock Status Register -#define PMC_MCKR (48) // Master Clock Register -#define PMC_PCKR (64) // Programmable Clock Register -#define PMC_IER (96) // Interrupt Enable Register -#define PMC_IDR (100) // Interrupt Disable Register -#define PMC_SR (104) // Status Register -#define PMC_IMR (108) // Interrupt Mask Register -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 1) // (PMC) USB Device Port Clock -#define AT91C_PMC_MCKUDP (0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend -#define AT91C_PMC_UHP (0x1 << 4) // (PMC) USB Host Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK4 (0x1 << 12) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK5 (0x1 << 13) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK6 (0x1 << 14) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK7 (0x1 << 15) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected -#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division -#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same -#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock -#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is three times faster than the master clock -#define AT91C_PMC_MDIV_4 (0x3 << 8) // (PMC) The processor clock is four times faster than the master clock -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask -#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK4RDY (0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK5RDY (0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK6RDY (0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK7RDY (0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -// *** Register offset in AT91S_CKGR structure *** -#define CKGR_MOR ( 0) // Main Oscillator Register -#define CKGR_MCFR ( 4) // Main Clock Frequency Register -#define CKGR_PLLAR ( 8) // PLL A Register -#define CKGR_PLLBR (12) // PLL B Register -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCTEST (0x1 << 1) // (CKGR) Oscillator Test -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- -#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter -#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range -#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet -#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier -#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) PLL A Source -// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter -#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range -#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet -#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier -#define AT91C_CKGR_USB_96M (0x1 << 28) // (CKGR) Divider for USB Ports -#define AT91C_CKGR_USB_PLL (0x1 << 29) // (CKGR) PLL Use - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -// *** Register offset in AT91S_PIO structure *** -#define PIO_PER ( 0) // PIO Enable Register -#define PIO_PDR ( 4) // PIO Disable Register -#define PIO_PSR ( 8) // PIO Status Register -#define PIO_OER (16) // Output Enable Register -#define PIO_ODR (20) // Output Disable Registerr -#define PIO_OSR (24) // Output Status Register -#define PIO_IFER (32) // Input Filter Enable Register -#define PIO_IFDR (36) // Input Filter Disable Register -#define PIO_IFSR (40) // Input Filter Status Register -#define PIO_SODR (48) // Set Output Data Register -#define PIO_CODR (52) // Clear Output Data Register -#define PIO_ODSR (56) // Output Data Status Register -#define PIO_PDSR (60) // Pin Data Status Register -#define PIO_IER (64) // Interrupt Enable Register -#define PIO_IDR (68) // Interrupt Disable Register -#define PIO_IMR (72) // Interrupt Mask Register -#define PIO_ISR (76) // Interrupt Status Register -#define PIO_MDER (80) // Multi-driver Enable Register -#define PIO_MDDR (84) // Multi-driver Disable Register -#define PIO_MDSR (88) // Multi-driver Status Register -#define PIO_PPUDR (96) // Pull-up Disable Register -#define PIO_PPUER (100) // Pull-up Enable Register -#define PIO_PPUSR (104) // Pad Pull-up Status Register -#define PIO_ASR (112) // Select A Register -#define PIO_BSR (116) // Select B Register -#define PIO_ABSR (120) // AB Select Status Register -#define PIO_OWER (160) // Output Write Enable Register -#define PIO_OWDR (164) // Output Write Disable Register -#define PIO_OWSR (168) // Output Write Status Register - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -// *** Register offset in AT91S_DBGU structure *** -#define DBGU_CR ( 0) // Control Register -#define DBGU_MR ( 4) // Mode Register -#define DBGU_IER ( 8) // Interrupt Enable Register -#define DBGU_IDR (12) // Interrupt Disable Register -#define DBGU_IMR (16) // Interrupt Mask Register -#define DBGU_CSR (20) // Channel Status Register -#define DBGU_RHR (24) // Receiver Holding Register -#define DBGU_THR (28) // Transmitter Holding Register -#define DBGU_BRGR (32) // Baud Rate Generator Register -#define DBGU_C1R (64) // Chip ID1 Register -#define DBGU_C2R (68) // Chip ID2 Register -#define DBGU_FNTR (72) // Force NTRST Register -#define DBGU_RPR (256) // Receive Pointer Register -#define DBGU_RCR (260) // Receive Counter Register -#define DBGU_TPR (264) // Transmit Pointer Register -#define DBGU_TCR (268) // Transmit Counter Register -#define DBGU_RNPR (272) // Receive Next Pointer Register -#define DBGU_RNCR (276) // Receive Next Counter Register -#define DBGU_TNPR (280) // Transmit Next Pointer Register -#define DBGU_TNCR (284) // Transmit Next Counter Register -#define DBGU_PTCR (288) // PDC Transfer Control Register -#define DBGU_PTSR (292) // PDC Transfer Status Register -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral Data Controller -// ***************************************************************************** -// *** Register offset in AT91S_PDC structure *** -#define PDC_RPR ( 0) // Receive Pointer Register -#define PDC_RCR ( 4) // Receive Counter Register -#define PDC_TPR ( 8) // Transmit Pointer Register -#define PDC_TCR (12) // Transmit Counter Register -#define PDC_RNPR (16) // Receive Next Pointer Register -#define PDC_RNCR (20) // Receive Next Counter Register -#define PDC_TNPR (24) // Transmit Next Pointer Register -#define PDC_TNCR (28) // Transmit Next Counter Register -#define PDC_PTCR (32) // PDC Transfer Control Register -#define PDC_PTSR (36) // PDC Transfer Status Register -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -// *** Register offset in AT91S_AIC structure *** -#define AIC_SMR ( 0) // Source Mode Register -#define AIC_SVR (128) // Source Vector Register -#define AIC_IVR (256) // IRQ Vector Register -#define AIC_FVR (260) // FIQ Vector Register -#define AIC_ISR (264) // Interrupt Status Register -#define AIC_IPR (268) // Interrupt Pending Register -#define AIC_IMR (272) // Interrupt Mask Register -#define AIC_CISR (276) // Core Interrupt Status Register -#define AIC_IECR (288) // Interrupt Enable Command Register -#define AIC_IDCR (292) // Interrupt Disable Command Register -#define AIC_ICCR (296) // Interrupt Clear Command Register -#define AIC_ISCR (300) // Interrupt Set Command Register -#define AIC_EOICR (304) // End of Interrupt Command Register -#define AIC_SPU (308) // Spurious Vector Register -#define AIC_DCR (312) // Debug Control Register (Protect) -#define AIC_FFER (320) // Fast Forcing Enable Register -#define AIC_FFDR (324) // Fast Forcing Disable Register -#define AIC_FFSR (328) // Fast Forcing Status Register -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive -#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -// *** Register offset in AT91S_SPI structure *** -#define SPI_CR ( 0) // Control Register -#define SPI_MR ( 4) // Mode Register -#define SPI_RDR ( 8) // Receive Data Register -#define SPI_TDR (12) // Transmit Data Register -#define SPI_SR (16) // Status Register -#define SPI_IER (20) // Interrupt Enable Register -#define SPI_IDR (24) // Interrupt Disable Register -#define SPI_IMR (28) // Interrupt Mask Register -#define SPI_CSR (48) // Chip Select Register -#define SPI_RPR (256) // Receive Pointer Register -#define SPI_RCR (260) // Receive Counter Register -#define SPI_TPR (264) // Transmit Pointer Register -#define SPI_TCR (268) // Transmit Counter Register -#define SPI_RNPR (272) // Receive Next Pointer Register -#define SPI_RNCR (276) // Receive Next Counter Register -#define SPI_TNPR (280) // Transmit Next Pointer Register -#define SPI_TNCR (284) // Transmit Next Counter Register -#define SPI_PTCR (288) // PDC Transfer Control Register -#define SPI_PTSR (292) // PDC Transfer Status Register -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_DIV32 (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_SPENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_SPENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SSC structure *** -#define SSC_CR ( 0) // Control Register -#define SSC_CMR ( 4) // Clock Mode Register -#define SSC_RCMR (16) // Receive Clock ModeRegister -#define SSC_RFMR (20) // Receive Frame Mode Register -#define SSC_TCMR (24) // Transmit Clock Mode Register -#define SSC_TFMR (28) // Transmit Frame Mode Register -#define SSC_RHR (32) // Receive Holding Register -#define SSC_THR (36) // Transmit Holding Register -#define SSC_RSHR (48) // Receive Sync Holding Register -#define SSC_TSHR (52) // Transmit Sync Holding Register -#define SSC_RC0R (56) // Receive Compare 0 Register -#define SSC_RC1R (60) // Receive Compare 1 Register -#define SSC_SR (64) // Status Register -#define SSC_IER (68) // Interrupt Enable Register -#define SSC_IDR (72) // Interrupt Disable Register -#define SSC_IMR (76) // Interrupt Mask Register -#define SSC_RPR (256) // Receive Pointer Register -#define SSC_RCR (260) // Receive Counter Register -#define SSC_TPR (264) // Transmit Pointer Register -#define SSC_TCR (268) // Transmit Counter Register -#define SSC_RNPR (272) // Receive Next Pointer Register -#define SSC_RNCR (276) // Receive Next Counter Register -#define SSC_TNPR (280) // Transmit Next Pointer Register -#define SSC_TNCR (284) // Transmit Next Counter Register -#define SSC_PTCR (288) // PDC Transfer Control Register -#define SSC_PTSR (292) // PDC Transfer Status Register -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -// *** Register offset in AT91S_USART structure *** -#define US_CR ( 0) // Control Register -#define US_MR ( 4) // Mode Register -#define US_IER ( 8) // Interrupt Enable Register -#define US_IDR (12) // Interrupt Disable Register -#define US_IMR (16) // Interrupt Mask Register -#define US_CSR (20) // Channel Status Register -#define US_RHR (24) // Receiver Holding Register -#define US_THR (28) // Transmitter Holding Register -#define US_BRGR (32) // Baud Rate Generator Register -#define US_RTOR (36) // Receiver Time-out Register -#define US_TTGR (40) // Transmitter Time-guard Register -#define US_FIDI (64) // FI_DI_Ratio Register -#define US_NER (68) // Nb Errors Register -#define US_XXR (72) // XON_XOFF Register -#define US_IF (76) // IRDA_FILTER Register -#define US_RPR (256) // Receive Pointer Register -#define US_RCR (260) // Receive Counter Register -#define US_TPR (264) // Transmit Pointer Register -#define US_TCR (268) // Transmit Counter Register -#define US_RNPR (272) // Receive Next Pointer Register -#define US_RNCR (276) // Receive Next Counter Register -#define US_TNPR (280) // Transmit Next Pointer Register -#define US_TNCR (284) // Transmit Next Counter Register -#define US_PTCR (288) // PDC Transfer Control Register -#define US_PTSR (292) // PDC Transfer Status Register -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -// *** Register offset in AT91S_TWI structure *** -#define TWI_CR ( 0) // Control Register -#define TWI_MMR ( 4) // Master Mode Register -#define TWI_SMR ( 8) // Slave Mode Register -#define TWI_IADR (12) // Internal Address Register -#define TWI_CWGR (16) // Clock Waveform Generator Register -#define TWI_SR (32) // Status Register -#define TWI_IER (36) // Interrupt Enable Register -#define TWI_IDR (40) // Interrupt Disable Register -#define TWI_IMR (44) // Interrupt Mask Register -#define TWI_RHR (48) // Receive Holding Register -#define TWI_THR (52) // Transmit Holding Register -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled -#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- -#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read -#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access -#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Multimedia Card Interface -// ***************************************************************************** -// *** Register offset in AT91S_MCI structure *** -#define MCI_CR ( 0) // MCI Control Register -#define MCI_MR ( 4) // MCI Mode Register -#define MCI_DTOR ( 8) // MCI Data Timeout Register -#define MCI_SDCR (12) // MCI SD Card Register -#define MCI_ARGR (16) // MCI Argument Register -#define MCI_CMDR (20) // MCI Command Register -#define MCI_RSPR (32) // MCI Response Register -#define MCI_RDR (48) // MCI Receive Data Register -#define MCI_TDR (52) // MCI Transmit Data Register -#define MCI_SR (64) // MCI Status Register -#define MCI_IER (68) // MCI Interrupt Enable Register -#define MCI_IDR (72) // MCI Interrupt Disable Register -#define MCI_IMR (76) // MCI Interrupt Mask Register -#define MCI_RPR (256) // Receive Pointer Register -#define MCI_RCR (260) // Receive Counter Register -#define MCI_TPR (264) // Transmit Pointer Register -#define MCI_TCR (268) // Transmit Counter Register -#define MCI_RNPR (272) // Receive Next Pointer Register -#define MCI_RNCR (276) // Receive Next Counter Register -#define MCI_TNPR (280) // Transmit Next Pointer Register -#define MCI_TNCR (284) // Transmit Next Counter Register -#define MCI_PTCR (288) // PDC Transfer Control Register -#define MCI_PTSR (292) // PDC Transfer Status Register -// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- -#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable -#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable -#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable -#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable -// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- -#define AT91C_MCI_CLKDIV (0x1 << 0) // (MCI) Clock Divider -#define AT91C_MCI_PWSDIV (0x1 << 8) // (MCI) Power Saving Divider -#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value -#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode -#define AT91C_MCI_BLKLEN (0x1 << 18) // (MCI) Data Block Length -// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- -#define AT91C_MCI_DTOCYC (0x1 << 0) // (MCI) Data Timeout Cycle Number -#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier -#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1 -#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16 -#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128 -#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256 -#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024 -#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096 -#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536 -#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576 -// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- -#define AT91C_MCI_SCDSEL (0x1 << 0) // (MCI) SD Card Selector -#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SD Card Bus Width -// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- -#define AT91C_MCI_CMDNB (0x1F << 0) // (MCI) Command Number -#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type -#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response -#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response -#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response -#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD -#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD -#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD -#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD -#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command -#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response -#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command -#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond -#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD -#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer -#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer -#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer -#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction -#define AT91C_MCI_TRTYP (0x3 << 19) // (MCI) Transfer Type -#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) Block Transfer type -#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) Multiple Block transfer type -#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) Stream transfer type -// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- -#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag -#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag -#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag -#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag -#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag -#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag -#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag -#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag -#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag -#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag -#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag -#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag -#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag -#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag -#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag -#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag -#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag -#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag -#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag -// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- -// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- -// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -// *** Register offset in AT91S_UDP structure *** -#define UDP_NUM ( 0) // Frame Number Register -#define UDP_GLBSTATE ( 4) // Global State Register -#define UDP_FADDR ( 8) // Function Address Register -#define UDP_IER (16) // Interrupt Enable Register -#define UDP_IDR (20) // Interrupt Disable Register -#define UDP_IMR (24) // Interrupt Mask Register -#define UDP_ISR (28) // Interrupt Status Register -#define UDP_ICR (32) // Interrupt Clear Register -#define UDP_RSTEP (40) // Reset Endpoint Register -#define UDP_CSR (48) // Endpoint Control and Status Register -#define UDP_FDR (80) // Endpoint FIFO Data Register -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt -#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 -#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_TC structure *** -#define TC_CCR ( 0) // Channel Control Register -#define TC_CMR ( 4) // Channel Mode Register -#define TC_CV (16) // Counter Value -#define TC_RA (20) // Register A -#define TC_RB (24) // Register B -#define TC_RC (28) // Register C -#define TC_SR (32) // Status Register -#define TC_IER (36) // Interrupt Enable Register -#define TC_IDR (40) // Interrupt Disable Register -#define TC_IMR (44) // Interrupt Mask Register -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -// *** Register offset in AT91S_TCB structure *** -#define TCB_TC0 ( 0) // TC Channel 0 -#define TCB_TC1 (64) // TC Channel 1 -#define TCB_TC2 (128) // TC Channel 2 -#define TCB_BCR (192) // TC Block Control Register -#define TCB_BMR (196) // TC Block Mode Register -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Host Interface -// ***************************************************************************** -// *** Register offset in AT91S_UHP structure *** -#define UHP_HcRevision ( 0) // Revision -#define UHP_HcControl ( 4) // Operating modes for the Host Controller -#define UHP_HcCommandStatus ( 8) // Command & status Register -#define UHP_HcInterruptStatus (12) // Interrupt Status Register -#define UHP_HcInterruptEnable (16) // Interrupt Enable Register -#define UHP_HcInterruptDisable (20) // Interrupt Disable Register -#define UHP_HcHCCA (24) // Pointer to the Host Controller Communication Area -#define UHP_HcPeriodCurrentED (28) // Current Isochronous or Interrupt Endpoint Descriptor -#define UHP_HcControlHeadED (32) // First Endpoint Descriptor of the Control list -#define UHP_HcControlCurrentED (36) // Endpoint Control and Status Register -#define UHP_HcBulkHeadED (40) // First endpoint register of the Bulk list -#define UHP_HcBulkCurrentED (44) // Current endpoint of the Bulk list -#define UHP_HcBulkDoneHead (48) // Last completed transfer descriptor -#define UHP_HcFmInterval (52) // Bit time between 2 consecutive SOFs -#define UHP_HcFmRemaining (56) // Bit time remaining in the current Frame -#define UHP_HcFmNumber (60) // Frame number -#define UHP_HcPeriodicStart (64) // Periodic Start -#define UHP_HcLSThreshold (68) // LS Threshold -#define UHP_HcRhDescriptorA (72) // Root Hub characteristics A -#define UHP_HcRhDescriptorB (76) // Root Hub characteristics B -#define UHP_HcRhStatus (80) // Root Hub Status register -#define UHP_HcRhPortStatus (84) // Root Hub Port Status Register - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC -// ***************************************************************************** -// *** Register offset in AT91S_EMAC structure *** -#define EMAC_CTL ( 0) // Network Control Register -#define EMAC_CFG ( 4) // Network Configuration Register -#define EMAC_SR ( 8) // Network Status Register -#define EMAC_TAR (12) // Transmit Address Register -#define EMAC_TCR (16) // Transmit Control Register -#define EMAC_TSR (20) // Transmit Status Register -#define EMAC_RBQP (24) // Receive Buffer Queue Pointer -#define EMAC_RSR (32) // Receive Status Register -#define EMAC_ISR (36) // Interrupt Status Register -#define EMAC_IER (40) // Interrupt Enable Register -#define EMAC_IDR (44) // Interrupt Disable Register -#define EMAC_IMR (48) // Interrupt Mask Register -#define EMAC_MAN (52) // PHY Maintenance Register -#define EMAC_FRA (64) // Frames Transmitted OK Register -#define EMAC_SCOL (68) // Single Collision Frame Register -#define EMAC_MCOL (72) // Multiple Collision Frame Register -#define EMAC_OK (76) // Frames Received OK Register -#define EMAC_SEQE (80) // Frame Check Sequence Error Register -#define EMAC_ALE (84) // Alignment Error Register -#define EMAC_DTE (88) // Deferred Transmission Frame Register -#define EMAC_LCOL (92) // Late Collision Register -#define EMAC_ECOL (96) // Excessive Collision Register -#define EMAC_CSE (100) // Carrier Sense Error Register -#define EMAC_TUE (104) // Transmit Underrun Error Register -#define EMAC_CDE (108) // Code Error Register -#define EMAC_ELR (112) // Excessive Length Error Register -#define EMAC_RJB (116) // Receive Jabber Register -#define EMAC_USF (120) // Undersize Frame Register -#define EMAC_SQEE (124) // SQE Test Error Register -#define EMAC_DRFC (128) // Discarded RX Frame Register -#define EMAC_HSH (144) // Hash Address High[63:32] -#define EMAC_HSL (148) // Hash Address Low[31:0] -#define EMAC_SA1L (152) // Specific Address 1 Low, First 4 bytes -#define EMAC_SA1H (156) // Specific Address 1 High, Last 2 bytes -#define EMAC_SA2L (160) // Specific Address 2 Low, First 4 bytes -#define EMAC_SA2H (164) // Specific Address 2 High, Last 2 bytes -#define EMAC_SA3L (168) // Specific Address 3 Low, First 4 bytes -#define EMAC_SA3H (172) // Specific Address 3 High, Last 2 bytes -#define EMAC_SA4L (176) // Specific Address 4 Low, First 4 bytes -#define EMAC_SA4H (180) // Specific Address 4 High, Last 2 bytesr -// -------- EMAC_CTL : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LBL (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CSR (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_ISR (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WES (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_BR (0x1 << 2) // (EMAC) Bit rate. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_RMII (0x1 << 13) // (EMAC) -// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- -#define AT91C_EMAC_LEN (0x7FF << 0) // (EMAC) -#define AT91C_EMAC_NCRC (0x1 << 15) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- -#define AT91C_EMAC_OVR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLE (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXIDLE (0x1 << 3) // (EMAC) -#define AT91C_EMAC_BNQ (0x1 << 4) // (EMAC) -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_DONE (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOM (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RBNA (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TOVR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUND (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RTRY (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TBRE (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOM (0x1 << 7) // (EMAC) -#define AT91C_EMAC_TIDLE (0x1 << 8) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_HIGH (0x1 << 30) // (EMAC) -#define AT91C_EMAC_LOW (0x1 << 31) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR External Bus Interface -// ***************************************************************************** -// *** Register offset in AT91S_EBI structure *** -#define EBI_CSA ( 0) // Chip Select Assignment Register -#define EBI_CFGR ( 4) // Configuration Register -// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- -#define AT91C_EBI_CS0A (0x1 << 0) // (EBI) Chip Select 0 Assignment -#define AT91C_EBI_CS0A_SMC (0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller. -#define AT91C_EBI_CS0A_BFC (0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. -#define AT91C_EBI_CS1A (0x1 << 1) // (EBI) Chip Select 1 Assignment -#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. -#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. -#define AT91C_EBI_CS3A (0x1 << 3) // (EBI) Chip Select 3 Assignment -#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. -#define AT91C_EBI_CS3A_SMC_SmartMedia (0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. -#define AT91C_EBI_CS4A (0x1 << 4) // (EBI) Chip Select 4 Assignment -#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. -#define AT91C_EBI_CS4A_SMC_CompactFlash (0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. -// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- -#define AT91C_EBI_DBPUC (0x1 << 0) // (EBI) Data Bus Pull-Up Configuration -#define AT91C_EBI_EBSEN (0x1 << 1) // (EBI) Bus Sharing Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface -// ***************************************************************************** -// *** Register offset in AT91S_SMC2 structure *** -#define SMC2_CSR ( 0) // SMC2 Chip Select Register -// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- -#define AT91C_SMC2_NWS (0x7F << 0) // (SMC2) Number of Wait States -#define AT91C_SMC2_WSEN (0x1 << 7) // (SMC2) Wait State Enable -#define AT91C_SMC2_TDF (0xF << 8) // (SMC2) Data Float Time -#define AT91C_SMC2_BAT (0x1 << 12) // (SMC2) Byte Access Type -#define AT91C_SMC2_DBW (0x1 << 13) // (SMC2) Data Bus Width -#define AT91C_SMC2_DBW_16 (0x1 << 13) // (SMC2) 16-bit. -#define AT91C_SMC2_DBW_8 (0x2 << 13) // (SMC2) 8-bit. -#define AT91C_SMC2_DRP (0x1 << 15) // (SMC2) Data Read Protocol -#define AT91C_SMC2_ACSS (0x3 << 16) // (SMC2) Address to Chip Select Setup -#define AT91C_SMC2_ACSS_STANDARD (0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. -#define AT91C_SMC2_ACSS_1_CYCLE (0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access. -#define AT91C_SMC2_ACSS_2_CYCLES (0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access. -#define AT91C_SMC2_ACSS_3_CYCLES (0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access. -#define AT91C_SMC2_RWSETUP (0x7 << 24) // (SMC2) Read and Write Signal Setup Time -#define AT91C_SMC2_RWHOLD (0x7 << 29) // (SMC2) Read and Write Signal Hold Time - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR SDRAM Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SDRC structure *** -#define SDRC_MR ( 0) // SDRAM Controller Mode Register -#define SDRC_TR ( 4) // SDRAM Controller Refresh Timer Register -#define SDRC_CR ( 8) // SDRAM Controller Configuration Register -#define SDRC_SRR (12) // SDRAM Controller Self Refresh Register -#define SDRC_LPR (16) // SDRAM Controller Low Power Register -#define SDRC_IER (20) // SDRAM Controller Interrupt Enable Register -#define SDRC_IDR (24) // SDRAM Controller Interrupt Disable Register -#define SDRC_IMR (28) // SDRAM Controller Interrupt Mask Register -#define SDRC_ISR (32) // SDRAM Controller Interrupt Mask Register -// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- -#define AT91C_SDRC_MODE (0xF << 0) // (SDRC) Mode -#define AT91C_SDRC_MODE_NORMAL_CMD (0x0) // (SDRC) Normal Mode -#define AT91C_SDRC_MODE_NOP_CMD (0x1) // (SDRC) NOP Command -#define AT91C_SDRC_MODE_PRCGALL_CMD (0x2) // (SDRC) All Banks Precharge Command -#define AT91C_SDRC_MODE_LMR_CMD (0x3) // (SDRC) Load Mode Register Command -#define AT91C_SDRC_MODE_RFSH_CMD (0x4) // (SDRC) Refresh Command -#define AT91C_SDRC_DBW (0x1 << 4) // (SDRC) Data Bus Width -#define AT91C_SDRC_DBW_32_BITS (0x0 << 4) // (SDRC) 32 Bits datas bus -#define AT91C_SDRC_DBW_16_BITS (0x1 << 4) // (SDRC) 16 Bits datas bus -// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- -#define AT91C_SDRC_COUNT (0xFFF << 0) // (SDRC) Refresh Counter -// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- -#define AT91C_SDRC_NC (0x3 << 0) // (SDRC) Number of Column Bits -#define AT91C_SDRC_NC_8 (0x0) // (SDRC) 8 Bits -#define AT91C_SDRC_NC_9 (0x1) // (SDRC) 9 Bits -#define AT91C_SDRC_NC_10 (0x2) // (SDRC) 10 Bits -#define AT91C_SDRC_NC_11 (0x3) // (SDRC) 11 Bits -#define AT91C_SDRC_NR (0x3 << 2) // (SDRC) Number of Row Bits -#define AT91C_SDRC_NR_11 (0x0 << 2) // (SDRC) 11 Bits -#define AT91C_SDRC_NR_12 (0x1 << 2) // (SDRC) 12 Bits -#define AT91C_SDRC_NR_13 (0x2 << 2) // (SDRC) 13 Bits -#define AT91C_SDRC_NB (0x1 << 4) // (SDRC) Number of Banks -#define AT91C_SDRC_NB_2_BANKS (0x0 << 4) // (SDRC) 2 banks -#define AT91C_SDRC_NB_4_BANKS (0x1 << 4) // (SDRC) 4 banks -#define AT91C_SDRC_CAS (0x3 << 5) // (SDRC) CAS Latency -#define AT91C_SDRC_CAS_2 (0x2 << 5) // (SDRC) 2 cycles -#define AT91C_SDRC_TWR (0xF << 7) // (SDRC) Number of Write Recovery Time Cycles -#define AT91C_SDRC_TRC (0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles -#define AT91C_SDRC_TRP (0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles -#define AT91C_SDRC_TRCD (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles -#define AT91C_SDRC_TRAS (0xF << 23) // (SDRC) Number of RAS Active Time Cycles -#define AT91C_SDRC_TXSR (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles -// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- -#define AT91C_SDRC_SRCB (0x1 << 0) // (SDRC) Self-refresh Command Bit -// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- -#define AT91C_SDRC_LPCB (0x1 << 0) // (SDRC) Low-power Command Bit -// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- -#define AT91C_SDRC_RES (0x1 << 0) // (SDRC) Refresh Error Status -// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- -// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- -// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Burst Flash Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_BFC structure *** -#define BFC_MR ( 0) // BFC Mode Register -// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- -#define AT91C_BFC_BFCOM (0x3 << 0) // (BFC) Burst Flash Controller Operating Mode -#define AT91C_BFC_BFCOM_DISABLED (0x0) // (BFC) NPCS0 is driven by the SMC or remains high. -#define AT91C_BFC_BFCOM_ASYNC (0x1) // (BFC) Asynchronous -#define AT91C_BFC_BFCOM_BURST_READ (0x2) // (BFC) Burst Read -#define AT91C_BFC_BFCC (0x3 << 2) // (BFC) Burst Flash Controller Operating Mode -#define AT91C_BFC_BFCC_MCK (0x1 << 2) // (BFC) Master Clock. -#define AT91C_BFC_BFCC_MCK_DIV_2 (0x2 << 2) // (BFC) Master Clock divided by 2. -#define AT91C_BFC_BFCC_MCK_DIV_4 (0x3 << 2) // (BFC) Master Clock divided by 4. -#define AT91C_BFC_AVL (0xF << 4) // (BFC) Address Valid Latency -#define AT91C_BFC_PAGES (0x7 << 8) // (BFC) Page Size -#define AT91C_BFC_PAGES_NO_PAGE (0x0 << 8) // (BFC) No page handling. -#define AT91C_BFC_PAGES_16 (0x1 << 8) // (BFC) 16 bytes page size. -#define AT91C_BFC_PAGES_32 (0x2 << 8) // (BFC) 32 bytes page size. -#define AT91C_BFC_PAGES_64 (0x3 << 8) // (BFC) 64 bytes page size. -#define AT91C_BFC_PAGES_128 (0x4 << 8) // (BFC) 128 bytes page size. -#define AT91C_BFC_PAGES_256 (0x5 << 8) // (BFC) 256 bytes page size. -#define AT91C_BFC_PAGES_512 (0x6 << 8) // (BFC) 512 bytes page size. -#define AT91C_BFC_PAGES_1024 (0x7 << 8) // (BFC) 1024 bytes page size. -#define AT91C_BFC_OEL (0x3 << 12) // (BFC) Output Enable Latency -#define AT91C_BFC_BAAEN (0x1 << 16) // (BFC) Burst Address Advance Enable -#define AT91C_BFC_BFOEH (0x1 << 17) // (BFC) Burst Flash Output Enable Handling -#define AT91C_BFC_MUXEN (0x1 << 18) // (BFC) Multiplexed Bus Enable -#define AT91C_BFC_RDYEN (0x1 << 19) // (BFC) Ready Enable Mode - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91RM9200 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_PUER (0xFFFFFF54) // (MC) MC Protection Unit Enable Register -#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_PUP (0xFFFFFF50) // (MC) MC Protection Unit Peripherals -#define AT91C_MC_PUIA (0xFFFFFF10) // (MC) MC Protection Unit Area -#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for RTC peripheral ========== -#define AT91C_RTC_IMR (0xFFFFFE28) // (RTC) Interrupt Mask Register -#define AT91C_RTC_IER (0xFFFFFE20) // (RTC) Interrupt Enable Register -#define AT91C_RTC_SR (0xFFFFFE18) // (RTC) Status Register -#define AT91C_RTC_TIMALR (0xFFFFFE10) // (RTC) Time Alarm Register -#define AT91C_RTC_TIMR (0xFFFFFE08) // (RTC) Time Register -#define AT91C_RTC_CR (0xFFFFFE00) // (RTC) Control Register -#define AT91C_RTC_VER (0xFFFFFE2C) // (RTC) Valid Entry Register -#define AT91C_RTC_IDR (0xFFFFFE24) // (RTC) Interrupt Disable Register -#define AT91C_RTC_SCCR (0xFFFFFE1C) // (RTC) Status Clear Command Register -#define AT91C_RTC_CALALR (0xFFFFFE14) // (RTC) Calendar Alarm Register -#define AT91C_RTC_CALR (0xFFFFFE0C) // (RTC) Calendar Register -#define AT91C_RTC_MR (0xFFFFFE04) // (RTC) Mode Register -// ========== Register definition for ST peripheral ========== -#define AT91C_ST_CRTR (0xFFFFFD24) // (ST) Current Real-time Register -#define AT91C_ST_IMR (0xFFFFFD1C) // (ST) Interrupt Mask Register -#define AT91C_ST_IER (0xFFFFFD14) // (ST) Interrupt Enable Register -#define AT91C_ST_RTMR (0xFFFFFD0C) // (ST) Real-time Mode Register -#define AT91C_ST_PIMR (0xFFFFFD04) // (ST) Period Interval Mode Register -#define AT91C_ST_RTAR (0xFFFFFD20) // (ST) Real-time Alarm Register -#define AT91C_ST_IDR (0xFFFFFD18) // (ST) Interrupt Disable Register -#define AT91C_ST_SR (0xFFFFFD10) // (ST) Status Register -#define AT91C_ST_WDMR (0xFFFFFD08) // (ST) Watchdog Mode Register -#define AT91C_ST_CR (0xFFFFFD00) // (ST) Control Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLBR (0xFFFFFC2C) // (CKGR) PLL B Register -#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_PLLAR (0xFFFFFC28) // (CKGR) PLL A Register -#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PIOD peripheral ========== -#define AT91C_PIOD_PDSR (0xFFFFFA3C) // (PIOD) Pin Data Status Register -#define AT91C_PIOD_CODR (0xFFFFFA34) // (PIOD) Clear Output Data Register -#define AT91C_PIOD_OWER (0xFFFFFAA0) // (PIOD) Output Write Enable Register -#define AT91C_PIOD_MDER (0xFFFFFA50) // (PIOD) Multi-driver Enable Register -#define AT91C_PIOD_IMR (0xFFFFFA48) // (PIOD) Interrupt Mask Register -#define AT91C_PIOD_IER (0xFFFFFA40) // (PIOD) Interrupt Enable Register -#define AT91C_PIOD_ODSR (0xFFFFFA38) // (PIOD) Output Data Status Register -#define AT91C_PIOD_SODR (0xFFFFFA30) // (PIOD) Set Output Data Register -#define AT91C_PIOD_PER (0xFFFFFA00) // (PIOD) PIO Enable Register -#define AT91C_PIOD_OWDR (0xFFFFFAA4) // (PIOD) Output Write Disable Register -#define AT91C_PIOD_PPUER (0xFFFFFA64) // (PIOD) Pull-up Enable Register -#define AT91C_PIOD_MDDR (0xFFFFFA54) // (PIOD) Multi-driver Disable Register -#define AT91C_PIOD_ISR (0xFFFFFA4C) // (PIOD) Interrupt Status Register -#define AT91C_PIOD_IDR (0xFFFFFA44) // (PIOD) Interrupt Disable Register -#define AT91C_PIOD_PDR (0xFFFFFA04) // (PIOD) PIO Disable Register -#define AT91C_PIOD_ODR (0xFFFFFA14) // (PIOD) Output Disable Registerr -#define AT91C_PIOD_OWSR (0xFFFFFAA8) // (PIOD) Output Write Status Register -#define AT91C_PIOD_ABSR (0xFFFFFA78) // (PIOD) AB Select Status Register -#define AT91C_PIOD_ASR (0xFFFFFA70) // (PIOD) Select A Register -#define AT91C_PIOD_PPUSR (0xFFFFFA68) // (PIOD) Pad Pull-up Status Register -#define AT91C_PIOD_PPUDR (0xFFFFFA60) // (PIOD) Pull-up Disable Register -#define AT91C_PIOD_MDSR (0xFFFFFA58) // (PIOD) Multi-driver Status Register -#define AT91C_PIOD_PSR (0xFFFFFA08) // (PIOD) PIO Status Register -#define AT91C_PIOD_OER (0xFFFFFA10) // (PIOD) Output Enable Register -#define AT91C_PIOD_OSR (0xFFFFFA18) // (PIOD) Output Status Register -#define AT91C_PIOD_IFER (0xFFFFFA20) // (PIOD) Input Filter Enable Register -#define AT91C_PIOD_BSR (0xFFFFFA74) // (PIOD) Select B Register -#define AT91C_PIOD_IFDR (0xFFFFFA24) // (PIOD) Input Filter Disable Register -#define AT91C_PIOD_IFSR (0xFFFFFA28) // (PIOD) Input Filter Status Register -// ========== Register definition for PIOC peripheral ========== -#define AT91C_PIOC_IFDR (0xFFFFF824) // (PIOC) Input Filter Disable Register -#define AT91C_PIOC_ODR (0xFFFFF814) // (PIOC) Output Disable Registerr -#define AT91C_PIOC_ABSR (0xFFFFF878) // (PIOC) AB Select Status Register -#define AT91C_PIOC_SODR (0xFFFFF830) // (PIOC) Set Output Data Register -#define AT91C_PIOC_IFSR (0xFFFFF828) // (PIOC) Input Filter Status Register -#define AT91C_PIOC_CODR (0xFFFFF834) // (PIOC) Clear Output Data Register -#define AT91C_PIOC_ODSR (0xFFFFF838) // (PIOC) Output Data Status Register -#define AT91C_PIOC_IER (0xFFFFF840) // (PIOC) Interrupt Enable Register -#define AT91C_PIOC_IMR (0xFFFFF848) // (PIOC) Interrupt Mask Register -#define AT91C_PIOC_OWDR (0xFFFFF8A4) // (PIOC) Output Write Disable Register -#define AT91C_PIOC_MDDR (0xFFFFF854) // (PIOC) Multi-driver Disable Register -#define AT91C_PIOC_PDSR (0xFFFFF83C) // (PIOC) Pin Data Status Register -#define AT91C_PIOC_IDR (0xFFFFF844) // (PIOC) Interrupt Disable Register -#define AT91C_PIOC_ISR (0xFFFFF84C) // (PIOC) Interrupt Status Register -#define AT91C_PIOC_PDR (0xFFFFF804) // (PIOC) PIO Disable Register -#define AT91C_PIOC_OWSR (0xFFFFF8A8) // (PIOC) Output Write Status Register -#define AT91C_PIOC_OWER (0xFFFFF8A0) // (PIOC) Output Write Enable Register -#define AT91C_PIOC_ASR (0xFFFFF870) // (PIOC) Select A Register -#define AT91C_PIOC_PPUSR (0xFFFFF868) // (PIOC) Pad Pull-up Status Register -#define AT91C_PIOC_PPUDR (0xFFFFF860) // (PIOC) Pull-up Disable Register -#define AT91C_PIOC_MDSR (0xFFFFF858) // (PIOC) Multi-driver Status Register -#define AT91C_PIOC_MDER (0xFFFFF850) // (PIOC) Multi-driver Enable Register -#define AT91C_PIOC_IFER (0xFFFFF820) // (PIOC) Input Filter Enable Register -#define AT91C_PIOC_OSR (0xFFFFF818) // (PIOC) Output Status Register -#define AT91C_PIOC_OER (0xFFFFF810) // (PIOC) Output Enable Register -#define AT91C_PIOC_PSR (0xFFFFF808) // (PIOC) PIO Status Register -#define AT91C_PIOC_PER (0xFFFFF800) // (PIOC) PIO Enable Register -#define AT91C_PIOC_BSR (0xFFFFF874) // (PIOC) Select B Register -#define AT91C_PIOC_PPUER (0xFFFFF864) // (PIOC) Pull-up Enable Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pad Pull-up Status Register -#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register -#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register -#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register -#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register -#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_SSC2 peripheral ========== -#define AT91C_SSC2_PTCR (0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register -#define AT91C_SSC2_TNPR (0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register -#define AT91C_SSC2_RNPR (0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register -#define AT91C_SSC2_TPR (0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register -#define AT91C_SSC2_RPR (0xFFFD8100) // (PDC_SSC2) Receive Pointer Register -#define AT91C_SSC2_PTSR (0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register -#define AT91C_SSC2_TNCR (0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register -#define AT91C_SSC2_RNCR (0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register -#define AT91C_SSC2_TCR (0xFFFD810C) // (PDC_SSC2) Transmit Counter Register -#define AT91C_SSC2_RCR (0xFFFD8104) // (PDC_SSC2) Receive Counter Register -// ========== Register definition for SSC2 peripheral ========== -#define AT91C_SSC2_IMR (0xFFFD804C) // (SSC2) Interrupt Mask Register -#define AT91C_SSC2_IER (0xFFFD8044) // (SSC2) Interrupt Enable Register -#define AT91C_SSC2_RC1R (0xFFFD803C) // (SSC2) Receive Compare 1 Register -#define AT91C_SSC2_TSHR (0xFFFD8034) // (SSC2) Transmit Sync Holding Register -#define AT91C_SSC2_CMR (0xFFFD8004) // (SSC2) Clock Mode Register -#define AT91C_SSC2_IDR (0xFFFD8048) // (SSC2) Interrupt Disable Register -#define AT91C_SSC2_TCMR (0xFFFD8018) // (SSC2) Transmit Clock Mode Register -#define AT91C_SSC2_RCMR (0xFFFD8010) // (SSC2) Receive Clock ModeRegister -#define AT91C_SSC2_CR (0xFFFD8000) // (SSC2) Control Register -#define AT91C_SSC2_RFMR (0xFFFD8014) // (SSC2) Receive Frame Mode Register -#define AT91C_SSC2_TFMR (0xFFFD801C) // (SSC2) Transmit Frame Mode Register -#define AT91C_SSC2_THR (0xFFFD8024) // (SSC2) Transmit Holding Register -#define AT91C_SSC2_SR (0xFFFD8040) // (SSC2) Status Register -#define AT91C_SSC2_RC0R (0xFFFD8038) // (SSC2) Receive Compare 0 Register -#define AT91C_SSC2_RSHR (0xFFFD8030) // (SSC2) Receive Sync Holding Register -#define AT91C_SSC2_RHR (0xFFFD8020) // (SSC2) Receive Holding Register -// ========== Register definition for PDC_SSC1 peripheral ========== -#define AT91C_SSC1_PTCR (0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register -#define AT91C_SSC1_TNPR (0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register -#define AT91C_SSC1_RNPR (0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register -#define AT91C_SSC1_TPR (0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register -#define AT91C_SSC1_RPR (0xFFFD4100) // (PDC_SSC1) Receive Pointer Register -#define AT91C_SSC1_PTSR (0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register -#define AT91C_SSC1_TNCR (0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register -#define AT91C_SSC1_RNCR (0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register -#define AT91C_SSC1_TCR (0xFFFD410C) // (PDC_SSC1) Transmit Counter Register -#define AT91C_SSC1_RCR (0xFFFD4104) // (PDC_SSC1) Receive Counter Register -// ========== Register definition for SSC1 peripheral ========== -#define AT91C_SSC1_RFMR (0xFFFD4014) // (SSC1) Receive Frame Mode Register -#define AT91C_SSC1_CMR (0xFFFD4004) // (SSC1) Clock Mode Register -#define AT91C_SSC1_IDR (0xFFFD4048) // (SSC1) Interrupt Disable Register -#define AT91C_SSC1_SR (0xFFFD4040) // (SSC1) Status Register -#define AT91C_SSC1_RC0R (0xFFFD4038) // (SSC1) Receive Compare 0 Register -#define AT91C_SSC1_RSHR (0xFFFD4030) // (SSC1) Receive Sync Holding Register -#define AT91C_SSC1_RHR (0xFFFD4020) // (SSC1) Receive Holding Register -#define AT91C_SSC1_TCMR (0xFFFD4018) // (SSC1) Transmit Clock Mode Register -#define AT91C_SSC1_RCMR (0xFFFD4010) // (SSC1) Receive Clock ModeRegister -#define AT91C_SSC1_CR (0xFFFD4000) // (SSC1) Control Register -#define AT91C_SSC1_IMR (0xFFFD404C) // (SSC1) Interrupt Mask Register -#define AT91C_SSC1_IER (0xFFFD4044) // (SSC1) Interrupt Enable Register -#define AT91C_SSC1_RC1R (0xFFFD403C) // (SSC1) Receive Compare 1 Register -#define AT91C_SSC1_TSHR (0xFFFD4034) // (SSC1) Transmit Sync Holding Register -#define AT91C_SSC1_THR (0xFFFD4024) // (SSC1) Transmit Holding Register -#define AT91C_SSC1_TFMR (0xFFFD401C) // (SSC1) Transmit Frame Mode Register -// ========== Register definition for PDC_SSC0 peripheral ========== -#define AT91C_SSC0_PTCR (0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register -#define AT91C_SSC0_TNPR (0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register -#define AT91C_SSC0_RNPR (0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register -#define AT91C_SSC0_TPR (0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register -#define AT91C_SSC0_RPR (0xFFFD0100) // (PDC_SSC0) Receive Pointer Register -#define AT91C_SSC0_PTSR (0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register -#define AT91C_SSC0_TNCR (0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register -#define AT91C_SSC0_RNCR (0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register -#define AT91C_SSC0_TCR (0xFFFD010C) // (PDC_SSC0) Transmit Counter Register -#define AT91C_SSC0_RCR (0xFFFD0104) // (PDC_SSC0) Receive Counter Register -// ========== Register definition for SSC0 peripheral ========== -#define AT91C_SSC0_IMR (0xFFFD004C) // (SSC0) Interrupt Mask Register -#define AT91C_SSC0_IER (0xFFFD0044) // (SSC0) Interrupt Enable Register -#define AT91C_SSC0_RC1R (0xFFFD003C) // (SSC0) Receive Compare 1 Register -#define AT91C_SSC0_TSHR (0xFFFD0034) // (SSC0) Transmit Sync Holding Register -#define AT91C_SSC0_THR (0xFFFD0024) // (SSC0) Transmit Holding Register -#define AT91C_SSC0_TFMR (0xFFFD001C) // (SSC0) Transmit Frame Mode Register -#define AT91C_SSC0_RFMR (0xFFFD0014) // (SSC0) Receive Frame Mode Register -#define AT91C_SSC0_CMR (0xFFFD0004) // (SSC0) Clock Mode Register -#define AT91C_SSC0_IDR (0xFFFD0048) // (SSC0) Interrupt Disable Register -#define AT91C_SSC0_SR (0xFFFD0040) // (SSC0) Status Register -#define AT91C_SSC0_RC0R (0xFFFD0038) // (SSC0) Receive Compare 0 Register -#define AT91C_SSC0_RSHR (0xFFFD0030) // (SSC0) Receive Sync Holding Register -#define AT91C_SSC0_RHR (0xFFFD0020) // (SSC0) Receive Holding Register -#define AT91C_SSC0_TCMR (0xFFFD0018) // (SSC0) Transmit Clock Mode Register -#define AT91C_SSC0_RCMR (0xFFFD0010) // (SSC0) Receive Clock ModeRegister -#define AT91C_SSC0_CR (0xFFFD0000) // (SSC0) Control Register -// ========== Register definition for PDC_US3 peripheral ========== -#define AT91C_US3_PTSR (0xFFFCC124) // (PDC_US3) PDC Transfer Status Register -#define AT91C_US3_TNCR (0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register -#define AT91C_US3_RNCR (0xFFFCC114) // (PDC_US3) Receive Next Counter Register -#define AT91C_US3_TCR (0xFFFCC10C) // (PDC_US3) Transmit Counter Register -#define AT91C_US3_RCR (0xFFFCC104) // (PDC_US3) Receive Counter Register -#define AT91C_US3_PTCR (0xFFFCC120) // (PDC_US3) PDC Transfer Control Register -#define AT91C_US3_TNPR (0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register -#define AT91C_US3_RNPR (0xFFFCC110) // (PDC_US3) Receive Next Pointer Register -#define AT91C_US3_TPR (0xFFFCC108) // (PDC_US3) Transmit Pointer Register -#define AT91C_US3_RPR (0xFFFCC100) // (PDC_US3) Receive Pointer Register -// ========== Register definition for US3 peripheral ========== -#define AT91C_US3_IF (0xFFFCC04C) // (US3) IRDA_FILTER Register -#define AT91C_US3_NER (0xFFFCC044) // (US3) Nb Errors Register -#define AT91C_US3_RTOR (0xFFFCC024) // (US3) Receiver Time-out Register -#define AT91C_US3_THR (0xFFFCC01C) // (US3) Transmitter Holding Register -#define AT91C_US3_CSR (0xFFFCC014) // (US3) Channel Status Register -#define AT91C_US3_IDR (0xFFFCC00C) // (US3) Interrupt Disable Register -#define AT91C_US3_MR (0xFFFCC004) // (US3) Mode Register -#define AT91C_US3_XXR (0xFFFCC048) // (US3) XON_XOFF Register -#define AT91C_US3_FIDI (0xFFFCC040) // (US3) FI_DI_Ratio Register -#define AT91C_US3_TTGR (0xFFFCC028) // (US3) Transmitter Time-guard Register -#define AT91C_US3_BRGR (0xFFFCC020) // (US3) Baud Rate Generator Register -#define AT91C_US3_RHR (0xFFFCC018) // (US3) Receiver Holding Register -#define AT91C_US3_IMR (0xFFFCC010) // (US3) Interrupt Mask Register -#define AT91C_US3_IER (0xFFFCC008) // (US3) Interrupt Enable Register -#define AT91C_US3_CR (0xFFFCC000) // (US3) Control Register -// ========== Register definition for PDC_US2 peripheral ========== -#define AT91C_US2_PTSR (0xFFFC8124) // (PDC_US2) PDC Transfer Status Register -#define AT91C_US2_TNCR (0xFFFC811C) // (PDC_US2) Transmit Next Counter Register -#define AT91C_US2_RNCR (0xFFFC8114) // (PDC_US2) Receive Next Counter Register -#define AT91C_US2_TCR (0xFFFC810C) // (PDC_US2) Transmit Counter Register -#define AT91C_US2_PTCR (0xFFFC8120) // (PDC_US2) PDC Transfer Control Register -#define AT91C_US2_RCR (0xFFFC8104) // (PDC_US2) Receive Counter Register -#define AT91C_US2_TNPR (0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register -#define AT91C_US2_RPR (0xFFFC8100) // (PDC_US2) Receive Pointer Register -#define AT91C_US2_TPR (0xFFFC8108) // (PDC_US2) Transmit Pointer Register -#define AT91C_US2_RNPR (0xFFFC8110) // (PDC_US2) Receive Next Pointer Register -// ========== Register definition for US2 peripheral ========== -#define AT91C_US2_XXR (0xFFFC8048) // (US2) XON_XOFF Register -#define AT91C_US2_FIDI (0xFFFC8040) // (US2) FI_DI_Ratio Register -#define AT91C_US2_TTGR (0xFFFC8028) // (US2) Transmitter Time-guard Register -#define AT91C_US2_BRGR (0xFFFC8020) // (US2) Baud Rate Generator Register -#define AT91C_US2_RHR (0xFFFC8018) // (US2) Receiver Holding Register -#define AT91C_US2_IMR (0xFFFC8010) // (US2) Interrupt Mask Register -#define AT91C_US2_IER (0xFFFC8008) // (US2) Interrupt Enable Register -#define AT91C_US2_CR (0xFFFC8000) // (US2) Control Register -#define AT91C_US2_IF (0xFFFC804C) // (US2) IRDA_FILTER Register -#define AT91C_US2_NER (0xFFFC8044) // (US2) Nb Errors Register -#define AT91C_US2_RTOR (0xFFFC8024) // (US2) Receiver Time-out Register -#define AT91C_US2_THR (0xFFFC801C) // (US2) Transmitter Holding Register -#define AT91C_US2_CSR (0xFFFC8014) // (US2) Channel Status Register -#define AT91C_US2_IDR (0xFFFC800C) // (US2) Interrupt Disable Register -#define AT91C_US2_MR (0xFFFC8004) // (US2) Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register -#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register -#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register -#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for PDC_MCI peripheral ========== -#define AT91C_MCI_PTCR (0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register -#define AT91C_MCI_TNPR (0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register -#define AT91C_MCI_RNPR (0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register -#define AT91C_MCI_TPR (0xFFFB4108) // (PDC_MCI) Transmit Pointer Register -#define AT91C_MCI_RPR (0xFFFB4100) // (PDC_MCI) Receive Pointer Register -#define AT91C_MCI_PTSR (0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register -#define AT91C_MCI_TNCR (0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register -#define AT91C_MCI_RNCR (0xFFFB4114) // (PDC_MCI) Receive Next Counter Register -#define AT91C_MCI_TCR (0xFFFB410C) // (PDC_MCI) Transmit Counter Register -#define AT91C_MCI_RCR (0xFFFB4104) // (PDC_MCI) Receive Counter Register -// ========== Register definition for MCI peripheral ========== -#define AT91C_MCI_IDR (0xFFFB4048) // (MCI) MCI Interrupt Disable Register -#define AT91C_MCI_SR (0xFFFB4040) // (MCI) MCI Status Register -#define AT91C_MCI_RDR (0xFFFB4030) // (MCI) MCI Receive Data Register -#define AT91C_MCI_RSPR (0xFFFB4020) // (MCI) MCI Response Register -#define AT91C_MCI_ARGR (0xFFFB4010) // (MCI) MCI Argument Register -#define AT91C_MCI_DTOR (0xFFFB4008) // (MCI) MCI Data Timeout Register -#define AT91C_MCI_CR (0xFFFB4000) // (MCI) MCI Control Register -#define AT91C_MCI_IMR (0xFFFB404C) // (MCI) MCI Interrupt Mask Register -#define AT91C_MCI_IER (0xFFFB4044) // (MCI) MCI Interrupt Enable Register -#define AT91C_MCI_TDR (0xFFFB4034) // (MCI) MCI Transmit Data Register -#define AT91C_MCI_CMDR (0xFFFB4014) // (MCI) MCI Command Register -#define AT91C_MCI_SDCR (0xFFFB400C) // (MCI) MCI SD Card Register -#define AT91C_MCI_MR (0xFFFB4004) // (MCI) MCI Mode Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register -// ========== Register definition for TC5 peripheral ========== -#define AT91C_TC5_CMR (0xFFFA4084) // (TC5) Channel Mode Register -#define AT91C_TC5_IDR (0xFFFA40A8) // (TC5) Interrupt Disable Register -#define AT91C_TC5_SR (0xFFFA40A0) // (TC5) Status Register -#define AT91C_TC5_RB (0xFFFA4098) // (TC5) Register B -#define AT91C_TC5_CV (0xFFFA4090) // (TC5) Counter Value -#define AT91C_TC5_CCR (0xFFFA4080) // (TC5) Channel Control Register -#define AT91C_TC5_IMR (0xFFFA40AC) // (TC5) Interrupt Mask Register -#define AT91C_TC5_IER (0xFFFA40A4) // (TC5) Interrupt Enable Register -#define AT91C_TC5_RC (0xFFFA409C) // (TC5) Register C -#define AT91C_TC5_RA (0xFFFA4094) // (TC5) Register A -// ========== Register definition for TC4 peripheral ========== -#define AT91C_TC4_IMR (0xFFFA406C) // (TC4) Interrupt Mask Register -#define AT91C_TC4_IER (0xFFFA4064) // (TC4) Interrupt Enable Register -#define AT91C_TC4_RC (0xFFFA405C) // (TC4) Register C -#define AT91C_TC4_RA (0xFFFA4054) // (TC4) Register A -#define AT91C_TC4_CMR (0xFFFA4044) // (TC4) Channel Mode Register -#define AT91C_TC4_IDR (0xFFFA4068) // (TC4) Interrupt Disable Register -#define AT91C_TC4_SR (0xFFFA4060) // (TC4) Status Register -#define AT91C_TC4_RB (0xFFFA4058) // (TC4) Register B -#define AT91C_TC4_CV (0xFFFA4050) // (TC4) Counter Value -#define AT91C_TC4_CCR (0xFFFA4040) // (TC4) Channel Control Register -// ========== Register definition for TC3 peripheral ========== -#define AT91C_TC3_IMR (0xFFFA402C) // (TC3) Interrupt Mask Register -#define AT91C_TC3_CV (0xFFFA4010) // (TC3) Counter Value -#define AT91C_TC3_CCR (0xFFFA4000) // (TC3) Channel Control Register -#define AT91C_TC3_IER (0xFFFA4024) // (TC3) Interrupt Enable Register -#define AT91C_TC3_CMR (0xFFFA4004) // (TC3) Channel Mode Register -#define AT91C_TC3_RA (0xFFFA4014) // (TC3) Register A -#define AT91C_TC3_RC (0xFFFA401C) // (TC3) Register C -#define AT91C_TC3_IDR (0xFFFA4028) // (TC3) Interrupt Disable Register -#define AT91C_TC3_RB (0xFFFA4018) // (TC3) Register B -#define AT91C_TC3_SR (0xFFFA4020) // (TC3) Status Register -// ========== Register definition for TCB1 peripheral ========== -#define AT91C_TCB1_BCR (0xFFFA4140) // (TCB1) TC Block Control Register -#define AT91C_TCB1_BMR (0xFFFA4144) // (TCB1) TC Block Mode Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register -#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register -#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register -#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TCB0 peripheral ========== -#define AT91C_TCB0_BMR (0xFFFA00C4) // (TCB0) TC Block Mode Register -#define AT91C_TCB0_BCR (0xFFFA00C0) // (TCB0) TC Block Control Register -// ========== Register definition for UHP peripheral ========== -#define AT91C_UHP_HcRhDescriptorA (0x00300048) // (UHP) Root Hub characteristics A -#define AT91C_UHP_HcRhPortStatus (0x00300054) // (UHP) Root Hub Port Status Register -#define AT91C_UHP_HcRhDescriptorB (0x0030004C) // (UHP) Root Hub characteristics B -#define AT91C_UHP_HcControl (0x00300004) // (UHP) Operating modes for the Host Controller -#define AT91C_UHP_HcInterruptStatus (0x0030000C) // (UHP) Interrupt Status Register -#define AT91C_UHP_HcRhStatus (0x00300050) // (UHP) Root Hub Status register -#define AT91C_UHP_HcRevision (0x00300000) // (UHP) Revision -#define AT91C_UHP_HcCommandStatus (0x00300008) // (UHP) Command & status Register -#define AT91C_UHP_HcInterruptEnable (0x00300010) // (UHP) Interrupt Enable Register -#define AT91C_UHP_HcHCCA (0x00300018) // (UHP) Pointer to the Host Controller Communication Area -#define AT91C_UHP_HcControlHeadED (0x00300020) // (UHP) First Endpoint Descriptor of the Control list -#define AT91C_UHP_HcInterruptDisable (0x00300014) // (UHP) Interrupt Disable Register -#define AT91C_UHP_HcPeriodCurrentED (0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor -#define AT91C_UHP_HcControlCurrentED (0x00300024) // (UHP) Endpoint Control and Status Register -#define AT91C_UHP_HcBulkCurrentED (0x0030002C) // (UHP) Current endpoint of the Bulk list -#define AT91C_UHP_HcFmInterval (0x00300034) // (UHP) Bit time between 2 consecutive SOFs -#define AT91C_UHP_HcBulkHeadED (0x00300028) // (UHP) First endpoint register of the Bulk list -#define AT91C_UHP_HcBulkDoneHead (0x00300030) // (UHP) Last completed transfer descriptor -#define AT91C_UHP_HcFmRemaining (0x00300038) // (UHP) Bit time remaining in the current Frame -#define AT91C_UHP_HcPeriodicStart (0x00300040) // (UHP) Periodic Start -#define AT91C_UHP_HcLSThreshold (0x00300044) // (UHP) LS Threshold -#define AT91C_UHP_HcFmNumber (0x0030003C) // (UHP) Frame number -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_RSR (0xFFFBC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_MAN (0xFFFBC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_HSH (0xFFFBC090) // (EMAC) Hash Address High[63:32] -#define AT91C_EMAC_MCOL (0xFFFBC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_IER (0xFFFBC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA2H (0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes -#define AT91C_EMAC_HSL (0xFFFBC094) // (EMAC) Hash Address Low[31:0] -#define AT91C_EMAC_LCOL (0xFFFBC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_OK (0xFFFBC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_CFG (0xFFFBC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_SA3L (0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes -#define AT91C_EMAC_SEQE (0xFFFBC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_ECOL (0xFFFBC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_ELR (0xFFFBC070) // (EMAC) Excessive Length Error Register -#define AT91C_EMAC_SR (0xFFFBC008) // (EMAC) Network Status Register -#define AT91C_EMAC_RBQP (0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_CSE (0xFFFBC064) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_RJB (0xFFFBC074) // (EMAC) Receive Jabber Register -#define AT91C_EMAC_USF (0xFFFBC078) // (EMAC) Undersize Frame Register -#define AT91C_EMAC_IDR (0xFFFBC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_SA1L (0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes -#define AT91C_EMAC_IMR (0xFFFBC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_FRA (0xFFFBC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_SA3H (0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes -#define AT91C_EMAC_SA1H (0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes -#define AT91C_EMAC_SCOL (0xFFFBC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_ALE (0xFFFBC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_TAR (0xFFFBC00C) // (EMAC) Transmit Address Register -#define AT91C_EMAC_SA4L (0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes -#define AT91C_EMAC_SA2L (0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes -#define AT91C_EMAC_TUE (0xFFFBC068) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_DTE (0xFFFBC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TCR (0xFFFBC010) // (EMAC) Transmit Control Register -#define AT91C_EMAC_CTL (0xFFFBC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4H (0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr -#define AT91C_EMAC_CDE (0xFFFBC06C) // (EMAC) Code Error Register -#define AT91C_EMAC_SQEE (0xFFFBC07C) // (EMAC) SQE Test Error Register -#define AT91C_EMAC_TSR (0xFFFBC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_DRFC (0xFFFBC080) // (EMAC) Discarded RX Frame Register -// ========== Register definition for EBI peripheral ========== -#define AT91C_EBI_CFGR (0xFFFFFF64) // (EBI) Configuration Register -#define AT91C_EBI_CSA (0xFFFFFF60) // (EBI) Chip Select Assignment Register -// ========== Register definition for SMC2 peripheral ========== -#define AT91C_SMC2_CSR (0xFFFFFF70) // (SMC2) SMC2 Chip Select Register -// ========== Register definition for SDRC peripheral ========== -#define AT91C_SDRC_IMR (0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register -#define AT91C_SDRC_IER (0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register -#define AT91C_SDRC_SRR (0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register -#define AT91C_SDRC_TR (0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register -#define AT91C_SDRC_ISR (0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register -#define AT91C_SDRC_IDR (0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register -#define AT91C_SDRC_LPR (0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register -#define AT91C_SDRC_CR (0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register -#define AT91C_SDRC_MR (0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register -// ========== Register definition for BFC peripheral ========== -#define AT91C_BFC_MR (0xFFFFFFC0) // (BFC) BFC Mode Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_MISO (AT91C_PIO_PA0) // SPI Master In Slave -#define AT91C_PA0_PCK3 (AT91C_PIO_PA0) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_MOSI (AT91C_PIO_PA1) // SPI Master Out Slave -#define AT91C_PA1_PCK0 (AT91C_PIO_PA1) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_ETX1 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 1 -#define AT91C_PA10_MCDB1 (AT91C_PIO_PA10) // Multimedia Card B Data 1 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_ECRS_ECRSDV (AT91C_PIO_PA11) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PA11_MCDB2 (AT91C_PIO_PA11) // Multimedia Card B Data 2 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_ERX0 (AT91C_PIO_PA12) // Ethernet MAC Receive Data 0 -#define AT91C_PA12_MCDB3 (AT91C_PIO_PA12) // Multimedia Card B Data 3 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_ERX1 (AT91C_PIO_PA13) // Ethernet MAC Receive Data 1 -#define AT91C_PA13_TCLK0 (AT91C_PIO_PA13) // Timer Counter 0 external clock input -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_ERXER (AT91C_PIO_PA14) // Ethernet MAC Receive Error -#define AT91C_PA14_TCLK1 (AT91C_PIO_PA14) // Timer Counter 1 external clock input -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_EMDC (AT91C_PIO_PA15) // Ethernet MAC Management Data Clock -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_EMDIO (AT91C_PIO_PA16) // Ethernet MAC Management Data Input/Output -#define AT91C_PA16_IRQ6 (AT91C_PIO_PA16) // AIC Interrupt input 6 -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TXD0 (AT91C_PIO_PA17) // USART 0 Transmit Data -#define AT91C_PA17_TIOA0 (AT91C_PIO_PA17) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RXD0 (AT91C_PIO_PA18) // USART 0 Receive Data -#define AT91C_PA18_TIOB0 (AT91C_PIO_PA18) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_SCK0 (AT91C_PIO_PA19) // USART 0 Serial Clock -#define AT91C_PA19_TIOA1 (AT91C_PIO_PA19) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SPCK (AT91C_PIO_PA2) // SPI Serial Clock -#define AT91C_PA2_IRQ4 (AT91C_PIO_PA2) // AIC Interrupt Input 4 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CTS0 (AT91C_PIO_PA20) // USART 0 Clear To Send -#define AT91C_PA20_TIOB1 (AT91C_PIO_PA20) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RTS0 (AT91C_PIO_PA21) // Usart 0 Ready To Send -#define AT91C_PA21_TIOA2 (AT91C_PIO_PA21) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_RXD2 (AT91C_PIO_PA22) // USART 2 Receive Data -#define AT91C_PA22_TIOB2 (AT91C_PIO_PA22) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TXD2 (AT91C_PIO_PA23) // USART 2 Transmit Data -#define AT91C_PA23_IRQ3 (AT91C_PIO_PA23) // Interrupt input 3 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_SCK2 (AT91C_PIO_PA24) // USART2 Serial Clock -#define AT91C_PA24_PCK1 (AT91C_PIO_PA24) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_TWD (AT91C_PIO_PA25) // TWI Two-wire Serial Data -#define AT91C_PA25_IRQ2 (AT91C_PIO_PA25) // Interrupt input 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_TWCK (AT91C_PIO_PA26) // TWI Two-wire Serial Clock -#define AT91C_PA26_IRQ1 (AT91C_PIO_PA26) // Interrupt input 1 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_MCCK (AT91C_PIO_PA27) // Multimedia Card Clock -#define AT91C_PA27_TCLK3 (AT91C_PIO_PA27) // Timer Counter 3 External Clock Input -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_MCCDA (AT91C_PIO_PA28) // Multimedia Card A Command -#define AT91C_PA28_TCLK4 (AT91C_PIO_PA28) // Timer Counter 4 external Clock Input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_MCDA0 (AT91C_PIO_PA29) // Multimedia Card A Data 0 -#define AT91C_PA29_TCLK5 (AT91C_PIO_PA29) // Timer Counter 5 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_NPCS0 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 0 -#define AT91C_PA3_IRQ5 (AT91C_PIO_PA3) // AIC Interrupt Input 5 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_DRXD (AT91C_PIO_PA30) // DBGU Debug Receive Data -#define AT91C_PA30_CTS2 (AT91C_PIO_PA30) // Usart 2 Clear To Send -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_DTXD (AT91C_PIO_PA31) // DBGU Debug Transmit Data -#define AT91C_PA31_RTS2 (AT91C_PIO_PA31) // USART 2 Ready To Send -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_NPCS1 (AT91C_PIO_PA4) // SPI Peripheral Chip Select 1 -#define AT91C_PA4_PCK1 (AT91C_PIO_PA4) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_NPCS2 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 2 -#define AT91C_PA5_TXD3 (AT91C_PIO_PA5) // USART 3 Transmit Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_NPCS3 (AT91C_PIO_PA6) // SPI Peripheral Chip Select 3 -#define AT91C_PA6_RXD3 (AT91C_PIO_PA6) // USART 3 Receive Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_ETXCK_EREFCK (AT91C_PIO_PA7) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PA7_PCK2 (AT91C_PIO_PA7) // PMC Programmable Clock 2 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_ETXEN (AT91C_PIO_PA8) // Ethernet MAC Transmit Enable -#define AT91C_PA8_MCCDB (AT91C_PIO_PA8) // Multimedia Card B Command -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_ETX0 (AT91C_PIO_PA9) // Ethernet MAC Transmit Data 0 -#define AT91C_PA9_MCDB0 (AT91C_PIO_PA9) // Multimedia Card B Data 0 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_TF0 (AT91C_PIO_PB0) // SSC Transmit Frame Sync 0 -#define AT91C_PB0_TIOB3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_TK0 (AT91C_PIO_PB1) // SSC Transmit Clock 0 -#define AT91C_PB1_CTS3 (AT91C_PIO_PB1) // USART 3 Clear To Send -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_RK1 (AT91C_PIO_PB10) // SSC Receive Clock 1 -#define AT91C_PB10_TIOA5 (AT91C_PIO_PB10) // Timer Counter 5 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_RF1 (AT91C_PIO_PB11) // SSC Receive Frame Sync 1 -#define AT91C_PB11_TIOB5 (AT91C_PIO_PB11) // Timer Counter 5 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_TF2 (AT91C_PIO_PB12) // SSC Transmit Frame Sync 2 -#define AT91C_PB12_ETX2 (AT91C_PIO_PB12) // Ethernet MAC Transmit Data 2 -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_TK2 (AT91C_PIO_PB13) // SSC Transmit Clock 2 -#define AT91C_PB13_ETX3 (AT91C_PIO_PB13) // Ethernet MAC Transmit Data 3 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_TD2 (AT91C_PIO_PB14) // SSC Transmit Data 2 -#define AT91C_PB14_ETXER (AT91C_PIO_PB14) // Ethernet MAC Transmikt Coding Error -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_RD2 (AT91C_PIO_PB15) // SSC Receive Data 2 -#define AT91C_PB15_ERX2 (AT91C_PIO_PB15) // Ethernet MAC Receive Data 2 -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_RK2 (AT91C_PIO_PB16) // SSC Receive Clock 2 -#define AT91C_PB16_ERX3 (AT91C_PIO_PB16) // Ethernet MAC Receive Data 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_RF2 (AT91C_PIO_PB17) // SSC Receive Frame Sync 2 -#define AT91C_PB17_ERXDV (AT91C_PIO_PB17) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_RI1 (AT91C_PIO_PB18) // USART 1 Ring Indicator -#define AT91C_PB18_ECOL (AT91C_PIO_PB18) // Ethernet MAC Collision Detected -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_DTR1 (AT91C_PIO_PB19) // USART 1 Data Terminal ready -#define AT91C_PB19_ERXCK (AT91C_PIO_PB19) // Ethernet MAC Receive Clock -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_TD0 (AT91C_PIO_PB2) // SSC Transmit data -#define AT91C_PB2_SCK3 (AT91C_PIO_PB2) // USART 3 Serial Clock -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_TXD1 (AT91C_PIO_PB20) // USART 1 Transmit Data -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_RXD1 (AT91C_PIO_PB21) // USART 1 Receive Data -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_SCK1 (AT91C_PIO_PB22) // USART1 Serial Clock -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_CTS1 (AT91C_PIO_PB24) // USART 1 Clear To Send -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_DSR1 (AT91C_PIO_PB25) // USART 1 Data Set ready -#define AT91C_PB25_EF100 (AT91C_PIO_PB25) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_RTS1 (AT91C_PIO_PB26) // Usart 0 Ready To Send -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_PCK0 (AT91C_PIO_PB27) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_FIQ (AT91C_PIO_PB28) // AIC Fast Interrupt Input -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_IRQ0 (AT91C_PIO_PB29) // Interrupt input 0 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_RD0 (AT91C_PIO_PB3) // SSC Receive Data -#define AT91C_PB3_MCDA1 (AT91C_PIO_PB3) // Multimedia Card A Data 1 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_RK0 (AT91C_PIO_PB4) // SSC Receive Clock -#define AT91C_PB4_MCDA2 (AT91C_PIO_PB4) // Multimedia Card A Data 2 -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_RF0 (AT91C_PIO_PB5) // SSC Receive Frame Sync 0 -#define AT91C_PB5_MCDA3 (AT91C_PIO_PB5) // Multimedia Card A Data 3 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_TF1 (AT91C_PIO_PB6) // SSC Transmit Frame Sync 1 -#define AT91C_PB6_TIOA3 (AT91C_PIO_PB6) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_TK1 (AT91C_PIO_PB7) // SSC Transmit Clock 1 -#define AT91C_PB7_TIOB3 (AT91C_PIO_PB7) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_TD1 (AT91C_PIO_PB8) // SSC Transmit Data 1 -#define AT91C_PB8_TIOA4 (AT91C_PIO_PB8) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_RD1 (AT91C_PIO_PB9) // SSC Receive Data 1 -#define AT91C_PB9_TIOB4 (AT91C_PIO_PB9) // Timer Counter 4 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0 -#define AT91C_PC0_BFCK (AT91C_PIO_PC0) // Burst Flash Clock -#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1 -#define AT91C_PC1_BFRDY_SMOE (AT91C_PIO_PC1) // Burst Flash Ready -#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10 -#define AT91C_PC10_NCS4_CFCS (AT91C_PIO_PC10) // Compact Flash Chip Select -#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11 -#define AT91C_PC11_NCS5_CFCE1 (AT91C_PIO_PC11) // Chip Select 5 / Compact Flash Chip Enable 1 -#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12 -#define AT91C_PC12_NCS6_CFCE2 (AT91C_PIO_PC12) // Chip Select 6 / Compact Flash Chip Enable 2 -#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13 -#define AT91C_PC13_NCS7 (AT91C_PIO_PC13) // Chip Select 7 -#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14 -#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15 -#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16 -#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus [16] -#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17 -#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus [17] -#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18 -#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus [18] -#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19 -#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus [19] -#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2 -#define AT91C_PC2_BFAVD (AT91C_PIO_PC2) // Burst Flash Address Valid -#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20 -#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus [20] -#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21 -#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus [21] -#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22 -#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus [22] -#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23 -#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus [23] -#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24 -#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus [24] -#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25 -#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus [25] -#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26 -#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus [26] -#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27 -#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus [27] -#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28 -#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus [28] -#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29 -#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus [29] -#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3 -#define AT91C_PC3_BFBAA_SMWE (AT91C_PIO_PC3) // Burst Flash Address Advance / SmartMedia Write Enable -#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30 -#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus [30] -#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31 -#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus [31] -#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4 -#define AT91C_PC4_BFOE (AT91C_PIO_PC4) // Burst Flash Output Enable -#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5 -#define AT91C_PC5_BFWE (AT91C_PIO_PC5) // Burst Flash Write Enable -#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6 -#define AT91C_PC6_NWAIT (AT91C_PIO_PC6) // NWAIT -#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7 -#define AT91C_PC7_A23 (AT91C_PIO_PC7) // Address Bus[23] -#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8 -#define AT91C_PC8_A24 (AT91C_PIO_PC8) // Address Bus[24] -#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9 -#define AT91C_PC9_A25_CFRNW (AT91C_PIO_PC9) // Address Bus[25] / Compact Flash Read Not Write -#define AT91C_PIO_PD0 (1 << 0) // Pin Controlled by PD0 -#define AT91C_PD0_ETX0 (AT91C_PIO_PD0) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PD1 (1 << 1) // Pin Controlled by PD1 -#define AT91C_PD1_ETX1 (AT91C_PIO_PD1) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PD10 (1 << 10) // Pin Controlled by PD10 -#define AT91C_PD10_PCK3 (AT91C_PIO_PD10) // PMC Programmable Clock Output 3 -#define AT91C_PD10_TPS1 (AT91C_PIO_PD10) // ETM ARM9 pipeline status 1 -#define AT91C_PIO_PD11 (1 << 11) // Pin Controlled by PD11 -#define AT91C_PD11_ (AT91C_PIO_PD11) // -#define AT91C_PD11_TPS2 (AT91C_PIO_PD11) // ETM ARM9 pipeline status 2 -#define AT91C_PIO_PD12 (1 << 12) // Pin Controlled by PD12 -#define AT91C_PD12_ (AT91C_PIO_PD12) // -#define AT91C_PD12_TPK0 (AT91C_PIO_PD12) // ETM Trace Packet 0 -#define AT91C_PIO_PD13 (1 << 13) // Pin Controlled by PD13 -#define AT91C_PD13_ (AT91C_PIO_PD13) // -#define AT91C_PD13_TPK1 (AT91C_PIO_PD13) // ETM Trace Packet 1 -#define AT91C_PIO_PD14 (1 << 14) // Pin Controlled by PD14 -#define AT91C_PD14_ (AT91C_PIO_PD14) // -#define AT91C_PD14_TPK2 (AT91C_PIO_PD14) // ETM Trace Packet 2 -#define AT91C_PIO_PD15 (1 << 15) // Pin Controlled by PD15 -#define AT91C_PD15_TD0 (AT91C_PIO_PD15) // SSC Transmit data -#define AT91C_PD15_TPK3 (AT91C_PIO_PD15) // ETM Trace Packet 3 -#define AT91C_PIO_PD16 (1 << 16) // Pin Controlled by PD16 -#define AT91C_PD16_TD1 (AT91C_PIO_PD16) // SSC Transmit Data 1 -#define AT91C_PD16_TPK4 (AT91C_PIO_PD16) // ETM Trace Packet 4 -#define AT91C_PIO_PD17 (1 << 17) // Pin Controlled by PD17 -#define AT91C_PD17_TD2 (AT91C_PIO_PD17) // SSC Transmit Data 2 -#define AT91C_PD17_TPK5 (AT91C_PIO_PD17) // ETM Trace Packet 5 -#define AT91C_PIO_PD18 (1 << 18) // Pin Controlled by PD18 -#define AT91C_PD18_NPCS1 (AT91C_PIO_PD18) // SPI Peripheral Chip Select 1 -#define AT91C_PD18_TPK6 (AT91C_PIO_PD18) // ETM Trace Packet 6 -#define AT91C_PIO_PD19 (1 << 19) // Pin Controlled by PD19 -#define AT91C_PD19_NPCS2 (AT91C_PIO_PD19) // SPI Peripheral Chip Select 2 -#define AT91C_PD19_TPK7 (AT91C_PIO_PD19) // ETM Trace Packet 7 -#define AT91C_PIO_PD2 (1 << 2) // Pin Controlled by PD2 -#define AT91C_PD2_ETX2 (AT91C_PIO_PD2) // Ethernet MAC Transmit Data 2 -#define AT91C_PIO_PD20 (1 << 20) // Pin Controlled by PD20 -#define AT91C_PD20_NPCS3 (AT91C_PIO_PD20) // SPI Peripheral Chip Select 3 -#define AT91C_PD20_TPK8 (AT91C_PIO_PD20) // ETM Trace Packet 8 -#define AT91C_PIO_PD21 (1 << 21) // Pin Controlled by PD21 -#define AT91C_PD21_RTS0 (AT91C_PIO_PD21) // Usart 0 Ready To Send -#define AT91C_PD21_TPK9 (AT91C_PIO_PD21) // ETM Trace Packet 9 -#define AT91C_PIO_PD22 (1 << 22) // Pin Controlled by PD22 -#define AT91C_PD22_RTS1 (AT91C_PIO_PD22) // Usart 0 Ready To Send -#define AT91C_PD22_TPK10 (AT91C_PIO_PD22) // ETM Trace Packet 10 -#define AT91C_PIO_PD23 (1 << 23) // Pin Controlled by PD23 -#define AT91C_PD23_RTS2 (AT91C_PIO_PD23) // USART 2 Ready To Send -#define AT91C_PD23_TPK11 (AT91C_PIO_PD23) // ETM Trace Packet 11 -#define AT91C_PIO_PD24 (1 << 24) // Pin Controlled by PD24 -#define AT91C_PD24_RTS3 (AT91C_PIO_PD24) // USART 3 Ready To Send -#define AT91C_PD24_TPK12 (AT91C_PIO_PD24) // ETM Trace Packet 12 -#define AT91C_PIO_PD25 (1 << 25) // Pin Controlled by PD25 -#define AT91C_PD25_DTR1 (AT91C_PIO_PD25) // USART 1 Data Terminal ready -#define AT91C_PD25_TPK13 (AT91C_PIO_PD25) // ETM Trace Packet 13 -#define AT91C_PIO_PD26 (1 << 26) // Pin Controlled by PD26 -#define AT91C_PD26_TPK14 (AT91C_PIO_PD26) // ETM Trace Packet 14 -#define AT91C_PIO_PD27 (1 << 27) // Pin Controlled by PD27 -#define AT91C_PD27_TPK15 (AT91C_PIO_PD27) // ETM Trace Packet 15 -#define AT91C_PIO_PD3 (1 << 3) // Pin Controlled by PD3 -#define AT91C_PD3_ETX3 (AT91C_PIO_PD3) // Ethernet MAC Transmit Data 3 -#define AT91C_PIO_PD4 (1 << 4) // Pin Controlled by PD4 -#define AT91C_PD4_ETXEN (AT91C_PIO_PD4) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PD5 (1 << 5) // Pin Controlled by PD5 -#define AT91C_PD5_ETXER (AT91C_PIO_PD5) // Ethernet MAC Transmikt Coding Error -#define AT91C_PIO_PD6 (1 << 6) // Pin Controlled by PD6 -#define AT91C_PD6_DTXD (AT91C_PIO_PD6) // DBGU Debug Transmit Data -#define AT91C_PIO_PD7 (1 << 7) // Pin Controlled by PD7 -#define AT91C_PD7_PCK0 (AT91C_PIO_PD7) // PMC Programmable Clock Output 0 -#define AT91C_PD7_TSYNC (AT91C_PIO_PD7) // ETM Synchronization signal -#define AT91C_PIO_PD8 (1 << 8) // Pin Controlled by PD8 -#define AT91C_PD8_PCK1 (AT91C_PIO_PD8) // PMC Programmable Clock Output 1 -#define AT91C_PD8_TCLK (AT91C_PIO_PD8) // ETM Trace Clock signal -#define AT91C_PIO_PD9 (1 << 9) // Pin Controlled by PD9 -#define AT91C_PD9_PCK2 (AT91C_PIO_PD9) // PMC Programmable Clock 2 -#define AT91C_PD9_TPS0 (AT91C_PIO_PD9) // ETM ARM9 pipeline status 0 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C -#define AT91C_ID_PIOD ( 5) // Parallel IO Controller D -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_US2 ( 8) // USART 2 -#define AT91C_ID_US3 ( 9) // USART 3 -#define AT91C_ID_MCI (10) // Multimedia Card Interface -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TWI (12) // Two-Wire Interface -#define AT91C_ID_SPI (13) // Serial Peripheral Interface -#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0 -#define AT91C_ID_SSC1 (15) // Serial Synchronous Controller 1 -#define AT91C_ID_SSC2 (16) // Serial Synchronous Controller 2 -#define AT91C_ID_TC0 (17) // Timer Counter 0 -#define AT91C_ID_TC1 (18) // Timer Counter 1 -#define AT91C_ID_TC2 (19) // Timer Counter 2 -#define AT91C_ID_TC3 (20) // Timer Counter 3 -#define AT91C_ID_TC4 (21) // Timer Counter 4 -#define AT91C_ID_TC5 (22) // Timer Counter 5 -#define AT91C_ID_UHP (23) // USB Host port -#define AT91C_ID_EMAC (24) // Ethernet MAC -#define AT91C_ID_IRQ0 (25) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (26) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ID_IRQ2 (27) // Advanced Interrupt Controller (IRQ2) -#define AT91C_ID_IRQ3 (28) // Advanced Interrupt Controller (IRQ3) -#define AT91C_ID_IRQ4 (29) // Advanced Interrupt Controller (IRQ4) -#define AT91C_ID_IRQ5 (30) // Advanced Interrupt Controller (IRQ5) -#define AT91C_ID_IRQ6 (31) // Advanced Interrupt Controller (IRQ6) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_RTC (0xFFFFFE00) // (RTC) Base Address -#define AT91C_BASE_ST (0xFFFFFD00) // (ST) Base Address -#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PIOD (0xFFFFFA00) // (PIOD) Base Address -#define AT91C_BASE_PIOC (0xFFFFF800) // (PIOC) Base Address -#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_SSC2 (0xFFFD8100) // (PDC_SSC2) Base Address -#define AT91C_BASE_SSC2 (0xFFFD8000) // (SSC2) Base Address -#define AT91C_BASE_PDC_SSC1 (0xFFFD4100) // (PDC_SSC1) Base Address -#define AT91C_BASE_SSC1 (0xFFFD4000) // (SSC1) Base Address -#define AT91C_BASE_PDC_SSC0 (0xFFFD0100) // (PDC_SSC0) Base Address -#define AT91C_BASE_SSC0 (0xFFFD0000) // (SSC0) Base Address -#define AT91C_BASE_PDC_US3 (0xFFFCC100) // (PDC_US3) Base Address -#define AT91C_BASE_US3 (0xFFFCC000) // (US3) Base Address -#define AT91C_BASE_PDC_US2 (0xFFFC8100) // (PDC_US2) Base Address -#define AT91C_BASE_US2 (0xFFFC8000) // (US2) Base Address -#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PDC_MCI (0xFFFB4100) // (PDC_MCI) Base Address -#define AT91C_BASE_MCI (0xFFFB4000) // (MCI) Base Address -#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC5 (0xFFFA4080) // (TC5) Base Address -#define AT91C_BASE_TC4 (0xFFFA4040) // (TC4) Base Address -#define AT91C_BASE_TC3 (0xFFFA4000) // (TC3) Base Address -#define AT91C_BASE_TCB1 (0xFFFA4080) // (TCB1) Base Address -#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TCB0 (0xFFFA0000) // (TCB0) Base Address -#define AT91C_BASE_UHP (0x00300000) // (UHP) Base Address -#define AT91C_BASE_EMAC (0xFFFBC000) // (EMAC) Base Address -#define AT91C_BASE_EBI (0xFFFFFF60) // (EBI) Base Address -#define AT91C_BASE_SMC2 (0xFFFFFF70) // (SMC2) Base Address -#define AT91C_BASE_SDRC (0xFFFFFF90) // (SDRC) Base Address -#define AT91C_BASE_BFC (0xFFFFFFC0) // (BFC) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91RM9200 -// ***************************************************************************** -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte) -#define AT91C_IROM (0x00100000) // Internal ROM base address -#define AT91C_IROM_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte) - - diff --git a/target/linux/at91/image/dfboot/src/include/led.h b/target/linux/at91/image/dfboot/src/include/led.h deleted file mode 100644 index 9bebd9c3c..000000000 --- a/target/linux/at91/image/dfboot/src/include/led.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2006 - * Atmel Nordic AB - * Ulf Samuelsson - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - #ifndef __LED_H -#define __LED_H - -#ifndef __ASSEMBLY__ -extern void LED_init (void); -extern void LED_set(unsigned int led); -extern void red_LED_on(void); -extern void red_LED_off(void); -extern void green_LED_on(void); -extern void green_LED_off(void); -extern void yellow_LED_on(void); -extern void yellow_LED_off(void); -extern void LED_blink(unsigned int led); -#else - .extern LED_init - .extern LED_set - .extern LED_blink - .extern red_LED_on - .extern red_LED_off - .extern yellow_LED_on - .extern yellow_LED_off - .extern green_LED_on - .extern green_LED_off -#endif -#endif diff --git a/target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h b/target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h deleted file mode 100644 index c322b32a4..000000000 --- a/target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h +++ /dev/null @@ -1,2978 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : lib_AT91RM9200.h -//* Object : AT91RM9200 inlined functions -//* Generated : AT91 SW Application Group 11/19/2003 (17:20:51) -//* -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 02 12:29:40 2002// -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_rtc_1245d.h/1.1/Fri Jan 31 12:19:12 2003// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_spi_AT91RMxxxx.h/1.2/Fri Jan 31 12:19:31 2003// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_pmc.h/1.3/Thu Nov 14 07:40:45 2002// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:53 2002// -//* CVS Reference : /lib_mci.h/1.2/Wed Nov 20 14:18:55 2002// -//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:11 2002// -//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// -//* CVS Reference : /lib_st.h/1.4/Fri Jan 31 12:20:13 2003// -//*---------------------------------------------------------------------------- - -#ifndef lib_AT91RM9200_H -#define lib_AT91RM9200_H - -/* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} -/* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ - pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ - pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ - return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR RTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTC_InterruptEnable -//* \brief Enable RTC Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_RTC_InterruptEnable( - AT91PS_RTC pRtc, // \arg pointer to a RTC controller - unsigned int flag) // \arg RTC interrupt to be enabled -{ - pRtc->RTC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTC_InterruptDisable -//* \brief Disable RTC Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_RTC_InterruptDisable( - AT91PS_RTC pRtc, // \arg pointer to a RTC controller - unsigned int flag) // \arg RTC interrupt to be disabled -{ - pRtc->RTC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTC_GetInterruptMaskStatus -//* \brief Return RTC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_RTC_GetInterruptMaskStatus( // \return RTC Interrupt Mask Status - AT91PS_RTC pRtc) // \arg pointer to a RTC controller -{ - return pRtc->RTC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTC_IsInterruptMasked -//* \brief Test if RTC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_RTC_IsInterruptMasked( - AT91PS_RTC pRtc, // \arg pointer to a RTC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_RTC_GetInterruptMaskStatus(pRtc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_SetBaudrate ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg SSC baudrate -{ - unsigned int baud_value; - //* Define the baud rate divisor register - if (speed == 0) - baud_value = 0; - else - { - baud_value = (unsigned int) (mainClock * 10)/(2*speed); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - } - - pSSC->SSC_CMR = baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_Configure ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx) // \arg mode Register to be programmed -{ - //* Disable interrupts - pSSC->SSC_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); - - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; - - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; - - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; - - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); - - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_EnableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable receiver - pSSC->SSC_CR = AT91C_SSC_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_DisableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable receiver - pSSC->SSC_CR = AT91C_SSC_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_EnableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable transmitter - pSSC->SSC_CR = AT91C_SSC_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_DisableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable transmitter - pSSC->SSC_CR = AT91C_SSC_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_EnableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pSSC->SSC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_DisableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pSSC->SSC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SSC_ReceiveFrame ( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SSC_SendFrame( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc) // \arg pointer to a SSC controller -{ - return pSsc->SSC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_SSC_IsInterruptMasked( - AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Open -//* \brief Open a SPI Port -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgCs ( - int cs, // SPI cs number (0 to 3) - int val) // chip select register -{ - //* Write to the CSR register - *(AT91C_SPI_CSR + cs) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_EnableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pSPI->SPI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_DisableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pSPI->SPI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Reset ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Enable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Disable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgMode ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register -{ - //* Write to the MR register - pSPI->SPI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgPCS ( - AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device) // PCS of the Device -{ - //* Write to the MR register - pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_ReceiveFrame ( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_SendFrame( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Close ( - AT91PS_SPI pSPI) // \arg pointer to a SPI controller -{ - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0 ; - pSPI->SPI_CSR[1] = 0 ; - pSPI->SPI_CSR[2] = 0 ; - pSPI->SPI_CSR[3] = 0 ; - - //* Reset the SPI mode - pSPI->SPI_MR = 0 ; - - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_PutChar ( - AT91PS_SPI pSPI, - unsigned int character, - unsigned int cs_number ) -{ - unsigned int value_for_cs; - value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -static inline int AT91F_SPI_GetChar ( - const AT91PS_SPI pSPI) -{ - return((pSPI->SPI_RDR) & 0xFFFF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi) // \arg pointer to a SPI controller -{ - return pSpi->SPI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_SPI_IsInterruptMasked( - AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_TC_InterruptEnable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be enabled -{ - pTc->TC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_TC_InterruptDisable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be disabled -{ - pTc->TC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc) // \arg pointer to a TC controller -{ - return pTc->TC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_TC_IsInterruptMasked( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetProcessorClock -//* \brief Return processor clock in Hz (for AT91RM3400 and AT91RM9200) -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_GetProcessorClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLLA_CLK: // PLLA clock is selected - reg = pCKGR->CKGR_PLLAR; - pllDivider = (reg & AT91C_CKGR_DIVA); - pllMultiplier = ((reg & AT91C_CKGR_MULA) >> 16) + 1; - if (reg & AT91C_CKGR_SRCA) // Source is Main clock - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - else // Source is Slow clock - return slowClock / pllDivider * pllMultiplier / prescaler; - case AT91C_PMC_CSS_PLLB_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLBR; - pllDivider = (reg & AT91C_CKGR_DIVB); - pllMultiplier = ((reg & AT91C_CKGR_MULB) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz (just for AT91RM9200) -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return AT91F_PMC_GetProcessorClock(pPMC, pCKGR, slowClock) / - (((pPMC->PMC_MCKR & AT91C_PMC_MDIV) >> 8)+1); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int ccs, // \arg clock selection: AT91C_PMC_CSS_SLOW_CLK, AT91C_PMC_CSS_MAIN_CLK, AT91C_PMC_CSS_PLLA_CLK, AT91C_PMC_CSS_PLLB_CLK - unsigned int pres) // \arg Programmable clock prescalar AT91C_PMC_PRES_CLK, AT91C_PMC_PRES_CLK_2, ..., AT91C_PMC_PRES_CLK_64 -{ - pPMC->PMC_PCKR[pck] = ccs | pres; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -/* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ - pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ - pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ - pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ - pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ - pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ - pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ - pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ - pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ - pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ - pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_EnableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pTWI->TWI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_DisableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pTWI->TWI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller -{ - //* Disable interrupts - pTWI->TWI_IDR = (unsigned int) -1; - - //* Reset peripheral - pTWI->TWI_CR = AT91C_TWI_SWRST; - - //* Set Master mode - pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi) // \arg pointer to a TWI controller -{ - return pTwi->TWI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_TWI_IsInterruptMasked( - AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_Baudrate ( - const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate) // \arg UART baudrate -{ - unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - return baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -static inline void AT91F_US_SetBaudrate ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg UART baudrate -{ - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -static inline void AT91F_US_SetTimeguard ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard) // \arg timeguard value -{ - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -static inline void AT91F_US_EnableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUSART->US_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -static inline void AT91F_US_DisableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IER register - pUSART->US_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -static inline void AT91F_US_Configure ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode , // \arg mode Register to be programmed - unsigned int baudRate , // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed -{ - //* Disable interrupts - pUSART->US_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; - - //* Define the baud rate divisor register - AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); - - //* Write the Timeguard Register - AT91F_US_SetTimeguard(pUSART, timeguard); - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Define the USART mode - pUSART->US_MR = mode ; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -static inline void AT91F_US_EnableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -static inline void AT91F_US_EnableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -static inline void AT91F_US_ResetRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset receiver - pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -static inline void AT91F_US_ResetTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset transmitter - pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -static inline void AT91F_US_DisableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable receiver - pUSART->US_CR = AT91C_US_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -static inline void AT91F_US_DisableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable transmitter - pUSART->US_CR = AT91C_US_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -static inline void AT91F_US_Close ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0 ; - - //* Reset the USART mode - pUSART->US_MR = 0 ; - - //* Reset the Timeguard Register - pUSART->US_TTGR = 0; - - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_TxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_TXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_RxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_RXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_Error ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & - (AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE)); // Parity error -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -static inline void AT91F_US_PutChar ( - AT91PS_USART pUSART, - int character ) -{ - pUSART->US_THR = (character & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -static inline int AT91F_US_GetChar ( - const AT91PS_USART pUSART) -{ - return((pUSART->US_RHR) & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_SendFrame( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_ReceiveFrame ( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -static inline void AT91F_US_SetIrdaFilter ( - AT91PS_USART pUSART, - unsigned char value -) -{ - pUSART->US_IF = value; -} - -/* ***************************************************************************** - SOFTWARE API FOR MCI - ***************************************************************************** */ -//* Classic MCI Mode Register Configuration with PDC mode enabled and MCK = MCI Clock -#define AT91C_MCI_MR_PDCMODE (AT91C_MCI_CLKDIV |\ - AT91C_MCI_PWSDIV |\ - (AT91C_MCI_PWSDIV<<1) |\ - AT91C_MCI_PDCMODE) - -//* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer -#define AT91C_MCI_DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL) - -//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A -#define AT91C_MCI_MMC_SLOTA (AT91C_MCI_SCDSEL & 0x0) - -//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B -#define AT91C_MCI_MMC_SLOTB (AT91C_MCI_SCDSEL) - -//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A -#define AT91C_MCI_SDCARD_4BITS_SLOTA ( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS ) - -//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B -#define AT91C_MCI_SDCARD_4BITS_SLOTB (AT91C_MCI_SCDSEL | AT91C_MCI_SCDBUS) - - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Configure -//* \brief Configure the MCI -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_Configure ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int DTOR_register, // \arg Data Timeout Register to be programmed - unsigned int MR_register, // \arg Mode Register to be programmed - unsigned int SDCR_register) // \arg SDCard Register to be programmed -{ - //* Reset the MCI - pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN; - - //* Disable all the interrupts - pMCI->MCI_IDR = 0xFFFFFFFF; - - //* Set the Data Timeout Register - pMCI->MCI_DTOR = DTOR_register; - - //* Set the Mode Register - pMCI->MCI_MR = MR_register; - - //* Set the SDCard Register - pMCI->MCI_SDCR = SDCR_register; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_EnableIt -//* \brief Enable MCI IT -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_EnableIt ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pMCI->MCI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_DisableIt -//* \brief Disable MCI IT -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_DisableIt ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pMCI->MCI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Enable_Interface -//* \brief Enable the MCI Interface -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_Enable_Interface ( - AT91PS_MCI pMCI) // \arg pointer to a MCI controller -{ - //* Enable the MCI - pMCI->MCI_CR = AT91C_MCI_MCIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Disable_Interface -//* \brief Disable the MCI Interface -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_Disable_Interface ( - AT91PS_MCI pMCI) // \arg pointer to a MCI controller -{ - //* Disable the MCI - pMCI->MCI_CR = AT91C_MCI_MCIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Cfg_ModeRegister -//* \brief Configure the MCI Mode Register -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_Cfg_ModeRegister ( - AT91PS_MCI pMCI, // \arg pointer to a MCI controller - unsigned int mode_register) // \arg value to set in the mode register -{ - //* Configure the MCI MR - pMCI->MCI_MR = mode_register; -} -/* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} -/* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EnableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUDP->UDP_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_DisableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pUDP->UDP_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_SetAddress ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address) // \arg new UDP address -{ - pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EnableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg endpoints to be enabled -{ - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_DisableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg endpoints to be enabled -{ - pUDP->UDP_GLBSTATE &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_SetState ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg new UDP address -{ - pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state - AT91PS_UDP pUDP) // \arg pointer to a UDP controller -{ - return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_ResetEp ( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg Endpoints to be reset -{ - pUDP->UDP_RSTEP = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpStall( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpWrite( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value) // \arg value to be written in the DPR -{ - pUDP->UDP_FDR[endpoint] = value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_EpRead( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_FDR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpEndOfWr( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpClear( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpSet( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_EpStatus( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_CSR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status - AT91PS_UDP pUdp) // \arg pointer to a UDP controller -{ - return pUdp->UDP_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_UDP_IsInterruptMasked( - AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR ST - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_SetPeriodInterval -//* \brief Set Periodic Interval Interrupt (period in ms) -//*---------------------------------------------------------------------------- -static inline void AT91F_ST_SetPeriodInterval( - AT91PS_ST pSt, - unsigned int period) -{ - volatile int status; - pSt->ST_IDR = AT91C_ST_PITS; /* Interrupt disable Register */ - - status = pSt->ST_SR; - pSt->ST_PIMR = period << 5; /* Period Interval Mode Register == timer interval = 1ms*/ -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_EnableIt -//* \brief Enable system timer interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_ST_EnableIt( - AT91PS_ST pSt, - unsigned int flag) -{ - pSt->ST_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_DisableIt -//* \brief Disable system timer interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_ST_DisableIt( - AT91PS_ST pSt, - unsigned int flag) -{ - pSt->ST_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_GetInterruptMaskStatus -//* \brief Return ST Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ST_GetInterruptMaskStatus( // \return ST Interrupt Mask Status - AT91PS_ST pSt) // \arg pointer to a ST controller -{ - return pSt->ST_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_IsInterruptMasked -//* \brief Test if ST Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_ST_IsInterruptMasked( - AT91PS_ST pSt, // \arg pointer to a ST controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ST_GetInterruptMaskStatus(pSt) & flag); -} -//*---------------------------------------------------------------------------- -//* \fn AT91F_EBI_CfgPIO -//* \brief Configure PIO controllers to drive EBI signals -//*---------------------------------------------------------------------------- -static inline void AT91F_EBI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOC, // PIO controller base address - ((unsigned int) AT91C_PC8_A24 ) | - ((unsigned int) AT91C_PC7_A23 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA31_DTXD ) | - ((unsigned int) AT91C_PA30_DRXD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SYS_CfgPMC -//* \brief Enable Peripheral clock in PMC for SYS -//*---------------------------------------------------------------------------- -static inline void AT91F_SYS_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UHP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UHP -//*---------------------------------------------------------------------------- -static inline void AT91F_UHP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UHP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SDRC_CfgPIO -//* \brief Configure PIO controllers to drive SDRC signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SDRC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOC, // PIO controller base address - ((unsigned int) AT91C_PC20_D20 ) | - ((unsigned int) AT91C_PC21_D21 ) | - ((unsigned int) AT91C_PC30_D30 ) | - ((unsigned int) AT91C_PC22_D22 ) | - ((unsigned int) AT91C_PC31_D31 ) | - ((unsigned int) AT91C_PC23_D23 ) | - ((unsigned int) AT91C_PC16_D16 ) | - ((unsigned int) AT91C_PC24_D24 ) | - ((unsigned int) AT91C_PC17_D17 ) | - ((unsigned int) AT91C_PC25_D25 ) | - ((unsigned int) AT91C_PC18_D18 ) | - ((unsigned int) AT91C_PC26_D26 ) | - ((unsigned int) AT91C_PC19_D19 ) | - ((unsigned int) AT91C_PC27_D27 ) | - ((unsigned int) AT91C_PC28_D28 ) | - ((unsigned int) AT91C_PC29_D29 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPMC -//* \brief Enable Peripheral clock in PMC for EMAC -//*---------------------------------------------------------------------------- -static inline void AT91F_EMAC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_EMAC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPIO -//* \brief Configure PIO controllers to drive EMAC signals -//*---------------------------------------------------------------------------- -static inline void AT91F_EMAC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA14_ERXER ) | - ((unsigned int) AT91C_PA12_ERX0 ) | - ((unsigned int) AT91C_PA13_ERX1 ) | - ((unsigned int) AT91C_PA8_ETXEN ) | - ((unsigned int) AT91C_PA16_EMDIO ) | - ((unsigned int) AT91C_PA9_ETX0 ) | - ((unsigned int) AT91C_PA10_ETX1 ) | - ((unsigned int) AT91C_PA11_ECRS_ECRSDV) | - ((unsigned int) AT91C_PA15_EMDC ) | - ((unsigned int) AT91C_PA7_ETXCK_EREFCK), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RTC -//*---------------------------------------------------------------------------- -static inline void AT91F_RTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC2 -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC2_CfgPIO -//* \brief Configure PIO controllers to drive SSC2 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB12_TF2 ) | - ((unsigned int) AT91C_PB17_RF2 ) | - ((unsigned int) AT91C_PB13_TK2 ) | - ((unsigned int) AT91C_PB16_RK2 ) | - ((unsigned int) AT91C_PB14_TD2 ) | - ((unsigned int) AT91C_PB15_RD2 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC1 -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC1_CfgPIO -//* \brief Configure PIO controllers to drive SSC1 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB11_RF1 ) | - ((unsigned int) AT91C_PB10_RK1 ) | - ((unsigned int) AT91C_PB8_TD1 ) | - ((unsigned int) AT91C_PB9_RD1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC0 -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPIO -//* \brief Configure PIO controllers to drive SPI signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA3_NPCS0 ) | - ((unsigned int) AT91C_PA4_NPCS1 ) | - ((unsigned int) AT91C_PA1_MOSI ) | - ((unsigned int) AT91C_PA5_NPCS2 ) | - ((unsigned int) AT91C_PA6_NPCS3 ) | - ((unsigned int) AT91C_PA0_MISO ) | - ((unsigned int) AT91C_PA2_SPCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC5_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC5 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC5_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC5)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC4_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC4 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC4_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC4)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC3_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC3 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC3_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC3)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SMC2_CfgPIO -//* \brief Configure PIO controllers to drive SMC2 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SMC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOC, // PIO controller base address - ((unsigned int) AT91C_PC10_NCS4_CFCS) | - ((unsigned int) AT91C_PC9_A25_CFRNW) | - ((unsigned int) AT91C_PC12_NCS6_CFCE2) | - ((unsigned int) AT91C_PC11_NCS5_CFCE1), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA24_PCK1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB27_PCK0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOD_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOD -//*---------------------------------------------------------------------------- -static inline void AT91F_PIOD_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOD)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOC -//*---------------------------------------------------------------------------- -static inline void AT91F_PIOC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOB_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOB -//*---------------------------------------------------------------------------- -static inline void AT91F_PIOB_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOB)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -static inline void AT91F_PIOA_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOA)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TWI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA25_TWD ) | - ((unsigned int) AT91C_PA26_TWCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US3_CfgPMC -//* \brief Enable Peripheral clock in PMC for US3 -//*---------------------------------------------------------------------------- -static inline void AT91F_US3_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US3)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US2_CfgPMC -//* \brief Enable Peripheral clock in PMC for US2 -//*---------------------------------------------------------------------------- -static inline void AT91F_US2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US2_CfgPIO -//* \brief Configure PIO controllers to drive US2 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_US2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA23_TXD2 ) | - ((unsigned int) AT91C_PA22_RXD2 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -static inline void AT91F_US1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_US1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB21_RXD1 ) | - ((unsigned int) AT91C_PB26_RTS1 ) | - ((unsigned int) AT91C_PB25_DSR1 ) | - ((unsigned int) AT91C_PB24_CTS1 ) | - ((unsigned int) AT91C_PB19_DTR1 ) | - ((unsigned int) AT91C_PB23_DCD1 ) | - ((unsigned int) AT91C_PB20_TXD1 ) | - ((unsigned int) AT91C_PB18_RI1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -static inline void AT91F_US0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_US0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA17_TXD0 ) | - ((unsigned int) AT91C_PA21_RTS0 ) | - ((unsigned int) AT91C_PA19_SCK0 ) | - ((unsigned int) AT91C_PA20_CTS0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgPMC -//* \brief Enable Peripheral clock in PMC for MCI -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_MCI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_CfgPIO -//* \brief Configure PIO controllers to drive MCI signals -//*---------------------------------------------------------------------------- -static inline void AT91F_MCI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA28_MCCDA ) | - ((unsigned int) AT91C_PA29_MCDA0 ) | - ((unsigned int) AT91C_PA27_MCCK ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB5_MCDA3 ) | - ((unsigned int) AT91C_PB3_MCDA1 ) | - ((unsigned int) AT91C_PB4_MCDA2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_IRQ4) | - ((unsigned int) 1 << AT91C_ID_FIQ) | - ((unsigned int) 1 << AT91C_ID_IRQ5) | - ((unsigned int) 1 << AT91C_ID_IRQ6) | - ((unsigned int) 1 << AT91C_ID_IRQ0) | - ((unsigned int) 1 << AT91C_ID_IRQ1) | - ((unsigned int) 1 << AT91C_ID_IRQ2) | - ((unsigned int) 1 << AT91C_ID_IRQ3)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UDP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ST_CfgPMC -//* \brief Enable Peripheral clock in PMC for ST -//*---------------------------------------------------------------------------- -static inline void AT91F_ST_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -#endif // lib_AT91RM9200_H diff --git a/target/linux/at91/image/dfboot/src/init.c b/target/linux/at91/image/dfboot/src/init.c deleted file mode 100644 index 4088973f7..000000000 --- a/target/linux/at91/image/dfboot/src/init.c +++ /dev/null @@ -1,165 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : init.c -//* Object : Low level initialisations written in C -//* Creation : HIi 10/10/2003 -//* -//*---------------------------------------------------------------------------- -#include "config.h" -#include "AT91RM9200.h" -#include "lib_AT91RM9200.h" -#include "stdio.h" - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DataAbort -//* \brief This function reports an Abort -//*---------------------------------------------------------------------------- -static void AT91F_SpuriousHandler() -{ - puts("ISI"); - while (1); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DataAbort -//* \brief This function reports an Abort -//*---------------------------------------------------------------------------- -static void AT91F_DataAbort() -{ - puts("IDA"); - while (1); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_FetchAbort -//* \brief This function reports an Abort -//*---------------------------------------------------------------------------- -static void AT91F_FetchAbort() -{ - puts("IFA"); - while (1); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UndefHandler -//* \brief This function reports that no handler have been set for current IT -//*---------------------------------------------------------------------------- -static void AT91F_UndefHandler() -{ - puts("IUD"); - while (1); -} - - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_InitSdram -//* Object : Initialize the SDRAM -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -static void AT91F_InitSdram() -{ - int *pRegister; - - //* Configure PIOC as peripheral (D16/D31) - - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOC, // PIO controller base address - 0xFFFF0030, - 0 - ); - - //*Init SDRAM - pRegister = (int *)0xFFFFFF98; - *pRegister = 0x2188c155; - pRegister = (int *)0xFFFFFF90; - *pRegister = 0x2; - pRegister = (int *)0x20000000; - *pRegister = 0; - pRegister = (int *)0xFFFFFF90; - *pRegister = 0x4; - pRegister = (int *)0x20000000; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - pRegister = (int *)0xFFFFFF90; - *pRegister = 0x3; - pRegister = (int *)0x20000080; - *pRegister = 0; - - pRegister = (int *)0xFFFFFF94; - *pRegister = 0x2e0; - pRegister = (int *)0x20000000; - *pRegister = 0; - - pRegister = (int *)0xFFFFFF90; - *pRegister = 0x00; - pRegister = (int *)0x20000000; - *pRegister = 0; -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_InitFlash -//* \brief This function performs low level HW initialization -//*---------------------------------------------------------------------------- -static void AT91F_InitMemories() -{ - int *pEbi = (int *)0xFFFFFF60; - - //* Setup MEMC to support all connected memories (CS0 = FLASH; CS1=SDRAM) - pEbi = (int *)0xFFFFFF60; - *pEbi = 0x00000002; - - //* CS0 cs for flash - pEbi = (int *)0xFFFFFF70; - *pEbi = 0x00003284; - - AT91F_InitSdram(); -} - - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_LowLevelInit -//* \brief This function performs very low level HW initialization -//*---------------------------------------------------------------------------- -void AT91F_LowLevelInit(void) -{ - int i; - - // Init Interrupt Controller - AT91F_AIC_Open( - AT91C_BASE_AIC, // pointer to the AIC registers - AT91C_AIC_BRANCH_OPCODE, // IRQ exception vector - AT91F_UndefHandler, // FIQ exception vector - AT91F_UndefHandler, // AIC default handler - AT91F_SpuriousHandler, // AIC spurious handler - 0); // Protect mode - - // Perform 8 End Of Interrupt Command to make sýre AIC will not Lock out nIRQ - for(i=0; i<8; i++) - AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC); - - AT91F_AIC_SetExceptionVector((unsigned int *)0x0C, AT91F_FetchAbort); - AT91F_AIC_SetExceptionVector((unsigned int *)0x10, AT91F_DataAbort); - AT91F_AIC_SetExceptionVector((unsigned int *)0x4, AT91F_UndefHandler); - - //Initialize SDRAM and Flash - AT91F_InitMemories(); - -} - diff --git a/target/linux/at91/image/dfboot/src/jump.S b/target/linux/at91/image/dfboot/src/jump.S deleted file mode 100644 index cc6931156..000000000 --- a/target/linux/at91/image/dfboot/src/jump.S +++ /dev/null @@ -1,4 +0,0 @@ -.global Jump - -Jump: mov pc, r0 - diff --git a/target/linux/at91/image/dfboot/src/led.c b/target/linux/at91/image/dfboot/src/led.c deleted file mode 100644 index 40d49113c..000000000 --- a/target/linux/at91/image/dfboot/src/led.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2006 - * Atmel Nordic AB - * Ulf Samuelsson - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define GREEN_LED AT91C_PIO_PB0 -#define YELLOW_LED AT91C_PIO_PB1 -#define RED_LED AT91C_PIO_PB2 - -void LED_set(unsigned int led) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_SODR = (led ^ 0x7) & 0x7; // All 0's => Set PIO high => OFF - PIOB->PIO_CODR = led & 0x7; // All 1's => Set PIO low => ON -} - -void green_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_CODR = GREEN_LED; - PIOB->PIO_CODR = (1 << 0); -} - -void yellow_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_CODR = YELLOW_LED; - PIOB->PIO_CODR = (1 << 1); -} - -void red_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_CODR = RED_LED; - PIOB->PIO_CODR = (1 << 2); -} - -void green_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_SODR = GREEN_LED; - PIOB->PIO_SODR = (1 << 0); -} - -void yellow_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_SODR = YELLOW_LED; - PIOB->PIO_SODR = (1 << 1); -} - -void red_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; -// PIOB->PIO_SODR = RED_LED; - PIOB->PIO_SODR = (1 << 2); -} - -void LED_blink(unsigned int led) -{ - volatile int i,j; - for(i = 0; i < 5; i++) { - LED_set((1 << led)&0x7); - for(j= 0; j < 200000; j++); - LED_set(0); - for(j= 0; j < 200000; j++); - } -} - - -void LED_init (void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - AT91PS_PMC PMC = AT91C_BASE_PMC; - PMC->PMC_PCER = (1 << AT91C_ID_PIOB); // Enable PIOB clock - // Disable peripherals on LEDs - PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; - // Enable pins as outputs - PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; - // Turn all LEDs OFF - PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; -} diff --git a/target/linux/at91/image/dfboot/src/main.c b/target/linux/at91/image/dfboot/src/main.c deleted file mode 100644 index c0705dec6..000000000 --- a/target/linux/at91/image/dfboot/src/main.c +++ /dev/null @@ -1,811 +0,0 @@ -/*---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - *---------------------------------------------------------------------------- - * The software is delivered "AS IS" without warranty or condition of any - * kind, either express, implied or statutory. This includes without - * limitation any warranty or condition with respect to merchantability or - * fitness for any particular purpose, or against the infringements of - * intellectual property rights of others. - *---------------------------------------------------------------------------- - * File Name : main.c - * Object : - * Creation : HIi 10/10/2003 - * Modif : HIi 15/06/2004 : add crc32 to verify the download - * from dataflash - * : HIi 21/09/2004 : Set first PLLA to 180Mhz and MCK to - * 60Mhz to speed up dataflash boot (15Mhz) - * : MLC 12/04/2005 : Modify SetPLL() to avoid errata - * : USA 30/12/2005 : Change to page Size 1056 - * Change startaddress to C0008400 - * Change SPI Speed to ~4 Mhz - * Add retry on CRC Error - *---------------------------------------------------------------------------- - */ -#include "config.h" -#include "stdio.h" -#include "AT91RM9200.h" -#include "lib_AT91RM9200.h" -#include "com.h" -#include "main.h" -#include "dataflash.h" -#include "AT91C_MCI_Device.h" - -#define DEBUGOUT -#define XMODEM -#define MEMDISP - -#ifdef PAGESZ_1056 -#define PAGESIZE 1056 -#else -#define PAGESIZE 1024 -#endif - -#define AT91C_SDRAM_START 0x20000000 -#define AT91C_BOOT_ADDR 0x21F00000 -#define AT91C_BOOT_SIZE 128*PAGESIZE -#ifdef PAGESZ_1056 -#define AT91C_BOOT_DATAFLASH_ADDR 0xC0008400 -#else -#define AT91C_BOOT_DATAFLASH_ADDR 0xC0008000 -#endif -#define AT91C_PLLA_VALUE 0x237A3E5A // crystal= 18.432MHz - fixes BRG error at 115kbps -//#define AT91C_PLLA_VALUE 0x2026BE04 // crystal= 18.432MHz -//#define AT91C_PLLA_VALUE 0x202CBE01 // crystal= 4MHz - - - -#define DISP_LINE_LEN 16 - -// Reason for boot failure -#define IMAGE_BAD_SIZE 0 -#define IMAGE_READ_FAILURE 1 -#define IMAGE_CRC_ERROR 2 -#define IMAGE_ERROR 3 -#define SUCCESS -1 - -/* prototypes*/ -extern void AT91F_ST_ASM_HANDLER(void); -extern void Jump(unsigned int addr); - -const char *menu_dataflash[] = { -#ifdef XMODEM - "1: P DFboot\n", - "2: P U-Boot\n", -#endif - "3: P SDCard\n", -#ifdef PAGESZ_1056 - "4: R UBOOT\n", -#else - "4: R UBOOT\n", -#endif -#ifdef XMODEM - "5: P DF [addr]\n", -#endif - "6: RD DF [addr]\n", - "7: E DF\n" -}; -#ifdef XMODEM -#define MAXMENU 7 -#else -#define MAXMENU 4 -#endif - -char message[20]; -#ifdef XMODEM -volatile char XmodemComplete = 0; -#endif -unsigned int StTick = 0; - -AT91S_RomBoot const *pAT91; -#ifdef XMODEM -AT91S_SBuffer sXmBuffer; -AT91S_SvcXmodem svcXmodem; -AT91S_Pipe xmodemPipe; -#endif -AT91S_CtlTempo ctlTempo; - - -//*-------------------------------------------------------------------------------------- -//* Function Name : GetTickCount() -//* Object : Return the number of systimer tick -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -unsigned int GetTickCount(void) -{ - return StTick; -} - -#ifdef XMODEM -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91_XmodemComplete() -//* Object : Perform the remap and jump to appli in RAM -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -static void AT91_XmodemComplete(AT91S_PipeStatus status, void *pVoid) -{ - /* stop the Xmodem tempo */ - svcXmodem.tempo.Stop(&(svcXmodem.tempo)); - XmodemComplete = 1; -} - - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_XmodemProtocol(AT91S_PipeStatus status, void *pVoid) -//* Object : Xmodem dispatcher -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -static void XmodemProtocol(AT91S_PipeStatus status, void *pVoid) -{ - AT91PS_SBuffer pSBuffer = (AT91PS_SBuffer) xmodemPipe.pBuffer->pChild; - AT91PS_USART pUsart = svcXmodem.pUsart; - - if (pSBuffer->szRdBuffer == 0) { - /* Start a tempo to wait the Xmodem protocol complete */ - svcXmodem.tempo.Start(&(svcXmodem.tempo), 10, 0, AT91_XmodemComplete, pUsart); - } -} -#endif - -//*-------------------------------------------------------------------------------------- -//* Function Name : irq1_c_handler() -//* Object : C Interrupt handler for Interrutp source 1 -//* Input Parameters : none -//* Output Parameters : none -//*-------------------------------------------------------------------------------------- -void AT91F_ST_HANDLER(void) -{ - volatile unsigned int csr = *AT91C_DBGU_CSR; -#ifdef XMODEM - unsigned int error; -#endif - - if (AT91C_BASE_ST->ST_SR & 0x01) { - StTick++; - ctlTempo.CtlTempoTick(&ctlTempo); - return; - } - -#ifdef XMODEM - error = AT91F_US_Error((AT91PS_USART)AT91C_BASE_DBGU); - if (csr & error) { - /* Stop previous Xmodem transmition*/ - *(AT91C_DBGU_CR) = AT91C_US_RSTSTA; - AT91F_US_DisableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_ENDRX); - AT91F_US_EnableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_RXRDY); - - } - - else if (csr & (AT91C_US_TXRDY | AT91C_US_ENDTX | AT91C_US_TXEMPTY | - AT91C_US_RXRDY | AT91C_US_ENDRX | AT91C_US_TIMEOUT | - AT91C_US_RXBUFF)) { - if ( !(svcXmodem.eot) ) - svcXmodem.Handler(&svcXmodem, csr); - } -#endif -} - - -//*----------------------------------------------------------------------------- -//* Function Name : AT91F_DisplayMenu() -//* Object : -//* Input Parameters : -//* Return value : -//*----------------------------------------------------------------------------- -static int AT91F_DisplayMenu(void) -{ - int i, mci_present = 0; - printf("\nDF LOADER %s %s %s\n",AT91C_VERSION,__DATE__,__TIME__); - AT91F_DataflashPrintInfo(); - mci_present = AT91F_MCI_Init(); - for(i = 0; i < MAXMENU; i++) { - puts(menu_dataflash[i]); - } - return mci_present; -} - - -//*----------------------------------------------------------------------------- -//* Function Name : AsciiToHex() -//* Object : ascii to hexa conversion -//* Input Parameters : -//* Return value : -//*----------------------------------------------------------------------------- -static unsigned int AsciiToHex(char *s, unsigned int *val) -{ - int n; - - *val=0; - - if(s[0] == '0' && ((s[1] == 'x') || (s[1] == 'X'))) - s+=2; - n = 0; - while((n < 8) && (s[n] !=0)) - { - *val <<= 4; - if ( (s[n] >= '0') && (s[n] <='9')) - *val += (s[n] - '0'); - else - if ((s[n] >= 'a') && (s[n] <='f')) - *val += (s[n] - 0x57); - else - if ((s[n] >= 'A') && (s[n] <='F')) - *val += (s[n] - 0x37); - else - return 0; - n++; - } - - return 1; -} - - -#ifdef MEMDISP -//*----------------------------------------------------------------------------- -//* Function Name : AT91F_MemoryDisplay() -//* Object : Display the content of the dataflash -//* Input Parameters : -//* Return value : -//*----------------------------------------------------------------------------- -static int AT91F_MemoryDisplay(unsigned int addr, unsigned int length) -{ - unsigned long i, nbytes, linebytes; - char *cp; -// unsigned int *uip; -// unsigned short *usp; - unsigned char *ucp; - char linebuf[DISP_LINE_LEN]; - -// nbytes = length * size; - nbytes = length; - do - { -// uip = (unsigned int *)linebuf; -// usp = (unsigned short *)linebuf; - ucp = (unsigned char *)linebuf; - - printf("%08x:", addr); - linebytes = (nbytes > DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; - if((addr & 0xF0000000) == 0x20000000) { - for(i = 0; i < linebytes; i ++) { - linebuf[i] = *(char *)(addr+i); - } - } else { - read_dataflash(addr, linebytes, linebuf); - } - for (i=0; i 0x7e)) - printf("."); - else - printf("%c", *cp); - cp++; - } - printf("\n"); - nbytes -= linebytes; - } while (nbytes > 0); - return 0; -} -#endif - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_SetPLL -//* Object : Set the PLLA to 180Mhz and Master clock to 60 Mhz -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -static unsigned int AT91F_SetPLL(void) -{ - AT91_REG tmp; - AT91PS_PMC pPmc = AT91C_BASE_PMC; - AT91PS_CKGR pCkgr = AT91C_BASE_CKGR; - - pPmc->PMC_IDR = 0xFFFFFFFF; - - /* -Setup the PLL A */ - pCkgr->CKGR_PLLAR = AT91C_PLLA_VALUE; - - while (!(*AT91C_PMC_SR & AT91C_PMC_LOCKA)); - - /* - Switch Master Clock from PLLB to PLLA/3 */ - tmp = pPmc->PMC_MCKR; - /* See Atmel Errata #27 and #28 */ - if (tmp & 0x0000001C) { - tmp = (tmp & ~0x0000001C); - pPmc->PMC_MCKR = tmp; - while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)); - } - if (tmp != 0x00000202) { - pPmc->PMC_MCKR = 0x00000202; - if ((tmp & 0x00000003) != 0x00000002) - while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)); - } - - return 1; -} - - -//*-------------------------------------------------------------------------------------- -//* Function Name : AT91F_ResetRegisters -//* Object : Restore the initial state to registers -//* Input Parameters : -//* Output Parameters : -//*-------------------------------------------------------------------------------------- -static unsigned int AT91F_ResetRegisters(void) -{ - volatile int i = 0; - - /* set the PIOs in input*/ - /* This disables the UART output, so dont execute for now*/ - -#ifndef DEBUGOUT - *AT91C_PIOA_ODR = 0xFFFFFFFF; /* Disables all the output pins */ - *AT91C_PIOA_PER = 0xFFFFFFFF; /* Enables the PIO to control all the pins */ -#endif - - AT91F_AIC_DisableIt (AT91C_BASE_AIC, AT91C_ID_SYS); - /* close all peripheral clocks */ - -#ifndef DEBUGOUT - AT91C_BASE_PMC->PMC_PCDR = 0xFFFFFFFC; -#endif - /* Disable core interrupts and set supervisor mode */ - __asm__ ("msr CPSR_c, #0xDF"); //* ARM_MODE_SYS(0x1F) | I_BIT(0x80) | F_BIT(0x40) - /* Clear all the interrupts */ - *AT91C_AIC_ICCR = 0xffffffff; - - /* read the AIC_IVR and AIC_FVR */ - i = *AT91C_AIC_IVR; - i = *AT91C_AIC_FVR; - - /* write the end of interrupt control register */ - *AT91C_AIC_EOICR = 0; - - return 1; -} - - -static int AT91F_LoadBoot(void) -{ -// volatile unsigned int crc1 = 0, crc2 = 0; - volatile unsigned int SizeToDownload = 0x21400; - volatile unsigned int AddressToDownload = AT91C_BOOT_ADDR; - -#if 0 - /* Read vector 6 to extract size to load */ - if (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, 32, - (char *)AddressToDownload) != AT91C_DATAFLASH_OK) - { - printf("Bad Code Size\n"); - return IMAGE_BAD_SIZE; - } - /* calculate the size to download */ - SizeToDownload = *(int *)(AddressToDownload + AT91C_OFFSET_VECT6); -#endif - -// printf("\nLoad UBOOT from dataflash[%x] to SDRAM[%x]\n", -// AT91C_BOOT_DATAFLASH_ADDR, AT91C_BOOT_ADDR); - if (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, SizeToDownload + 8, - (char *)AddressToDownload) != AT91C_DATAFLASH_OK) - { - printf("F DF RD\n"); - return IMAGE_READ_FAILURE; - } -#if 0 - pAT91->CRC32((const unsigned char *)AT91C_BOOT_ADDR, - (unsigned int)SizeToDownload , (unsigned int *)&crc2); - crc1 = (int)(*(char *)(AddressToDownload + SizeToDownload)) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 2) << 16) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 3) << 24); - - /* Restore the value of Vector 6 */ - *(int *)(AddressToDownload + AT91C_OFFSET_VECT6) = - *(int *)(AddressToDownload + SizeToDownload + 4); - - if (crc1 != crc2) { - printf("DF CRC bad %x != %x\n",crc1,crc2); - return IMAGE_CRC_ERROR; - } -#endif - return SUCCESS; -} - -static int AT91F_StartBoot(void) -{ - int sts; - if((sts = AT91F_LoadBoot()) != SUCCESS) return sts; -// printf("\n"); -// printf("PLLA[180MHz], MCK[60Mhz] ==> Start UBOOT\n"); - if (AT91F_ResetRegisters()) - { - printf("Jump"); - Jump(AT91C_BOOT_ADDR); -// LED_blink(0); - } - return IMAGE_ERROR; -} - -#if 0 -static void AT91F_RepeatedStartBoot(void) -{ - int i; - for(i = 0; i < CRC_RETRIES; i++) { - if(AT91F_StartBoot() != IMAGE_CRC_ERROR){ -// LED_blink(1); - return; - } - } - return; -} -#endif - -#define TRUE 1 -#define FALSE 0 -#define TRX_MAGIC 0x30524448 /* "HDR0" */ -#define TRX_VERSION 1 - -struct trx_header { - unsigned int magic; - unsigned int len; - unsigned int crc32; - unsigned int flag_version; - unsigned int offsets[3]; -}; - -#define AT91C_MCI_TIMEOUT 1000000 - -extern AT91S_MciDevice MCI_Device; -extern void AT91F_MCIDeviceWaitReady(unsigned int); -extern int AT91F_MCI_ReadBlockSwab(AT91PS_MciDevice, int, unsigned int *, int); - -int Program_From_MCI(void) -{ - int i; - unsigned int Max_Read_DataBlock_Length; - int block = 0; - int buffer = AT91C_DOWNLOAD_BASE_ADDRESS; - int bufpos = AT91C_DOWNLOAD_BASE_ADDRESS; - int NbPage = 0; - struct trx_header *p; - - p = (struct trx_header *)bufpos; - - Max_Read_DataBlock_Length = MCI_Device.pMCI_DeviceFeatures->Max_Read_DataBlock_Length; - - AT91F_MCIDeviceWaitReady(AT91C_MCI_TIMEOUT); - - AT91F_MCI_ReadBlockSwab(&MCI_Device, block*Max_Read_DataBlock_Length, (unsigned int *)bufpos, Max_Read_DataBlock_Length); - - if (p->magic != TRX_MAGIC) { - printf("Inv IMG 0x%08x\n", p->magic); - return FALSE; - } - - printf("RDSD"); - AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15 | AT91C_PIO_PC8 | AT91C_PIO_PC14; - for (i=0; i<(p->len/512); i++) { - AT91F_MCI_ReadBlockSwab(&MCI_Device, block*Max_Read_DataBlock_Length, (unsigned int *)bufpos, Max_Read_DataBlock_Length); - block++; - bufpos += Max_Read_DataBlock_Length; - } - - NbPage = 0; - i = dataflash_info[0].Device.pages_number; - while(i >>= 1) - NbPage++; - i = ((p->offsets[1] - p->offsets[0])/ 512) + 1 + (NbPage << 13) + (dataflash_info[0].Device.pages_size << 17); - *(int *)(buffer + p->offsets[0] + AT91C_OFFSET_VECT6) = i; - - printf(" WDFB"); - AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15 | AT91C_PIO_PC14; - AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC8; - write_dataflash(0xc0000000, buffer + p->offsets[0], p->offsets[1] - p->offsets[0]); - printf(" WUB"); - AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15; - AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC8 | AT91C_PIO_PC14; - write_dataflash(0xc0008000, buffer + p->offsets[1], p->offsets[2] - p->offsets[1]); - printf(" WKRFS"); - AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC8 | AT91C_PIO_PC15; - AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC7 | AT91C_PIO_PC14; - write_dataflash(0xc0042000, buffer + p->offsets[2], p->len - p->offsets[2]); - AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC8 | AT91C_PIO_PC14; - AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC7 | AT91C_PIO_PC15; - return TRUE; -} - -//*---------------------------------------------------------------------------- -//* Function Name : main -//* Object : Main function -//* Input Parameters : none -//* Output Parameters : True -//*---------------------------------------------------------------------------- -int main(void) -{ -#ifdef XMODEM - AT91PS_Buffer pXmBuffer; - AT91PS_SvcComm pSvcXmodem; -#endif - AT91S_SvcTempo svcBootTempo; // Link to a AT91S_Tempo object - unsigned int ix; - volatile unsigned int AddressToDownload, SizeToDownload; - unsigned int DeviceAddress = 0; - char command = 0; -#ifdef XMODEM - volatile int i = 0; - unsigned int crc1 = 0, crc2 = 0; - volatile int device; - int NbPage; -#endif - volatile int Nb_Device = 0; - int mci_present = 0; - - pAT91 = AT91C_ROM_BOOT_ADDRESS; - - if (!AT91F_SetPLL()) - { - printf("F SetPLL"); - while(1); - } - - at91_init_uarts(); - - /* Tempo Initialisation */ - pAT91->OpenCtlTempo(&ctlTempo, (void *) &(pAT91->SYSTIMER_DESC)); - ctlTempo.CtlTempoStart((void *) &(pAT91->SYSTIMER_DESC)); - - // Attach the tempo to a tempo controler - ctlTempo.CtlTempoCreate(&ctlTempo, &svcBootTempo); -// LED_init(); -// LED_blink(2); - -#ifdef XMODEM - /* Xmodem Initialisation */ - pXmBuffer = pAT91->OpenSBuffer(&sXmBuffer); - pSvcXmodem = pAT91->OpenSvcXmodem(&svcXmodem, - (AT91PS_USART)AT91C_BASE_DBGU, &ctlTempo); - pAT91->OpenPipe(&xmodemPipe, pSvcXmodem, pXmBuffer); -#endif - - /* System Timer initialization */ - AT91F_AIC_ConfigureIt( - AT91C_BASE_AIC, // AIC base address - AT91C_ID_SYS, // System peripheral ID - AT91C_AIC_PRIOR_HIGHEST, // Max priority - AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, // Level sensitive - AT91F_ST_ASM_HANDLER - ); - /* Enable ST interrupt */ - AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS); - -#ifndef PRODTEST - /* Start tempo to start Boot in a delay of - * AT91C_DELAY_TO_BOOT sec if no key pressed */ - svcBootTempo.Start(&svcBootTempo, AT91C_DELAY_TO_BOOT, - 0, AT91F_StartBoot, NULL); -#endif - - while(1) - { - while(command == 0) - { - AddressToDownload = AT91C_DOWNLOAD_BASE_ADDRESS; - SizeToDownload = AT91C_DOWNLOAD_MAX_SIZE; - DeviceAddress = 0; - - /* try to detect Dataflash */ - if (!Nb_Device) - Nb_Device = AT91F_DataflashInit(); - - mci_present = AT91F_DisplayMenu(); - -#ifdef PRODTEST - if (mci_present) { - if (Program_From_MCI()) - AT91F_StartBoot(); - } -#endif - - message[0] = 0; - AT91F_ReadLine ("Enter: ", message); - -#ifndef PRODTEST - /* stop tempo ==> stop autoboot */ - svcBootTempo.Stop(&svcBootTempo); -#endif - - command = message[0]; - for(ix = 1; (message[ix] == ' ') && (ix < 12); ix++); // Skip some whitespace - - if(!AsciiToHex(&message[ix], &DeviceAddress) ) - DeviceAddress = 0; // Illegal DeviceAddress - - switch(command) - { -#ifdef XMODEM - case '1': - case '2': - case '5': - if(command == '1') { - DeviceAddress = 0xC0000000; -// printf("Download DataflashBoot.bin to [0x%x]\n", DeviceAddress); - } else if(command == '2') { - DeviceAddress = AT91C_BOOT_DATAFLASH_ADDR; -// printf("Download u-boot.bin to [0x%x]\n", DeviceAddress); - } else { -// printf("Download Dataflash to [0x%x]\n", DeviceAddress); - } - switch(DeviceAddress & 0xFF000000) - { - case CFG_DATAFLASH_LOGIC_ADDR_CS0: - if (dataflash_info[0].id == 0){ - printf("No DF"); - AT91F_WaitKeyPressed(); - command = 0; - } - - device = 0; - break; - - case CFG_DATAFLASH_LOGIC_ADDR_CS3: - if (dataflash_info[1].id == 0){ - printf("No DF"); - AT91F_WaitKeyPressed(); - command = 0; - } - device = 1; - break; - - default: - command = 0; - break; - } - break; -#endif - - case '3': - if (mci_present) - Program_From_MCI(); - command = 0; - break; - - case '4': - AT91F_StartBoot(); - command = 0; - break; - -#ifdef MEMDISP - case '6': - do - { - AT91F_MemoryDisplay(DeviceAddress, 256); - AT91F_ReadLine (NULL, message); - DeviceAddress += 0x100; - } - while(message[0] == '\0'); - command = 0; - break; -#endif - - case '7': - switch(DeviceAddress & 0xFF000000) - { - case CFG_DATAFLASH_LOGIC_ADDR_CS0: - break; - case CFG_DATAFLASH_LOGIC_ADDR_CS3: - break; - default: - command = 0; - break; - } - - if (command != 0) { - AT91F_ReadLine ("RDY ERA\nSure?", - message); - if(message[0] == 'Y' || message[0] == 'y') { - erase_dataflash(DeviceAddress & 0xFF000000); -// printf("Erase complete\n\n"); - } -// else -// printf("Erase aborted\n"); - } - command = 0; - - break; - - default: - command = 0; - break; - } - } -#ifdef XMODEM - for(i = 0; i <= AT91C_DOWNLOAD_MAX_SIZE; i++) - *(unsigned char *)(AddressToDownload + i) = 0; - - xmodemPipe.Read(&xmodemPipe, (char *)AddressToDownload, - SizeToDownload, XmodemProtocol, 0); - while(XmodemComplete !=1); - SizeToDownload = (unsigned int)((svcXmodem.pData) - - (unsigned int)AddressToDownload); - - /* Modification of vector 6 */ - if ((DeviceAddress == CFG_DATAFLASH_LOGIC_ADDR_CS0)) { - // Vector 6 must be compliant to the BootRom description (ref Datasheet) - NbPage = 0; - i = dataflash_info[device].Device.pages_number; - while(i >>= 1) - NbPage++; - i = (SizeToDownload / 512)+1 + (NbPage << 13) + - (dataflash_info[device].Device.pages_size << 17); //+4 to add crc32 - SizeToDownload = 512 * (i &0xFF); - } - else - { - /* Save the contents of vector 6 ==> will be restored - * at boot time (AT91F_StartBoot) */ - *(int *)(AddressToDownload + SizeToDownload + 4) = - *(int *)(AddressToDownload + AT91C_OFFSET_VECT6); - /* Modify Vector 6 to contain the size of the - * file to copy (Dataflash -> SDRAM)*/ - i = SizeToDownload; - } - - *(int *)(AddressToDownload + AT91C_OFFSET_VECT6) = i; -// printf("\nModification of Arm Vector 6 :%x\n", i); - -// printf("\nWrite %d bytes in DataFlash [0x%x]\n",SizeToDownload, DeviceAddress); - crc1 = 0; - pAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc1); - - /* Add the crc32 at the end of the code */ - *(char *)(AddressToDownload + SizeToDownload) = (char)(crc1 & 0x000000FF); - *(char *)(AddressToDownload + SizeToDownload + 1) = (char)((crc1 & 0x0000FF00) >> 8); - *(char *)(AddressToDownload + SizeToDownload + 2) = (char)((crc1 & 0x00FF0000) >> 16); - *(char *)(AddressToDownload + SizeToDownload + 3) = (char)((crc1 & 0xFF000000) >> 24); - - /* write dataflash */ - write_dataflash (DeviceAddress, AddressToDownload, (SizeToDownload + 8)); - - /* clear the buffer before read */ - for(i=0; i <= SizeToDownload; i++) - *(unsigned char *)(AddressToDownload + i) = 0; - - /* Read dataflash to check the validity of the data */ - read_dataflash (DeviceAddress, (SizeToDownload + 4), (char *)(AddressToDownload)); - - printf("VFY: "); - crc2 = 0; - - pAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc2); - crc1 = (int)(*(char *)(AddressToDownload + SizeToDownload)) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 2) << 16) + - (int)(*(char *)(AddressToDownload + SizeToDownload + 3) << 24); - - if (crc1 != crc2) - printf("ERR"); - else - printf("OK"); - - command = 0; - XmodemComplete = 0; - AT91F_WaitKeyPressed(); -#endif - } -} - diff --git a/target/linux/at91/image/dfboot/src/main.h b/target/linux/at91/image/dfboot/src/main.h deleted file mode 100644 index a8cd325ca..000000000 --- a/target/linux/at91/image/dfboot/src/main.h +++ /dev/null @@ -1,43 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : main.h -//* Object : -//* -//* 1.0 27/03/03 HIi : Creation -//* 1.01 03/05/04 HIi : AT9C_VERSION incremented to 1.01 -//* 1.02 15/06/04 HIi : AT9C_VERSION incremented to 1.02 ==> -//* Add crc32 to verify dataflash download -//* 1.03 18/04/05 MLC : AT91C_VERSION incremented to 1.03g -//* Repeat boot on CRC Failure -//* Change Page Size to 1056 -//* Reduce SPI speed to 4 Mbit -//* Change U-Boot boot address to a 1056 byte page boundary -//* 1.04 30/04/05 USA : AT91C_VERSION incremented to 1.04 -//* 1.05 07/08/06 USA : AT91C_VERSION incremented to 1.05 -//* Will only support loading Dataflashboot.bin and U-Boot -//*---------------------------------------------------------------------------- - -#ifndef main_h -#define main_h - -#include "embedded_services.h" - -#define AT91C_DOWNLOAD_BASE_ADDRESS 0x20000000 -#define AT91C_DOWNLOAD_MAX_SIZE 0x00040000 - -#define AT91C_OFFSET_VECT6 0x14 //* Offset for ARM vector 6 - -#define AT91C_VERSION "VER 1.05" - - -// Global variables and functions definition -extern unsigned int GetTickCount(void); -#endif - diff --git a/target/linux/at91/image/dfboot/src/mci_device.c b/target/linux/at91/image/dfboot/src/mci_device.c deleted file mode 100644 index cce74a3ae..000000000 --- a/target/linux/at91/image/dfboot/src/mci_device.c +++ /dev/null @@ -1,743 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : mci_device.c -//* Object : TEST DataFlash Functions -//* Creation : FB 26/11/2002 -//* -//*---------------------------------------------------------------------------- - -#include -#include "stdio.h" - -#define AT91C_MCI_TIMEOUT 1000000 /* For AT91F_MCIDeviceWaitReady */ -#define BUFFER_SIZE_MCI_DEVICE 512 -#define MASTER_CLOCK 60000000 -#define FALSE 0 -#define TRUE 1 - -//* External Functions -extern void AT91F_ASM_MCI_Handler(void); -//* Global Variables -AT91S_MciDeviceFeatures MCI_Device_Features; -AT91S_MciDeviceDesc MCI_Device_Desc; -AT91S_MciDevice MCI_Device; - -#undef ENABLE_WRITE -#undef MMC - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SendCommand -//* \brief Generic function to send a command to the MMC or SDCard -//*---------------------------------------------------------------------------- -int AT91F_MCI_SendCommand ( - AT91PS_MciDevice pMCI_Device, - unsigned int Cmd, - unsigned int Arg) -{ - unsigned int error,status; - //unsigned int tick=0; - - // Send the command - AT91C_BASE_MCI->MCI_ARGR = Arg; - AT91C_BASE_MCI->MCI_CMDR = Cmd; - - // wait for CMDRDY Status flag to read the response - do - { - status = AT91C_BASE_MCI->MCI_SR; - //tick++; - } - while( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) ); - - // Test error ==> if crc error and response R3 ==> don't check error - error = (AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR; - if(error != 0 ) - { - // if the command is SEND_OP_COND the CRC error flag is always present (cf : R3 response) - if ( (Cmd != AT91C_SDCARD_APP_OP_COND_CMD) && (Cmd != AT91C_MMC_SEND_OP_COND_CMD) ) - return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR); - else - { - if (error != AT91C_MCI_RCRCE) - return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR); - } - } - return AT91C_CMD_SEND_OK; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SDCard_SendAppCommand -//* \brief Specific function to send a specific command to the SDCard -//*---------------------------------------------------------------------------- -int AT91F_MCI_SDCard_SendAppCommand ( - AT91PS_MciDevice pMCI_Device, - unsigned int Cmd_App, - unsigned int Arg ) -{ - unsigned int status; - //unsigned int tick=0; - - // Send the CMD55 for application specific command - AT91C_BASE_MCI->MCI_ARGR = (pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address << 16 ); - AT91C_BASE_MCI->MCI_CMDR = AT91C_APP_CMD; - - // wait for CMDRDY Status flag to read the response - do - { - status = AT91C_BASE_MCI->MCI_SR; - //tick++; - } - while( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) ); - - // if an error occurs - if (((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR) != 0 ) - return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR); - - // check if it is a specific command and then send the command - if ( (Cmd_App && AT91C_SDCARD_APP_ALL_CMD) == 0) - return AT91C_CMD_SEND_ERROR; - - return( AT91F_MCI_SendCommand(pMCI_Device,Cmd_App,Arg) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetStatus -//* \brief Addressed card sends its status register -//*---------------------------------------------------------------------------- -int AT91F_MCI_GetStatus(AT91PS_MciDevice pMCI_Device,unsigned int relative_card_address) -{ - if (AT91F_MCI_SendCommand(pMCI_Device, - AT91C_SEND_STATUS_CMD, - relative_card_address <<16) == AT91C_CMD_SEND_OK) - return (AT91C_BASE_MCI->MCI_RSPR[0]); - - return AT91C_CMD_SEND_ERROR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Device_Handler -//* \brief MCI C interrupt handler -//*---------------------------------------------------------------------------- -void AT91F_MCI_Device_Handler( - AT91PS_MciDevice pMCI_Device, - unsigned int status) -{ - // If End of Tx Buffer Empty interrupt occurred - if ( status & AT91C_MCI_TXBUFE ) - { - AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_TXBUFE; - AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTDIS; - - pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE; - } // End of if AT91C_MCI_TXBUFF - - // If End of Rx Buffer Full interrupt occurred - if ( status & AT91C_MCI_RXBUFF ) - { - AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_RXBUFF; - AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTDIS; - - pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE; - } // End of if AT91C_MCI_RXBUFF - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Handler -//* \brief MCI Handler -//*---------------------------------------------------------------------------- -void AT91F_MCI_Handler(void) -{ - int status; - - status = ( AT91C_BASE_MCI->MCI_SR & AT91C_BASE_MCI->MCI_IMR ); - - AT91F_MCI_Device_Handler(&MCI_Device,status); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_ReadBlock -//* \brief Read an ENTIRE block or PARTIAL block -//*---------------------------------------------------------------------------- -int AT91F_MCI_ReadBlock( - AT91PS_MciDevice pMCI_Device, - int src, - unsigned int *dataBuffer, - int sizeToRead ) -{ - //////////////////////////////////////////////////////////////////////////////////////////// - if(pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE) - return AT91C_READ_ERROR; - - if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA) - return AT91C_READ_ERROR; - - if ( (src + sizeToRead) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity ) - return AT91C_READ_ERROR; - - // If source does not fit a begin of a block - if ( (src % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 ) - return AT91C_READ_ERROR; - - // Test if the MMC supports Partial Read Block - // ALWAYS SUPPORTED IN SD Memory Card - if( (sizeToRead < pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) - && (pMCI_Device->pMCI_DeviceFeatures->Read_Partial == 0x00) ) - return AT91C_READ_ERROR; - - if( sizeToRead > pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) - return AT91C_READ_ERROR; - //////////////////////////////////////////////////////////////////////////////////////////// - - // Init Mode Register - AT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length << 16) | AT91C_MCI_PDCMODE); - - if (sizeToRead %4) - sizeToRead = (sizeToRead /4)+1; - else - sizeToRead = sizeToRead/4; - - AT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); - AT91C_BASE_PDC_MCI->PDC_RPR = (unsigned int)dataBuffer; - AT91C_BASE_PDC_MCI->PDC_RCR = sizeToRead; - - // Send the Read single block command - if ( AT91F_MCI_SendCommand(pMCI_Device, AT91C_READ_SINGLE_BLOCK_CMD, src) != AT91C_CMD_SEND_OK ) - return AT91C_READ_ERROR; - - pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_RX_SINGLE_BLOCK; - - // Enable AT91C_MCI_RXBUFF Interrupt - AT91C_BASE_MCI->MCI_IER = AT91C_MCI_RXBUFF; - - // (PDC) Receiver Transfer Enable - AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTEN; - - return AT91C_READ_OK; -} - - -#ifdef ENABLE_WRITE -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_WriteBlock -//* \brief Write an ENTIRE block but not always PARTIAL block !!! -//*---------------------------------------------------------------------------- -int AT91F_MCI_WriteBlock( - AT91PS_MciDevice pMCI_Device, - int dest, - unsigned int *dataBuffer, - int sizeToWrite ) -{ - //////////////////////////////////////////////////////////////////////////////////////////// - if( pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE) - return AT91C_WRITE_ERROR; - - if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA) - return AT91C_WRITE_ERROR; - - if ( (dest + sizeToWrite) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity ) - return AT91C_WRITE_ERROR; - - // If source does not fit a begin of a block - if ( (dest % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 ) - return AT91C_WRITE_ERROR; - - // Test if the MMC supports Partial Write Block - if( (sizeToWrite < pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length) - && (pMCI_Device->pMCI_DeviceFeatures->Write_Partial == 0x00) ) - return AT91C_WRITE_ERROR; - - if( sizeToWrite > pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length ) - return AT91C_WRITE_ERROR; - //////////////////////////////////////////////////////////////////////////////////////////// - - // Init Mode Register - AT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length << 16) | AT91C_MCI_PDCMODE); - - if (sizeToWrite %4) - sizeToWrite = (sizeToWrite /4)+1; - else - sizeToWrite = sizeToWrite/4; - - // Init PDC for write sequence - AT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); - AT91C_BASE_PDC_MCI->PDC_TPR = (unsigned int) dataBuffer; - AT91C_BASE_PDC_MCI->PDC_TCR = sizeToWrite; - - // Send the write single block command - if ( AT91F_MCI_SendCommand(pMCI_Device, AT91C_WRITE_BLOCK_CMD, dest) != AT91C_CMD_SEND_OK) - return AT91C_WRITE_ERROR; - - pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_TX_SINGLE_BLOCK; - - // Enable AT91C_MCI_TXBUFE Interrupt - AT91C_BASE_MCI->MCI_IER = AT91C_MCI_TXBUFE; - - // Enables TX for PDC transfert requests - AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTEN; - - return AT91C_WRITE_OK; -} -#endif - -#ifdef MMC -//*------------------------------------------------------------------------------------------------------------ -//* \fn AT91F_MCI_MMC_SelectCard -//* \brief Toggles a card between the Stand_by and Transfer states or between Programming and Disconnect states -//*------------------------------------------------------------------------------------------------------------ -int AT91F_MCI_MMC_SelectCard(AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address) -{ - int status; - - //* Check if the MMC card chosen is already the selected one - status = AT91F_MCI_GetStatus(pMCI_Device,relative_card_address); - - if (status < 0) - return AT91C_CARD_SELECTED_ERROR; - - if ((status & AT91C_SR_CARD_SELECTED) == AT91C_SR_CARD_SELECTED) - return AT91C_CARD_SELECTED_OK; - - //* Search for the MMC Card to be selected, status = the Corresponding Device Number - status = 0; - while( (pMCI_Device->pMCI_DeviceFeatures[status].Relative_Card_Address != relative_card_address) - && (status < AT91C_MAX_MCI_CARDS) ) - status++; - - if (status > AT91C_MAX_MCI_CARDS) - return AT91C_CARD_SELECTED_ERROR; - - if (AT91F_MCI_SendCommand( pMCI_Device, - AT91C_SEL_DESEL_CARD_CMD, - pMCI_Device->pMCI_DeviceFeatures[status].Relative_Card_Address << 16) == AT91C_CMD_SEND_OK) - return AT91C_CARD_SELECTED_OK; - return AT91C_CARD_SELECTED_ERROR; -} -#endif - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_GetCSD -//* \brief Asks to the specified card to send its CSD -//*---------------------------------------------------------------------------- -int AT91F_MCI_GetCSD (AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address , unsigned int * response) -{ - - if(AT91F_MCI_SendCommand(pMCI_Device, - AT91C_SEND_CSD_CMD, - (relative_card_address << 16)) != AT91C_CMD_SEND_OK) - return AT91C_CMD_SEND_ERROR; - - response[0] = AT91C_BASE_MCI->MCI_RSPR[0]; - response[1] = AT91C_BASE_MCI->MCI_RSPR[1]; - response[2] = AT91C_BASE_MCI->MCI_RSPR[2]; - response[3] = AT91C_BASE_MCI->MCI_RSPR[3]; - - return AT91C_CMD_SEND_OK; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SetBlocklength -//* \brief Select a block length for all following block commands (R/W) -//*---------------------------------------------------------------------------- -int AT91F_MCI_SetBlocklength(AT91PS_MciDevice pMCI_Device,unsigned int length) -{ - return( AT91F_MCI_SendCommand(pMCI_Device, AT91C_SET_BLOCKLEN_CMD, length) ); -} - -#ifdef MMC -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_MMC_GetAllOCR -//* \brief Asks to all cards to send their operations conditions -//*---------------------------------------------------------------------------- -int AT91F_MCI_MMC_GetAllOCR (AT91PS_MciDevice pMCI_Device) -{ - unsigned int response =0x0; - - while(1) - { - response = AT91F_MCI_SendCommand(pMCI_Device, - AT91C_MMC_SEND_OP_COND_CMD, - AT91C_MMC_HOST_VOLTAGE_RANGE); - if (response != AT91C_CMD_SEND_OK) - return AT91C_INIT_ERROR; - - response = AT91C_BASE_MCI->MCI_RSPR[0]; - - if ( (response & AT91C_CARD_POWER_UP_BUSY) == AT91C_CARD_POWER_UP_BUSY) - return(response); - } -} -#endif - -#ifdef MMC -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_MMC_GetAllCID -//* \brief Asks to the MMC on the chosen slot to send its CID -//*---------------------------------------------------------------------------- -int AT91F_MCI_MMC_GetAllCID (AT91PS_MciDevice pMCI_Device, unsigned int *response) -{ - int Nb_Cards_Found=-1; - - while(1) - { - if(AT91F_MCI_SendCommand(pMCI_Device, - AT91C_MMC_ALL_SEND_CID_CMD, - AT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK) - return Nb_Cards_Found; - else - { - Nb_Cards_Found = 0; - //* Assignation of the relative address to the MMC CARD - pMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Relative_Card_Address = Nb_Cards_Found + AT91C_FIRST_RCA; - //* Set the insert flag - pMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Card_Inserted = AT91C_MMC_CARD_INSERTED; - - if (AT91F_MCI_SendCommand(pMCI_Device, - AT91C_MMC_SET_RELATIVE_ADDR_CMD, - (Nb_Cards_Found + AT91C_FIRST_RCA) << 16) != AT91C_CMD_SEND_OK) - return AT91C_CMD_SEND_ERROR; - - //* If no error during assignation address ==> Increment Nb_cards_Found - Nb_Cards_Found++ ; - } - } -} -#endif -#ifdef MMC -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_MMC_Init -//* \brief Return the MMC initialisation status -//*---------------------------------------------------------------------------- -int AT91F_MCI_MMC_Init (AT91PS_MciDevice pMCI_Device) -{ - unsigned int tab_response[4]; - unsigned int mult,blocknr; - unsigned int i,Nb_Cards_Found=0; - - //* Resets all MMC Cards in Idle state - AT91F_MCI_SendCommand(pMCI_Device, AT91C_MMC_GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT); - - if(AT91F_MCI_MMC_GetAllOCR(pMCI_Device) == AT91C_INIT_ERROR) - return AT91C_INIT_ERROR; - - Nb_Cards_Found = AT91F_MCI_MMC_GetAllCID(pMCI_Device,tab_response); - if (Nb_Cards_Found != AT91C_CMD_SEND_ERROR) - { - //* Set the Mode Register - AT91C_BASE_MCI->MCI_MR = AT91C_MCI_MR_PDCMODE; - - for(i = 0; i < Nb_Cards_Found; i++) - { - if (AT91F_MCI_GetCSD(pMCI_Device, - pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address, - tab_response) != AT91C_CMD_SEND_OK) - pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address = 0; - else - { - pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M ); - pMCI_Device->pMCI_DeviceFeatures[i].Max_Write_DataBlock_Length = 1 << ((tab_response[3] >> AT91C_CSD_WBLEN_S) & AT91C_CSD_WBLEN_M ); - pMCI_Device->pMCI_DeviceFeatures[i].Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v22_SECT_SIZE_S) & AT91C_CSD_v22_SECT_SIZE_M ); - pMCI_Device->pMCI_DeviceFeatures[i].Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M; - pMCI_Device->pMCI_DeviceFeatures[i].Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M; - - // None in MMC specification version 2.2 - pMCI_Device->pMCI_DeviceFeatures[i].Erase_Block_Enable = 0; - - pMCI_Device->pMCI_DeviceFeatures[i].Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M; - pMCI_Device->pMCI_DeviceFeatures[i].Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M; - - //// Compute Memory Capacity - // compute MULT - mult = 1 << ( ((tab_response[2] >> AT91C_CSD_C_SIZE_M_S) & AT91C_CSD_C_SIZE_M_M) + 2 ); - // compute MSB of C_SIZE - blocknr = ((tab_response[1] >> AT91C_CSD_CSIZE_H_S) & AT91C_CSD_CSIZE_H_M) << 2; - // compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR - blocknr = mult * ( ( blocknr + ( (tab_response[2] >> AT91C_CSD_CSIZE_L_S) & AT91C_CSD_CSIZE_L_M) ) + 1 ); - - pMCI_Device->pMCI_DeviceFeatures[i].Memory_Capacity = pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length * blocknr; - //// End of Compute Memory Capacity - - } // end of else - } // end of for - - return AT91C_INIT_OK; - } // end of if - - return AT91C_INIT_ERROR; -} -#endif - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SDCard_GetOCR -//* \brief Asks to all cards to send their operations conditions -//*---------------------------------------------------------------------------- -int AT91F_MCI_SDCard_GetOCR (AT91PS_MciDevice pMCI_Device) -{ - unsigned int response =0x0; - - // The RCA to be used for CMD55 in Idle state shall be the card's default RCA=0x0000. - pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = 0x0; - - while( (response & AT91C_CARD_POWER_UP_BUSY) != AT91C_CARD_POWER_UP_BUSY ) - { - response = AT91F_MCI_SDCard_SendAppCommand(pMCI_Device, - AT91C_SDCARD_APP_OP_COND_CMD, - AT91C_MMC_HOST_VOLTAGE_RANGE); - if (response != AT91C_CMD_SEND_OK) - return AT91C_INIT_ERROR; - - response = AT91C_BASE_MCI->MCI_RSPR[0]; - } - - return(AT91C_BASE_MCI->MCI_RSPR[0]); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SDCard_GetCID -//* \brief Asks to the SDCard on the chosen slot to send its CID -//*---------------------------------------------------------------------------- -int AT91F_MCI_SDCard_GetCID (AT91PS_MciDevice pMCI_Device, unsigned int *response) -{ - if(AT91F_MCI_SendCommand(pMCI_Device, - AT91C_ALL_SEND_CID_CMD, - AT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK) - return AT91C_CMD_SEND_ERROR; - - response[0] = AT91C_BASE_MCI->MCI_RSPR[0]; - response[1] = AT91C_BASE_MCI->MCI_RSPR[1]; - response[2] = AT91C_BASE_MCI->MCI_RSPR[2]; - response[3] = AT91C_BASE_MCI->MCI_RSPR[3]; - - return AT91C_CMD_SEND_OK; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SDCard_SetBusWidth -//* \brief Set bus width for SDCard -//*---------------------------------------------------------------------------- -int AT91F_MCI_SDCard_SetBusWidth(AT91PS_MciDevice pMCI_Device) -{ - volatile int ret_value; - char bus_width; - - do - { - ret_value =AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address); - } - while((ret_value > 0) && ((ret_value & AT91C_SR_READY_FOR_DATA) == 0)); - - // Select Card - AT91F_MCI_SendCommand(pMCI_Device, - AT91C_SEL_DESEL_CARD_CMD, - (pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address)<<16); - - // Set bus width for Sdcard - if(pMCI_Device->pMCI_DeviceDesc->SDCard_bus_width == AT91C_MCI_SCDBUS) - bus_width = AT91C_BUS_WIDTH_4BITS; - else bus_width = AT91C_BUS_WIDTH_1BIT; - - if (AT91F_MCI_SDCard_SendAppCommand(pMCI_Device,AT91C_SDCARD_SET_BUS_WIDTH_CMD,bus_width) != AT91C_CMD_SEND_OK) - return AT91C_CMD_SEND_ERROR; - - return AT91C_CMD_SEND_OK; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_SDCard_Init -//* \brief Return the SDCard initialisation status -//*---------------------------------------------------------------------------- -int AT91F_MCI_SDCard_Init (AT91PS_MciDevice pMCI_Device) -{ - unsigned int tab_response[4]; - unsigned int mult,blocknr; - - AT91F_MCI_SendCommand(pMCI_Device, AT91C_GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT); - - if(AT91F_MCI_SDCard_GetOCR(pMCI_Device) == AT91C_INIT_ERROR) - return AT91C_INIT_ERROR; - - if (AT91F_MCI_SDCard_GetCID(pMCI_Device,tab_response) == AT91C_CMD_SEND_OK) - { - pMCI_Device->pMCI_DeviceFeatures->Card_Inserted = AT91C_SD_CARD_INSERTED; - - if (AT91F_MCI_SendCommand(pMCI_Device, AT91C_SET_RELATIVE_ADDR_CMD, 0) == AT91C_CMD_SEND_OK) - { - pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = (AT91C_BASE_MCI->MCI_RSPR[0] >> 16); - if (AT91F_MCI_GetCSD(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address,tab_response) == AT91C_CMD_SEND_OK) - { - pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M ); - pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length = 1 << ((tab_response[3] >> AT91C_CSD_WBLEN_S) & AT91C_CSD_WBLEN_M ); - pMCI_Device->pMCI_DeviceFeatures->Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v21_SECT_SIZE_S) & AT91C_CSD_v21_SECT_SIZE_M ); - pMCI_Device->pMCI_DeviceFeatures->Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M; - pMCI_Device->pMCI_DeviceFeatures->Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M; - pMCI_Device->pMCI_DeviceFeatures->Erase_Block_Enable = (tab_response[3] >> AT91C_CSD_v21_ER_BLEN_EN_S) & AT91C_CSD_v21_ER_BLEN_EN_M; - pMCI_Device->pMCI_DeviceFeatures->Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M; - pMCI_Device->pMCI_DeviceFeatures->Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M; - - //// Compute Memory Capacity - // compute MULT - mult = 1 << ( ((tab_response[2] >> AT91C_CSD_C_SIZE_M_S) & AT91C_CSD_C_SIZE_M_M) + 2 ); - // compute MSB of C_SIZE - blocknr = ((tab_response[1] >> AT91C_CSD_CSIZE_H_S) & AT91C_CSD_CSIZE_H_M) << 2; - // compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR - blocknr = mult * ( ( blocknr + ( (tab_response[2] >> AT91C_CSD_CSIZE_L_S) & AT91C_CSD_CSIZE_L_M) ) + 1 ); - - pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity = pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length * blocknr; - //// End of Compute Memory Capacity - printf("SD-Card: %d Bytes\n\r", pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity); - - if( AT91F_MCI_SDCard_SetBusWidth(pMCI_Device) == AT91C_CMD_SEND_OK ) - { - if (AT91F_MCI_SetBlocklength(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) == AT91C_CMD_SEND_OK) - return AT91C_INIT_OK; - } - } - } - } - return AT91C_INIT_ERROR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CfgDevice -//* \brief This function is used to initialise MMC or SDCard Features -//*---------------------------------------------------------------------------- -void AT91F_CfgDevice(void) -{ - // Init Device Structure - - MCI_Device_Features.Relative_Card_Address = 0; - MCI_Device_Features.Card_Inserted = AT91C_CARD_REMOVED; - MCI_Device_Features.Max_Read_DataBlock_Length = 0; - MCI_Device_Features.Max_Write_DataBlock_Length = 0; - MCI_Device_Features.Read_Partial = 0; - MCI_Device_Features.Write_Partial = 0; - MCI_Device_Features.Erase_Block_Enable = 0; - MCI_Device_Features.Sector_Size = 0; - MCI_Device_Features.Memory_Capacity = 0; - - MCI_Device_Desc.state = AT91C_MCI_IDLE; - MCI_Device_Desc.SDCard_bus_width = AT91C_MCI_SCDBUS; - - // Init AT91S_DataFlash Global Structure, by default AT45DB choosen !!! - MCI_Device.pMCI_DeviceDesc = &MCI_Device_Desc; - MCI_Device.pMCI_DeviceFeatures = &MCI_Device_Features; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCI_Init -//* \brief Initialsise Card -//*---------------------------------------------------------------------------- -int AT91F_MCI_Init(void) -{ - -/////////////////////////////////////////////////////////////////////////////////////////// -// MCI Init : common to MMC and SDCard -/////////////////////////////////////////////////////////////////////////////////////////// - - // Set up PIO SDC_TYPE to switch on MMC/SDCard and not DataFlash Card - AT91F_PIO_CfgOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7); - AT91F_PIO_SetOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7); - - // Init MCI for MMC and SDCard interface - AT91F_MCI_CfgPIO(); - AT91F_MCI_CfgPMC(); - AT91F_PDC_Open(AT91C_BASE_PDC_MCI); - - // Disable all the interrupts - AT91C_BASE_MCI->MCI_IDR = 0xFFFFFFFF; - - // Init MCI Device Structures - AT91F_CfgDevice(); - - // Configure MCI interrupt - AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, - AT91C_ID_MCI, - AT91C_AIC_PRIOR_HIGHEST, - AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, - AT91F_ASM_MCI_Handler); - - // Enable MCI interrupt - AT91F_AIC_EnableIt(AT91C_BASE_AIC,AT91C_ID_MCI); - - // Enable Receiver - AT91F_US_EnableRx((AT91PS_USART) AT91C_BASE_DBGU); - - AT91F_MCI_Configure(AT91C_BASE_MCI, - AT91C_MCI_DTOR_1MEGA_CYCLES, - AT91C_MCI_MR_PDCMODE, // 15MHz for MCK = 60MHz (CLKDIV = 1) - AT91C_MCI_SDCARD_4BITS_SLOTA); - - if(AT91F_MCI_SDCard_Init(&MCI_Device) != AT91C_INIT_OK) - return FALSE; - else - return TRUE; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MCIDeviceWaitReady -//* \brief Wait for MCI Device ready -//*---------------------------------------------------------------------------- -void AT91F_MCIDeviceWaitReady(unsigned int timeout) -{ - volatile int status; - - do - { - status = AT91C_BASE_MCI->MCI_SR; - timeout--; - } - while( !(status & AT91C_MCI_NOTBUSY) && (timeout>0) ); -} - -unsigned int swab32(unsigned int data) -{ - unsigned int res = 0; - - res = (data & 0x000000ff) << 24 | - (data & 0x0000ff00) << 8 | - (data & 0x00ff0000) >> 8 | - (data & 0xff000000) >> 24; - - return res; -} - -//*-------------------------------------------------------------------- -//* \fn AT91F_MCI_ReadBlockSwab -//* \brief Read Block and swap byte order -//*-------------------------------------------------------------------- -int AT91F_MCI_ReadBlockSwab( - AT91PS_MciDevice pMCI_Device, - int src, - unsigned int *databuffer, - int sizeToRead) -{ - int i; - unsigned char *buf = (unsigned char *)databuffer; - - //* Read Block 1 - for(i=0;i -#include - -#ifndef NULL -#define NULL ((void *)0) -#endif - -void at91_init_uarts(void); -int puts(const char *str); -int putc(int c); -int putchar(int c); -int getc(); - -int strlen(const char *str); - -int hvfprintf(const char *fmt, va_list ap); - -int printf(const char *fmt, ...); diff --git a/target/linux/at91/image/u-boot/Makefile b/target/linux/at91/image/u-boot/Makefile deleted file mode 100644 index f53df11a9..000000000 --- a/target/linux/at91/image/u-boot/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# Copyright (C) 2006 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=u-boot -PKG_VERSION:=1.1.4 -PKG_RELEASE:=1 - -PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION) -PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 -PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot -PKG_MD5SUM:= -PKG_CAT:=bzcat - -include $(INCLUDE_DIR)/package.mk - -UBOOT_CONFIG=$(strip $(subst ",, $(CONFIG_UBOOT_TARGET))) -LAN_IP=$(strip $(CONFIG_UBOOT_IPADDR)) -LAN_SERVERIP=$(strip $(subst ",, $(CONFIG_UBOOT_SERVERIP))) - -define Build/Compile - $(MAKE) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIG)_config - export CROSS_COMPILE=$(TARGET_CROSS); \ - export LAN_IP=$(LAN_IP); \ - export LAN_SERVERIP=$(LAN_SERVERIP); \ - $(MAKE) -C $(PKG_BUILD_DIR) - mkdir -p $(PKG_BUILD_DIR)/ubclient - $(CP) ./ubclient/* $(PKG_BUILD_DIR)/ubclient - export LAN_IP=$(LAN_IP); \ - export LAN_SERVERIP=$(LAN_SERVERIP); \ - $(MAKE) -C $(PKG_BUILD_DIR)/ubclient \ - $(TARGET_CONFIGURE_OPTS) \ - CFLAGS="$(TARGET_CFLAGS) -Dtarget_$(BOARD)=1" -endef - -define Build/InstallDev - dd if=$(PKG_BUILD_DIR)/u-boot.bin of=$(PKG_BUILD_DIR)/u-boot.block bs=232k count=1 conv=sync -# $(INSTALL_DIR) $(STAGING_DIR)/ubclient/sbin -# $(INSTALL_BIN) $(PKG_BUILD_DIR)/ubclient/ubpar $(STAGING_DIR)/ubclient/sbin/ - $(CP) $(PKG_BUILD_DIR)/ubclient/ubpar ../../base-files/sbin -endef - -$(eval $(call Build/DefaultTargets)) diff --git a/target/linux/at91/image/u-boot/patches/001-lowlevel-config.patch b/target/linux/at91/image/u-boot/patches/001-lowlevel-config.patch deleted file mode 100644 index 25f92e496..000000000 --- a/target/linux/at91/image/u-boot/patches/001-lowlevel-config.patch +++ /dev/null @@ -1,91 +0,0 @@ ---- u-boot-1.1.4/cpu/arm920t/config.mk 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.klaus/cpu/arm920t/config.mk 2006-02-27 19:07:41.000000000 +0100 -@@ -30,5 +30,5 @@ - # Supply options according to compiler version - # - # ========================================================================= --PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32) - PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) ---- u-boot-1.1.4/cpu/arm920t/start.S 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.klaus/cpu/arm920t/start.S 2006-02-22 16:45:24.000000000 +0100 -@@ -237,6 +237,7 @@ - */ - - -+#ifndef CONFIG_SKIP_LOWLEVEL_INIT - cpu_init_crit: - /* - * flush v4 I/D caches -@@ -265,6 +266,7 @@ - mov lr, ip - mov pc, lr - -+#endif - - /* - ************************************************************************* ---- u-boot-1.1.4/examples/Makefile 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.klaus/examples/Makefile 2006-03-02 02:37:14.000000000 +0100 -@@ -30,7 +30,7 @@ - endif - - ifeq ($(ARCH),arm) --LOAD_ADDR = 0xc100000 -+LOAD_ADDR = 0x21000000 - endif - - ifeq ($(ARCH),mips) ---- u-boot-1.1.4/include/config.h 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.klaus/include/config.h 2006-02-27 19:04:46.000000000 +0100 -@@ -0,0 +1,2 @@ -+/* Automatically generated - do not edit */ -+#include ---- u-boot-1.1.4/include/config.mk 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.klaus/include/config.mk 2006-02-27 19:04:46.000000000 +0100 -@@ -0,0 +1,4 @@ -+ARCH = arm -+CPU = arm920t -+BOARD = at91rm9200dk -+SOC = at91rm9200 ---- u-boot-1.1.4/include/configs/at91rm9200dk.h 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.klaus/include/configs/at91rm9200dk.h 2006-02-26 22:44:17.000000000 +0100 -@@ -25,6 +25,11 @@ - #ifndef __CONFIG_H - #define __CONFIG_H - -+// Added 2 defines to skip re-init lowlevel and relocate HCG HLH -+// -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SKIP_RELOCATE_UBOOT -+ - /* ARM asynchronous clock */ - #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ - #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ -@@ -165,12 +170,12 @@ - #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ - #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - --#undef CFG_ENV_IS_IN_DATAFLASH -+#define CFG_ENV_IS_IN_DATAFLASH - - #ifdef CFG_ENV_IS_IN_DATAFLASH --#define CFG_ENV_OFFSET 0x20000 -+#define CFG_ENV_OFFSET 0x21000 - #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) --#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -+#define CFG_ENV_SIZE 0x8400 /* 0x8000 */ - #else - #define CFG_ENV_IS_IN_FLASH 1 - #ifdef CONFIG_SKIP_LOWLEVEL_INIT ---- u-boot-1.1.4/Makefile 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.klaus/Makefile 2006-03-02 02:49:23.000000000 +0100 -@@ -57,7 +57,7 @@ - CROSS_COMPILE = powerpc-linux- - endif - ifeq ($(ARCH),arm) --CROSS_COMPILE = arm-linux- -+CROSS_COMPILE = ../staging_dir/bin/arm-linux- - endif - ifeq ($(ARCH),i386) - ifeq ($(HOSTARCH),i387) diff --git a/target/linux/at91/image/u-boot/patches/002-dataflash_machine.patch b/target/linux/at91/image/u-boot/patches/002-dataflash_machine.patch deleted file mode 100644 index cf7648c52..000000000 --- a/target/linux/at91/image/u-boot/patches/002-dataflash_machine.patch +++ /dev/null @@ -1,6065 +0,0 @@ -diff -Naur u-boot-1.1.4.org/board/vlink/at45.c u-boot-1.1.4.tmp/board/vlink/at45.c ---- u-boot-1.1.4.org/board/vlink/at45.c 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/at45.c 2005-12-16 17:39:27.000000000 +0100 -@@ -0,0 +1,621 @@ -+/* Driver for ATMEL DataFlash support -+ * Author : Hamid Ikdoumi (Atmel) -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ * -+ */ -+ -+#include -+#include -+#include -+ -+#ifdef CONFIG_HAS_DATAFLASH -+#include -+ -+#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to -+the Continuous Array Read function */ -+ -+/* AC Characteristics */ -+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -+#define DATAFLASH_TCSS (0xC << 16) -+#define DATAFLASH_TCHS (0x1 << 24) -+ -+#define AT91C_TIMEOUT_WRDY 200000 -+#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ -+#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ -+ -+void AT91F_SpiInit(void) { -+ -+/*-------------------------------------------------------------------*/ -+/* SPI DataFlash Init */ -+/*-------------------------------------------------------------------*/ -+ /* Configure PIOs */ -+ AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | -+ AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; -+ AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | -+ AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; -+ /* Enable CLock */ -+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; -+ -+ /* Reset the SPI */ -+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; -+ -+ /* Configure SPI in Master Mode with No CS selected !!! */ -+ AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; -+ -+ /* Configure CS0 and CS3 */ -+ *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & -+ DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); -+ -+ *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & -+ DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); -+ -+} -+ -+void AT91F_SpiEnable(int cs) { -+ switch(cs) { -+ case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ -+ AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; -+ AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); -+ break; -+ case 3: /* Configure SPI CS3 for Serial DataFlash Card */ -+ /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ -+ AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ -+ AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ -+ /* Clear Output */ -+ AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; -+ /* Configure PCS */ -+ AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; -+ AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); -+ break; -+ } -+ -+ /* SPI_Enable */ -+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; -+} -+ -+/*----------------------------------------------------------------------------*/ -+/* \fn AT91F_SpiWrite */ -+/* \brief Set the PDC registers for a transfert */ -+/*----------------------------------------------------------------------------*/ -+unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) -+{ -+ unsigned int timeout; -+ -+ pDesc->state = BUSY; -+ -+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; -+ -+ /* Initialize the Transmit and Receive Pointer */ -+ AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; -+ AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; -+ -+ /* Intialize the Transmit and Receive Counters */ -+ AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; -+ AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; -+ -+ if ( pDesc->tx_data_size != 0 ) { -+ /* Initialize the Next Transmit and Next Receive Pointer */ -+ AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; -+ AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; -+ -+ /* Intialize the Next Transmit and Next Receive Counters */ -+ AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; -+ AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; -+ } -+ -+ /* arm simple, non interrupt dependent timer */ -+ reset_timer_masked(); -+ timeout = 0; -+ -+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; -+ while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); -+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; -+ pDesc->state = IDLE; -+ -+ if (timeout >= CFG_SPI_WRITE_TOUT){ -+ printf("Error Timeout\n\r"); -+ return DATAFLASH_ERROR; -+ } -+ -+ return DATAFLASH_OK; -+} -+ -+ -+/*----------------------------------------------------------------------*/ -+/* \fn AT91F_DataFlashSendCommand */ -+/* \brief Generic function to send a command to the dataflash */ -+/*----------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashSendCommand( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char OpCode, -+ unsigned int CmdSize, -+ unsigned int DataflashAddress) -+{ -+ unsigned int adr; -+ -+ if ( (pDataFlash->pDataFlashDesc->state) != IDLE) -+ return DATAFLASH_BUSY; -+ -+ /* process the address to obtain page address and byte address */ -+ adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); -+ -+ /* fill the command buffer */ -+ pDataFlash->pDataFlashDesc->command[0] = OpCode; -+ if (pDataFlash->pDevice->pages_number >= 16384) { -+ pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); -+ pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); -+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); -+ pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); -+ } else { -+ pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); -+ pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); -+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; -+ pDataFlash->pDataFlashDesc->command[4] = 0; -+ } -+ pDataFlash->pDataFlashDesc->command[5] = 0; -+ pDataFlash->pDataFlashDesc->command[6] = 0; -+ pDataFlash->pDataFlashDesc->command[7] = 0; -+ -+ /* Initialize the SpiData structure for the spi write fuction */ -+ pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; -+ pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; -+ pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; -+ pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; -+ -+ /* send the command and read the data */ -+ return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); -+} -+ -+ -+/*----------------------------------------------------------------------*/ -+/* \fn AT91F_DataFlashGetStatus */ -+/* \brief Read the status register of the dataflash */ -+/*----------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) -+{ -+ AT91S_DataFlashStatus status; -+ -+ /* if a transfert is in progress ==> return 0 */ -+ if( (pDesc->state) != IDLE) -+ return DATAFLASH_BUSY; -+ -+ /* first send the read status command (D7H) */ -+ pDesc->command[0] = DB_STATUS; -+ pDesc->command[1] = 0; -+ -+ pDesc->DataFlash_state = GET_STATUS; -+ pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ -+ pDesc->tx_cmd_pt = pDesc->command ; -+ pDesc->rx_cmd_pt = pDesc->command ; -+ pDesc->rx_cmd_size = 2 ; -+ pDesc->tx_cmd_size = 2 ; -+ status = AT91F_SpiWrite (pDesc); -+ -+ pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); -+ -+ return status; -+} -+ -+ -+/*----------------------------------------------------------------------*/ -+/* \fn AT91F_DataFlashWaitReady */ -+/* \brief wait for dataflash ready (bit7 of the status register == 1) */ -+/*----------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) -+{ -+ pDataFlashDesc->DataFlash_state = IDLE; -+ -+ do { -+ AT91F_DataFlashGetStatus(pDataFlashDesc); -+ timeout--; -+ } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); -+ -+ if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) -+ return DATAFLASH_ERROR; -+ -+ return DATAFLASH_OK; -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_DataFlashContinuousRead */ -+/* Object : Continuous stream Read */ -+/* Input Parameters : DataFlash Service */ -+/* : = dataflash address */ -+/* : <*dataBuffer> = data buffer pointer */ -+/* : = data buffer size */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( -+ AT91PS_DataFlash pDataFlash, -+ int src, -+ unsigned char *dataBuffer, -+ int sizeToRead ) -+{ -+ AT91S_DataFlashStatus status; -+ /* Test the size to read in the device */ -+ if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) -+ return DATAFLASH_MEMORY_OVERFLOW; -+ -+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; -+ pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; -+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; -+ pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; -+ -+ status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); -+ /* Send the command to the dataflash */ -+ return(status); -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_DataFlashPagePgmBuf */ -+/* Object : Main memory page program through buffer 1 or buffer 2 */ -+/* Input Parameters : DataFlash Service */ -+/* : <*src> = Source buffer */ -+/* : = dataflash destination address */ -+/* : = data buffer size */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char *src, -+ unsigned int dest, -+ unsigned int SizeToWrite) -+{ -+ int cmdsize; -+ pDataFlash->pDataFlashDesc->tx_data_pt = src ; -+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; -+ pDataFlash->pDataFlashDesc->rx_data_pt = src; -+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; -+ -+ cmdsize = 4; -+ /* Send the command to the dataflash */ -+ if (pDataFlash->pDevice->pages_number >= 16384) -+ cmdsize = 5; -+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_MainMemoryToBufferTransfert */ -+/* Object : Read a page in the SRAM Buffer 1 or 2 */ -+/* Input Parameters : DataFlash Service */ -+/* : Page concerned */ -+/* : */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char BufferCommand, -+ unsigned int page) -+{ -+ int cmdsize; -+ /* Test if the buffer command is legal */ -+ if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) -+ return DATAFLASH_BAD_COMMAND; -+ -+ /* no data to transmit or receive */ -+ pDataFlash->pDataFlashDesc->tx_data_size = 0; -+ cmdsize = 4; -+ if (pDataFlash->pDevice->pages_number >= 16384) -+ cmdsize = 5; -+ return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); -+} -+ -+ -+/*----------------------------------------------------------------------------- */ -+/* Function Name : AT91F_DataFlashWriteBuffer */ -+/* Object : Write data to the internal sram buffer 1 or 2 */ -+/* Input Parameters : DataFlash Service */ -+/* : = command to write buffer1 or buffer2 */ -+/* : <*dataBuffer> = data buffer to write */ -+/* : = address in the internal buffer */ -+/* : = data buffer size */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char BufferCommand, -+ unsigned char *dataBuffer, -+ unsigned int bufferAddress, -+ int SizeToWrite ) -+{ -+ int cmdsize; -+ /* Test if the buffer command is legal */ -+ if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) -+ return DATAFLASH_BAD_COMMAND; -+ -+ /* buffer address must be lower than page size */ -+ if (bufferAddress > pDataFlash->pDevice->pages_size) -+ return DATAFLASH_BAD_ADDRESS; -+ -+ if ( (pDataFlash->pDataFlashDesc->state) != IDLE) -+ return DATAFLASH_BUSY; -+ -+ /* Send first Write Command */ -+ pDataFlash->pDataFlashDesc->command[0] = BufferCommand; -+ pDataFlash->pDataFlashDesc->command[1] = 0; -+ if (pDataFlash->pDevice->pages_number >= 16384) { -+ pDataFlash->pDataFlashDesc->command[2] = 0; -+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; -+ pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; -+ cmdsize = 5; -+ } else { -+ pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; -+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; -+ pDataFlash->pDataFlashDesc->command[4] = 0; -+ cmdsize = 4; -+ } -+ -+ pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; -+ pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; -+ pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; -+ pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; -+ -+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; -+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; -+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; -+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; -+ -+ return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -+} -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_PageErase */ -+/* Object : Erase a page */ -+/* Input Parameters : DataFlash Service */ -+/* : Page concerned */ -+/* : */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_PageErase( -+ AT91PS_DataFlash pDataFlash, -+ unsigned int page) -+{ -+ int cmdsize; -+ /* Test if the buffer command is legal */ -+ /* no data to transmit or receive */ -+ pDataFlash->pDataFlashDesc->tx_data_size = 0; -+ -+ cmdsize = 4; -+ if (pDataFlash->pDevice->pages_number >= 16384) -+ cmdsize = 5; -+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_BlockErase */ -+/* Object : Erase a Block */ -+/* Input Parameters : DataFlash Service */ -+/* : Page concerned */ -+/* : */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_BlockErase( -+ AT91PS_DataFlash pDataFlash, -+ unsigned int block) -+{ -+ int cmdsize; -+ /* Test if the buffer command is legal */ -+ /* no data to transmit or receive */ -+ pDataFlash->pDataFlashDesc->tx_data_size = 0; -+ cmdsize = 4; -+ if (pDataFlash->pDevice->pages_number >= 16384) -+ cmdsize = 5; -+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); -+} -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_WriteBufferToMain */ -+/* Object : Write buffer to the main memory */ -+/* Input Parameters : DataFlash Service */ -+/* : = command to send to buffer1 or buffer2 */ -+/* : = main memory address */ -+/* Return value : State of the dataflash */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_WriteBufferToMain ( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char BufferCommand, -+ unsigned int dest ) -+{ -+ int cmdsize; -+ /* Test if the buffer command is correct */ -+ if ((BufferCommand != DB_BUF1_PAGE_PGM) && -+ (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && -+ (BufferCommand != DB_BUF2_PAGE_PGM) && -+ (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) -+ return DATAFLASH_BAD_COMMAND; -+ -+ /* no data to transmit or receive */ -+ pDataFlash->pDataFlashDesc->tx_data_size = 0; -+ -+ cmdsize = 4; -+ if (pDataFlash->pDevice->pages_number >= 16384) -+ cmdsize = 5; -+ /* Send the command to the dataflash */ -+ return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_PartialPageWrite */ -+/* Object : Erase partielly a page */ -+/* Input Parameters : = page number */ -+/* : = adr to begin the fading */ -+/* : = Number of bytes to erase */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_PartialPageWrite ( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char *src, -+ unsigned int dest, -+ unsigned int size) -+{ -+ unsigned int page; -+ unsigned int AdrInPage; -+ -+ page = dest / (pDataFlash->pDevice->pages_size); -+ AdrInPage = dest % (pDataFlash->pDevice->pages_size); -+ -+ /* Read the contents of the page in the Sram Buffer */ -+ AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ /*Update the SRAM buffer */ -+ AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); -+ -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ -+ /* Erase page if a 128 Mbits device */ -+ if (pDataFlash->pDevice->pages_number >= 16384) { -+ AT91F_PageErase(pDataFlash, page); -+ /* Rewrite the modified Sram Buffer in the main memory */ -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ } -+ -+ /* Rewrite the modified Sram Buffer in the main memory */ -+ return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_DataFlashWrite */ -+/* Object : */ -+/* Input Parameters : <*src> = Source buffer */ -+/* : = dataflash adress */ -+/* : = data buffer size */ -+/*------------------------------------------------------------------------------*/ -+AT91S_DataFlashStatus AT91F_DataFlashWrite( -+ AT91PS_DataFlash pDataFlash, -+ unsigned char *src, -+ int dest, -+ int size ) -+{ -+ unsigned int length; -+ unsigned int page; -+ unsigned int status; -+ -+ AT91F_SpiEnable(pDataFlash->pDevice->cs); -+ -+ if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) -+ return DATAFLASH_MEMORY_OVERFLOW; -+ -+ /* If destination does not fit a page start address */ -+ if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { -+ length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); -+ -+ if (size < length) -+ length = size; -+ -+ if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) -+ return DATAFLASH_ERROR; -+ -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ -+ /* Update size, source and destination pointers */ -+ size -= length; -+ dest += length; -+ src += length; -+ } -+ -+ while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { -+ /* program dataflash page */ -+ page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); -+ -+ status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ -+ status = AT91F_PageErase(pDataFlash, page); -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ if (!status) -+ return DATAFLASH_ERROR; -+ -+ status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); -+ if(!status) -+ return DATAFLASH_ERROR; -+ -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ -+ /* Update size, source and destination pointers */ -+ size -= pDataFlash->pDevice->pages_size ; -+ dest += pDataFlash->pDevice->pages_size ; -+ src += pDataFlash->pDevice->pages_size ; -+ } -+ -+ /* If still some bytes to read */ -+ if ( size > 0 ) { -+ /* program dataflash page */ -+ if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) -+ return DATAFLASH_ERROR; -+ -+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); -+ } -+ return DATAFLASH_OK; -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_DataFlashRead */ -+/* Object : Read a block in dataflash */ -+/* Input Parameters : */ -+/* Return value : */ -+/*------------------------------------------------------------------------------*/ -+int AT91F_DataFlashRead( -+ AT91PS_DataFlash pDataFlash, -+ unsigned long addr, -+ unsigned long size, -+ char *buffer) -+{ -+ unsigned long SizeToRead; -+ -+ AT91F_SpiEnable(pDataFlash->pDevice->cs); -+ -+ if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) -+ return -1; -+ -+ while (size) { -+ SizeToRead = (size < 0x8000)? size:0x8000; -+ -+ if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) -+ return -1; -+ -+ if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) -+ return -1; -+ -+ size -= SizeToRead; -+ addr += SizeToRead; -+ buffer += SizeToRead; -+ } -+ -+ return DATAFLASH_OK; -+} -+ -+ -+/*------------------------------------------------------------------------------*/ -+/* Function Name : AT91F_DataflashProbe */ -+/* Object : */ -+/* Input Parameters : */ -+/* Return value : Dataflash status register */ -+/*------------------------------------------------------------------------------*/ -+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) -+{ -+ AT91F_SpiEnable(cs); -+ AT91F_DataFlashGetStatus(pDesc); -+ return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); -+} -+ -+#endif -diff -Naur u-boot-1.1.4.org/board/vlink/config.mk u-boot-1.1.4.tmp/board/vlink/config.mk ---- u-boot-1.1.4.org/board/vlink/config.mk 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/config.mk 2005-12-16 17:39:27.000000000 +0100 -@@ -0,0 +1 @@ -+TEXT_BASE = 0x21f00000 -diff -Naur u-boot-1.1.4.org/board/vlink/flash.c u-boot-1.1.4.tmp/board/vlink/flash.c ---- u-boot-1.1.4.org/board/vlink/flash.c 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/flash.c 2006-06-05 02:44:43.000000000 +0200 -@@ -0,0 +1,504 @@ -+/* -+ * (C) Copyright 2002 -+ * Lineo, Inc. -+ * Bernhard Kuhn -+ * -+ * (C) Copyright 2002 -+ * Sysgo Real-Time Solutions, GmbH -+ * Alex Zuepke -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include -+ -+ulong myflush(void); -+ -+ -+/* Flash Organization Structure */ -+typedef struct OrgDef -+{ -+ unsigned int sector_number; -+ unsigned int sector_size; -+} OrgDef; -+ -+ -+/* Flash Organizations */ -+OrgDef OrgAT49BV16x4[] = -+{ -+ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ -+ { 2, 32*1024 }, /* 2 * 32 kBytes sectors */ -+ { 30, 64*1024 }, /* 30 * 64 kBytes sectors */ -+}; -+ -+OrgDef OrgAT49BV16x4A[] = -+{ -+ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ -+ { 31, 64*1024 }, /* 31 * 64 kBytes sectors */ -+}; -+ -+OrgDef OrgAT49BV6416[] = -+{ -+ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ -+ { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ -+}; -+ -+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -+ -+/* AT49BV1614A Codes */ -+#define FLASH_CODE1 0xAA -+#define FLASH_CODE2 0x55 -+#define ID_IN_CODE 0x90 -+#define ID_OUT_CODE 0xF0 -+ -+ -+#define CMD_READ_ARRAY 0x00F0 -+#define CMD_UNLOCK1 0x00AA -+#define CMD_UNLOCK2 0x0055 -+#define CMD_ERASE_SETUP 0x0080 -+#define CMD_ERASE_CONFIRM 0x0030 -+#define CMD_PROGRAM 0x00A0 -+#define CMD_UNLOCK_BYPASS 0x0020 -+#define CMD_SECTOR_UNLOCK 0x0070 -+ -+#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1))) -+#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1))) -+ -+#define BIT_ERASE_DONE 0x0080 -+#define BIT_RDY_MASK 0x0080 -+#define BIT_PROGRAM_ERROR 0x0020 -+#define BIT_TIMEOUT 0x80000000 /* our flag */ -+ -+#define READY 1 -+#define ERR 2 -+#define TMO 4 -+ -+/*----------------------------------------------------------------------- -+ */ -+void flash_identification (flash_info_t * info) -+{ -+ volatile u16 manuf_code, device_code, add_device_code; -+ -+ MEM_FLASH_ADDR1 = FLASH_CODE1; -+ MEM_FLASH_ADDR2 = FLASH_CODE2; -+ MEM_FLASH_ADDR1 = ID_IN_CODE; -+ -+ manuf_code = *(volatile u16 *) CFG_FLASH_BASE; -+ device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2); -+ add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1)); -+ -+ MEM_FLASH_ADDR1 = FLASH_CODE1; -+ MEM_FLASH_ADDR2 = FLASH_CODE2; -+ MEM_FLASH_ADDR1 = ID_OUT_CODE; -+ -+ /* Vendor type */ -+ info->flash_id = ATM_MANUFACT & FLASH_VENDMASK; -+ printf ("Atmel: "); -+ -+ if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) { -+ -+ if ((add_device_code & FLASH_TYPEMASK) == -+ (ATM_ID_BV1614A & FLASH_TYPEMASK)) { -+ info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK; -+ printf ("AT49BV1614A (16Mbit)\n"); -+ } else { /* AT49BV1614 Flash */ -+ info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK; -+ printf ("AT49BV1614 (16Mbit)\n"); -+ } -+ -+ } else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) { -+ info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK; -+ printf ("AT49BV6416 (64Mbit)\n"); -+ } -+} -+ -+ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks) -+{ -+ int i, nb_sectors = 0; -+ -+ for (i=0; istart[sector]); -+ -+ MEM_FLASH_ADDR1 = CMD_UNLOCK1; -+ *addr = CMD_SECTOR_UNLOCK; -+} -+ -+ -+ulong flash_init (void) -+{ -+ int i, j, k; -+ unsigned int flash_nb_blocks, sector; -+ unsigned int start_address; -+ OrgDef *pOrgDef; -+ -+ ulong size = 0; -+ -+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { -+ ulong flashbase = 0; -+ -+ flash_identification (&flash_info[i]); -+ -+ if ((flash_info[i].flash_id & FLASH_TYPEMASK) == -+ (ATM_ID_BV1614 & FLASH_TYPEMASK)) { -+ -+ pOrgDef = OrgAT49BV16x4; -+ flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef); -+ } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == -+ (ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */ -+ -+ pOrgDef = OrgAT49BV16x4A; -+ flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef); -+ } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == -+ (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ -+ -+ pOrgDef = OrgAT49BV6416; -+ flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef); -+ } else { -+ flash_nb_blocks = 0; -+ pOrgDef = OrgAT49BV16x4; -+ } -+ -+ flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks); -+ memset (flash_info[i].protect, 0, flash_info[i].sector_count); -+ -+ if (i == 0) -+ flashbase = PHYS_FLASH_1; -+ else -+ panic ("configured too many flash banks!\n"); -+ -+ sector = 0; -+ start_address = flashbase; -+ flash_info[i].size = 0; -+ -+ for (j = 0; j < flash_nb_blocks; j++) { -+ for (k = 0; k < pOrgDef[j].sector_number; k++) { -+ flash_info[i].start[sector++] = start_address; -+ start_address += pOrgDef[j].sector_size; -+ flash_info[i].size += pOrgDef[j].sector_size; -+ } -+ } -+ -+ size += flash_info[i].size; -+ -+ if ((flash_info[i].flash_id & FLASH_TYPEMASK) == -+ (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ -+ -+ /* Unlock all sectors at reset */ -+ for (j=0; jflash_id & FLASH_VENDMASK) { -+ case (ATM_MANUFACT & FLASH_VENDMASK): -+ printf ("Atmel: "); -+ break; -+ default: -+ printf ("Unknown Vendor "); -+ break; -+ } -+ -+ switch (info->flash_id & FLASH_TYPEMASK) { -+ case (ATM_ID_BV1614 & FLASH_TYPEMASK): -+ printf ("AT49BV1614 (16Mbit)\n"); -+ break; -+ case (ATM_ID_BV1614A & FLASH_TYPEMASK): -+ printf ("AT49BV1614A (16Mbit)\n"); -+ break; -+ case (ATM_ID_BV6416 & FLASH_TYPEMASK): -+ printf ("AT49BV6416 (64Mbit)\n"); -+ break; -+ default: -+ printf ("Unknown Chip Type\n"); -+ return; -+ } -+ -+ printf (" Size: %ld MB in %d Sectors\n", -+ info->size >> 20, info->sector_count); -+ -+ printf (" Sector Start Addresses:"); -+ for (i = 0; i < info->sector_count; i++) { -+ if ((i % 5) == 0) { -+ printf ("\n "); -+ } -+ printf (" %08lX%s", info->start[i], -+ info->protect[i] ? " (RO)" : " "); -+ } -+ printf ("\n"); -+} -+ -+/*----------------------------------------------------------------------- -+ */ -+ -+int flash_erase (flash_info_t * info, int s_first, int s_last) -+{ -+ ulong result; -+ int iflag, cflag, prot, sect; -+ int rc = ERR_OK; -+ int chip1; -+ -+ /* first look for protection bits */ -+ -+ if (info->flash_id == FLASH_UNKNOWN) -+ return ERR_UNKNOWN_FLASH_TYPE; -+ -+ if ((s_first < 0) || (s_first > s_last)) { -+ return ERR_INVAL; -+ } -+ -+ if ((info->flash_id & FLASH_VENDMASK) != -+ (ATM_MANUFACT & FLASH_VENDMASK)) { -+ return ERR_UNKNOWN_FLASH_VENDOR; -+ } -+ -+ prot = 0; -+ for (sect = s_first; sect <= s_last; ++sect) { -+ if (info->protect[sect]) { -+ prot++; -+ } -+ } -+ if (prot) -+ return ERR_PROTECTED; -+ -+ /* -+ * Disable interrupts which might cause a timeout -+ * here. Remember that our exception vectors are -+ * at address 0 in the flash, and we don't want a -+ * (ticker) exception to happen while the flash -+ * chip is in programming mode. -+ */ -+ cflag = icache_status (); -+ icache_disable (); -+ iflag = disable_interrupts (); -+ -+ /* Start erase on unprotected sectors */ -+ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { -+ printf ("Erasing sector %2d ... ", sect); -+ -+ /* arm simple, non interrupt dependent timer */ -+ reset_timer_masked (); -+ -+ if (info->protect[sect] == 0) { /* not protected */ -+ volatile u16 *addr = (volatile u16 *) (info->start[sect]); -+ -+ MEM_FLASH_ADDR1 = CMD_UNLOCK1; -+ MEM_FLASH_ADDR2 = CMD_UNLOCK2; -+ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; -+ -+ MEM_FLASH_ADDR1 = CMD_UNLOCK1; -+ MEM_FLASH_ADDR2 = CMD_UNLOCK2; -+ *addr = CMD_ERASE_CONFIRM; -+ -+ /* wait until flash is ready */ -+ chip1 = 0; -+ -+ do { -+ result = *addr; -+ -+ /* check timeout */ -+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { -+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; -+ chip1 = TMO; -+ break; -+ } -+ -+ if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) -+ chip1 = READY; -+ -+ } while (!chip1); -+ -+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; -+ -+ if (chip1 == ERR) { -+ rc = ERR_PROG_ERROR; -+ goto outahere; -+ } -+ if (chip1 == TMO) { -+ rc = ERR_TIMOUT; -+ goto outahere; -+ } -+ -+ printf ("ok.\n"); -+ } else { /* it was protected */ -+ printf ("protected!\n"); -+ } -+ } -+ -+ if (ctrlc ()) -+ printf ("User Interrupt!\n"); -+ -+outahere: -+ /* allow flash to settle - wait 10 ms */ -+ udelay_masked (10000); -+ -+ if (iflag) -+ enable_interrupts (); -+ -+ if (cflag) -+ icache_enable (); -+ -+ return rc; -+} -+ -+/*----------------------------------------------------------------------- -+ * Copy memory to flash -+ */ -+ -+volatile static int write_word (flash_info_t * info, ulong dest, -+ ulong data) -+{ -+ volatile u16 *addr = (volatile u16 *) dest; -+ ulong result; -+ int rc = ERR_OK; -+ int cflag, iflag; -+ int chip1; -+ -+ /* -+ * Check if Flash is (sufficiently) erased -+ */ -+ result = *addr; -+ if ((result & data) != data) -+ return ERR_NOT_ERASED; -+ -+ -+ /* -+ * Disable interrupts which might cause a timeout -+ * here. Remember that our exception vectors are -+ * at address 0 in the flash, and we don't want a -+ * (ticker) exception to happen while the flash -+ * chip is in programming mode. -+ */ -+ cflag = icache_status (); -+ icache_disable (); -+ iflag = disable_interrupts (); -+ -+ MEM_FLASH_ADDR1 = CMD_UNLOCK1; -+ MEM_FLASH_ADDR2 = CMD_UNLOCK2; -+ MEM_FLASH_ADDR1 = CMD_PROGRAM; -+ *addr = data; -+ -+ /* arm simple, non interrupt dependent timer */ -+ reset_timer_masked (); -+ -+ /* wait until flash is ready */ -+ chip1 = 0; -+ do { -+ result = *addr; -+ -+ /* check timeout */ -+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { -+ chip1 = ERR | TMO; -+ break; -+ } -+ if (!chip1 && ((result & 0x80) == (data & 0x80))) -+ chip1 = READY; -+ -+ } while (!chip1); -+ -+ *addr = CMD_READ_ARRAY; -+ -+ if (chip1 == ERR || *addr != data) -+ rc = ERR_PROG_ERROR; -+ -+ if (iflag) -+ enable_interrupts (); -+ -+ if (cflag) -+ icache_enable (); -+ -+ return rc; -+} -+ -+/*----------------------------------------------------------------------- -+ * Copy memory to flash. -+ */ -+ -+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -+{ -+ ulong wp, data; -+ int rc; -+ -+ if (addr & 1) { -+ printf ("unaligned destination not supported\n"); -+ return ERR_ALIGN; -+ }; -+ -+ if ((int) src & 1) { -+ printf ("unaligned source not supported\n"); -+ return ERR_ALIGN; -+ }; -+ -+ wp = addr; -+ -+ while (cnt >= 2) { -+ data = *((volatile u16 *) src); -+ if ((rc = write_word (info, wp, data)) != 0) { -+ return (rc); -+ } -+ src += 2; -+ wp += 2; -+ cnt -= 2; -+ } -+ -+ if (cnt == 1) { -+ data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << -+ 8); -+ if ((rc = write_word (info, wp, data)) != 0) { -+ return (rc); -+ } -+ src += 1; -+ wp += 1; -+ cnt -= 1; -+ }; -+ -+ return ERR_OK; -+} -diff -Naur u-boot-1.1.4.org/board/vlink/Makefile u-boot-1.1.4.tmp/board/vlink/Makefile ---- u-boot-1.1.4.org/board/vlink/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/Makefile 2006-06-05 02:48:33.000000000 +0200 -@@ -0,0 +1,46 @@ -+# -+# (C) Copyright 2003 -+# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -+# -+# See file CREDITS for list of people who contributed to this -+# project. -+# -+# This program is free software; you can redistribute it and/or -+# modify it under the terms of the GNU General Public License as -+# published by the Free Software Foundation; either version 2 of -+# the License, or (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+# MA 02111-1307 USA -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = lib$(BOARD).a -+ -+OBJS := vlink.o at45.o flash.o -+ -+$(LIB): $(OBJS) $(SOBJS) -+ $(AR) crv $@ $(OBJS) $(SOBJS) -+ -+clean: -+ rm -f $(SOBJS) $(OBJS) -+ -+distclean: clean -+ rm -f $(LIB) core *.bak .depend -+ -+######################################################################### -+ -+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) -+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -+ -+-include .depend -+ -+######################################################################### -diff -Naur u-boot-1.1.4.org/board/vlink/u-boot.lds u-boot-1.1.4.tmp/board/vlink/u-boot.lds ---- u-boot-1.1.4.org/board/vlink/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/u-boot.lds 2005-12-16 17:39:27.000000000 +0100 -@@ -0,0 +1,57 @@ -+/* -+ * (C) Copyright 2002 -+ * Gary Jennejohn, DENX Software Engineering, -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -+OUTPUT_ARCH(arm) -+ENTRY(_start) -+SECTIONS -+{ -+ . = 0x00000000; -+ -+ . = ALIGN(4); -+ .text : -+ { -+ cpu/arm920t/start.o (.text) -+ *(.text) -+ } -+ -+ . = ALIGN(4); -+ .rodata : { *(.rodata) } -+ -+ . = ALIGN(4); -+ .data : { *(.data) } -+ -+ . = ALIGN(4); -+ .got : { *(.got) } -+ -+ . = .; -+ __u_boot_cmd_start = .; -+ .u_boot_cmd : { *(.u_boot_cmd) } -+ __u_boot_cmd_end = .; -+ -+ . = ALIGN(4); -+ __bss_start = .; -+ .bss : { *(.bss) } -+ _end = .; -+} -diff -Naur u-boot-1.1.4.org/board/vlink/vlink.c u-boot-1.1.4.tmp/board/vlink/vlink.c ---- u-boot-1.1.4.org/board/vlink/vlink.c 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/board/vlink/vlink.c 2006-06-05 03:10:22.000000000 +0200 -@@ -0,0 +1,89 @@ -+/* -+ * (C) Copyright 2002 -+ * Sysgo Real-Time Solutions, GmbH -+ * Marius Groeger -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+/* ------------------------------------------------------------------------- */ -+/* -+ * Miscelaneous platform dependent initialisations -+ */ -+ -+int board_init (void) -+{ -+ DECLARE_GLOBAL_DATA_PTR; -+ -+ /* Enable Ctrlc */ -+ console_init_f (); -+ -+ /* Correct IRDA resistor problem */ -+ /* Set PA23_TXD in Output */ -+ (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; -+ -+ /* memory and cpu-speed are setup before relocation */ -+ /* so we do _nothing_ here */ -+ -+ /* arch number of Versalink-Board */ -+ gd->bd->bi_arch_number = MACH_TYPE_VLINK; -+ /* adress of boot parameters */ -+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -+ -+ return 0; -+} -+ -+int dram_init (void) -+{ -+ DECLARE_GLOBAL_DATA_PTR; -+ -+ gd->bd->bi_dram[0].start = PHYS_SDRAM; -+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; -+ return 0; -+} -+ -+#ifdef CONFIG_DRIVER_ETHER -+#if (CONFIG_COMMANDS & CFG_CMD_NET) -+ -+/* -+ * Name: -+ * at91rm9200_GetPhyInterface -+ * Description: -+ * Initialise the interface functions to the PHY -+ * Arguments: -+ * None -+ * Return value: -+ * None -+ */ -+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -+{ -+ p_phyops->Init = dm9161_InitPhy; -+ p_phyops->IsPhyConnected = dm9161_IsPhyConnected; -+ p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; -+ p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -+} -+ -+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ -+#endif /* CONFIG_DRIVER_ETHER */ -diff -Naur u-boot-1.1.4.org/include/asm-arm/mach-types.h u-boot-1.1.4.tmp/include/asm-arm/mach-types.h ---- u-boot-1.1.4.org/include/asm-arm/mach-types.h 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.tmp/include/asm-arm/mach-types.h 2006-06-05 01:29:25.000000000 +0200 -@@ -424,7 +424,7 @@ - #define MACH_TYPE_MPORT3S 411 - #define MACH_TYPE_RA_ALPHA 412 - #define MACH_TYPE_XCEP 413 --#define MACH_TYPE_ARCOM_MERCURY 414 -+#define MACH_TYPE_ARCOM_VULCAN 414 - #define MACH_TYPE_STARGATE 415 - #define MACH_TYPE_ARMADILLOJ 416 - #define MACH_TYPE_ELROY_JACK 417 -@@ -457,7 +457,7 @@ - #define MACH_TYPE_XM250 444 - #define MACH_TYPE_T6TC1XB 445 - #define MACH_TYPE_ESS710 446 --#define MACH_TYPE_MX3ADS 447 -+#define MACH_TYPE_MX31ADS 447 - #define MACH_TYPE_HIMALAYA 448 - #define MACH_TYPE_BOLFENK 449 - #define MACH_TYPE_AT91RM9200KR 450 -@@ -563,8 +563,8 @@ - #define MACH_TYPE_ENS_CMU 550 - #define MACH_TYPE_MM6_SDB 551 - #define MACH_TYPE_SATURN 552 --#define MACH_TYPE_ARGONPLUSEVB 553 --#define MACH_TYPE_SCMA11EVB 554 -+#define MACH_TYPE_I30030EVB 553 -+#define MACH_TYPE_MXC27530EVB 554 - #define MACH_TYPE_SMDK2800 555 - #define MACH_TYPE_MTWILSON 556 - #define MACH_TYPE_ZITI 557 -@@ -644,7 +644,7 @@ - #define MACH_TYPE_MX2JAZZ 631 - #define MACH_TYPE_MULTIIO 632 - #define MACH_TYPE_HRDISPLAY 633 --#define MACH_TYPE_SCMA11BB 634 -+#define MACH_TYPE_MXC27530ADS 634 - #define MACH_TYPE_TRIZEPS3 635 - #define MACH_TYPE_ZEFEERDZA 636 - #define MACH_TYPE_ZEFEERDZB 637 -@@ -718,7 +718,7 @@ - #define MACH_TYPE_GEM 707 - #define MACH_TYPE_I858 708 - #define MACH_TYPE_HX2750 709 --#define MACH_TYPE_ZEUSEVB 710 -+#define MACH_TYPE_MXC91131EVB 710 - #define MACH_TYPE_P700 711 - #define MACH_TYPE_CPE 712 - #define MACH_TYPE_SPITZ 713 -@@ -736,6 +736,331 @@ - #define MACH_TYPE_LN2410SBC 725 - #define MACH_TYPE_CB3RUFC 726 - #define MACH_TYPE_MP2USB 727 -+#define MACH_TYPE_NTNP425C 728 -+#define MACH_TYPE_COLIBRI 729 -+#define MACH_TYPE_PCM7220 730 -+#define MACH_TYPE_GATEWAY7001 731 -+#define MACH_TYPE_PCM027 732 -+#define MACH_TYPE_CMPXA 733 -+#define MACH_TYPE_ANUBIS 734 -+#define MACH_TYPE_ITE8152 735 -+#define MACH_TYPE_LPC3XXX 736 -+#define MACH_TYPE_PUPPETEER 737 -+#define MACH_TYPE_MACH_VADATECH 738 -+#define MACH_TYPE_E570 739 -+#define MACH_TYPE_X50 740 -+#define MACH_TYPE_RECON 741 -+#define MACH_TYPE_XBOARDGP8 742 -+#define MACH_TYPE_FPIC2 743 -+#define MACH_TYPE_AKITA 744 -+#define MACH_TYPE_A81 745 -+#define MACH_TYPE_SVM_SC25X 746 -+#define MACH_TYPE_VADATECH020 747 -+#define MACH_TYPE_TLI 748 -+#define MACH_TYPE_EDB9315LC 749 -+#define MACH_TYPE_PASSEC 750 -+#define MACH_TYPE_DS_TIGER 751 -+#define MACH_TYPE_E310 752 -+#define MACH_TYPE_E330 753 -+#define MACH_TYPE_RT3000 754 -+#define MACH_TYPE_NOKIA770 755 -+#define MACH_TYPE_PNX0106 756 -+#define MACH_TYPE_HX21XX 757 -+#define MACH_TYPE_FARADAY 758 -+#define MACH_TYPE_SBC9312 759 -+#define MACH_TYPE_BATMAN 760 -+#define MACH_TYPE_JPD201 761 -+#define MACH_TYPE_MIPSA 762 -+#define MACH_TYPE_KACOM 763 -+#define MACH_TYPE_SWARCOCPU 764 -+#define MACH_TYPE_SWARCODSL 765 -+#define MACH_TYPE_BLUEANGEL 766 -+#define MACH_TYPE_HAIRYGRAMA 767 -+#define MACH_TYPE_BANFF 768 -+#define MACH_TYPE_CARMEVA 769 -+#define MACH_TYPE_SAM255 770 -+#define MACH_TYPE_PPM10 771 -+#define MACH_TYPE_EDB9315A 772 -+#define MACH_TYPE_SUNSET 773 -+#define MACH_TYPE_STARGATE2 774 -+#define MACH_TYPE_INTELMOTE2 775 -+#define MACH_TYPE_TRIZEPS4 776 -+#define MACH_TYPE_MAINSTONE2 777 -+#define MACH_TYPE_EZ_IXP42X 778 -+#define MACH_TYPE_TAPWAVE_ZODIAC 779 -+#define MACH_TYPE_UNIVERSALMETER 780 -+#define MACH_TYPE_HICOARM9 781 -+#define MACH_TYPE_PNX4008 782 -+#define MACH_TYPE_KWS6000 783 -+#define MACH_TYPE_PORTUX920T 784 -+#define MACH_TYPE_EZ_X5 785 -+#define MACH_TYPE_OMAP_RUDOLPH 786 -+#define MACH_TYPE_CPUAT91 787 -+#define MACH_TYPE_REA9200 788 -+#define MACH_TYPE_ACTS_PUNE_SA1110 789 -+#define MACH_TYPE_IXP425 790 -+#define MACH_TYPE_I30030ADS 791 -+#define MACH_TYPE_PERCH 792 -+#define MACH_TYPE_EIS05R1 793 -+#define MACH_TYPE_PEPPERPAD 794 -+#define MACH_TYPE_SB3010 795 -+#define MACH_TYPE_RM9200 796 -+#define MACH_TYPE_DMA03 797 -+#define MACH_TYPE_ROAD_S101 798 -+#define MACH_TYPE_IQ_NEXTGEN_A 799 -+#define MACH_TYPE_IQ_NEXTGEN_B 800 -+#define MACH_TYPE_IQ_NEXTGEN_C 801 -+#define MACH_TYPE_IQ_NEXTGEN_D 802 -+#define MACH_TYPE_IQ_NEXTGEN_E 803 -+#define MACH_TYPE_MALLOW_AT91 804 -+#define MACH_TYPE_CYBERTRACKER_I 805 -+#define MACH_TYPE_GESBC931X 806 -+#define MACH_TYPE_CENTIPAD 807 -+#define MACH_TYPE_ARMSOC 808 -+#define MACH_TYPE_SE4200 809 -+#define MACH_TYPE_EMS197A 810 -+#define MACH_TYPE_MICRO9 811 -+#define MACH_TYPE_MICRO9L 812 -+#define MACH_TYPE_UC5471DSP 813 -+#define MACH_TYPE_SJ5471ENG 814 -+#define MACH_TYPE_CMPXA26X 815 -+#define MACH_TYPE_NC 816 -+#define MACH_TYPE_OMAP_PALMTE 817 -+#define MACH_TYPE_AJAX52X 818 -+#define MACH_TYPE_SIRIUSTAR 819 -+#define MACH_TYPE_IODATA_HDLG 820 -+#define MACH_TYPE_AT91RM9200UTL 821 -+#define MACH_TYPE_BIOSAFE 822 -+#define MACH_TYPE_MP1000 823 -+#define MACH_TYPE_PARSY 824 -+#define MACH_TYPE_CCXP 825 -+#define MACH_TYPE_OMAP_GSAMPLE 826 -+#define MACH_TYPE_REALVIEW_EB 827 -+#define MACH_TYPE_SAMOA 828 -+#define MACH_TYPE_T3XSCALE 829 -+#define MACH_TYPE_I878 830 -+#define MACH_TYPE_BORZOI 831 -+#define MACH_TYPE_GECKO 832 -+#define MACH_TYPE_DS101 833 -+#define MACH_TYPE_OMAP_PALMTT2 834 -+#define MACH_TYPE_XSCALE_PALMLD 835 -+#define MACH_TYPE_CC9C 836 -+#define MACH_TYPE_SBC1670 837 -+#define MACH_TYPE_IXDP28X5 838 -+#define MACH_TYPE_OMAP_PALMTT 839 -+#define MACH_TYPE_ML696K 840 -+#define MACH_TYPE_ARCOM_ZEUS 841 -+#define MACH_TYPE_OSIRIS 842 -+#define MACH_TYPE_MAESTRO 843 -+#define MACH_TYPE_TUNGE2 844 -+#define MACH_TYPE_IXBBM 845 -+#define MACH_TYPE_MX27 846 -+#define MACH_TYPE_AX8004 847 -+#define MACH_TYPE_AT91SAM9261EK 848 -+#define MACH_TYPE_LOFT 849 -+#define MACH_TYPE_MAGPIE 850 -+#define MACH_TYPE_MX21 851 -+#define MACH_TYPE_MB87M3400 852 -+#define MACH_TYPE_MGUARD_DELTA 853 -+#define MACH_TYPE_DAVINCI_DVDP 854 -+#define MACH_TYPE_HTCUNIVERSAL 855 -+#define MACH_TYPE_TPAD 856 -+#define MACH_TYPE_ROVERP3 857 -+#define MACH_TYPE_JORNADA928 858 -+#define MACH_TYPE_MV88FXX81 859 -+#define MACH_TYPE_STMP36XX 860 -+#define MACH_TYPE_SXNI79524 861 -+#define MACH_TYPE_AMS_DELTA 862 -+#define MACH_TYPE_URANIUM 863 -+#define MACH_TYPE_UCON 864 -+#define MACH_TYPE_NAS100D 865 -+#define MACH_TYPE_L083_1000 866 -+#define MACH_TYPE_EZX 867 -+#define MACH_TYPE_PNX5220 868 -+#define MACH_TYPE_BUTTE 869 -+#define MACH_TYPE_SRM2 870 -+#define MACH_TYPE_DSBR 871 -+#define MACH_TYPE_CRYSTALBALL 872 -+#define MACH_TYPE_TINYPXA27X 873 -+#define MACH_TYPE_HERBIE 874 -+#define MACH_TYPE_MAGICIAN 875 -+#define MACH_TYPE_CM4002 876 -+#define MACH_TYPE_B4 877 -+#define MACH_TYPE_MAUI 878 -+#define MACH_TYPE_CYBERTRACKER_G 879 -+#define MACH_TYPE_NXDKN 880 -+#define MACH_TYPE_MIO8390 881 -+#define MACH_TYPE_OMI_BOARD 882 -+#define MACH_TYPE_MX21CIV 883 -+#define MACH_TYPE_MAHI_CDAC 884 -+#define MACH_TYPE_XSCALE_PALMTX 885 -+#define MACH_TYPE_S3C2413 887 -+#define MACH_TYPE_SAMSYS_EP0 888 -+#define MACH_TYPE_WG302V1 889 -+#define MACH_TYPE_WG302V2 890 -+#define MACH_TYPE_EB42X 891 -+#define MACH_TYPE_IQ331ES 892 -+#define MACH_TYPE_COSYDSP 893 -+#define MACH_TYPE_UPLAT7D 894 -+#define MACH_TYPE_PTDAVINCI 895 -+#define MACH_TYPE_MBUS 896 -+#define MACH_TYPE_NADIA2VB 897 -+#define MACH_TYPE_R1000 898 -+#define MACH_TYPE_HW90250 899 -+#define MACH_TYPE_OMAP_2430SDP 900 -+#define MACH_TYPE_DAVINCI_EVM 901 -+#define MACH_TYPE_OMAP_TORNADO 902 -+#define MACH_TYPE_OLOCREEK 903 -+#define MACH_TYPE_PALMZ72 904 -+#define MACH_TYPE_NXDB500 905 -+#define MACH_TYPE_APF9328 906 -+#define MACH_TYPE_OMAP_WIPOQ 907 -+#define MACH_TYPE_OMAP_TWIP 908 -+#define MACH_TYPE_XSCALE_PALMTREO650 909 -+#define MACH_TYPE_ACUMEN 910 -+#define MACH_TYPE_XP100 911 -+#define MACH_TYPE_FS2410 912 -+#define MACH_TYPE_PXA270_CERF 913 -+#define MACH_TYPE_SQ2FTLPALM 914 -+#define MACH_TYPE_BSEMSERVER 915 -+#define MACH_TYPE_NETCLIENT 916 -+#define MACH_TYPE_XSCALE_PALMTT5 917 -+#define MACH_TYPE_OMAP_PALMTC 918 -+#define MACH_TYPE_OMAP_APOLLON 919 -+#define MACH_TYPE_MXC30030EVB 920 -+#define MACH_TYPE_REA_2D 921 -+#define MACH_TYPE_TI3E524 922 -+#define MACH_TYPE_ATEB9200 923 -+#define MACH_TYPE_AUCKLAND 924 -+#define MACH_TYPE_AK3320M 925 -+#define MACH_TYPE_DURAMAX 926 -+#define MACH_TYPE_N35 927 -+#define MACH_TYPE_PRONGHORN 928 -+#define MACH_TYPE_FUNDY 929 -+#define MACH_TYPE_LOGICPD_PXA270 930 -+#define MACH_TYPE_CPU777 931 -+#define MACH_TYPE_SIMICON9201 932 -+#define MACH_TYPE_LEAP2_HPM 933 -+#define MACH_TYPE_CM922TXA10 934 -+#define MACH_TYPE_PXA 935 -+#define MACH_TYPE_SANDGATE2 936 -+#define MACH_TYPE_SANDGATE2G 937 -+#define MACH_TYPE_SANDGATE2P 938 -+#define MACH_TYPE_FRED_JACK 939 -+#define MACH_TYPE_TTG_COLOR1 940 -+#define MACH_TYPE_NXEB500HMI 941 -+#define MACH_TYPE_NETDCU8 942 -+#define MACH_TYPE_ML675050_CPU_BOA 943 -+#define MACH_TYPE_NG_FVX538 944 -+#define MACH_TYPE_NG_FVS338 945 -+#define MACH_TYPE_PNX4103 946 -+#define MACH_TYPE_HESDB 947 -+#define MACH_TYPE_XSILO 948 -+#define MACH_TYPE_ESPRESSO 949 -+#define MACH_TYPE_EMLC 950 -+#define MACH_TYPE_SISTERON 951 -+#define MACH_TYPE_RX1950 952 -+#define MACH_TYPE_TSC_VENUS 953 -+#define MACH_TYPE_DS101J 954 -+#define MACH_TYPE_MXC30030ADS 955 -+#define MACH_TYPE_FUJITSU_WIMAXSOC 956 -+#define MACH_TYPE_DUALPCMODEM 957 -+#define MACH_TYPE_GESBC9312 958 -+#define MACH_TYPE_HTCAPACHE 959 -+#define MACH_TYPE_IXDP435 960 -+#define MACH_TYPE_CATPROVT100 961 -+#define MACH_TYPE_PICOTUX1XX 962 -+#define MACH_TYPE_PICOTUX2XX 963 -+#define MACH_TYPE_DSMG600 964 -+#define MACH_TYPE_EMPC2 965 -+#define MACH_TYPE_VENTURA 966 -+#define MACH_TYPE_PHIDGET_SBC 967 -+#define MACH_TYPE_IJ3K 968 -+#define MACH_TYPE_PISGAH 969 -+#define MACH_TYPE_OMAP_FSAMPLE 970 -+#define MACH_TYPE_SG720 971 -+#define MACH_TYPE_REDFOX 972 -+#define MACH_TYPE_MYSH_EP9315_1 973 -+#define MACH_TYPE_TPF106 974 -+#define MACH_TYPE_AT91RM9200KG 975 -+#define MACH_TYPE_SLEDB 976 -+#define MACH_TYPE_ONTRACK 977 -+#define MACH_TYPE_PM1200 978 -+#define MACH_TYPE_ESS24XXX 979 -+#define MACH_TYPE_COREMP7 980 -+#define MACH_TYPE_NEXCODER_6446 981 -+#define MACH_TYPE_STVC8380 982 -+#define MACH_TYPE_TEKLYNX 983 -+#define MACH_TYPE_CARBONADO 984 -+#define MACH_TYPE_SYSMOS_MP730 985 -+#define MACH_TYPE_SNAPPER_CL15 986 -+#define MACH_TYPE_PGIGIM 987 -+#define MACH_TYPE_PTX9160P2 988 -+#define MACH_TYPE_DCORE1 989 -+#define MACH_TYPE_VICTORPXA 990 -+#define MACH_TYPE_MX2DTB 991 -+#define MACH_TYPE_PXA_IREX_ER0100 992 -+#define MACH_TYPE_OMAP_PALMZ71 993 -+#define MACH_TYPE_BARTEC_DEG 994 -+#define MACH_TYPE_HW50251 995 -+#define MACH_TYPE_IBOX 996 -+#define MACH_TYPE_ATLASLH7A404 997 -+#define MACH_TYPE_PT2026 998 -+#define MACH_TYPE_HTCALPINE 999 -+#define MACH_TYPE_BARTEC_VTU 1000 -+#define MACH_TYPE_VCOREII 1001 -+#define MACH_TYPE_PDNB3 1002 -+#define MACH_TYPE_HTCBEETLES 1003 -+#define MACH_TYPE_S3C6400 1004 -+#define MACH_TYPE_S3C2443 1005 -+#define MACH_TYPE_OMAP_LDK 1006 -+#define MACH_TYPE_SMDK2460 1007 -+#define MACH_TYPE_SMDK2440 1008 -+#define MACH_TYPE_SMDK2412 1009 -+#define MACH_TYPE_WEBBOX 1010 -+#define MACH_TYPE_CWWNDP 1011 -+#define MACH_TYPE_DRAGON 1012 -+#define MACH_TYPE_OPENDO_CPU_BOARD 1013 -+#define MACH_TYPE_CCM2200 1014 -+#define MACH_TYPE_ETWARM 1015 -+#define MACH_TYPE_M93030 1016 -+#define MACH_TYPE_CC7U 1017 -+#define MACH_TYPE_MTT_RANGER 1018 -+#define MACH_TYPE_NEXUS 1019 -+#define MACH_TYPE_DESMAN 1020 -+#define MACH_TYPE_BKDE303 1021 -+#define MACH_TYPE_SMDK2413 1022 -+#define MACH_TYPE_AML_M7200 1023 -+#define MACH_TYPE_AML_M5900 1024 -+#define MACH_TYPE_SG640 1025 -+#define MACH_TYPE_EDG79524 1026 -+#define MACH_TYPE_AI2410 1027 -+#define MACH_TYPE_IXP465 1028 -+#define MACH_TYPE_BALLOON3 1029 -+#define MACH_TYPE_HEINS 1030 -+#define MACH_TYPE_MPLUSEVA 1031 -+#define MACH_TYPE_RT042 1032 -+#define MACH_TYPE_CWIEM 1033 -+#define MACH_TYPE_CM_X270 1034 -+#define MACH_TYPE_CM_X255 1035 -+#define MACH_TYPE_ESH_AT91 1036 -+#define MACH_TYPE_SANDGATE3 1037 -+#define MACH_TYPE_PRIMO 1038 -+#define MACH_TYPE_GEMSTONE 1039 -+#define MACH_TYPE_PRONGHORNMETRO 1040 -+#define MACH_TYPE_SIDEWINDER 1041 -+#define MACH_TYPE_PICOMOD1 1042 -+#define MACH_TYPE_SG590 1043 -+#define MACH_TYPE_AKAI9307 1044 -+#define MACH_TYPE_FONTAINE 1045 -+#define MACH_TYPE_WOMBAT 1046 -+#define MACH_TYPE_ACQ300 1047 -+#define MACH_TYPE_MOD_270 1048 -+#define MACH_TYPE_VC0820 1049 -+#define MACH_TYPE_ANI_AIM 1050 -+#define MACH_TYPE_JELLYFISH 1051 -+#define MACH_TYPE_AMANITA 1052 -+#define MACH_TYPE_VLINK 1053 - - #ifdef CONFIG_ARCH_EBSA110 - # ifdef machine_arch_type -@@ -3540,9 +3865,9 @@ - # else - # define machine_arch_type MACH_TYPE_RAMSES - # endif --# define machine_is_ramses() (machine_arch_type == MACH_TYPE_RAMSES) -+# define machine_is_mnci() (machine_arch_type == MACH_TYPE_RAMSES) - #else --# define machine_is_ramses() (0) -+# define machine_is_mnci() (0) - #endif - - #ifdef CONFIG_ARCH_S28X -@@ -4500,9 +4825,9 @@ - # else - # define machine_arch_type MACH_TYPE_M825XX - # endif --# define machine_is_m825xx() (machine_arch_type == MACH_TYPE_M825XX) -+# define machine_is_comcerto() (machine_arch_type == MACH_TYPE_M825XX) - #else --# define machine_is_m825xx() (0) -+# define machine_is_comcerto() (0) - #endif - - #ifdef CONFIG_SA1100_M7100 -@@ -5657,16 +5982,16 @@ - # define machine_is_xcep() (0) - #endif - --#ifdef CONFIG_MACH_ARCOM_MERCURY -+#ifdef CONFIG_MACH_ARCOM_VULCAN - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_ARCOM_MERCURY -+# define machine_arch_type MACH_TYPE_ARCOM_VULCAN - # endif --# define machine_is_arcom_mercury() (machine_arch_type == MACH_TYPE_ARCOM_MERCURY) -+# define machine_is_arcom_vulcan() (machine_arch_type == MACH_TYPE_ARCOM_VULCAN) - #else --# define machine_is_arcom_mercury() (0) -+# define machine_is_arcom_vulcan() (0) - #endif - - #ifdef CONFIG_MACH_STARGATE -@@ -6053,16 +6378,16 @@ - # define machine_is_ess710() (0) - #endif - --#ifdef CONFIG_MACH_MX3ADS -+#ifdef CONFIG_MACH_MX31ADS - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_MX3ADS -+# define machine_arch_type MACH_TYPE_MX31ADS - # endif --# define machine_is_mx3ads() (machine_arch_type == MACH_TYPE_MX3ADS) -+# define machine_is_mx31ads() (machine_arch_type == MACH_TYPE_MX31ADS) - #else --# define machine_is_mx3ads() (0) -+# define machine_is_mx31ads() (0) - #endif - - #ifdef CONFIG_MACH_HIMALAYA -@@ -7325,28 +7650,28 @@ - # define machine_is_saturn() (0) - #endif - --#ifdef CONFIG_MACH_ARGONPLUSEVB -+#ifdef CONFIG_MACH_I30030EVB - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_ARGONPLUSEVB -+# define machine_arch_type MACH_TYPE_I30030EVB - # endif --# define machine_is_argonplusevb() (machine_arch_type == MACH_TYPE_ARGONPLUSEVB) -+# define machine_is_i30030evb() (machine_arch_type == MACH_TYPE_I30030EVB) - #else --# define machine_is_argonplusevb() (0) -+# define machine_is_i30030evb() (0) - #endif - --#ifdef CONFIG_MACH_SCMA11EVB -+#ifdef CONFIG_MACH_MXC27530EVB - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_SCMA11EVB -+# define machine_arch_type MACH_TYPE_MXC27530EVB - # endif --# define machine_is_scma11evb() (machine_arch_type == MACH_TYPE_SCMA11EVB) -+# define machine_is_mxc27530evb() (machine_arch_type == MACH_TYPE_MXC27530EVB) - #else --# define machine_is_scma11evb() (0) -+# define machine_is_mxc27530evb() (0) - #endif - - #ifdef CONFIG_MACH_SMDK2800 -@@ -8297,16 +8622,16 @@ - # define machine_is_hrdisplay() (0) - #endif - --#ifdef CONFIG_MACH_SCMA11BB -+#ifdef CONFIG_MACH_MXC27530ADS - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_SCMA11BB -+# define machine_arch_type MACH_TYPE_MXC27530ADS - # endif --# define machine_is_scma11bb() (machine_arch_type == MACH_TYPE_SCMA11BB) -+# define machine_is_mxc27530ads() (machine_arch_type == MACH_TYPE_MXC27530ADS) - #else --# define machine_is_scma11bb() (0) -+# define machine_is_mxc27530ads() (0) - #endif - - #ifdef CONFIG_MACH_TRIZEPS3 -@@ -9185,16 +9510,16 @@ - # define machine_is_hx2750() (0) - #endif - --#ifdef CONFIG_MACH_ZEUSEVB -+#ifdef CONFIG_MACH_MXC91131EVB - # ifdef machine_arch_type - # undef machine_arch_type - # define machine_arch_type __machine_arch_type - # else --# define machine_arch_type MACH_TYPE_ZEUSEVB -+# define machine_arch_type MACH_TYPE_MXC91131EVB - # endif --# define machine_is_zeusevb() (machine_arch_type == MACH_TYPE_ZEUSEVB) -+# define machine_is_mxc91131evb() (machine_arch_type == MACH_TYPE_MXC91131EVB) - #else --# define machine_is_zeusevb() (0) -+# define machine_is_mxc91131evb() (0) - #endif - - #ifdef CONFIG_MACH_P700 -@@ -9401,6 +9726,3906 @@ - # define machine_is_mp2usb() (0) - #endif - -+#ifdef CONFIG_MACH_NTNP425C -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NTNP425C -+# endif -+# define machine_is_ntnp425c() (machine_arch_type == MACH_TYPE_NTNP425C) -+#else -+# define machine_is_ntnp425c() (0) -+#endif -+ -+#ifdef CONFIG_MACH_COLIBRI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_COLIBRI -+# endif -+# define machine_is_colibri() (machine_arch_type == MACH_TYPE_COLIBRI) -+#else -+# define machine_is_colibri() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PCM7220 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PCM7220 -+# endif -+# define machine_is_pcm7220() (machine_arch_type == MACH_TYPE_PCM7220) -+#else -+# define machine_is_pcm7220() (0) -+#endif -+ -+#ifdef CONFIG_MACH_GATEWAY7001 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_GATEWAY7001 -+# endif -+# define machine_is_gateway7001() (machine_arch_type == MACH_TYPE_GATEWAY7001) -+#else -+# define machine_is_gateway7001() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PCM027 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PCM027 -+# endif -+# define machine_is_pcm027() (machine_arch_type == MACH_TYPE_PCM027) -+#else -+# define machine_is_pcm027() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CMPXA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CMPXA -+# endif -+# define machine_is_cmpxa() (machine_arch_type == MACH_TYPE_CMPXA) -+#else -+# define machine_is_cmpxa() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ANUBIS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ANUBIS -+# endif -+# define machine_is_anubis() (machine_arch_type == MACH_TYPE_ANUBIS) -+#else -+# define machine_is_anubis() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ITE8152 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ITE8152 -+# endif -+# define machine_is_ite8152() (machine_arch_type == MACH_TYPE_ITE8152) -+#else -+# define machine_is_ite8152() (0) -+#endif -+ -+#ifdef CONFIG_MACH_LPC3XXX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_LPC3XXX -+# endif -+# define machine_is_lpc3xxx() (machine_arch_type == MACH_TYPE_LPC3XXX) -+#else -+# define machine_is_lpc3xxx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PUPPETEER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PUPPETEER -+# endif -+# define machine_is_puppeteer() (machine_arch_type == MACH_TYPE_PUPPETEER) -+#else -+# define machine_is_puppeteer() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MACH_VADATECH -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MACH_VADATECH -+# endif -+# define machine_is_vt001() (machine_arch_type == MACH_TYPE_MACH_VADATECH) -+#else -+# define machine_is_vt001() (0) -+#endif -+ -+#ifdef CONFIG_MACH_E570 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_E570 -+# endif -+# define machine_is_e570() (machine_arch_type == MACH_TYPE_E570) -+#else -+# define machine_is_e570() (0) -+#endif -+ -+#ifdef CONFIG_MACH_X50 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_X50 -+# endif -+# define machine_is_x50() (machine_arch_type == MACH_TYPE_X50) -+#else -+# define machine_is_x50() (0) -+#endif -+ -+#ifdef CONFIG_MACH_RECON -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_RECON -+# endif -+# define machine_is_recon() (machine_arch_type == MACH_TYPE_RECON) -+#else -+# define machine_is_recon() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XBOARDGP8 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XBOARDGP8 -+# endif -+# define machine_is_xboardgp8() (machine_arch_type == MACH_TYPE_XBOARDGP8) -+#else -+# define machine_is_xboardgp8() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FPIC2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FPIC2 -+# endif -+# define machine_is_fpic2() (machine_arch_type == MACH_TYPE_FPIC2) -+#else -+# define machine_is_fpic2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AKITA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AKITA -+# endif -+# define machine_is_akita() (machine_arch_type == MACH_TYPE_AKITA) -+#else -+# define machine_is_akita() (0) -+#endif -+ -+#ifdef CONFIG_MACH_A81 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_A81 -+# endif -+# define machine_is_a81() (machine_arch_type == MACH_TYPE_A81) -+#else -+# define machine_is_a81() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SVM_SC25X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SVM_SC25X -+# endif -+# define machine_is_svm_sc25x() (machine_arch_type == MACH_TYPE_SVM_SC25X) -+#else -+# define machine_is_svm_sc25x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VADATECH020 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VADATECH020 -+# endif -+# define machine_is_vt020() (machine_arch_type == MACH_TYPE_VADATECH020) -+#else -+# define machine_is_vt020() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TLI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TLI -+# endif -+# define machine_is_tli() (machine_arch_type == MACH_TYPE_TLI) -+#else -+# define machine_is_tli() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EDB9315LC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EDB9315LC -+# endif -+# define machine_is_edb9315lc() (machine_arch_type == MACH_TYPE_EDB9315LC) -+#else -+# define machine_is_edb9315lc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PASSEC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PASSEC -+# endif -+# define machine_is_passec() (machine_arch_type == MACH_TYPE_PASSEC) -+#else -+# define machine_is_passec() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DS_TIGER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DS_TIGER -+# endif -+# define machine_is_ds_tiger() (machine_arch_type == MACH_TYPE_DS_TIGER) -+#else -+# define machine_is_ds_tiger() (0) -+#endif -+ -+#ifdef CONFIG_MACH_E310 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_E310 -+# endif -+# define machine_is_e310() (machine_arch_type == MACH_TYPE_E310) -+#else -+# define machine_is_e310() (0) -+#endif -+ -+#ifdef CONFIG_MACH_E330 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_E330 -+# endif -+# define machine_is_e330() (machine_arch_type == MACH_TYPE_E330) -+#else -+# define machine_is_e330() (0) -+#endif -+ -+#ifdef CONFIG_MACH_RT3000 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_RT3000 -+# endif -+# define machine_is_rt3000() (machine_arch_type == MACH_TYPE_RT3000) -+#else -+# define machine_is_rt3000() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NOKIA770 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NOKIA770 -+# endif -+# define machine_is_nokia770() (machine_arch_type == MACH_TYPE_NOKIA770) -+#else -+# define machine_is_nokia770() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PNX0106 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PNX0106 -+# endif -+# define machine_is_pnx0106() (machine_arch_type == MACH_TYPE_PNX0106) -+#else -+# define machine_is_pnx0106() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HX21XX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HX21XX -+# endif -+# define machine_is_hx21xx() (machine_arch_type == MACH_TYPE_HX21XX) -+#else -+# define machine_is_hx21xx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FARADAY -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FARADAY -+# endif -+# define machine_is_faraday() (machine_arch_type == MACH_TYPE_FARADAY) -+#else -+# define machine_is_faraday() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SBC9312 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SBC9312 -+# endif -+# define machine_is_sbc9312() (machine_arch_type == MACH_TYPE_SBC9312) -+#else -+# define machine_is_sbc9312() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BATMAN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BATMAN -+# endif -+# define machine_is_batman() (machine_arch_type == MACH_TYPE_BATMAN) -+#else -+# define machine_is_batman() (0) -+#endif -+ -+#ifdef CONFIG_MACH_JPD201 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_JPD201 -+# endif -+# define machine_is_jpd201() (machine_arch_type == MACH_TYPE_JPD201) -+#else -+# define machine_is_jpd201() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MIPSA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MIPSA -+# endif -+# define machine_is_mipsa() (machine_arch_type == MACH_TYPE_MIPSA) -+#else -+# define machine_is_mipsa() (0) -+#endif -+ -+#ifdef CONFIG_MACH_KACOM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_KACOM -+# endif -+# define machine_is_kacom() (machine_arch_type == MACH_TYPE_KACOM) -+#else -+# define machine_is_kacom() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SWARCOCPU -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SWARCOCPU -+# endif -+# define machine_is_swarcocpu() (machine_arch_type == MACH_TYPE_SWARCOCPU) -+#else -+# define machine_is_swarcocpu() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SWARCODSL -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SWARCODSL -+# endif -+# define machine_is_swarcodsl() (machine_arch_type == MACH_TYPE_SWARCODSL) -+#else -+# define machine_is_swarcodsl() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BLUEANGEL -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BLUEANGEL -+# endif -+# define machine_is_blueangel() (machine_arch_type == MACH_TYPE_BLUEANGEL) -+#else -+# define machine_is_blueangel() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HAIRYGRAMA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HAIRYGRAMA -+# endif -+# define machine_is_hairygrama() (machine_arch_type == MACH_TYPE_HAIRYGRAMA) -+#else -+# define machine_is_hairygrama() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BANFF -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BANFF -+# endif -+# define machine_is_banff() (machine_arch_type == MACH_TYPE_BANFF) -+#else -+# define machine_is_banff() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CARMEVA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CARMEVA -+# endif -+# define machine_is_carmeva() (machine_arch_type == MACH_TYPE_CARMEVA) -+#else -+# define machine_is_carmeva() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SAM255 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SAM255 -+# endif -+# define machine_is_sam255() (machine_arch_type == MACH_TYPE_SAM255) -+#else -+# define machine_is_sam255() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PPM10 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PPM10 -+# endif -+# define machine_is_ppm10() (machine_arch_type == MACH_TYPE_PPM10) -+#else -+# define machine_is_ppm10() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EDB9315A -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EDB9315A -+# endif -+# define machine_is_edb9315a() (machine_arch_type == MACH_TYPE_EDB9315A) -+#else -+# define machine_is_edb9315a() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SUNSET -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SUNSET -+# endif -+# define machine_is_sunset() (machine_arch_type == MACH_TYPE_SUNSET) -+#else -+# define machine_is_sunset() (0) -+#endif -+ -+#ifdef CONFIG_MACH_STARGATE2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_STARGATE2 -+# endif -+# define machine_is_stargate2() (machine_arch_type == MACH_TYPE_STARGATE2) -+#else -+# define machine_is_stargate2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_INTELMOTE2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_INTELMOTE2 -+# endif -+# define machine_is_intelmote2() (machine_arch_type == MACH_TYPE_INTELMOTE2) -+#else -+# define machine_is_intelmote2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TRIZEPS4 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TRIZEPS4 -+# endif -+# define machine_is_trizeps4() (machine_arch_type == MACH_TYPE_TRIZEPS4) -+#else -+# define machine_is_trizeps4() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAINSTONE2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAINSTONE2 -+# endif -+# define machine_is_mainstone2() (machine_arch_type == MACH_TYPE_MAINSTONE2) -+#else -+# define machine_is_mainstone2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EZ_IXP42X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EZ_IXP42X -+# endif -+# define machine_is_ez_ixp42x() (machine_arch_type == MACH_TYPE_EZ_IXP42X) -+#else -+# define machine_is_ez_ixp42x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TAPWAVE_ZODIAC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TAPWAVE_ZODIAC -+# endif -+# define machine_is_tapwave_zodiac() (machine_arch_type == MACH_TYPE_TAPWAVE_ZODIAC) -+#else -+# define machine_is_tapwave_zodiac() (0) -+#endif -+ -+#ifdef CONFIG_MACH_UNIVERSALMETER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_UNIVERSALMETER -+# endif -+# define machine_is_universalmeter() (machine_arch_type == MACH_TYPE_UNIVERSALMETER) -+#else -+# define machine_is_universalmeter() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HICOARM9 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HICOARM9 -+# endif -+# define machine_is_hicoarm9() (machine_arch_type == MACH_TYPE_HICOARM9) -+#else -+# define machine_is_hicoarm9() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PNX4008 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PNX4008 -+# endif -+# define machine_is_pnx4008() (machine_arch_type == MACH_TYPE_PNX4008) -+#else -+# define machine_is_pnx4008() (0) -+#endif -+ -+#ifdef CONFIG_MACH_KWS6000 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_KWS6000 -+# endif -+# define machine_is_kws6000() (machine_arch_type == MACH_TYPE_KWS6000) -+#else -+# define machine_is_kws6000() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PORTUX920T -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PORTUX920T -+# endif -+# define machine_is_portux920t() (machine_arch_type == MACH_TYPE_PORTUX920T) -+#else -+# define machine_is_portux920t() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EZ_X5 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EZ_X5 -+# endif -+# define machine_is_ez_x5() (machine_arch_type == MACH_TYPE_EZ_X5) -+#else -+# define machine_is_ez_x5() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_RUDOLPH -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_RUDOLPH -+# endif -+# define machine_is_omap_rudolph() (machine_arch_type == MACH_TYPE_OMAP_RUDOLPH) -+#else -+# define machine_is_omap_rudolph() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CPUAT91 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CPUAT91 -+# endif -+# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91) -+#else -+# define machine_is_cpuat91() (0) -+#endif -+ -+#ifdef CONFIG_MACH_REA9200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_REA9200 -+# endif -+# define machine_is_rea9200() (machine_arch_type == MACH_TYPE_REA9200) -+#else -+# define machine_is_rea9200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ACTS_PUNE_SA1110 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ACTS_PUNE_SA1110 -+# endif -+# define machine_is_acts_pune_sa1110() (machine_arch_type == MACH_TYPE_ACTS_PUNE_SA1110) -+#else -+# define machine_is_acts_pune_sa1110() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IXP425 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IXP425 -+# endif -+# define machine_is_ixp425() (machine_arch_type == MACH_TYPE_IXP425) -+#else -+# define machine_is_ixp425() (0) -+#endif -+ -+#ifdef CONFIG_MACH_I30030ADS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_I30030ADS -+# endif -+# define machine_is_i30030ads() (machine_arch_type == MACH_TYPE_I30030ADS) -+#else -+# define machine_is_i30030ads() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PERCH -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PERCH -+# endif -+# define machine_is_perch() (machine_arch_type == MACH_TYPE_PERCH) -+#else -+# define machine_is_perch() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EIS05R1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EIS05R1 -+# endif -+# define machine_is_eis05r1() (machine_arch_type == MACH_TYPE_EIS05R1) -+#else -+# define machine_is_eis05r1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PEPPERPAD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PEPPERPAD -+# endif -+# define machine_is_pepperpad() (machine_arch_type == MACH_TYPE_PEPPERPAD) -+#else -+# define machine_is_pepperpad() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SB3010 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SB3010 -+# endif -+# define machine_is_sb3010() (machine_arch_type == MACH_TYPE_SB3010) -+#else -+# define machine_is_sb3010() (0) -+#endif -+ -+#ifdef CONFIG_MACH_RM9200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_RM9200 -+# endif -+# define machine_is_rm9200() (machine_arch_type == MACH_TYPE_RM9200) -+#else -+# define machine_is_rm9200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DMA03 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DMA03 -+# endif -+# define machine_is_dma03() (machine_arch_type == MACH_TYPE_DMA03) -+#else -+# define machine_is_dma03() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ROAD_S101 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ROAD_S101 -+# endif -+# define machine_is_road_s101() (machine_arch_type == MACH_TYPE_ROAD_S101) -+#else -+# define machine_is_road_s101() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ_NEXTGEN_A -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_A -+# endif -+# define machine_is_iq_nextgen_a() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_A) -+#else -+# define machine_is_iq_nextgen_a() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ_NEXTGEN_B -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_B -+# endif -+# define machine_is_iq_nextgen_b() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_B) -+#else -+# define machine_is_iq_nextgen_b() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ_NEXTGEN_C -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_C -+# endif -+# define machine_is_iq_nextgen_c() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_C) -+#else -+# define machine_is_iq_nextgen_c() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ_NEXTGEN_D -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_D -+# endif -+# define machine_is_iq_nextgen_d() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_D) -+#else -+# define machine_is_iq_nextgen_d() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ_NEXTGEN_E -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_E -+# endif -+# define machine_is_iq_nextgen_e() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_E) -+#else -+# define machine_is_iq_nextgen_e() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MALLOW_AT91 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MALLOW_AT91 -+# endif -+# define machine_is_mallow_at91() (machine_arch_type == MACH_TYPE_MALLOW_AT91) -+#else -+# define machine_is_mallow_at91() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CYBERTRACKER_I -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CYBERTRACKER_I -+# endif -+# define machine_is_cybertracker_i() (machine_arch_type == MACH_TYPE_CYBERTRACKER_I) -+#else -+# define machine_is_cybertracker_i() (0) -+#endif -+ -+#ifdef CONFIG_MACH_GESBC931X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_GESBC931X -+# endif -+# define machine_is_gesbc931x() (machine_arch_type == MACH_TYPE_GESBC931X) -+#else -+# define machine_is_gesbc931x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CENTIPAD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CENTIPAD -+# endif -+# define machine_is_centipad() (machine_arch_type == MACH_TYPE_CENTIPAD) -+#else -+# define machine_is_centipad() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ARMSOC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ARMSOC -+# endif -+# define machine_is_armsoc() (machine_arch_type == MACH_TYPE_ARMSOC) -+#else -+# define machine_is_armsoc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SE4200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SE4200 -+# endif -+# define machine_is_se4200() (machine_arch_type == MACH_TYPE_SE4200) -+#else -+# define machine_is_se4200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EMS197A -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EMS197A -+# endif -+# define machine_is_ems197a() (machine_arch_type == MACH_TYPE_EMS197A) -+#else -+# define machine_is_ems197a() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MICRO9 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MICRO9 -+# endif -+# define machine_is_micro9() (machine_arch_type == MACH_TYPE_MICRO9) -+#else -+# define machine_is_micro9() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MICRO9L -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MICRO9L -+# endif -+# define machine_is_micro9l() (machine_arch_type == MACH_TYPE_MICRO9L) -+#else -+# define machine_is_micro9l() (0) -+#endif -+ -+#ifdef CONFIG_MACH_UC5471DSP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_UC5471DSP -+# endif -+# define machine_is_uc5471dsp() (machine_arch_type == MACH_TYPE_UC5471DSP) -+#else -+# define machine_is_uc5471dsp() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SJ5471ENG -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SJ5471ENG -+# endif -+# define machine_is_sj5471eng() (machine_arch_type == MACH_TYPE_SJ5471ENG) -+#else -+# define machine_is_sj5471eng() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CMPXA26X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CMPXA26X -+# endif -+# define machine_is_none() (machine_arch_type == MACH_TYPE_CMPXA26X) -+#else -+# define machine_is_none() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NC -+# endif -+# define machine_is_nc1() (machine_arch_type == MACH_TYPE_NC) -+#else -+# define machine_is_nc1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_PALMTE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_PALMTE -+# endif -+# define machine_is_omap_palmte() (machine_arch_type == MACH_TYPE_OMAP_PALMTE) -+#else -+# define machine_is_omap_palmte() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AJAX52X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AJAX52X -+# endif -+# define machine_is_ajax52x() (machine_arch_type == MACH_TYPE_AJAX52X) -+#else -+# define machine_is_ajax52x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SIRIUSTAR -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SIRIUSTAR -+# endif -+# define machine_is_siriustar() (machine_arch_type == MACH_TYPE_SIRIUSTAR) -+#else -+# define machine_is_siriustar() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IODATA_HDLG -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IODATA_HDLG -+# endif -+# define machine_is_iodata_hdlg() (machine_arch_type == MACH_TYPE_IODATA_HDLG) -+#else -+# define machine_is_iodata_hdlg() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AT91RM9200UTL -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AT91RM9200UTL -+# endif -+# define machine_is_at91rm9200utl() (machine_arch_type == MACH_TYPE_AT91RM9200UTL) -+#else -+# define machine_is_at91rm9200utl() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BIOSAFE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BIOSAFE -+# endif -+# define machine_is_biosafe() (machine_arch_type == MACH_TYPE_BIOSAFE) -+#else -+# define machine_is_biosafe() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MP1000 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MP1000 -+# endif -+# define machine_is_mp1000() (machine_arch_type == MACH_TYPE_MP1000) -+#else -+# define machine_is_mp1000() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PARSY -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PARSY -+# endif -+# define machine_is_parsy() (machine_arch_type == MACH_TYPE_PARSY) -+#else -+# define machine_is_parsy() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CCXP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CCXP -+# endif -+# define machine_is_ccxp270() (machine_arch_type == MACH_TYPE_CCXP) -+#else -+# define machine_is_ccxp270() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_GSAMPLE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_GSAMPLE -+# endif -+# define machine_is_omap_gsample() (machine_arch_type == MACH_TYPE_OMAP_GSAMPLE) -+#else -+# define machine_is_omap_gsample() (0) -+#endif -+ -+#ifdef CONFIG_MACH_REALVIEW_EB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_REALVIEW_EB -+# endif -+# define machine_is_realview_eb() (machine_arch_type == MACH_TYPE_REALVIEW_EB) -+#else -+# define machine_is_realview_eb() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SAMOA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SAMOA -+# endif -+# define machine_is_samoa() (machine_arch_type == MACH_TYPE_SAMOA) -+#else -+# define machine_is_samoa() (0) -+#endif -+ -+#ifdef CONFIG_MACH_T3XSCALE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_T3XSCALE -+# endif -+# define machine_is_t3xscale() (machine_arch_type == MACH_TYPE_T3XSCALE) -+#else -+# define machine_is_t3xscale() (0) -+#endif -+ -+#ifdef CONFIG_MACH_I878 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_I878 -+# endif -+# define machine_is_i878() (machine_arch_type == MACH_TYPE_I878) -+#else -+# define machine_is_i878() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BORZOI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BORZOI -+# endif -+# define machine_is_borzoi() (machine_arch_type == MACH_TYPE_BORZOI) -+#else -+# define machine_is_borzoi() (0) -+#endif -+ -+#ifdef CONFIG_MACH_GECKO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_GECKO -+# endif -+# define machine_is_gecko() (machine_arch_type == MACH_TYPE_GECKO) -+#else -+# define machine_is_gecko() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DS101 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DS101 -+# endif -+# define machine_is_ds101() (machine_arch_type == MACH_TYPE_DS101) -+#else -+# define machine_is_ds101() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_PALMTT2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_PALMTT2 -+# endif -+# define machine_is_omap_palmtt2() (machine_arch_type == MACH_TYPE_OMAP_PALMTT2) -+#else -+# define machine_is_omap_palmtt2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XSCALE_PALMLD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XSCALE_PALMLD -+# endif -+# define machine_is_xscale_palmld() (machine_arch_type == MACH_TYPE_XSCALE_PALMLD) -+#else -+# define machine_is_xscale_palmld() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CC9C -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CC9C -+# endif -+# define machine_is_cc9c() (machine_arch_type == MACH_TYPE_CC9C) -+#else -+# define machine_is_cc9c() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SBC1670 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SBC1670 -+# endif -+# define machine_is_sbc1670() (machine_arch_type == MACH_TYPE_SBC1670) -+#else -+# define machine_is_sbc1670() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IXDP28X5 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IXDP28X5 -+# endif -+# define machine_is_ixdp28x5() (machine_arch_type == MACH_TYPE_IXDP28X5) -+#else -+# define machine_is_ixdp28x5() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_PALMTT -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_PALMTT -+# endif -+# define machine_is_omap_palmtt() (machine_arch_type == MACH_TYPE_OMAP_PALMTT) -+#else -+# define machine_is_omap_palmtt() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ML696K -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ML696K -+# endif -+# define machine_is_ml696k() (machine_arch_type == MACH_TYPE_ML696K) -+#else -+# define machine_is_ml696k() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ARCOM_ZEUS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ARCOM_ZEUS -+# endif -+# define machine_is_arcom_zeus() (machine_arch_type == MACH_TYPE_ARCOM_ZEUS) -+#else -+# define machine_is_arcom_zeus() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OSIRIS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OSIRIS -+# endif -+# define machine_is_osiris() (machine_arch_type == MACH_TYPE_OSIRIS) -+#else -+# define machine_is_osiris() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAESTRO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAESTRO -+# endif -+# define machine_is_maestro() (machine_arch_type == MACH_TYPE_MAESTRO) -+#else -+# define machine_is_maestro() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TUNGE2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TUNGE2 -+# endif -+# define machine_is_tunge2() (machine_arch_type == MACH_TYPE_TUNGE2) -+#else -+# define machine_is_tunge2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IXBBM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IXBBM -+# endif -+# define machine_is_ixbbm() (machine_arch_type == MACH_TYPE_IXBBM) -+#else -+# define machine_is_ixbbm() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MX27 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MX27 -+# endif -+# define machine_is_mx27ads() (machine_arch_type == MACH_TYPE_MX27) -+#else -+# define machine_is_mx27ads() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AX8004 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AX8004 -+# endif -+# define machine_is_ax8004() (machine_arch_type == MACH_TYPE_AX8004) -+#else -+# define machine_is_ax8004() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AT91SAM9261EK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AT91SAM9261EK -+# endif -+# define machine_is_at91sam9261ek() (machine_arch_type == MACH_TYPE_AT91SAM9261EK) -+#else -+# define machine_is_at91sam9261ek() (0) -+#endif -+ -+#ifdef CONFIG_MACH_LOFT -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_LOFT -+# endif -+# define machine_is_loft() (machine_arch_type == MACH_TYPE_LOFT) -+#else -+# define machine_is_loft() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAGPIE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAGPIE -+# endif -+# define machine_is_magpie() (machine_arch_type == MACH_TYPE_MAGPIE) -+#else -+# define machine_is_magpie() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MX21 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MX21 -+# endif -+# define machine_is_mx21ads() (machine_arch_type == MACH_TYPE_MX21) -+#else -+# define machine_is_mx21ads() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MB87M3400 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MB87M3400 -+# endif -+# define machine_is_mb87m3400() (machine_arch_type == MACH_TYPE_MB87M3400) -+#else -+# define machine_is_mb87m3400() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MGUARD_DELTA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MGUARD_DELTA -+# endif -+# define machine_is_mguard_delta() (machine_arch_type == MACH_TYPE_MGUARD_DELTA) -+#else -+# define machine_is_mguard_delta() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DAVINCI_DVDP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DAVINCI_DVDP -+# endif -+# define machine_is_davinci_dvdp() (machine_arch_type == MACH_TYPE_DAVINCI_DVDP) -+#else -+# define machine_is_davinci_dvdp() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HTCUNIVERSAL -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HTCUNIVERSAL -+# endif -+# define machine_is_htcuniversal() (machine_arch_type == MACH_TYPE_HTCUNIVERSAL) -+#else -+# define machine_is_htcuniversal() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TPAD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TPAD -+# endif -+# define machine_is_tpad() (machine_arch_type == MACH_TYPE_TPAD) -+#else -+# define machine_is_tpad() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ROVERP3 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ROVERP3 -+# endif -+# define machine_is_roverp3() (machine_arch_type == MACH_TYPE_ROVERP3) -+#else -+# define machine_is_roverp3() (0) -+#endif -+ -+#ifdef CONFIG_MACH_JORNADA928 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_JORNADA928 -+# endif -+# define machine_is_jornada928() (machine_arch_type == MACH_TYPE_JORNADA928) -+#else -+# define machine_is_jornada928() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MV88FXX81 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MV88FXX81 -+# endif -+# define machine_is_mv88fxx81() (machine_arch_type == MACH_TYPE_MV88FXX81) -+#else -+# define machine_is_mv88fxx81() (0) -+#endif -+ -+#ifdef CONFIG_MACH_STMP36XX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_STMP36XX -+# endif -+# define machine_is_stmp36xx() (machine_arch_type == MACH_TYPE_STMP36XX) -+#else -+# define machine_is_stmp36xx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SXNI79524 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SXNI79524 -+# endif -+# define machine_is_sxni79524() (machine_arch_type == MACH_TYPE_SXNI79524) -+#else -+# define machine_is_sxni79524() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AMS_DELTA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AMS_DELTA -+# endif -+# define machine_is_ams_delta() (machine_arch_type == MACH_TYPE_AMS_DELTA) -+#else -+# define machine_is_ams_delta() (0) -+#endif -+ -+#ifdef CONFIG_MACH_URANIUM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_URANIUM -+# endif -+# define machine_is_uranium() (machine_arch_type == MACH_TYPE_URANIUM) -+#else -+# define machine_is_uranium() (0) -+#endif -+ -+#ifdef CONFIG_MACH_UCON -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_UCON -+# endif -+# define machine_is_ucon() (machine_arch_type == MACH_TYPE_UCON) -+#else -+# define machine_is_ucon() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NAS100D -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NAS100D -+# endif -+# define machine_is_nas100d() (machine_arch_type == MACH_TYPE_NAS100D) -+#else -+# define machine_is_nas100d() (0) -+#endif -+ -+#ifdef CONFIG_MACH_L083_1000 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_L083_1000 -+# endif -+# define machine_is_l083() (machine_arch_type == MACH_TYPE_L083_1000) -+#else -+# define machine_is_l083() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EZX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EZX -+# endif -+# define machine_is_ezx() (machine_arch_type == MACH_TYPE_EZX) -+#else -+# define machine_is_ezx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PNX5220 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PNX5220 -+# endif -+# define machine_is_pnx5220() (machine_arch_type == MACH_TYPE_PNX5220) -+#else -+# define machine_is_pnx5220() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BUTTE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BUTTE -+# endif -+# define machine_is_butte() (machine_arch_type == MACH_TYPE_BUTTE) -+#else -+# define machine_is_butte() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SRM2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SRM2 -+# endif -+# define machine_is_srm2() (machine_arch_type == MACH_TYPE_SRM2) -+#else -+# define machine_is_srm2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DSBR -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DSBR -+# endif -+# define machine_is_dsbr() (machine_arch_type == MACH_TYPE_DSBR) -+#else -+# define machine_is_dsbr() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CRYSTALBALL -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CRYSTALBALL -+# endif -+# define machine_is_crystalball() (machine_arch_type == MACH_TYPE_CRYSTALBALL) -+#else -+# define machine_is_crystalball() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TINYPXA27X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TINYPXA27X -+# endif -+# define machine_is_tinypxa27x() (machine_arch_type == MACH_TYPE_TINYPXA27X) -+#else -+# define machine_is_tinypxa27x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HERBIE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HERBIE -+# endif -+# define machine_is_herbie() (machine_arch_type == MACH_TYPE_HERBIE) -+#else -+# define machine_is_herbie() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAGICIAN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAGICIAN -+# endif -+# define machine_is_magician() (machine_arch_type == MACH_TYPE_MAGICIAN) -+#else -+# define machine_is_magician() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CM4002 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CM4002 -+# endif -+# define machine_is_cm4002() (machine_arch_type == MACH_TYPE_CM4002) -+#else -+# define machine_is_cm4002() (0) -+#endif -+ -+#ifdef CONFIG_MACH_B4 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_B4 -+# endif -+# define machine_is_b4() (machine_arch_type == MACH_TYPE_B4) -+#else -+# define machine_is_b4() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAUI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAUI -+# endif -+# define machine_is_maui() (machine_arch_type == MACH_TYPE_MAUI) -+#else -+# define machine_is_maui() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CYBERTRACKER_G -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CYBERTRACKER_G -+# endif -+# define machine_is_cybertracker_g() (machine_arch_type == MACH_TYPE_CYBERTRACKER_G) -+#else -+# define machine_is_cybertracker_g() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NXDKN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NXDKN -+# endif -+# define machine_is_nxdkn() (machine_arch_type == MACH_TYPE_NXDKN) -+#else -+# define machine_is_nxdkn() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MIO8390 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MIO8390 -+# endif -+# define machine_is_mio8390() (machine_arch_type == MACH_TYPE_MIO8390) -+#else -+# define machine_is_mio8390() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMI_BOARD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMI_BOARD -+# endif -+# define machine_is_omi_board() (machine_arch_type == MACH_TYPE_OMI_BOARD) -+#else -+# define machine_is_omi_board() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MX21CIV -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MX21CIV -+# endif -+# define machine_is_mx21civ() (machine_arch_type == MACH_TYPE_MX21CIV) -+#else -+# define machine_is_mx21civ() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MAHI_CDAC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MAHI_CDAC -+# endif -+# define machine_is_mahi_cdac() (machine_arch_type == MACH_TYPE_MAHI_CDAC) -+#else -+# define machine_is_mahi_cdac() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XSCALE_PALMTX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XSCALE_PALMTX -+# endif -+# define machine_is_xscale_palmtx() (machine_arch_type == MACH_TYPE_XSCALE_PALMTX) -+#else -+# define machine_is_xscale_palmtx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_S3C2413 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_S3C2413 -+# endif -+# define machine_is_s3c2413() (machine_arch_type == MACH_TYPE_S3C2413) -+#else -+# define machine_is_s3c2413() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SAMSYS_EP0 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SAMSYS_EP0 -+# endif -+# define machine_is_samsys_ep0() (machine_arch_type == MACH_TYPE_SAMSYS_EP0) -+#else -+# define machine_is_samsys_ep0() (0) -+#endif -+ -+#ifdef CONFIG_MACH_WG302V1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_WG302V1 -+# endif -+# define machine_is_wg302v1() (machine_arch_type == MACH_TYPE_WG302V1) -+#else -+# define machine_is_wg302v1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_WG302V2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_WG302V2 -+# endif -+# define machine_is_wg302v2() (machine_arch_type == MACH_TYPE_WG302V2) -+#else -+# define machine_is_wg302v2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EB42X -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EB42X -+# endif -+# define machine_is_eb42x() (machine_arch_type == MACH_TYPE_EB42X) -+#else -+# define machine_is_eb42x() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IQ331ES -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IQ331ES -+# endif -+# define machine_is_iq331es() (machine_arch_type == MACH_TYPE_IQ331ES) -+#else -+# define machine_is_iq331es() (0) -+#endif -+ -+#ifdef CONFIG_MACH_COSYDSP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_COSYDSP -+# endif -+# define machine_is_cosydsp() (machine_arch_type == MACH_TYPE_COSYDSP) -+#else -+# define machine_is_cosydsp() (0) -+#endif -+ -+#ifdef CONFIG_MACH_UPLAT7D -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_UPLAT7D -+# endif -+# define machine_is_uplat7d_proto() (machine_arch_type == MACH_TYPE_UPLAT7D) -+#else -+# define machine_is_uplat7d_proto() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PTDAVINCI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PTDAVINCI -+# endif -+# define machine_is_ptdavinci() (machine_arch_type == MACH_TYPE_PTDAVINCI) -+#else -+# define machine_is_ptdavinci() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MBUS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MBUS -+# endif -+# define machine_is_mbus() (machine_arch_type == MACH_TYPE_MBUS) -+#else -+# define machine_is_mbus() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NADIA2VB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NADIA2VB -+# endif -+# define machine_is_nadia2vb() (machine_arch_type == MACH_TYPE_NADIA2VB) -+#else -+# define machine_is_nadia2vb() (0) -+#endif -+ -+#ifdef CONFIG_MACH_R1000 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_R1000 -+# endif -+# define machine_is_r1000() (machine_arch_type == MACH_TYPE_R1000) -+#else -+# define machine_is_r1000() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HW90250 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HW90250 -+# endif -+# define machine_is_hw90250() (machine_arch_type == MACH_TYPE_HW90250) -+#else -+# define machine_is_hw90250() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_2430SDP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_2430SDP -+# endif -+# define machine_is_omap_2430sdp() (machine_arch_type == MACH_TYPE_OMAP_2430SDP) -+#else -+# define machine_is_omap_2430sdp() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DAVINCI_EVM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DAVINCI_EVM -+# endif -+# define machine_is_davinci_evm() (machine_arch_type == MACH_TYPE_DAVINCI_EVM) -+#else -+# define machine_is_davinci_evm() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_TORNADO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_TORNADO -+# endif -+# define machine_is_omap_tornado() (machine_arch_type == MACH_TYPE_OMAP_TORNADO) -+#else -+# define machine_is_omap_tornado() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OLOCREEK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OLOCREEK -+# endif -+# define machine_is_olocreek() (machine_arch_type == MACH_TYPE_OLOCREEK) -+#else -+# define machine_is_olocreek() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PALMZ72 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PALMZ72 -+# endif -+# define machine_is_palmz72() (machine_arch_type == MACH_TYPE_PALMZ72) -+#else -+# define machine_is_palmz72() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NXDB500 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NXDB500 -+# endif -+# define machine_is_nxdb500() (machine_arch_type == MACH_TYPE_NXDB500) -+#else -+# define machine_is_nxdb500() (0) -+#endif -+ -+#ifdef CONFIG_MACH_APF9328 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_APF9328 -+# endif -+# define machine_is_apf9328() (machine_arch_type == MACH_TYPE_APF9328) -+#else -+# define machine_is_apf9328() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_WIPOQ -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_WIPOQ -+# endif -+# define machine_is_omap_wipoq() (machine_arch_type == MACH_TYPE_OMAP_WIPOQ) -+#else -+# define machine_is_omap_wipoq() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_TWIP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_TWIP -+# endif -+# define machine_is_omap_twip() (machine_arch_type == MACH_TYPE_OMAP_TWIP) -+#else -+# define machine_is_omap_twip() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XSCALE_PALMTREO650 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XSCALE_PALMTREO650 -+# endif -+# define machine_is_xscale_treo650() (machine_arch_type == MACH_TYPE_XSCALE_PALMTREO650) -+#else -+# define machine_is_xscale_treo650() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ACUMEN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ACUMEN -+# endif -+# define machine_is_acumen() (machine_arch_type == MACH_TYPE_ACUMEN) -+#else -+# define machine_is_acumen() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XP100 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XP100 -+# endif -+# define machine_is_xp100() (machine_arch_type == MACH_TYPE_XP100) -+#else -+# define machine_is_xp100() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FS2410 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FS2410 -+# endif -+# define machine_is_fs2410() (machine_arch_type == MACH_TYPE_FS2410) -+#else -+# define machine_is_fs2410() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PXA270_CERF -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PXA270_CERF -+# endif -+# define machine_is_pxa270_cerf() (machine_arch_type == MACH_TYPE_PXA270_CERF) -+#else -+# define machine_is_pxa270_cerf() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SQ2FTLPALM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SQ2FTLPALM -+# endif -+# define machine_is_sq2ftlpalm() (machine_arch_type == MACH_TYPE_SQ2FTLPALM) -+#else -+# define machine_is_sq2ftlpalm() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BSEMSERVER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BSEMSERVER -+# endif -+# define machine_is_bsemserver() (machine_arch_type == MACH_TYPE_BSEMSERVER) -+#else -+# define machine_is_bsemserver() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NETCLIENT -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NETCLIENT -+# endif -+# define machine_is_netclient() (machine_arch_type == MACH_TYPE_NETCLIENT) -+#else -+# define machine_is_netclient() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XSCALE_PALMTT5 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XSCALE_PALMTT5 -+# endif -+# define machine_is_xscale_palmtt5() (machine_arch_type == MACH_TYPE_XSCALE_PALMTT5) -+#else -+# define machine_is_xscale_palmtt5() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_PALMTC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_PALMTC -+# endif -+# define machine_is_xscale_palmtc() (machine_arch_type == MACH_TYPE_OMAP_PALMTC) -+#else -+# define machine_is_xscale_palmtc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_APOLLON -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_APOLLON -+# endif -+# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON) -+#else -+# define machine_is_omap_apollon() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MXC30030EVB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MXC30030EVB -+# endif -+# define machine_is_mxc30030evb() (machine_arch_type == MACH_TYPE_MXC30030EVB) -+#else -+# define machine_is_mxc30030evb() (0) -+#endif -+ -+#ifdef CONFIG_MACH_REA_2D -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_REA_2D -+# endif -+# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D) -+#else -+# define machine_is_rea_2d() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TI3E524 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TI3E524 -+# endif -+# define machine_is_eti3e524() (machine_arch_type == MACH_TYPE_TI3E524) -+#else -+# define machine_is_eti3e524() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ATEB9200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ATEB9200 -+# endif -+# define machine_is_ateb9200() (machine_arch_type == MACH_TYPE_ATEB9200) -+#else -+# define machine_is_ateb9200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AUCKLAND -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AUCKLAND -+# endif -+# define machine_is_auckland() (machine_arch_type == MACH_TYPE_AUCKLAND) -+#else -+# define machine_is_auckland() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AK3320M -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AK3320M -+# endif -+# define machine_is_ak3220m() (machine_arch_type == MACH_TYPE_AK3320M) -+#else -+# define machine_is_ak3220m() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DURAMAX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DURAMAX -+# endif -+# define machine_is_duramax() (machine_arch_type == MACH_TYPE_DURAMAX) -+#else -+# define machine_is_duramax() (0) -+#endif -+ -+#ifdef CONFIG_MACH_N35 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_N35 -+# endif -+# define machine_is_n35() (machine_arch_type == MACH_TYPE_N35) -+#else -+# define machine_is_n35() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PRONGHORN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PRONGHORN -+# endif -+# define machine_is_pronghorn() (machine_arch_type == MACH_TYPE_PRONGHORN) -+#else -+# define machine_is_pronghorn() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FUNDY -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FUNDY -+# endif -+# define machine_is_fundy() (machine_arch_type == MACH_TYPE_FUNDY) -+#else -+# define machine_is_fundy() (0) -+#endif -+ -+#ifdef CONFIG_MACH_LOGICPD_PXA270 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_LOGICPD_PXA270 -+# endif -+# define machine_is_logicpd_pxa270() (machine_arch_type == MACH_TYPE_LOGICPD_PXA270) -+#else -+# define machine_is_logicpd_pxa270() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CPU777 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CPU777 -+# endif -+# define machine_is_cpu777() (machine_arch_type == MACH_TYPE_CPU777) -+#else -+# define machine_is_cpu777() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SIMICON9201 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SIMICON9201 -+# endif -+# define machine_is_simicon9201() (machine_arch_type == MACH_TYPE_SIMICON9201) -+#else -+# define machine_is_simicon9201() (0) -+#endif -+ -+#ifdef CONFIG_MACH_LEAP2_HPM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_LEAP2_HPM -+# endif -+# define machine_is_leap2_hpm() (machine_arch_type == MACH_TYPE_LEAP2_HPM) -+#else -+# define machine_is_leap2_hpm() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CM922TXA10 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CM922TXA10 -+# endif -+# define machine_is_cm922txa10() (machine_arch_type == MACH_TYPE_CM922TXA10) -+#else -+# define machine_is_cm922txa10() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PXA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PXA -+# endif -+# define machine_is_sandgate() (machine_arch_type == MACH_TYPE_PXA) -+#else -+# define machine_is_sandgate() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SANDGATE2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SANDGATE2 -+# endif -+# define machine_is_sandgate2() (machine_arch_type == MACH_TYPE_SANDGATE2) -+#else -+# define machine_is_sandgate2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SANDGATE2G -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SANDGATE2G -+# endif -+# define machine_is_sandgate2g() (machine_arch_type == MACH_TYPE_SANDGATE2G) -+#else -+# define machine_is_sandgate2g() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SANDGATE2P -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SANDGATE2P -+# endif -+# define machine_is_sandgate2p() (machine_arch_type == MACH_TYPE_SANDGATE2P) -+#else -+# define machine_is_sandgate2p() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FRED_JACK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FRED_JACK -+# endif -+# define machine_is_fred_jack() (machine_arch_type == MACH_TYPE_FRED_JACK) -+#else -+# define machine_is_fred_jack() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TTG_COLOR1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TTG_COLOR1 -+# endif -+# define machine_is_ttg_color1() (machine_arch_type == MACH_TYPE_TTG_COLOR1) -+#else -+# define machine_is_ttg_color1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NXEB500HMI -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NXEB500HMI -+# endif -+# define machine_is_nxeb500hmi() (machine_arch_type == MACH_TYPE_NXEB500HMI) -+#else -+# define machine_is_nxeb500hmi() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NETDCU8 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NETDCU8 -+# endif -+# define machine_is_netdcu8() (machine_arch_type == MACH_TYPE_NETDCU8) -+#else -+# define machine_is_netdcu8() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ML675050_CPU_BOA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ML675050_CPU_BOA -+# endif -+# define machine_is_ml675050_cpu_boa() (machine_arch_type == MACH_TYPE_ML675050_CPU_BOA) -+#else -+# define machine_is_ml675050_cpu_boa() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NG_FVX538 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NG_FVX538 -+# endif -+# define machine_is_ng_fvx538() (machine_arch_type == MACH_TYPE_NG_FVX538) -+#else -+# define machine_is_ng_fvx538() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NG_FVS338 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NG_FVS338 -+# endif -+# define machine_is_ng_fvs338() (machine_arch_type == MACH_TYPE_NG_FVS338) -+#else -+# define machine_is_ng_fvs338() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PNX4103 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PNX4103 -+# endif -+# define machine_is_pnx4103() (machine_arch_type == MACH_TYPE_PNX4103) -+#else -+# define machine_is_pnx4103() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HESDB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HESDB -+# endif -+# define machine_is_hesdb() (machine_arch_type == MACH_TYPE_HESDB) -+#else -+# define machine_is_hesdb() (0) -+#endif -+ -+#ifdef CONFIG_MACH_XSILO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_XSILO -+# endif -+# define machine_is_xsilo() (machine_arch_type == MACH_TYPE_XSILO) -+#else -+# define machine_is_xsilo() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ESPRESSO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ESPRESSO -+# endif -+# define machine_is_espresso() (machine_arch_type == MACH_TYPE_ESPRESSO) -+#else -+# define machine_is_espresso() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EMLC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EMLC -+# endif -+# define machine_is_emlc() (machine_arch_type == MACH_TYPE_EMLC) -+#else -+# define machine_is_emlc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SISTERON -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SISTERON -+# endif -+# define machine_is_sisteron() (machine_arch_type == MACH_TYPE_SISTERON) -+#else -+# define machine_is_sisteron() (0) -+#endif -+ -+#ifdef CONFIG_MACH_RX1950 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_RX1950 -+# endif -+# define machine_is_rx1950() (machine_arch_type == MACH_TYPE_RX1950) -+#else -+# define machine_is_rx1950() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TSC_VENUS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TSC_VENUS -+# endif -+# define machine_is_tsc_venus() (machine_arch_type == MACH_TYPE_TSC_VENUS) -+#else -+# define machine_is_tsc_venus() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DS101J -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DS101J -+# endif -+# define machine_is_ds101j() (machine_arch_type == MACH_TYPE_DS101J) -+#else -+# define machine_is_ds101j() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MXC30030ADS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MXC30030ADS -+# endif -+# define machine_is_mxc30030ads() (machine_arch_type == MACH_TYPE_MXC30030ADS) -+#else -+# define machine_is_mxc30030ads() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FUJITSU_WIMAXSOC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FUJITSU_WIMAXSOC -+# endif -+# define machine_is_fujitsu_wimaxsoc() (machine_arch_type == MACH_TYPE_FUJITSU_WIMAXSOC) -+#else -+# define machine_is_fujitsu_wimaxsoc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DUALPCMODEM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DUALPCMODEM -+# endif -+# define machine_is_dualpcmodem() (machine_arch_type == MACH_TYPE_DUALPCMODEM) -+#else -+# define machine_is_dualpcmodem() (0) -+#endif -+ -+#ifdef CONFIG_MACH_GESBC9312 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_GESBC9312 -+# endif -+# define machine_is_gesbc9312() (machine_arch_type == MACH_TYPE_GESBC9312) -+#else -+# define machine_is_gesbc9312() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HTCAPACHE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HTCAPACHE -+# endif -+# define machine_is_htcapache() (machine_arch_type == MACH_TYPE_HTCAPACHE) -+#else -+# define machine_is_htcapache() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IXDP435 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IXDP435 -+# endif -+# define machine_is_ixdp435() (machine_arch_type == MACH_TYPE_IXDP435) -+#else -+# define machine_is_ixdp435() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CATPROVT100 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CATPROVT100 -+# endif -+# define machine_is_catprovt100() (machine_arch_type == MACH_TYPE_CATPROVT100) -+#else -+# define machine_is_catprovt100() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PICOTUX1XX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PICOTUX1XX -+# endif -+# define machine_is_picotux1xx() (machine_arch_type == MACH_TYPE_PICOTUX1XX) -+#else -+# define machine_is_picotux1xx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PICOTUX2XX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PICOTUX2XX -+# endif -+# define machine_is_picotux2xx() (machine_arch_type == MACH_TYPE_PICOTUX2XX) -+#else -+# define machine_is_picotux2xx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DSMG600 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DSMG600 -+# endif -+# define machine_is_dsmg600() (machine_arch_type == MACH_TYPE_DSMG600) -+#else -+# define machine_is_dsmg600() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EMPC2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EMPC2 -+# endif -+# define machine_is_empc2() (machine_arch_type == MACH_TYPE_EMPC2) -+#else -+# define machine_is_empc2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VENTURA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VENTURA -+# endif -+# define machine_is_ventura() (machine_arch_type == MACH_TYPE_VENTURA) -+#else -+# define machine_is_ventura() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PHIDGET_SBC -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PHIDGET_SBC -+# endif -+# define machine_is_phidget_sbc() (machine_arch_type == MACH_TYPE_PHIDGET_SBC) -+#else -+# define machine_is_phidget_sbc() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IJ3K -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IJ3K -+# endif -+# define machine_is_ij3k() (machine_arch_type == MACH_TYPE_IJ3K) -+#else -+# define machine_is_ij3k() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PISGAH -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PISGAH -+# endif -+# define machine_is_pisgah() (machine_arch_type == MACH_TYPE_PISGAH) -+#else -+# define machine_is_pisgah() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_FSAMPLE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_FSAMPLE -+# endif -+# define machine_is_omap_fsample() (machine_arch_type == MACH_TYPE_OMAP_FSAMPLE) -+#else -+# define machine_is_omap_fsample() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SG720 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SG720 -+# endif -+# define machine_is_sg720() (machine_arch_type == MACH_TYPE_SG720) -+#else -+# define machine_is_sg720() (0) -+#endif -+ -+#ifdef CONFIG_MACH_REDFOX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_REDFOX -+# endif -+# define machine_is_redfox() (machine_arch_type == MACH_TYPE_REDFOX) -+#else -+# define machine_is_redfox() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MYSH_EP9315_1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MYSH_EP9315_1 -+# endif -+# define machine_is_mysh_ep9315_1() (machine_arch_type == MACH_TYPE_MYSH_EP9315_1) -+#else -+# define machine_is_mysh_ep9315_1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TPF106 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TPF106 -+# endif -+# define machine_is_tpf106() (machine_arch_type == MACH_TYPE_TPF106) -+#else -+# define machine_is_tpf106() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AT91RM9200KG -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AT91RM9200KG -+# endif -+# define machine_is_at91rm9200kg() (machine_arch_type == MACH_TYPE_AT91RM9200KG) -+#else -+# define machine_is_at91rm9200kg() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SLEDB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SLEDB -+# endif -+# define machine_is_racemt2() (machine_arch_type == MACH_TYPE_SLEDB) -+#else -+# define machine_is_racemt2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ONTRACK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ONTRACK -+# endif -+# define machine_is_ontrack() (machine_arch_type == MACH_TYPE_ONTRACK) -+#else -+# define machine_is_ontrack() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PM1200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PM1200 -+# endif -+# define machine_is_pm1200() (machine_arch_type == MACH_TYPE_PM1200) -+#else -+# define machine_is_pm1200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ESS24XXX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ESS24XXX -+# endif -+# define machine_is_ess24562() (machine_arch_type == MACH_TYPE_ESS24XXX) -+#else -+# define machine_is_ess24562() (0) -+#endif -+ -+#ifdef CONFIG_MACH_COREMP7 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_COREMP7 -+# endif -+# define machine_is_coremp7() (machine_arch_type == MACH_TYPE_COREMP7) -+#else -+# define machine_is_coremp7() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NEXCODER_6446 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NEXCODER_6446 -+# endif -+# define machine_is_nexcoder_6446() (machine_arch_type == MACH_TYPE_NEXCODER_6446) -+#else -+# define machine_is_nexcoder_6446() (0) -+#endif -+ -+#ifdef CONFIG_MACH_STVC8380 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_STVC8380 -+# endif -+# define machine_is_stvc8380() (machine_arch_type == MACH_TYPE_STVC8380) -+#else -+# define machine_is_stvc8380() (0) -+#endif -+ -+#ifdef CONFIG_MACH_TEKLYNX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_TEKLYNX -+# endif -+# define machine_is_teklynx() (machine_arch_type == MACH_TYPE_TEKLYNX) -+#else -+# define machine_is_teklynx() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CARBONADO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CARBONADO -+# endif -+# define machine_is_carbonado() (machine_arch_type == MACH_TYPE_CARBONADO) -+#else -+# define machine_is_carbonado() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SYSMOS_MP730 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SYSMOS_MP730 -+# endif -+# define machine_is_sysmos_mp730() (machine_arch_type == MACH_TYPE_SYSMOS_MP730) -+#else -+# define machine_is_sysmos_mp730() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SNAPPER_CL15 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SNAPPER_CL15 -+# endif -+# define machine_is_snapper_cl15() (machine_arch_type == MACH_TYPE_SNAPPER_CL15) -+#else -+# define machine_is_snapper_cl15() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PGIGIM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PGIGIM -+# endif -+# define machine_is_pgigim() (machine_arch_type == MACH_TYPE_PGIGIM) -+#else -+# define machine_is_pgigim() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PTX9160P2 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PTX9160P2 -+# endif -+# define machine_is_ptx9160p2() (machine_arch_type == MACH_TYPE_PTX9160P2) -+#else -+# define machine_is_ptx9160p2() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DCORE1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DCORE1 -+# endif -+# define machine_is_dcore1() (machine_arch_type == MACH_TYPE_DCORE1) -+#else -+# define machine_is_dcore1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VICTORPXA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VICTORPXA -+# endif -+# define machine_is_victorpxa() (machine_arch_type == MACH_TYPE_VICTORPXA) -+#else -+# define machine_is_victorpxa() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MX2DTB -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MX2DTB -+# endif -+# define machine_is_mx2dtb() (machine_arch_type == MACH_TYPE_MX2DTB) -+#else -+# define machine_is_mx2dtb() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PXA_IREX_ER0100 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PXA_IREX_ER0100 -+# endif -+# define machine_is_pxa_irex_er0100() (machine_arch_type == MACH_TYPE_PXA_IREX_ER0100) -+#else -+# define machine_is_pxa_irex_er0100() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_PALMZ71 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_PALMZ71 -+# endif -+# define machine_is_omap_palmz71() (machine_arch_type == MACH_TYPE_OMAP_PALMZ71) -+#else -+# define machine_is_omap_palmz71() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BARTEC_DEG -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BARTEC_DEG -+# endif -+# define machine_is_bartec_deg() (machine_arch_type == MACH_TYPE_BARTEC_DEG) -+#else -+# define machine_is_bartec_deg() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HW50251 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HW50251 -+# endif -+# define machine_is_hw50251() (machine_arch_type == MACH_TYPE_HW50251) -+#else -+# define machine_is_hw50251() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IBOX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IBOX -+# endif -+# define machine_is_ibox() (machine_arch_type == MACH_TYPE_IBOX) -+#else -+# define machine_is_ibox() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ATLASLH7A404 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ATLASLH7A404 -+# endif -+# define machine_is_atlaslh7a404() (machine_arch_type == MACH_TYPE_ATLASLH7A404) -+#else -+# define machine_is_atlaslh7a404() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PT2026 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PT2026 -+# endif -+# define machine_is_pt2026() (machine_arch_type == MACH_TYPE_PT2026) -+#else -+# define machine_is_pt2026() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HTCALPINE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HTCALPINE -+# endif -+# define machine_is_htcalpine() (machine_arch_type == MACH_TYPE_HTCALPINE) -+#else -+# define machine_is_htcalpine() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BARTEC_VTU -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BARTEC_VTU -+# endif -+# define machine_is_bartec_vtu() (machine_arch_type == MACH_TYPE_BARTEC_VTU) -+#else -+# define machine_is_bartec_vtu() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VCOREII -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VCOREII -+# endif -+# define machine_is_vcoreii() (machine_arch_type == MACH_TYPE_VCOREII) -+#else -+# define machine_is_vcoreii() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PDNB3 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PDNB3 -+# endif -+# define machine_is_pdnb3() (machine_arch_type == MACH_TYPE_PDNB3) -+#else -+# define machine_is_pdnb3() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HTCBEETLES -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HTCBEETLES -+# endif -+# define machine_is_htcbeetles() (machine_arch_type == MACH_TYPE_HTCBEETLES) -+#else -+# define machine_is_htcbeetles() (0) -+#endif -+ -+#ifdef CONFIG_MACH_S3C6400 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_S3C6400 -+# endif -+# define machine_is_s3c6400() (machine_arch_type == MACH_TYPE_S3C6400) -+#else -+# define machine_is_s3c6400() (0) -+#endif -+ -+#ifdef CONFIG_MACH_S3C2443 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_S3C2443 -+# endif -+# define machine_is_s3c2443() (machine_arch_type == MACH_TYPE_S3C2443) -+#else -+# define machine_is_s3c2443() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OMAP_LDK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OMAP_LDK -+# endif -+# define machine_is_omap_ldk() (machine_arch_type == MACH_TYPE_OMAP_LDK) -+#else -+# define machine_is_omap_ldk() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SMDK2460 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SMDK2460 -+# endif -+# define machine_is_smdk2460() (machine_arch_type == MACH_TYPE_SMDK2460) -+#else -+# define machine_is_smdk2460() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SMDK2440 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SMDK2440 -+# endif -+# define machine_is_smdk2440() (machine_arch_type == MACH_TYPE_SMDK2440) -+#else -+# define machine_is_smdk2440() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SMDK2412 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SMDK2412 -+# endif -+# define machine_is_smdk2412() (machine_arch_type == MACH_TYPE_SMDK2412) -+#else -+# define machine_is_smdk2412() (0) -+#endif -+ -+#ifdef CONFIG_MACH_WEBBOX -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_WEBBOX -+# endif -+# define machine_is_webbox() (machine_arch_type == MACH_TYPE_WEBBOX) -+#else -+# define machine_is_webbox() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CWWNDP -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CWWNDP -+# endif -+# define machine_is_cwwndp() (machine_arch_type == MACH_TYPE_CWWNDP) -+#else -+# define machine_is_cwwndp() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DRAGON -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DRAGON -+# endif -+# define machine_is_dragon() (machine_arch_type == MACH_TYPE_DRAGON) -+#else -+# define machine_is_dragon() (0) -+#endif -+ -+#ifdef CONFIG_MACH_OPENDO_CPU_BOARD -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_OPENDO_CPU_BOARD -+# endif -+# define machine_is_opendo_cpu_board() (machine_arch_type == MACH_TYPE_OPENDO_CPU_BOARD) -+#else -+# define machine_is_opendo_cpu_board() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CCM2200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CCM2200 -+# endif -+# define machine_is_ccm2200() (machine_arch_type == MACH_TYPE_CCM2200) -+#else -+# define machine_is_ccm2200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ETWARM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ETWARM -+# endif -+# define machine_is_etwarm() (machine_arch_type == MACH_TYPE_ETWARM) -+#else -+# define machine_is_etwarm() (0) -+#endif -+ -+#ifdef CONFIG_MACH_M93030 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_M93030 -+# endif -+# define machine_is_m93030() (machine_arch_type == MACH_TYPE_M93030) -+#else -+# define machine_is_m93030() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CC7U -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CC7U -+# endif -+# define machine_is_cc7u() (machine_arch_type == MACH_TYPE_CC7U) -+#else -+# define machine_is_cc7u() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MTT_RANGER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MTT_RANGER -+# endif -+# define machine_is_mtt_ranger() (machine_arch_type == MACH_TYPE_MTT_RANGER) -+#else -+# define machine_is_mtt_ranger() (0) -+#endif -+ -+#ifdef CONFIG_MACH_NEXUS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_NEXUS -+# endif -+# define machine_is_nexus() (machine_arch_type == MACH_TYPE_NEXUS) -+#else -+# define machine_is_nexus() (0) -+#endif -+ -+#ifdef CONFIG_MACH_DESMAN -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_DESMAN -+# endif -+# define machine_is_desman() (machine_arch_type == MACH_TYPE_DESMAN) -+#else -+# define machine_is_desman() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BKDE303 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BKDE303 -+# endif -+# define machine_is_bkde303() (machine_arch_type == MACH_TYPE_BKDE303) -+#else -+# define machine_is_bkde303() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SMDK2413 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SMDK2413 -+# endif -+# define machine_is_smdk2413() (machine_arch_type == MACH_TYPE_SMDK2413) -+#else -+# define machine_is_smdk2413() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AML_M7200 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AML_M7200 -+# endif -+# define machine_is_aml_m7200() (machine_arch_type == MACH_TYPE_AML_M7200) -+#else -+# define machine_is_aml_m7200() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AML_M5900 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AML_M5900 -+# endif -+# define machine_is_aml_m5900() (machine_arch_type == MACH_TYPE_AML_M5900) -+#else -+# define machine_is_aml_m5900() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SG640 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SG640 -+# endif -+# define machine_is_sg640() (machine_arch_type == MACH_TYPE_SG640) -+#else -+# define machine_is_sg640() (0) -+#endif -+ -+#ifdef CONFIG_MACH_EDG79524 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_EDG79524 -+# endif -+# define machine_is_edg79524() (machine_arch_type == MACH_TYPE_EDG79524) -+#else -+# define machine_is_edg79524() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AI2410 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AI2410 -+# endif -+# define machine_is_ai2410() (machine_arch_type == MACH_TYPE_AI2410) -+#else -+# define machine_is_ai2410() (0) -+#endif -+ -+#ifdef CONFIG_MACH_IXP465 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_IXP465 -+# endif -+# define machine_is_ixp465() (machine_arch_type == MACH_TYPE_IXP465) -+#else -+# define machine_is_ixp465() (0) -+#endif -+ -+#ifdef CONFIG_MACH_BALLOON3 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_BALLOON3 -+# endif -+# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3) -+#else -+# define machine_is_balloon3() (0) -+#endif -+ -+#ifdef CONFIG_MACH_HEINS -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_HEINS -+# endif -+# define machine_is_heins() (machine_arch_type == MACH_TYPE_HEINS) -+#else -+# define machine_is_heins() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MPLUSEVA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MPLUSEVA -+# endif -+# define machine_is_mpluseva() (machine_arch_type == MACH_TYPE_MPLUSEVA) -+#else -+# define machine_is_mpluseva() (0) -+#endif -+ -+#ifdef CONFIG_MACH_RT042 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_RT042 -+# endif -+# define machine_is_rt042() (machine_arch_type == MACH_TYPE_RT042) -+#else -+# define machine_is_rt042() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CWIEM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CWIEM -+# endif -+# define machine_is_cwiem() (machine_arch_type == MACH_TYPE_CWIEM) -+#else -+# define machine_is_cwiem() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CM_X270 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CM_X270 -+# endif -+# define machine_is_cm_x270() (machine_arch_type == MACH_TYPE_CM_X270) -+#else -+# define machine_is_cm_x270() (0) -+#endif -+ -+#ifdef CONFIG_MACH_CM_X255 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_CM_X255 -+# endif -+# define machine_is_cm_x255() (machine_arch_type == MACH_TYPE_CM_X255) -+#else -+# define machine_is_cm_x255() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ESH_AT91 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ESH_AT91 -+# endif -+# define machine_is_esh_at91() (machine_arch_type == MACH_TYPE_ESH_AT91) -+#else -+# define machine_is_esh_at91() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SANDGATE3 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SANDGATE3 -+# endif -+# define machine_is_sandgate3() (machine_arch_type == MACH_TYPE_SANDGATE3) -+#else -+# define machine_is_sandgate3() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PRIMO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PRIMO -+# endif -+# define machine_is_primo() (machine_arch_type == MACH_TYPE_PRIMO) -+#else -+# define machine_is_primo() (0) -+#endif -+ -+#ifdef CONFIG_MACH_GEMSTONE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_GEMSTONE -+# endif -+# define machine_is_gemstone() (machine_arch_type == MACH_TYPE_GEMSTONE) -+#else -+# define machine_is_gemstone() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PRONGHORNMETRO -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PRONGHORNMETRO -+# endif -+# define machine_is_pronghorn_metro() (machine_arch_type == MACH_TYPE_PRONGHORNMETRO) -+#else -+# define machine_is_pronghorn_metro() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SIDEWINDER -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SIDEWINDER -+# endif -+# define machine_is_sidewinder() (machine_arch_type == MACH_TYPE_SIDEWINDER) -+#else -+# define machine_is_sidewinder() (0) -+#endif -+ -+#ifdef CONFIG_MACH_PICOMOD1 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_PICOMOD1 -+# endif -+# define machine_is_picomod1() (machine_arch_type == MACH_TYPE_PICOMOD1) -+#else -+# define machine_is_picomod1() (0) -+#endif -+ -+#ifdef CONFIG_MACH_SG590 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_SG590 -+# endif -+# define machine_is_sg590() (machine_arch_type == MACH_TYPE_SG590) -+#else -+# define machine_is_sg590() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AKAI9307 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AKAI9307 -+# endif -+# define machine_is_akai9307() (machine_arch_type == MACH_TYPE_AKAI9307) -+#else -+# define machine_is_akai9307() (0) -+#endif -+ -+#ifdef CONFIG_MACH_FONTAINE -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_FONTAINE -+# endif -+# define machine_is_fontaine() (machine_arch_type == MACH_TYPE_FONTAINE) -+#else -+# define machine_is_fontaine() (0) -+#endif -+ -+#ifdef CONFIG_MACH_WOMBAT -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_WOMBAT -+# endif -+# define machine_is_wombat() (machine_arch_type == MACH_TYPE_WOMBAT) -+#else -+# define machine_is_wombat() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ACQ300 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ACQ300 -+# endif -+# define machine_is_acq300() (machine_arch_type == MACH_TYPE_ACQ300) -+#else -+# define machine_is_acq300() (0) -+#endif -+ -+#ifdef CONFIG_MACH_MOD_270 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_MOD_270 -+# endif -+# define machine_is_mod_270() (machine_arch_type == MACH_TYPE_MOD_270) -+#else -+# define machine_is_mod_270() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VC0820 -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VC0820 -+# endif -+# define machine_is_vmc_vc0820() (machine_arch_type == MACH_TYPE_VC0820) -+#else -+# define machine_is_vmc_vc0820() (0) -+#endif -+ -+#ifdef CONFIG_MACH_ANI_AIM -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_ANI_AIM -+# endif -+# define machine_is_ani_aim() (machine_arch_type == MACH_TYPE_ANI_AIM) -+#else -+# define machine_is_ani_aim() (0) -+#endif -+ -+#ifdef CONFIG_MACH_JELLYFISH -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_JELLYFISH -+# endif -+# define machine_is_jellyfish() (machine_arch_type == MACH_TYPE_JELLYFISH) -+#else -+# define machine_is_jellyfish() (0) -+#endif -+ -+#ifdef CONFIG_MACH_AMANITA -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_AMANITA -+# endif -+# define machine_is_amanita() (machine_arch_type == MACH_TYPE_AMANITA) -+#else -+# define machine_is_amanita() (0) -+#endif -+ -+#ifdef CONFIG_MACH_VLINK -+# ifdef machine_arch_type -+# undef machine_arch_type -+# define machine_arch_type __machine_arch_type -+# else -+# define machine_arch_type MACH_TYPE_VLINK -+# endif -+# define machine_is_vlink() (machine_arch_type == MACH_TYPE_VLINK) -+#else -+# define machine_is_vlink() (0) -+#endif -+ - /* - * These have not yet been registered - */ -diff -Naur u-boot-1.1.4.org/include/config.h u-boot-1.1.4.tmp/include/config.h ---- u-boot-1.1.4.org/include/config.h 2006-06-05 05:04:25.000000000 +0200 -+++ u-boot-1.1.4.tmp/include/config.h 2006-06-05 05:03:47.000000000 +0200 -@@ -1,2 +1,2 @@ - /* Automatically generated - do not edit */ --#include -+#include -diff -Naur u-boot-1.1.4.org/include/config.mk u-boot-1.1.4.tmp/include/config.mk ---- u-boot-1.1.4.org/include/config.mk 2006-06-05 05:04:25.000000000 +0200 -+++ u-boot-1.1.4.tmp/include/config.mk 2006-06-05 05:03:47.000000000 +0200 -@@ -1,4 +1,4 @@ - ARCH = arm - CPU = arm920t --BOARD = at91rm9200dk -+BOARD = vlink - SOC = at91rm9200 -diff -Naur u-boot-1.1.4.org/include/configs/vlink.h u-boot-1.1.4.tmp/include/configs/vlink.h ---- u-boot-1.1.4.org/include/configs/vlink.h 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4.tmp/include/configs/vlink.h 2006-06-05 03:37:15.000000000 +0200 -@@ -0,0 +1,244 @@ -+/* -+ * Hamish Guthrie -+ * -+ * Configuation settings for the Figment Designs Versalink board. -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+// Added 2 defines to skip re-init lowlevel and relocate HCG HLH -+// -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SKIP_RELOCATE_UBOOT -+ -+/* ARM asynchronous clock */ -+#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ -+#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ -+/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ -+ -+#define AT91_SLOW_CLOCK 32768 /* slow clock */ -+ -+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -+#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -+#define CONFIG_VLINK 1 /* on a Versalink Board */ -+#define CONFIG_IDENT_STRING " FDL Versalink" -+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -+#define USE_920T_MMU 1 -+ -+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -+#define CONFIG_SETUP_MEMORY_TAGS 1 -+#define CONFIG_INITRD_TAG 1 -+ -+#ifndef CONFIG_SKIP_LOWLEVEL_INIT -+#define CFG_USE_MAIN_OSCILLATOR 1 -+/* flash */ -+#define MC_PUIA_VAL 0x00000000 -+#define MC_PUP_VAL 0x00000000 -+#define MC_PUER_VAL 0x00000000 -+#define MC_ASR_VAL 0x00000000 -+#define MC_AASR_VAL 0x00000000 -+#define EBI_CFGR_VAL 0x00000000 -+#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ -+ -+/* clocks */ -+#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -+#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -+#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -+ -+/* sdram */ -+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -+#define PIOC_BSR_VAL 0x00000000 -+#define PIOC_PDR_VAL 0xFFFF0000 -+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -+#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -+#define SDRAM 0x20000000 /* address of the SDRAM */ -+#define SDRAM1 0x20000080 /* address of the SDRAM */ -+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -+#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -+#define SDRC_MR_VAL1 0x00000004 /* refresh */ -+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -+/* -+ * Size of malloc() pool -+ */ -+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -+ -+#define CONFIG_BAUDRATE 115200 -+ -+/* -+ * Hardware drivers -+ */ -+ -+/* define one of these to choose the DBGU, USART0 or USART1 as console */ -+#define CONFIG_DBGU -+#undef CONFIG_USART0 -+#undef CONFIG_USART1 -+ -+#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ -+ -+#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ -+ -+#define CONFIG_BOOTDELAY 3 -+/* #define CONFIG_ENV_OVERWRITE 1 */ -+ -+#define CONFIG_COMMANDS \ -+ ((CONFIG_CMD_DFL | CFG_CMD_MII |\ -+ CFG_CMD_DHCP ) & \ -+ ~(CFG_CMD_BDI | \ -+ CFG_CMD_IMI | \ -+ CFG_CMD_AUTOSCRIPT | \ -+ CFG_CMD_FPGA | \ -+ CFG_CMD_MISC | \ -+ CFG_CMD_LOADS )) -+ -+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -+#include -+ -+#ifndef CONFIG_VLINK -+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -+#define SECTORSIZE 512 -+ -+#define ADDR_COLUMN 1 -+#define ADDR_PAGE 2 -+#define ADDR_COLUMN_PAGE 3 -+ -+#define NAND_ChipID_UNKNOWN 0x00 -+#define NAND_MAX_FLOORS 1 -+#define NAND_MAX_CHIPS 1 -+ -+#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -+#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ -+ -+#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) -+#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) -+ -+#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) -+ -+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) -+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) -+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -+/* the following are NOP's in our implementation */ -+#define NAND_CTL_CLRALE(nandptr) -+#define NAND_CTL_SETALE(nandptr) -+#define NAND_CTL_CLRCLE(nandptr) -+#define NAND_CTL_SETCLE(nandptr) -+#endif -+ -+#define CONFIG_NR_DRAM_BANKS 1 -+#define PHYS_SDRAM 0x20000000 -+#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ -+ -+#define CFG_MEMTEST_START PHYS_SDRAM -+#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 -+ -+#define CONFIG_DRIVER_ETHER -+#define CONFIG_NET_RETRY_COUNT 20 -+#define CONFIG_AT91C_USE_RMII -+ -+#define CONFIG_HAS_DATAFLASH 1 -+#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) -+#define CFG_MAX_DATAFLASH_BANKS 2 -+#define CFG_MAX_DATAFLASH_PAGES 16384 -+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ -+#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ -+ -+#ifdef CONFIG_VLINK -+#define PHYS_FLASH_1 0x10000000 -+#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ -+#define CFG_FLASH_BASE PHYS_FLASH_1 -+#define CFG_MAX_FLASH_BANKS 1 -+#define CFG_MAX_FLASH_SECT 256 -+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -+#endif -+ -+#define CFG_ENV_IS_IN_DATAFLASH -+ -+#ifdef CFG_ENV_IS_IN_DATAFLASH -+#define CFG_ENV_OFFSET 0x21000 -+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) -+#define CFG_ENV_SIZE 0x8400 /* 0x8000 */ -+#else -+#define CFG_ENV_IS_IN_FLASH 1 -+#ifdef CONFIG_SKIP_LOWLEVEL_INIT -+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ -+#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */ -+#else -+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ -+#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -+#endif /* CFG_ENV_IS_IN_DATAFLASH */ -+ -+ -+#define CFG_LOAD_ADDR 0x21000000 /* default load address */ -+ -+#ifdef CONFIG_SKIP_LOWLEVEL_INIT -+#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ -+#define CFG_U_BOOT_BASE PHYS_FLASH_1 -+#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */ -+#else -+#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ -+#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) -+#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ -+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -+ -+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } -+ -+#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ -+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -+#define CFG_MAXARGS 16 /* max number of command args */ -+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -+ -+#ifndef __ASSEMBLY__ -+/*----------------------------------------------------------------------- -+ * Board specific extension for bd_info -+ * -+ * This structure is embedded in the global bd_info (bd_t) structure -+ * and can be used by the board specific code (eg board/...) -+ */ -+ -+struct bd_info_ext { -+ /* helper variable for board environment handling -+ * -+ * env_crc_valid == 0 => uninitialised -+ * env_crc_valid > 0 => environment crc in flash is valid -+ * env_crc_valid < 0 => environment crc in flash is invalid -+ */ -+ int env_crc_valid; -+}; -+#endif -+ -+#define CFG_HZ 1000 -+#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ -+ /* AT91C_TC_TIMER_DIV1_CLOCK */ -+ -+#define CONFIG_STACKSIZE (32*1024) /* regular stack */ -+ -+#ifdef CONFIG_USE_IRQ -+#error CONFIG_USE_IRQ not supported -+#endif -+ -+#endif -diff -Naur u-boot-1.1.4.org/MAKEALL u-boot-1.1.4.tmp/MAKEALL ---- u-boot-1.1.4.org/MAKEALL 2005-12-16 17:39:27.000000000 +0100 -+++ u-boot-1.1.4.tmp/MAKEALL 2006-06-05 02:44:24.000000000 +0200 -@@ -180,7 +180,7 @@ - mx1ads mx1fs2 omap1510inn omap1610h2 \ - omap1610inn omap730p2 scb9328 smdk2400 \ - smdk2410 trab VCMA9 versatile \ -- versatileab versatilepb voiceblue -+ versatileab versatilepb voiceblue vlink - " - - ######################################################################### -diff -Naur u-boot-1.1.4.org/Makefile u-boot-1.1.4.tmp/Makefile ---- u-boot-1.1.4.org/Makefile 2006-06-02 15:58:57.000000000 +0200 -+++ u-boot-1.1.4.tmp/Makefile 2006-06-05 04:40:45.000000000 +0200 -@@ -1419,6 +1419,9 @@ - mp2usb_config : unconfig - @./mkconfig $(@:_config=) arm arm920t mp2usb NULL at91rm9200 - -+vlink_config : unconfig -+ @./mkconfig $(@:_config=) arm arm920t vlink NULL at91rm9200 -+ - - ######################################################################## - ## ARM Integrator boards - see doc/README-integrator for more info. diff --git a/target/linux/at91/image/u-boot/patches/003-mac_init.patch b/target/linux/at91/image/u-boot/patches/003-mac_init.patch deleted file mode 100644 index ec5dffa0c..000000000 --- a/target/linux/at91/image/u-boot/patches/003-mac_init.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- u-boot-1.1.4.org/lib_arm/board.c 2006-06-05 12:36:22.000000000 +0200 -+++ u-boot-1.1.4.tmp/lib_arm/board.c 2006-06-05 12:36:44.000000000 +0200 -@@ -332,6 +332,11 @@ - } - #endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ - -+#ifdef CONFIG_MACH_VLINK -+ printf("Initialising MAC address\n\r"); -+ eth_init(gd->bd); -+#endif -+ - /* Initialize from environment */ - if ((s = getenv ("loadaddr")) != NULL) { - load_addr = simple_strtoul (s, NULL, 16); diff --git a/target/linux/at91/image/u-boot/patches/004-mac_config.patch b/target/linux/at91/image/u-boot/patches/004-mac_config.patch deleted file mode 100644 index 73a8260d6..000000000 --- a/target/linux/at91/image/u-boot/patches/004-mac_config.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- u-boot-1.1.4.ttt/include/configs/vlink.h 2006-06-05 15:57:37.000000000 +0200 -+++ u-boot-1.1.4/include/configs/vlink.h 2006-06-07 13:11:01.000000000 +0200 -@@ -105,9 +105,9 @@ - - #define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | CFG_CMD_MII |\ -- CFG_CMD_DHCP ) & \ -- ~(CFG_CMD_BDI | \ -- CFG_CMD_IMI | \ -+ CFG_CMD_DHCP | \ -+ CFG_CMD_BDI ) & \ -+ ~(CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ diff --git a/target/linux/at91/image/u-boot/patches/005-remove_float.patch b/target/linux/at91/image/u-boot/patches/005-remove_float.patch deleted file mode 100644 index 802c96339..000000000 --- a/target/linux/at91/image/u-boot/patches/005-remove_float.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff -urN u-boot-1.1.4.old/cpu/arm920t/config.mk u-boot-1.1.4/cpu/arm920t/config.mk ---- u-boot-1.1.4.old/cpu/arm920t/config.mk 2007-03-19 12:44:39.000000000 +0100 -+++ u-boot-1.1.4/cpu/arm920t/config.mk 2007-03-20 09:23:54.000000000 +0100 -@@ -21,8 +21,7 @@ - # MA 02111-1307 USA - # - --PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ -- -msoft-float -+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 - - PLATFORM_CPPFLAGS += -march=armv4 - # ========================================================================= diff --git a/target/linux/at91/image/u-boot/patches/006-generate_params.patch b/target/linux/at91/image/u-boot/patches/006-generate_params.patch deleted file mode 100644 index d4427c3ec..000000000 --- a/target/linux/at91/image/u-boot/patches/006-generate_params.patch +++ /dev/null @@ -1,115 +0,0 @@ ---- u-boot-1.1.4.old/tools/Makefile 2007-03-22 18:17:25.000000000 +0100 -+++ u-boot-1.1.4/tools/Makefile 2007-03-22 17:08:46.000000000 +0100 -@@ -21,9 +21,9 @@ - # MA 02111-1307 USA - # - --BINS = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) -+BINS = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) ubparams$(SFX) - --OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o -+OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o ubparams.o - - ifeq ($(ARCH),mips) - BINS += inca-swap-bytes$(SFX) -@@ -118,6 +118,9 @@ - - all: .depend $(BINS) $(LOGO_H) subdirs - -+ubparams$(SFX): ubparams.o crc32.o -+ $(CC) $(CFLAGS) -o $@ $^ -+ - envcrc$(SFX): envcrc.o crc32.o environment.o - $(CC) $(CFLAGS) -o $@ $^ - -@@ -149,6 +152,9 @@ - $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ - $(STRIP) $@ - -+ubparams.o: ubparams.c -+ $(CC) -g $(CFLAGS) -c $< -+ - envcrc.o: envcrc.c - $(CC) -g $(CFLAGS) -c $< - ---- u-boot-1.1.4.old/tools/ubparams.c 1970-01-01 01:00:00.000000000 +0100 -+++ u-boot-1.1.4/tools/ubparams.c 2007-03-22 18:09:52.000000000 +0100 -@@ -0,0 +1,78 @@ -+/* -+ * ubparams.c -+ * -+ * Generate a u-boot parameter block with correct crc -+ * -+ * (C) 1007 Guthrie Consulting -+ * hamish@prodigi.ch -+ * -+ */ -+ -+#include -+#include -+#include -+ -+#ifndef __ASSEMBLY__ -+#define __ASSEMBLY__ -+#endif -+#define __ASM_STUB_PROCESSOR_H__ -+#include -+#undef __ASSEMBLY__ -+#include "environment.h" -+ -+#define XMK_STR(x) #x -+#define MK_STR(x) XMK_STR(x) -+ -+extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); -+ -+#if !defined(ENV_CRC) -+#define ENV_CRC ~0 -+#endif -+ -+unsigned int env_size = 0x8400; -+env_t environment = { -+ ENV_CRC, -+ "bootdelay=3\0" -+ "baudrate=115200\0" -+ "stdin=serial\0" -+ "stdout=serial\0" -+ "stderr=serial\0" -+ "partitions=mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data)\0" -+ "fbargs=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/mtdblock4 ro console=/dev/ttyS0,115200,mem=32M\0" -+ "rdba=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 console=/dev/ttyS0,115200,mem=32M\0" -+ "rdram=run rdba; tftp 21000000 vImage; tftp 21200000 root.squashfs; bootm 21000000\0" -+ "flash=run fbargs; bootm 0xc0042000\0" -+ "bootargs=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/mtdblock4 ro console=/dev/ttyS0,115200,mem=32M\0" -+ "bootcmd=bootm 0xc0042000\0" -+ "ethaddr=00:30:49:00:00:01\0" -+ "ipaddr=10.0.1.73\0" -+ "serverip=10.0.1.210\0" -+ "serial#=MX070205484\0" -+ "\0" -+ }; -+ -+int main(void) { -+ env_t *envptr, *source; -+ unsigned char *dataptr; -+ FILE *params; -+ -+ source = &environment; -+ envptr = (env_t *)malloc(CFG_ENV_SIZE); -+ dataptr = (unsigned char *)envptr + ENV_HEADER_SIZE; -+ -+ printf("Make u-boot params\n"); -+ printf("Params size is %d\n", CFG_ENV_SIZE); -+ -+ memset(envptr, 0, CFG_ENV_SIZE); -+ memcpy(envptr, source, sizeof(environment)); -+ -+ envptr->crc = crc32(0, envptr->data, ENV_SIZE); -+ -+ params = fopen("params", "w"); -+ fwrite(envptr, CFG_ENV_SIZE, 1, params); -+ fclose(params); -+ -+ free(envptr); -+ } -+ -+ diff --git a/target/linux/at91/image/u-boot/patches/007-ubparams_bugfix.patch b/target/linux/at91/image/u-boot/patches/007-ubparams_bugfix.patch deleted file mode 100644 index 3d069e4d3..000000000 --- a/target/linux/at91/image/u-boot/patches/007-ubparams_bugfix.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- u-boot-1.1.4.old/tools/ubparams.c 2007-03-22 18:09:52.000000000 +0100 -+++ u-boot-1.1.4/tools/ubparams.c 2007-03-22 18:29:32.000000000 +0100 -@@ -18,7 +18,7 @@ - #define __ASM_STUB_PROCESSOR_H__ - #include - #undef __ASSEMBLY__ --#include "environment.h" -+#include - - #define XMK_STR(x) #x - #define MK_STR(x) XMK_STR(x) diff --git a/target/linux/at91/image/u-boot/patches/008-ubparams_bugfix.patch b/target/linux/at91/image/u-boot/patches/008-ubparams_bugfix.patch deleted file mode 100644 index 9a16e1998..000000000 --- a/target/linux/at91/image/u-boot/patches/008-ubparams_bugfix.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- u-boot-1.1.4.old/tools/ubparams.c 2007-03-23 10:51:17.000000000 +0100 -+++ u-boot-1.1.4/tools/ubparams.c 2007-03-23 10:49:37.000000000 +0100 -@@ -73,6 +73,7 @@ - fclose(params); - - free(envptr); -+ return 0; - } - - diff --git a/target/linux/at91/image/u-boot/patches/009-mac_init_bugfix.patch b/target/linux/at91/image/u-boot/patches/009-mac_init_bugfix.patch deleted file mode 100644 index a36ebe325..000000000 --- a/target/linux/at91/image/u-boot/patches/009-mac_init_bugfix.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -urN u-boot-1.1.4.old/lib_arm/board.c u-boot-1.1.4/lib_arm/board.c ---- u-boot-1.1.4.old/lib_arm/board.c 2007-03-23 10:53:52.000000000 +0100 -+++ u-boot-1.1.4/lib_arm/board.c 2007-03-24 13:17:12.000000000 +0100 -@@ -332,7 +332,7 @@ - } - #endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ - --#ifdef CONFIG_MACH_VLINK -+#ifdef CONFIG_VLINK - printf("Initialising MAC address\n\r"); - eth_init(gd->bd); - #endif diff --git a/target/linux/at91/image/u-boot/patches/010-irda-patch-remove.patch b/target/linux/at91/image/u-boot/patches/010-irda-patch-remove.patch deleted file mode 100644 index 2f23f5b38..000000000 --- a/target/linux/at91/image/u-boot/patches/010-irda-patch-remove.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- u-boot-1.1.4.old/board/vlink/vlink.c 2007-04-03 11:42:39.000000000 +0200 -+++ u-boot-1.1.4/board/vlink/vlink.c 2007-04-03 11:48:33.000000000 +0200 -@@ -40,10 +40,6 @@ - /* Enable Ctrlc */ - console_init_f (); - -- /* Correct IRDA resistor problem */ -- /* Set PA23_TXD in Output */ -- (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; -- - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - diff --git a/target/linux/at91/image/u-boot/patches/011-ubparams_update.patch b/target/linux/at91/image/u-boot/patches/011-ubparams_update.patch deleted file mode 100644 index de02cc88c..000000000 --- a/target/linux/at91/image/u-boot/patches/011-ubparams_update.patch +++ /dev/null @@ -1,19 +0,0 @@ -diff -urN u-boot-1.1.4.old/tools/ubparams.c u-boot-1.1.4/tools/ubparams.c ---- u-boot-1.1.4.old/tools/ubparams.c 2007-05-01 13:20:17.000000000 +0200 -+++ u-boot-1.1.4/tools/ubparams.c 2007-05-04 10:13:34.000000000 +0200 -@@ -37,12 +37,11 @@ - "stdin=serial\0" - "stdout=serial\0" - "stderr=serial\0" -- "partitions=mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data)\0" -- "fbargs=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/mtdblock4 ro console=/dev/ttyS0,115200,mem=32M\0" -- "rdba=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 console=/dev/ttyS0,115200,mem=32M\0" -+ "fbargs=setenv bootargs root=/dev/mtdblock3 ro console=/dev/ttyS0,115200,mem=32M\0" -+ "rdba=setenv bootargs root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 console=/dev/ttyS0,115200,mem=32M\0" - "rdram=run rdba; tftp 21000000 vImage; tftp 21200000 root.squashfs; bootm 21000000\0" - "flash=run fbargs; bootm 0xc0042000\0" -- "bootargs=setenv bootargs mtdparts=AT45DB642.spi0:132k(bootloader),33k(ubparams),99k(spare),1056k(linux),2112k(rootfs),33k(nvram),-(rootfs_data) root=/dev/mtdblock4 ro console=/dev/ttyS0,115200,mem=32M\0" -+ "bootargs=setenv bootargs root=/dev/mtdblock3 ro console=/dev/ttyS0,115200,mem=32M\0" - "bootcmd=bootm 0xc0042000\0" - "ethaddr=00:30:49:00:00:01\0" - "ipaddr=10.0.1.73\0" diff --git a/target/linux/at91/image/u-boot/patches/012-make_3.81.patch b/target/linux/at91/image/u-boot/patches/012-make_3.81.patch deleted file mode 100644 index 767493f90..000000000 --- a/target/linux/at91/image/u-boot/patches/012-make_3.81.patch +++ /dev/null @@ -1,16 +0,0 @@ -diff -urN u-boot-1.1.4.orig/examples/Makefile u-boot-1.1.4/examples/Makefile ---- u-boot-1.1.4.orig/examples/Makefile 2007-05-13 13:45:44.000000000 +0200 -+++ u-boot-1.1.4/examples/Makefile 2007-05-13 13:48:43.000000000 +0200 -@@ -123,10 +123,10 @@ - $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ - -o $@ -e $(<:.o=) $< $(LIB) \ - -L$(gcclibdir) -lgcc --%.srec: % -+%.srec: %.o - $(OBJCOPY) -O srec $< $@ 2>/dev/null - --%.bin: % -+%.bin: %.o - $(OBJCOPY) -O binary $< $@ 2>/dev/null - - ######################################################################### diff --git a/target/linux/at91/image/u-boot/patches/013-params-in-config.patch b/target/linux/at91/image/u-boot/patches/013-params-in-config.patch deleted file mode 100644 index 5f4220923..000000000 --- a/target/linux/at91/image/u-boot/patches/013-params-in-config.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- u-boot-1.1.4.old/tools/Makefile 2007-06-13 13:35:59.000000000 +0200 -+++ u-boot-1.1.4/tools/Makefile 2007-06-14 15:33:04.000000000 +0200 -@@ -153,7 +153,7 @@ - $(STRIP) $@ - - ubparams.o: ubparams.c -- $(CC) -g $(CFLAGS) -c $< -+ $(CC) -g $(CFLAGS) -DLAN_IP=$(LAN_IP) -DLAN_SERVERIP=$(LAN_SERVERIP) -c $< - - envcrc.o: envcrc.c - $(CC) -g $(CFLAGS) -c $< ---- u-boot-1.1.4.old/tools/ubparams.c 2007-06-13 13:35:59.000000000 +0200 -+++ u-boot-1.1.4/tools/ubparams.c 2007-06-14 15:31:55.000000000 +0200 -@@ -44,8 +44,8 @@ - "bootargs=setenv bootargs root=/dev/mtdblock3 ro console=/dev/ttyS0,115200,mem=32M\0" - "bootcmd=bootm 0xc0042000\0" - "ethaddr=00:30:49:00:00:01\0" -- "ipaddr=10.0.1.73\0" -- "serverip=10.0.1.210\0" -+ "ipaddr=" MK_STR(LAN_IP) "\0" -+ "serverip=" MK_STR(LAN_SERVERIP) "\0" - "serial#=MX070205484\0" - "\0" - }; diff --git a/target/linux/at91/image/u-boot/patches/014-ubparam-kernel.patch b/target/linux/at91/image/u-boot/patches/014-ubparam-kernel.patch deleted file mode 100644 index 26f03474e..000000000 --- a/target/linux/at91/image/u-boot/patches/014-ubparam-kernel.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- u-boot-1.1.4.old/tools/ubparams.c 2007-06-19 14:24:39.000000000 +0200 -+++ u-boot-1.1.4/tools/ubparams.c 2007-06-19 14:25:05.000000000 +0200 -@@ -39,7 +39,7 @@ - "stderr=serial\0" - "fbargs=setenv bootargs root=/dev/mtdblock3 ro console=/dev/ttyS0,115200,mem=32M\0" - "rdba=setenv bootargs root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 console=/dev/ttyS0,115200,mem=32M\0" -- "rdram=run rdba; tftp 21000000 vImage; tftp 21200000 root.squashfs; bootm 21000000\0" -+ "rdram=run rdba; tftp 21000000 uImage; tftp 21200000 root.squashfs; bootm 21000000\0" - "flash=run fbargs; bootm 0xc0042000\0" - "bootargs=setenv bootargs root=/dev/mtdblock3 ro console=/dev/ttyS0,115200,mem=32M\0" - "bootcmd=bootm 0xc0042000\0" diff --git a/target/linux/at91/image/u-boot/patches/015-eabi_fixes.patch b/target/linux/at91/image/u-boot/patches/015-eabi_fixes.patch deleted file mode 100644 index ec94a4b40..000000000 --- a/target/linux/at91/image/u-boot/patches/015-eabi_fixes.patch +++ /dev/null @@ -1,52 +0,0 @@ -Index: git/lib_arm/div0.c -=================================================================== ---- git.orig/lib_arm/div0.c -+++ git/lib_arm/div0.c -@@ -22,9 +22,3 @@ - */ - - /* Replacement (=dummy) for GNU/Linux division-by zero handler */ --void __div0 (void) --{ -- extern void hang (void); -- -- hang(); --} -Index: git/Makefile -=================================================================== ---- git.orig/Makefile -+++ git/Makefile -@@ -225,7 +225,7 @@ LIBS := $(addprefix $(obj),$(LIBS)) - .PHONY : $(LIBS) - - # Add GCC lib --PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc -+PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc -lgcc_eh - - # The "tools" are needed early, so put this first - # Don't include stuff already done in $(LIBS) ---- a/board/vlink/vlink.c 2009-10-29 16:40:33.000000000 +0100 -+++ b/board/vlink/vlink.c 2009-10-29 16:43:27.000000000 +0100 -@@ -33,6 +33,9 @@ - * Miscelaneous platform dependent initialisations - */ - -+void raise() {} -+void abort() {} -+ - int board_init (void) - { - DECLARE_GLOBAL_DATA_PTR; ---- a/board/vlink/u-boot.lds 2009-10-29 16:40:33.000000000 +0100 -+++ b/board/vlink/u-boot.lds 2009-10-29 16:43:57.000000000 +0100 -@@ -38,6 +38,10 @@ - - . = ALIGN(4); - .rodata : { *(.rodata) } -+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } -+ __exidx_start = .; -+ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } -+ __exidx_end = .; - - . = ALIGN(4); - .data : { *(.data) } diff --git a/target/linux/at91/image/u-boot/ubclient/Makefile b/target/linux/at91/image/u-boot/ubclient/Makefile deleted file mode 100644 index f8ff67cd1..000000000 --- a/target/linux/at91/image/u-boot/ubclient/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# - -all: ubpar - -crc32.c: - ln -s ../lib_generic/crc32.c ./ - -%.o: %.c - $(CC) -I ../include $(CFLAGS) $(EXTRA_FLAGS) -DLAN_IP=$(LAN_IP) -DLAN_SERVERIP=$(LAN_SERVERIP) -c -o $@ $^ - -ubpar: ubpar.o crc32.o - $(CC) -o $@ $^ - -clean: - rm -f *.o ubpar diff --git a/target/linux/at91/image/u-boot/ubclient/ubpar.c b/target/linux/at91/image/u-boot/ubclient/ubpar.c deleted file mode 100644 index edc5b2cdb..000000000 --- a/target/linux/at91/image/u-boot/ubclient/ubpar.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * ubparams.c - * - * Generate a u-boot parameter block with correct crc - * - * (C) 1007 Guthrie Consulting - * hamish@prodigi.ch - * - */ - -#include -#include -#include - -#ifndef __ASSEMBLY__ -#define __ASSEMBLY__ -#endif -#define __ASM_STUB_PROCESSOR_H__ -#include -#undef __ASSEMBLY__ -#include - -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) - -extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); - -#if !defined(ENV_CRC) -#define ENV_CRC ~0 -#endif - -#ifdef LAN_IP - #warning LAN_IP -#else - #warning LAN_IP NOT DEFINED -#endif -#ifdef LAN_SERVERIP - #warning LAN_SERVERIP -#else - #warning LAN_SERVERIP NOT DEFINED -#endif - -static char *environment[] = { - "bootdelay=3\0" - "baudrate=115200\0" - "stdin=serial\0" - "stdout=serial\0" - "stderr=serial\0" - "fbargs=setenv bootargs root=/dev/mtdblock3 ro console=/dev/ttyS0,115200,mem=32M\0" - "rdba=setenv bootargs root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 console=/dev/ttyS0,115200,mem=32M\0" - "rdram=run rdba; tftp 21000000 uImage; tftp 21200000 root.squashfs; bootm 21000000\0" - "flash=run fbargs; bootm 0xc0042000\0" - "bootargs=setenv bootargs root=/dev/mtdblock3 ro console=/dev/ttyS0,115200,mem=32M\0" - "bootcmd=bootm 0xc0042000\0" - "ipaddr=" MK_STR(LAN_IP) "\0" - "serverip=" MK_STR(LAN_SERVERIP) "\0" - "\0" - }; - -int main(int argc, char *argv[]) { - env_t *envptr; - char *src, *srcptr; - char *dataptr; - FILE *params; - int argfail = 1; - char newmac[30]; - char newser[30]; - int paramlen = 0; - int progmac = 0; - int progser = 0; - - if (argc < 3) { - printf ("Invalid arguments\n"); - return 1; - } - - switch (argc) { - case 5: - if (strcmp(argv[3], "--serial") == 0) { - argfail = 0; - sprintf(newser, "serial#=%s", argv[4]); - progser = 1; - } - case 3: - if (strcmp(argv[1], "--mac") == 0) { - argfail = 0; - sprintf(newmac, "ethaddr=%s", argv[2]); - progmac = 1; - } - else - argfail = 1; - } - - if (argfail) { - printf("Invalid arguments\n"); - return 1; - } - - - src = srcptr = *environment; - envptr = (env_t *)malloc(CFG_ENV_SIZE); - dataptr = (char *)envptr + ENV_HEADER_SIZE; - - while(*srcptr) { - //printf("%d, %s\n", strlen(srcptr), srcptr); - paramlen += strlen(srcptr) + 1; - srcptr += strlen(srcptr) + 1; - } - - printf("Make u-boot params\n"); - printf("Params size is %d\n", CFG_ENV_SIZE); - - memset(envptr, 0, CFG_ENV_SIZE); - memcpy(dataptr, src, paramlen); - dataptr += paramlen; - - if (progmac) { - memcpy(dataptr, newmac, strlen(newmac)); - dataptr += strlen(newmac) + 1; - } - - if (progser) { - memcpy(dataptr, newser, strlen(newser)); - dataptr += strlen(newser) + 1; - } - - envptr->crc = crc32(0, envptr->data, ENV_SIZE); - - params = fopen("/dev/mtd1", "w"); - fwrite(envptr, CFG_ENV_SIZE, 1, params); - fclose(params); - - free(envptr); - return 0; -} diff --git a/target/linux/at91/patches-2.6.25/000-at91patches.patch b/target/linux/at91/patches-2.6.25/000-at91patches.patch deleted file mode 100644 index 06c29351e..000000000 --- a/target/linux/at91/patches-2.6.25/000-at91patches.patch +++ /dev/null @@ -1,13019 +0,0 @@ ---- a/arch/arm/mach-at91/Kconfig -+++ b/arch/arm/mach-at91/Kconfig -@@ -12,18 +12,28 @@ config ARCH_AT91RM9200 - - config ARCH_AT91SAM9260 - bool "AT91SAM9260 or AT91SAM9XE" -+ select GENERIC_TIME -+ select GENERIC_CLOCKEVENTS - - config ARCH_AT91SAM9261 - bool "AT91SAM9261" -+ select GENERIC_TIME -+ select GENERIC_CLOCKEVENTS - - config ARCH_AT91SAM9263 - bool "AT91SAM9263" -+ select GENERIC_TIME -+ select GENERIC_CLOCKEVENTS - - config ARCH_AT91SAM9RL - bool "AT91SAM9RL" -+ select GENERIC_TIME -+ select GENERIC_CLOCKEVENTS - - config ARCH_AT91CAP9 - bool "AT91CAP9" -+ select GENERIC_TIME -+ select GENERIC_CLOCKEVENTS - - config ARCH_AT91X40 - bool "AT91x40" -@@ -45,7 +55,7 @@ config MACH_ONEARM - depends on ARCH_AT91RM9200 - help - Select this if you are using Ajeco's 1ARM Single Board Computer. -- -+ - - config ARCH_AT91RM9200DK - bool "Atmel AT91RM9200-DK Development board" -@@ -94,7 +104,7 @@ config MACH_KB9200 - depends on ARCH_AT91RM9200 - help - Select this if you are using KwikByte's KB920x board. -- -+ - - config MACH_PICOTUX2XX - bool "picotux 200" -@@ -109,6 +119,38 @@ config MACH_KAFA - help - Select this if you are using Sperry-Sun's KAFA board. - -+config MACH_CHUB -+ bool "Promwad Chub board" -+ depends on ARCH_AT91RM9200 -+ help -+ Select this if you are using Promwad's Chub board. -+ -+config MACH_HOMEMATIC -+ bool "eQ-3 HomeMatic" -+ depends on ARCH_AT91RM9200 -+ help -+ Select this if you are using eQ-3's HomeMatic device. -+ -+ -+config MACH_ECBAT91 -+ bool "emQbit ECB_AT91 SBC" -+ depends on ARCH_AT91RM9200 -+ help -+ Select this if you are using emQbit's ECB_AT91 board. -+ -+ -+config MACH_SWEDATMS -+ bool "Sweda TMS Board" -+ depends on ARCH_AT91RM9200 -+ help -+ Select this if you are using Sweda TMS-100 board. -+ -+config MACH_TT9200 -+ bool "Toptech TT9200" -+ depends on ARCH_AT91RM9200 -+ help -+ Select this if you are using Toptech's TT9200 board. -+ - endif - - # ---------------------------------------------------------- -@@ -133,6 +175,34 @@ config MACH_AT91SAM9260EK - Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit - - -+config MACH_CAM60 -+ bool "KwikByte KB9260 (CAM60) board" -+ depends on ARCH_AT91SAM9260 -+ help -+ Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. -+ -+ -+config MACH_SAM9_L9260 -+ bool "Olimex SAM9-L9260 board" -+ depends on ARCH_AT91SAM9260 -+ help -+ Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. -+ -+ -+config MACH_USB_A9260 -+ bool "CALAO USB-A9260" -+ depends on ARCH_AT91SAM9260 -+ help -+ Select this if you are using a Calao Systems USB-A9260. -+ -+ -+config MACH_QIL_A9260 -+ bool "CALAO QIL-A9260 board" -+ depends on ARCH_AT91SAM9260 -+ help -+ Select this if you are using a Calao Systems QIL-A9260 Board. -+ -+ - endif - - # ---------------------------------------------------------- -@@ -163,6 +233,13 @@ config MACH_AT91SAM9263EK - Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. - - -+config MACH_USB_A9263 -+ bool "CALAO USB-A9263" -+ depends on ARCH_AT91SAM9263 -+ help -+ Select this if you are using a Calao Systems USB-A9263. -+ -+ - endif - - # ---------------------------------------------------------- -@@ -216,7 +293,7 @@ comment "AT91 Board Options" - - config MTD_AT91_DATAFLASH_CARD - bool "Enable DataFlash Card support" -- depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK) -+ depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK) - help - Enable support for the DataFlash card. - -@@ -237,6 +314,19 @@ config AT91_PROGRAMMABLE_CLOCKS - Select this if you need to program one or more of the PCK0..PCK3 - programmable clock outputs. - -+config AT91_SLOW_CLOCK -+ bool "Suspend-to-RAM disables main oscillator" -+ depends on SUSPEND -+ help -+ Select this if you want Suspend-to-RAM to save the most power -+ possible (without powering off the CPU) by disabling the PLLs -+ and main oscillator so that only the 32 KiHz clock is available. -+ -+ When only that slow-clock is available, some peripherals lose -+ functionality. Many can't issue wakeup events unless faster -+ clocks are available. Some lose their operating state and -+ need to be completely re-initialized. -+ - config AT91_TIMER_HZ - int "Kernel HZ (jiffies per second)" - range 32 1024 ---- a/arch/arm/mach-at91/Makefile -+++ b/arch/arm/mach-at91/Makefile -@@ -28,16 +28,26 @@ obj-$(CONFIG_MACH_CARMEVA) += board-carm - obj-$(CONFIG_MACH_KB9200) += board-kb9202.o - obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o - obj-$(CONFIG_MACH_KAFA) += board-kafa.o -+obj-$(CONFIG_MACH_CHUB) += board-chub.o - obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o -+obj-$(CONFIG_MACH_HOMEMATIC) += board-homematic.o -+obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o -+obj-$(CONFIG_MACH_SWEDATMS) += board-tms.o -+obj-$(CONFIG_MACH_TT9200) += board-tt9200.o - - # AT91SAM9260 board-specific support - obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o -+obj-$(CONFIG_MACH_CAM60) += board-cam60.o -+obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o -+obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o -+obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o - - # AT91SAM9261 board-specific support - obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o - - # AT91SAM9263 board-specific support - obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o -+obj-$(CONFIG_MACH_USB_A9263) += board-usb-a9263.o - - # AT91SAM9RL board-specific support - obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o -@@ -50,9 +60,11 @@ obj-$(CONFIG_MACH_AT91EB01) += board-eb0 - - # Drivers - obj-y += leds.o -+obj-$(CONFIG_FB_S1D13XXX) += ics1523.o - - # Power Management - obj-$(CONFIG_PM) += pm.o -+obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o - - ifeq ($(CONFIG_PM_DEBUG),y) - CFLAGS_pm.o += -DDEBUG ---- a/arch/arm/mach-at91/at91cap9.c -+++ b/arch/arm/mach-at91/at91cap9.c -@@ -13,12 +13,15 @@ - */ - - #include -+#include - - #include - #include -+#include - #include - #include - #include -+#include - - #include "generic.h" - #include "clock.h" -@@ -288,6 +291,12 @@ static void at91cap9_reset(void) - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); - } - -+static void at91cap9_poweroff(void) -+{ -+ at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); -+} -+ -+ - /* -------------------------------------------------------------------- - * AT91CAP9 processor initialization - * -------------------------------------------------------------------- */ -@@ -298,6 +307,7 @@ void __init at91cap9_initialize(unsigned - iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc)); - - at91_arch_reset = at91cap9_reset; -+ pm_power_off = at91cap9_poweroff; - at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); - - /* Init clock subsystem */ -@@ -308,6 +318,12 @@ void __init at91cap9_initialize(unsigned - - /* Register GPIO subsystem */ - at91_gpio_init(at91cap9_gpio, 4); -+ -+ /* Remember the silicon revision */ -+ if (cpu_is_at91cap9_revB()) -+ system_rev = 0xB; -+ else if (cpu_is_at91cap9_revC()) -+ system_rev = 0xC; - } - - /* -------------------------------------------------------------------- ---- a/arch/arm/mach-at91/at91cap9_devices.c -+++ b/arch/arm/mach-at91/at91cap9_devices.c -@@ -13,18 +13,20 @@ - */ - #include - #include -+#include - - #include - #include --#include -+#include - - #include