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convert brcm-2.4 to the new target structure
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7092 3c298f89-4303-0410-b956-a3cf2f4a3e73
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nbd
158
target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndchipc.c
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158
target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndchipc.c
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/*
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* BCM47XX support code for some chipcommon (old extif) facilities (uart)
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*
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* Copyright 2006, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
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*/
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#include <typedefs.h>
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#include <bcmdefs.h>
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#include <osl.h>
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#include <bcmutils.h>
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#include <sbutils.h>
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#include <bcmdevs.h>
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#include <bcmnvram.h>
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#include <sbconfig.h>
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#include <sbextif.h>
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#include <sbchipc.h>
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#include <hndcpu.h>
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/*
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* Returns TRUE if an external UART exists at the given base
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* register.
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*/
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static bool
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BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
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{
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uint8 save_mcr, status1;
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save_mcr = R_REG(osh, ®s[UART_MCR]);
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W_REG(osh, ®s[UART_MCR], UART_MCR_LOOP | 0x0a);
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status1 = R_REG(osh, ®s[UART_MSR]) & 0xf0;
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W_REG(osh, ®s[UART_MCR], save_mcr);
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return (status1 == 0x90);
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}
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/*
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* Initializes UART access. The callback function will be called once
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* per found UART.
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*/
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void
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BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
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uint reg_shift))
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{
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osl_t *osh;
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void *regs;
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ulong base;
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uint irq;
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int i, n;
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osh = sb_osh(sbh);
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if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
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extifregs_t *eir = (extifregs_t *) regs;
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sbconfig_t *sb;
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/* Determine external UART register base */
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sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
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base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
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/* Determine IRQ */
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irq = sb_irq(sbh);
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/* Disable GPIO interrupt initially */
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W_REG(osh, &eir->gpiointpolarity, 0);
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W_REG(osh, &eir->gpiointmask, 0);
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/* Search for external UARTs */
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n = 2;
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for (i = 0; i < 2; i++) {
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regs = (void *) REG_MAP(base + (i * 8), 8);
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if (serial_exists(osh, regs)) {
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/* Set GPIO 1 to be the external UART IRQ */
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W_REG(osh, &eir->gpiointmask, 2);
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/* XXXDetermine external UART clock */
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if (add)
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add(regs, irq, 13500000, 0);
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}
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}
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/* Add internal UART if enabled */
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if (R_REG(osh, &eir->corecontrol) & CC_UE)
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if (add)
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add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
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} else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
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chipcregs_t *cc = (chipcregs_t *) regs;
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uint32 rev, cap, pll, baud_base, div;
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/* Determine core revision and capabilities */
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rev = sb_corerev(sbh);
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cap = R_REG(osh, &cc->capabilities);
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pll = cap & CAP_PLL_MASK;
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/* Determine IRQ */
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irq = sb_irq(sbh);
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if (pll == PLL_TYPE1) {
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/* PLL clock */
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baud_base = sb_clock_rate(pll,
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R_REG(osh, &cc->clockcontrol_n),
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R_REG(osh, &cc->clockcontrol_m2));
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div = 1;
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} else {
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/* Fixed ALP clock */
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if (rev >= 11 && rev != 15) {
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baud_base = 20000000;
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div = 1;
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/* Set the override bit so we don't divide it */
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W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
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}
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/* Internal backplane clock */
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else if (rev >= 3) {
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baud_base = sb_clock(sbh);
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div = 2; /* Minimum divisor */
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W_REG(osh, &cc->clkdiv,
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((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
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}
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/* Fixed internal backplane clock */
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else {
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baud_base = 88000000;
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div = 48;
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}
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/* Clock source depends on strapping if UartClkOverride is unset */
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if ((rev > 0) &&
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((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
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if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
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/* Internal divided backplane clock */
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baud_base /= div;
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} else {
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/* Assume external clock of 1.8432 MHz */
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baud_base = 1843200;
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}
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}
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}
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/* Add internal UARTs */
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n = cap & CAP_UARTS_MASK;
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for (i = 0; i < n; i++) {
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/* Register offset changed after revision 0 */
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if (rev)
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regs = (void *)((ulong) &cc->uart0data + (i * 256));
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else
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regs = (void *)((ulong) &cc->uart0data + (i * 8));
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if (add)
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add(regs, irq, baud_base, 0);
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}
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}
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}
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