mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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convert brcm-2.4 to the new target structure
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7092 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
151
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbutils.h
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151
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbutils.h
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/*
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* Misc utility routines for accessing chip-specific features
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* of Broadcom HNBU SiliconBackplane-based chips.
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*
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* Copyright 2006, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
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*/
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#ifndef _sbutils_h_
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#define _sbutils_h_
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/*
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* Datastructure to export all chip specific common variables
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* public (read-only) portion of sbutils handle returned by
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* sb_attach()/sb_kattach()
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*/
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struct sb_pub {
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uint bustype; /* SB_BUS, PCI_BUS */
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uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
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uint buscorerev; /* buscore rev */
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uint buscoreidx; /* buscore index */
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int ccrev; /* chip common core rev */
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uint boardtype; /* board type */
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uint boardvendor; /* board vendor */
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uint chip; /* chip number */
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uint chiprev; /* chip revision */
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uint chippkg; /* chip package option */
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uint sonicsrev; /* sonics backplane rev */
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};
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typedef const struct sb_pub sb_t;
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/*
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* Many of the routines below take an 'sbh' handle as their first arg.
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* Allocate this by calling sb_attach(). Free it by calling sb_detach().
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* At any one time, the sbh is logically focused on one particular sb core
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* (the "current core").
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* Use sb_setcore() or sb_setcoreidx() to change the association to another core.
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*/
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#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
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/* exported externs */
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extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
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void *sdh, char **vars, uint *varsz);
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extern sb_t *sb_kattach(void);
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extern void sb_detach(sb_t *sbh);
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extern uint sb_chip(sb_t *sbh);
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extern uint sb_chiprev(sb_t *sbh);
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extern uint sb_chipcrev(sb_t *sbh);
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extern uint sb_chippkg(sb_t *sbh);
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extern uint sb_pcirev(sb_t *sbh);
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extern bool sb_war16165(sb_t *sbh);
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extern uint sb_pcmciarev(sb_t *sbh);
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extern uint sb_boardvendor(sb_t *sbh);
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extern uint sb_boardtype(sb_t *sbh);
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extern uint sb_bus(sb_t *sbh);
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extern uint sb_buscoretype(sb_t *sbh);
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extern uint sb_buscorerev(sb_t *sbh);
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extern uint sb_corelist(sb_t *sbh, uint coreid[]);
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extern uint sb_coreid(sb_t *sbh);
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extern uint sb_coreidx(sb_t *sbh);
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extern uint sb_coreunit(sb_t *sbh);
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extern uint sb_corevendor(sb_t *sbh);
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extern uint sb_corerev(sb_t *sbh);
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extern void *sb_osh(sb_t *sbh);
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extern void sb_setosh(sb_t *sbh, osl_t *osh);
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extern void *sb_coreregs(sb_t *sbh);
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extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
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extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
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extern bool sb_iscoreup(sb_t *sbh);
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extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
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extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
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extern int sb_corebist(sb_t *sbh);
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extern void sb_commit(sb_t *sbh);
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extern uint32 sb_base(uint32 admatch);
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extern uint32 sb_size(uint32 admatch);
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extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
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extern void sb_core_tofixup(sb_t *sbh);
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extern void sb_core_disable(sb_t *sbh, uint32 bits);
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extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
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extern uint32 sb_clock(sb_t *sbh);
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extern void sb_pci_setup(sb_t *sbh, uint coremask);
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extern void sb_pcmcia_init(sb_t *sbh);
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extern void sb_watchdog(sb_t *sbh, uint ticks);
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extern void *sb_gpiosetcore(sb_t *sbh);
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extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
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extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
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extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
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extern uint32 sb_gpioin(sb_t *sbh);
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extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
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extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
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extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
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extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
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extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
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extern void sb_clkctl_init(sb_t *sbh);
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extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
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extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
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extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
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extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
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void *intrsenabled_fn, void *intr_arg);
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extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
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extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
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uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
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uint8 *pciheader);
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extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
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extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
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extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
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extern bool sb_backplane64(sb_t *sbh);
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extern void sb_btcgpiowar(sb_t *sbh);
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extern bool sb_deviceremoved(sb_t *sbh);
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extern uint32 sb_socram_size(sb_t *sbh);
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/*
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* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
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* The returned path is NULL terminated and has trailing '/'.
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* Return 0 on success, nonzero otherwise.
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*/
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extern int sb_devpath(sb_t *sbh, char *path, int size);
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/* clkctl xtal what flags */
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#define XTAL 0x1 /* primary crystal oscillator (2050) */
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#define PLL 0x2 /* main chip pll */
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/* clkctl clk mode */
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#define CLK_FAST 0 /* force fast (pll) clock */
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#define CLK_DYNAMIC 2 /* enable dynamic clock control */
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/* GPIO usage priorities */
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#define GPIO_DRV_PRIORITY 0 /* Driver */
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#define GPIO_APP_PRIORITY 1 /* Application */
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#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
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/* device path */
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#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
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#endif /* _sbutils_h_ */
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