mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-01 08:01:31 +02:00
[U_BOOT]add-2GB-nand-support.patch
Signed-off-by: Xiangfu Liu <xiangfu.z@gmail.com>
This commit is contained in:
Xiangfu Liu
Xiangfu Liu
parent
da2604ac53
commit
81c4391daf
@ -0,0 +1,234 @@
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diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c
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index c23534d..572d22b 100644
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--- a/board/qi_lb60/qi_lb60.c
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+++ b/board/qi_lb60/qi_lb60.c
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@@ -45,47 +45,44 @@ static void gpio_init(void)
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__gpio_as_i2c();
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/*
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- * Initialize Other pins
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+ * Initialize MSC pins
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*/
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-/* unsigned int i;
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- __gpio_as_output( GPIO_AUDIO_POP );
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- __gpio_set_pin( GPIO_AUDIO_POP );
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-
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+ __gpio_as_msc();
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- for (i = 0; i < 8; i++){
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- __gpio_as_output( GPIO_KEYOUT_BASE + i );
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- __gpio_set_pin( GPIO_KEYOUT_BASE + i );
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+ /*
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+ * Initialize Other pins
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+ */
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+ unsigned int i;
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+ for (i = 0; i < 8; i++) {
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+ __gpio_as_output(GPIO_KEYOUT_BASE + i);
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+ __gpio_set_pin(GPIO_KEYOUT_BASE + i);
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}
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for (i = 0; i < 7; i++){
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- __gpio_as_input( GPIO_KEYIN_BASE + i );
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- __gpio_enable_pull( GPIO_KEYIN_BASE + i );
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+ __gpio_as_input(GPIO_KEYIN_BASE + i);
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+ __gpio_enable_pull(GPIO_KEYIN_BASE + i);
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}
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+ /* __gpio_as_input( GPIO_KEYIN_8 ); */
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+ /* __gpio_enable_pull( GPIO_KEYIN_8 ); */
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- __gpio_as_input( GPIO_KEYIN_8 );
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- __gpio_enable_pull( GPIO_KEYIN_8 );
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-
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-*/
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- __gpio_as_output( GPIO_LCD_CS );
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- __gpio_clear_pin( GPIO_LCD_CS );
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+ __gpio_as_output(GPIO_AUDIO_POP);
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+ __gpio_set_pin(GPIO_AUDIO_POP);
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- __gpio_as_output( GPIO_AMP_EN );
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- __gpio_clear_pin( GPIO_AMP_EN );
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+ __gpio_as_output(GPIO_LCD_CS);
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+ __gpio_clear_pin(GPIO_LCD_CS);
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- __gpio_as_output( GPIO_SDPW_EN );
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- __gpio_set_pin( GPIO_SDPW_EN );
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+ __gpio_as_output(GPIO_AMP_EN);
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+ __gpio_clear_pin(GPIO_AMP_EN);
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- __gpio_as_input( GPIO_SD_DETECT );
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- __gpio_enable_pull( GPIO_SD_DETECT );
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+ __gpio_as_output(GPIO_SDPW_EN);
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+ __gpio_disable_pull(GPIO_SDPW_EN);
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+ __gpio_clear_pin(GPIO_SDPW_EN);
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- __gpio_as_input( GPIO_USB_DETECT );
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- __gpio_enable_pull( GPIO_USB_DETECT );
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+ __gpio_as_input(GPIO_SD_DETECT);
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+ __gpio_disable_pull(GPIO_SD_DETECT);
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- /*
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- * Initialize MSC pins
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- */
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- __gpio_as_msc();
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- __gpio_set_pin(2 + 3 * 32);
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+ __gpio_as_input(GPIO_USB_DETECT);
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+ __gpio_enable_pull(GPIO_USB_DETECT);
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}
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void board_early_init(void)
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diff --git a/cpu/mips/jz_mmc.c b/cpu/mips/jz_mmc.c
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index 8a7c310..ec0a518 100644
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--- a/cpu/mips/jz_mmc.c
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+++ b/cpu/mips/jz_mmc.c
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@@ -61,7 +61,7 @@ do { \
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({ \
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int detected = 1; \
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__gpio_as_input(GPIO_SD_CD_N); \
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- if (__gpio_get_pin(GPIO_SD_CD_N)) \
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+ if (!__gpio_get_pin(GPIO_SD_CD_N)) \
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detected = 0; \
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detected; \
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})
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diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
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index 68a2e87..1e13653 100644
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--- a/include/configs/qi_lb60.h
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+++ b/include/configs/qi_lb60.h
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@@ -13,7 +13,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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-#define DEBUG
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#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
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#define CONFIG_JzRISC 1 /* JzRISC core */
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#define CONFIG_JZSOC 1 /* Jz SoC */
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@@ -23,16 +22,16 @@
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_PCMCIA_SLOT_A 1
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-#define CONFIG_LCD 1 /* LCD support */
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+#define CONFIG_LCD 1 /* LCD support */
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#define LCD_BPP LCD_COLOR32/*5:18,24,32 bits per pixel */
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#define CONFIG_JZLCD_FOXCONN_PT035TN01
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/* NAND Boot config code */
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#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
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-#define CONFIG_CPU_SPEED 252000000 /* CPU clock: 252 MHz */
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+#define CONFIG_CPU_SPEED 366000000 /* CPU clock: 366 MHz */
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#define CONFIG_EXTAL 12000000 /* EXTAL freq: 12 MHz */
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-#define CONFIG_SYS_HZ (CONFIG_EXTAL / 256) /* incrementer freq */
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+#define CONFIG_SYS_HZ (CONFIG_EXTAL / 256) /* incrementer freq */
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#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_CPU_SPEED
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#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
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@@ -46,16 +45,15 @@
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#define CONFIG_SYS_NO_FLASH 1
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
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-#define CONFIG_BOOTDELAY 5
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-#define CONFIG_BOOTFILE "uImage" /* file to load */
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-#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw"
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-#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
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-#define CONFIG_AUTOLOAD "n" /* No autoload */
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-
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-#define CONFIG_DRIVER_CS8900 1
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-#define CS8900_BASE (0xa8000000)
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+#define CONFIG_BOOTDELAY 3
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+#define CONFIG_BOOTFILE "uImage" /* file to load */
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+#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw nohz=off"
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+#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x300000;bootm"
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+
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+#define CONFIG_DRIVER_CS8900 1
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+#define CS8900_BASE (0xa8000000)
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#define CS8900_BUS16
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-#define CONFIG_ETHADDR 00:2a:cc:2a:af:fe /* Ethernet address */
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+#define CONFIG_ETHADDR 00:2a:cc:2a:af:fe /* Ethernet address */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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@@ -92,10 +90,10 @@
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#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
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-#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
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+#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
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#define CONFIG_SYS_MEMTEST_START 0x80100000
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-#define CONFIG_SYS_MEMTEST_END 0x80800000
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+#define CONFIG_SYS_MEMTEST_END 0x80800000
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#define CONFIG_RX_ETH_BUFFER 16 /* use 16 rx buffers on jz47xx eth */
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@@ -107,17 +105,22 @@
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/*
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* NAND FLASH configuration
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*/
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-#define CONFIG_NAND_PAGE_SIZE 2048
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-#define CONFIG_NAND_BLOCK_SIZE (256 << 10) /* NAND chip block size */
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-#define CONFIG_NAND_BADBLOCK_PAGE 127
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-/* NAND bad block was marked at this page in a block, starting from 0 */
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-#define CONFIG_NAND_ECC_POS 6
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-/* Ecc offset position in oob area, default value is 6 if it isn't defined. */
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-
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+#define QI_LB60_NAND_SIZE 2 /* if board nand flash is 1GB, set to 1
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+ * if board nand flash is 2GB, set to 2
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+ * this is for change the PAGE_SIZE and BLOCK_SIZE
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+ * will delete when there is no 1GB flash in board
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+ */
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+
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+#define CONFIG_NAND_PAGE_SIZE 2048 * QI_LB60_NAND_SIZE
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+#define CONFIG_NAND_BLOCK_SIZE (256 * QI_LB60_NAND_SIZE << 10) /* nand chip block size */
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+#define CONFIG_NAND_BADBLOCK_PAGE 127 /* nand bad block was marked at this page in a block,
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+ * starting from 0 */
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+#define CONFIG_NAND_ECC_POS 6 /* ECC offset position in oob area,
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+ * default value is 6 if it isn't defined */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE 0xB8000000
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-#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips*/
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+#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
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/*
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@@ -150,25 +153,8 @@
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/* environment starts here */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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-/*
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- * NOR FLASH and environment organization
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- */
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-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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-#define CONFIG_SYS_MAX_FLASH_SECT (128)/* max number of sectors on one chip */
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-
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-#define PHYS_FLASH_1 0xa8000000 /* Flash Bank #1 */
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-
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-/* The following #defines are needed to get flash environment right */
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-/* in pi/config.mk TEXT_BAS=0x88000000 */
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+/* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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-/* Reserve 256 kB for Monitor*/
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-#define CONFIG_MONITOR_LEN (256*1024)
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-
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-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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-
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-/* timeout values are in ticks */
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-#define CONFIG_FLASH_ERASE_TOUT (2 * CONFIG_HZ) /* Timeout for Flash Erase */
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-#define CONFIG_FLASH_WRITE_TOUT (2 * CONFIG_HZ) /* Timeout for Flash Write */
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/*
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* SDRAM Info.
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diff --git a/lib_mips/board.c b/lib_mips/board.c
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index 539f78f..6a0e060 100644
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--- a/lib_mips/board.c
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+++ b/lib_mips/board.c
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@@ -389,9 +389,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
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size = flash_init();
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display_flash_config (size);
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bd->bi_flashsize = size;
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+ bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
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#endif
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- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
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#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
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bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */
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#else
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