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git://projects.qi-hardware.com/openwrt-xburst.git
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[kernel] also apply gcc4.4.0 specific patches to 2.6.27 (#5318)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16439 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian
parent
6f5a624c71
commit
8335176e7a
@ -0,0 +1,171 @@
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From: Ralf Baechle <ralf@linux-mips.org>
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Date: Thu, 30 Apr 2009 16:14:56 +0000 (+0200)
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Subject: MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0.
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X-Git-Url: http://www.linux-mips.org/git?p=linux.git;a=commitdiff_plain;h=a1b68289997030df64cba8478d5767fe10e42a58
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MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0.
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The inline assembler used on 32-bit kernels was using the "h" constraint
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which was considered dangerous and removed for gcc 4.4.0.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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--- a/include/asm-mips/div64.h
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+++ b/include/asm-mips/div64.h
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@@ -6,105 +6,63 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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-#ifndef _ASM_DIV64_H
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-#define _ASM_DIV64_H
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+#ifndef __ASM_DIV64_H
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+#define __ASM_DIV64_H
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-#include <linux/types.h>
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+#include <asm-generic/div64.h>
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-#if (_MIPS_SZLONG == 32)
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+#if BITS_PER_LONG == 64
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-#include <asm/compiler.h>
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+#include <linux/types.h>
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/*
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* No traps on overflows for any of these...
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*/
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-#define do_div64_32(res, high, low, base) ({ \
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- unsigned long __quot32, __mod32; \
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- unsigned long __cf, __tmp, __tmp2, __i; \
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- \
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- __asm__(".set push\n\t" \
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- ".set noat\n\t" \
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- ".set noreorder\n\t" \
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- "move %2, $0\n\t" \
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- "move %3, $0\n\t" \
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- "b 1f\n\t" \
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- " li %4, 0x21\n" \
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- "0:\n\t" \
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- "sll $1, %0, 0x1\n\t" \
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- "srl %3, %0, 0x1f\n\t" \
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- "or %0, $1, %5\n\t" \
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- "sll %1, %1, 0x1\n\t" \
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- "sll %2, %2, 0x1\n" \
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- "1:\n\t" \
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- "bnez %3, 2f\n\t" \
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- " sltu %5, %0, %z6\n\t" \
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- "bnez %5, 3f\n" \
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- "2:\n\t" \
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- " addiu %4, %4, -1\n\t" \
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- "subu %0, %0, %z6\n\t" \
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- "addiu %2, %2, 1\n" \
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- "3:\n\t" \
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- "bnez %4, 0b\n\t" \
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- " srl %5, %1, 0x1f\n\t" \
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- ".set pop" \
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- : "=&r" (__mod32), "=&r" (__tmp), \
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- "=&r" (__quot32), "=&r" (__cf), \
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- "=&r" (__i), "=&r" (__tmp2) \
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- : "Jr" (base), "0" (high), "1" (low)); \
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- \
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- (res) = __quot32; \
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- __mod32; })
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-
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-#define do_div(n, base) ({ \
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- unsigned long long __quot; \
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- unsigned long __mod; \
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- unsigned long long __div; \
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- unsigned long __upper, __low, __high, __base; \
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- \
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- __div = (n); \
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- __base = (base); \
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- \
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- __high = __div >> 32; \
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- __low = __div; \
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- __upper = __high; \
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- \
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- if (__high) \
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- __asm__("divu $0, %z2, %z3" \
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- : "=h" (__upper), "=l" (__high) \
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- : "Jr" (__high), "Jr" (__base) \
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- : GCC_REG_ACCUM); \
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- \
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- __mod = do_div64_32(__low, __upper, __low, __base); \
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- \
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- __quot = __high; \
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- __quot = __quot << 32 | __low; \
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- (n) = __quot; \
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- __mod; })
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-
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-#endif /* (_MIPS_SZLONG == 32) */
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-
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-#if (_MIPS_SZLONG == 64)
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-
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-/*
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- * Hey, we're already 64-bit, no
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- * need to play games..
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- */
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-#define do_div(n, base) ({ \
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- unsigned long __quot; \
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- unsigned int __mod; \
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- unsigned long __div; \
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- unsigned int __base; \
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- \
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- __div = (n); \
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- __base = (base); \
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- \
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- __mod = __div % __base; \
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- __quot = __div / __base; \
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- \
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- (n) = __quot; \
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- __mod; })
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+#define __div64_32(n, base) \
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+({ \
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+ unsigned long __cf, __tmp, __tmp2, __i; \
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+ unsigned long __quot32, __mod32; \
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+ unsigned long __high, __low; \
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+ unsigned long long __n; \
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+ \
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+ __high = *__n >> 32; \
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+ __low = __n; \
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+ __asm__( \
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+ " .set push \n" \
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+ " .set noat \n" \
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+ " .set noreorder \n" \
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+ " move %2, $0 \n" \
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+ " move %3, $0 \n" \
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+ " b 1f \n" \
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+ " li %4, 0x21 \n" \
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+ "0: \n" \
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+ " sll $1, %0, 0x1 \n" \
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+ " srl %3, %0, 0x1f \n" \
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+ " or %0, $1, %5 \n" \
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+ " sll %1, %1, 0x1 \n" \
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+ " sll %2, %2, 0x1 \n" \
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+ "1: \n" \
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+ " bnez %3, 2f \n" \
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+ " sltu %5, %0, %z6 \n" \
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+ " bnez %5, 3f \n" \
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+ "2: \n" \
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+ " addiu %4, %4, -1 \n" \
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+ " subu %0, %0, %z6 \n" \
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+ " addiu %2, %2, 1 \n" \
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+ "3: \n" \
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+ " bnez %4, 0b\n\t" \
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+ " srl %5, %1, 0x1f\n\t" \
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+ " .set pop" \
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+ : "=&r" (__mod32), "=&r" (__tmp), \
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+ "=&r" (__quot32), "=&r" (__cf), \
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+ "=&r" (__i), "=&r" (__tmp2) \
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+ : "Jr" (base), "0" (__high), "1" (__low)); \
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+ \
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+ (__n) = __quot32; \
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+ __mod32; \
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+})
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-#endif /* (_MIPS_SZLONG == 64) */
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+#endif /* BITS_PER_LONG == 64 */
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-#endif /* _ASM_DIV64_H */
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+#endif /* __ASM_DIV64_H */
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@ -0,0 +1,163 @@
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From: Wu Zhangjin <wuzj@lemote.com>
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the gcc 4.4 support for MIPS mostly refer to this PATCH:
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http://www.nabble.com/-PATCH--MIPS:-Handle-removal-of-%27h%27-constraint-in-GCC-4.4-td22192768.html
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but have been tuned a little.
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because only gcc 4.4 have loongson-specific support, so, we need to
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choose the suitable -march argument for gcc <= 4.3 and gcc >= 4.4, and
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we also need to consider use -march=loongson2e and -march=loongson2f for
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loongson2e and loongson2f respectively. this is handled by adding two
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new kernel options: CPU_LOONGSON2E and CPU_LOONGSON2F(thanks for the
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solutin provided by ZhangLe).
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I have tested it on FuLoong(2f) in 32bit and 64bit with gcc-4.4 and
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gcc-4.3. so, basically, it works.
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Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
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---
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arch/mips/Makefile | 9 +++++-
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arch/mips/include/asm/compiler.h | 10 ++++++
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arch/mips/include/asm/delay.h | 58 +++++++++++++++++++++++++------------
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3 files changed, 57 insertions(+), 20 deletions(-)
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diff --git a/arch/mips/Makefile b/arch/mips/Makefile
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index a25c2e5..1ee5504 100644
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -120,7 +120,14 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
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cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
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cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
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cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
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-cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap
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+
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+# only gcc >= 4.4 have the loongson-specific support
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+cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
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+cflags-$(CONFIG_CPU_LOONGSON2E) += $(shell if [ $(call cc-version) -lt 0440 ] ; then \
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+ echo $(call cc-option,-march=r4600); else echo $(call cc-option,-march=loongson2e); fi ;)
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+cflags-$(CONFIG_CPU_LOONGSON2F) += $(shell if [ $(call cc-version) -lt 0440 ] ; then \
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+ echo $(call cc-option,-march=r4600); else echo $(call cc-option,-march=loongson2f); fi ;)
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+
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cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
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-Wa,-mips32 -Wa,--trap
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cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
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diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h
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index 71f5c5c..95256a8 100644
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--- a/include/asm-mips/compiler.h
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+++ b/include/asm-mips/compiler.h
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@@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2004, 2007 Maciej W. Rozycki
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+ * Copyright (C) 2009 Wu Zhangjin, wuzj@lemote.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@@ -16,4 +17,13 @@
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#define GCC_REG_ACCUM "accum"
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#endif
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+#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
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+#define GCC_NO_H_CONSTRAINT
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+#ifdef CONFIG_64BIT
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+typedef unsigned int uintx_t __attribute__((mode(TI)));
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+#else
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+typedef u64 uintx_t;
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+#endif
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+#endif
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+
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#endif /* _ASM_COMPILER_H */
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diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
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index b0bccd2..00d7969 100644
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--- a/include/asm-mips/delay.h
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+++ b/include/asm-mips/delay.h
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@@ -7,6 +7,7 @@
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* Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2007 Maciej W. Rozycki
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+ * Copyright (C) 2009 Wu Zhangjin, wuzj@lemote.com
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*/
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#ifndef _ASM_DELAY_H
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#define _ASM_DELAY_H
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@@ -48,6 +49,43 @@ static inline void __delay(unsigned long loops)
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: "0" (loops), "r" (1));
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}
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+/*
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+ * convert usecs to loops
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+ *
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+ * handle removal of 'h' constraint in GCC 4.4
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+ */
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+
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+#ifndef GCC_NO_H_CONSTRAINT /* gcc <= 4.3 */
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+static inline unsigned long __usecs_to_loops(unsigned long usecs,
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+ unsigned long lpj)
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+{
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|
+ unsigned long hi, lo;
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|
+
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|
+ if (sizeof(long) == 4)
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|
+ __asm__("multu\t%2, %3"
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|
+ : "=h" (usecs), "=l" (lo)
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|
+ : "r" (usecs), "r" (lpj)
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|
+ : GCC_REG_ACCUM);
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|
+ else if (sizeof(long) == 8 && !R4000_WAR)
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|
+ __asm__("dmultu\t%2, %3"
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|
+ : "=h" (usecs), "=l" (lo)
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|
+ : "r" (usecs), "r" (lpj)
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|
+ : GCC_REG_ACCUM);
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|
+ else if (sizeof(long) == 8 && R4000_WAR)
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|
+ __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
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|
+ : "=r" (usecs), "=h" (hi), "=l" (lo)
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|
+ : "r" (usecs), "r" (lpj)
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|
+ : GCC_REG_ACCUM);
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+
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+ return usecs;
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|
+}
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|
+#else /* GCC_NO_H_CONSTRAINT, gcc >= 4.4 */
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|
+static inline unsigned long __usecs_to_loops(unsigned long usecs,
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|
+ unsigned long lpj)
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|
+{
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|
+ return ((uintx_t)usecs * lpj) >> BITS_PER_LONG;
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|
+}
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|
+#endif
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|
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|
/*
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* Division by multiplication: you don't have to worry about
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|
@@ -62,8 +100,6 @@ static inline void __delay(unsigned long loops)
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|
static inline void __udelay(unsigned long usecs, unsigned long lpj)
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|
{
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|
- unsigned long hi, lo;
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|
-
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|
/*
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|
* The rates of 128 is rounded wrongly by the catchall case
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* for 64-bit. Excessive precission? Probably ...
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@@ -77,23 +113,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
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0x80000000ULL) >> 32);
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|
#endif
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|
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- if (sizeof(long) == 4)
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|
- __asm__("multu\t%2, %3"
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|
- : "=h" (usecs), "=l" (lo)
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|
- : "r" (usecs), "r" (lpj)
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|
- : GCC_REG_ACCUM);
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|
- else if (sizeof(long) == 8 && !R4000_WAR)
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|
- __asm__("dmultu\t%2, %3"
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|
- : "=h" (usecs), "=l" (lo)
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|
- : "r" (usecs), "r" (lpj)
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|
- : GCC_REG_ACCUM);
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|
- else if (sizeof(long) == 8 && R4000_WAR)
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|
- __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
|
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|
- : "=r" (usecs), "=h" (hi), "=l" (lo)
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||||||
|
- : "r" (usecs), "r" (lpj)
|
||||||
|
- : GCC_REG_ACCUM);
|
||||||
|
-
|
||||||
|
- __delay(usecs);
|
||||||
|
+ __delay(__usecs_to_loops(usecs, lpj));
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
|
||||||
|
--
|
||||||
|
1.6.0.4
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Loading…
Reference in New Issue
Block a user