mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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IRQ handler rewrite by Gabor Juhos, uses C no longer assembly
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7464 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian
@@ -1,157 +1,203 @@
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/*
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* Copyright (C) ADMtek Incorporated.
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* Creator : daniell@admtek.com.tw
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000, 2001 MIPS Technologies, Inc.
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* Copyright (C) 2001 Ralf Baechle
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* Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
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* $Id$
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*
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* ADM5120 specific interrupt handlers
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*
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* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
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* Copyright (C) 2007 OpenWrt.org
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#include <linux/autoconf.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/version.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/pm.h>
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#include <linux/ioport.h>
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#include <asm/irq.h>
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#include <asm/time.h>
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#include <asm/mipsregs.h>
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#include <asm/gdb-stub.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/bitops.h>
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#define MIPS_CPU_TIMER_IRQ 7
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#include <asm/mach-adm5120/adm5120_defs.h>
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#include <asm/mach-adm5120/adm5120_irq.h>
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extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
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extern irq_desc_t irq_desc[];
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extern asmlinkage void mipsIRQ(void);
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#define INTC_REG(r) (*(volatile u32 *)(KSEG1ADDR(ADM5120_INTC_BASE) + r))
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int mips_int_lock(void);
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void mips_int_unlock(int);
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static void adm5120_intc_irq_unmask(unsigned int irq);
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static void adm5120_intc_irq_mask(unsigned int irq);
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static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type);
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unsigned int mips_counter_frequency;
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static struct irq_chip adm5120_intc_irq_chip = {
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
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.name = "INTC",
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#else
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.typename = "INTC",
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#endif
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.unmask = adm5120_intc_irq_unmask,
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.mask = adm5120_intc_irq_mask,
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.mask_ack = adm5120_intc_irq_mask,
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.set_type = adm5120_intc_irq_set_type
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};
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#define ADM5120_INTC_REG(reg) (*(volatile u32 *)(KSEG1ADDR(0x12200000+(reg))))
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#define ADM5120_INTC_STATUS ADM5120_INTC_REG(0x00)
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#define ADM5120_INTC_ENABLE ADM5120_INTC_REG(0x08)
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#define ADM5120_INTC_DISABLE ADM5120_INTC_REG(0x0c)
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#define ADM5120_IRQ_MAX 9
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#define ADM5120_IRQ_MASK 0x3ff
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static struct irqaction adm5120_intc_irq_action = {
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.handler = no_action,
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.name = "cascade [INTC]"
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};
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void adm5120_hw0_irqdispatch(struct pt_regs *regs)
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static void adm5120_intc_irq_unmask(unsigned int irq)
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{
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unsigned long intsrc;
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int i;
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unsigned long flags;
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intsrc = ADM5120_INTC_STATUS & ADM5120_IRQ_MASK;
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if (intsrc) {
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for (i = 0; intsrc; intsrc >>= 1, i++)
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if (intsrc & 0x1)
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do_IRQ(i);
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} else
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spurious_interrupt();
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irq -= ADM5120_INTC_IRQ_BASE;
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local_irq_save(flags);
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INTC_REG(INTC_REG_IRQ_ENABLE) = (1 << irq);
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local_irq_restore(flags);
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}
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void mips_timer_interrupt(struct pt_regs *regs)
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static void adm5120_intc_irq_mask(unsigned int irq)
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{
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write_c0_compare(read_c0_count()+ mips_counter_frequency/HZ);
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ll_timer_interrupt(MIPS_CPU_TIMER_IRQ);
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unsigned long flags;
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irq -= ADM5120_INTC_IRQ_BASE;
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local_irq_save(flags);
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INTC_REG(INTC_REG_IRQ_DISABLE) = (1 << irq);
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local_irq_restore(flags);
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}
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/* Main interrupt dispatcher */
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asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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unsigned int cp0_cause = read_c0_cause() & read_c0_status();
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/* TODO: not yet tested */
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#if 1
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unsigned int sense;
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unsigned long mode;
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int err;
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if (cp0_cause & CAUSEF_IP7) {
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mips_timer_interrupt( regs);
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} else if (cp0_cause & CAUSEF_IP2) {
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adm5120_hw0_irqdispatch( regs);
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}
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}
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void enable_adm5120_irq(unsigned int irq)
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{
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int s;
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/* Disable all interrupts (FIQ/IRQ) */
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s = mips_int_lock();
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if ((irq < 0) || (irq > ADM5120_IRQ_MAX))
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goto err_exit;
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ADM5120_INTC_ENABLE = (1<<irq);
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err_exit:
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/* Restore the interrupts states */
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mips_int_unlock(s);
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}
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void disable_adm5120_irq(unsigned int irq)
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{
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int s;
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/* Disable all interrupts (FIQ/IRQ) */
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s = mips_int_lock();
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if ((irq < 0) || (irq > ADM5120_IRQ_MAX))
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goto err_exit;
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ADM5120_INTC_DISABLE = (1<<irq);
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err_exit:
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/* Restore the interrupts states */
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mips_int_unlock(s);
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}
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unsigned int startup_adm5120_irq(unsigned int irq)
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{
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enable_adm5120_irq(irq);
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err = 0;
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sense = flow_type & (IRQ_TYPE_SENSE_MASK);
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switch (sense) {
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case IRQ_TYPE_NONE:
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case IRQ_TYPE_LEVEL_HIGH:
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break;
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case IRQ_TYPE_LEVEL_LOW:
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switch (irq) {
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case ADM5120_IRQ_GPIO2:
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case ADM5120_IRQ_GPIO4:
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break;
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default:
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err = -EINVAL;
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break;
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}
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break;
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default:
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err = -EINVAL;
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break;
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}
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if (err)
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return err;
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switch (irq) {
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case ADM5120_IRQ_GPIO2:
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case ADM5120_IRQ_GPIO4:
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mode = INTC_REG(INTC_REG_INT_MODE);
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if (sense == IRQ_TYPE_LEVEL_LOW)
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mode |= (1 << (irq-ADM5120_INTC_IRQ_BASE));
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else
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mode &= (1 << (irq-ADM5120_INTC_IRQ_BASE));
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INTC_REG(INTC_REG_INT_MODE) = mode;
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/* fallthrogh */
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default:
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irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
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irq_desc[irq].status |= sense;
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break;
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}
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#endif
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return 0;
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}
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void shutdown_adm5120_irq(unsigned int irq)
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static void adm5120_intc_irq_dispatch(void)
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{
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disable_adm5120_irq(irq);
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unsigned long status;
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int irq;
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#if 1
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/* dispatch only one IRQ at a time */
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status = INTC_REG(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
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if (status) {
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irq = ADM5120_INTC_IRQ_BASE+fls(status)-1;
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do_IRQ(irq);
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} else
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spurious_interrupt();
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#else
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status = INTC_REG(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
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if (status) {
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for (irq=ADM5120_INTC_IRQ_BASE; irq <= ADM5120_INTC_IRQ_BASE +
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INTC_IRQ_LAST; irq++, status >>=1) {
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if ((status & 1) == 1)
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do_IRQ(irq);
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}
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} else
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spurious_interrupt();
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#endif
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}
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static inline void ack_adm5120_irq(unsigned int irq_nr)
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asmlinkage void plat_irq_dispatch(void)
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{
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ADM5120_INTC_DISABLE = (1 << irq_nr);
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unsigned long pending;
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pending = read_c0_status() & read_c0_cause();
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if (pending & STATUSF_IP7)
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do_IRQ(ADM5120_IRQ_COUNTER);
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else if (pending & STATUSF_IP2)
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adm5120_intc_irq_dispatch();
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else
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spurious_interrupt();
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}
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static void end_adm5120_irq(unsigned int irq_nr)
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{
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ADM5120_INTC_ENABLE = (1 << irq_nr);
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}
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static hw_irq_controller adm5120_irq_type = {
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.typename = "MIPS",
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.startup = startup_adm5120_irq,
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.shutdown = shutdown_adm5120_irq,
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.enable = enable_adm5120_irq,
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.disable = disable_adm5120_irq,
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.ack = ack_adm5120_irq,
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.end = end_adm5120_irq,
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.set_affinity = NULL,
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};
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void __init arch_init_irq(void)
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#define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
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static void __init adm5120_intc_irq_init(int base)
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{
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int i;
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for (i = 0; i <= ADM5120_IRQ_MAX; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &adm5120_irq_type;
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/* disable all interrupts */
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INTC_REG(INTC_REG_IRQ_DISABLE) = INTC_INT_ALL;
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/* setup all interrupts to generate IRQ instead of FIQ */
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INTC_REG(INTC_REG_INT_MODE) = 0;
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/* set active level for all external interrupts to HIGH */
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INTC_REG(INTC_REG_INT_LEVEL) = 0;
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/* disable usage of the TEST_SOURCE register */
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INTC_REG(INTC_REG_IRQ_SOURCE_SELECT) = 0;
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for(i=ADM5120_INTC_IRQ_BASE; i <= ADM5120_INTC_IRQ_BASE+INTC_IRQ_LAST;
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i++) {
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irq_desc[i].status = INTC_IRQ_STATUS;
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set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
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handle_level_irq);
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}
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setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
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}
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void __init arch_init_irq(void) {
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mips_cpu_irq_init();
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adm5120_intc_irq_init(ADM5120_INTC_IRQ_BASE);
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}
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