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Fix VLYNQ device enable for DG834Gv1

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This patch allows VLYNQ devices on the DG834Gv1 to be successfully
enabled.

Currently the "__vlynq_enable_device" function attempts to set the VLYNQ
device clock divisor to values from 1 through 8 until a link is
successfully established. On the DG834Gv1 (but not the DG834Gv2),
setting the VLYNQ device clock divisor to 1 (full rate) results in all
further VLYNQ operations failing (including software reset), so the
device is never enabled. This patches changes the function to only
attempt divisors 2 through 8, and hence the device is successfully
enabled.

Signed-off-by: Nick Forbes <nick.forbes@huntsworth.com>

---------


git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9656 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd 2007-12-04 12:49:54 +00:00
parent a087e6c06e
commit 863d4e55d3
1 changed files with 1 additions and 1 deletions
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2
target/linux/ar7/files/drivers/vlynq/vlynq.c
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@ -373,7 +373,7 @@ static int __vlynq_enable_device(struct vlynq_device *dev)
case vlynq_div_auto: case vlynq_div_auto:
/* Only try locally supplied clock, others cause problems */ /* Only try locally supplied clock, others cause problems */
vlynq_reg_write(dev->remote->control, 0); vlynq_reg_write(dev->remote->control, 0);
for (i = vlynq_ldiv1; i <= vlynq_ldiv8; i++) { for (i = vlynq_ldiv2; i <= vlynq_ldiv8; i++) {
vlynq_reg_write(dev->local->control, vlynq_reg_write(dev->local->control,
VLYNQ_CTRL_CLOCK_INT | VLYNQ_CTRL_CLOCK_INT |
VLYNQ_CTRL_CLOCK_DIV(i - vlynq_ldiv1)); VLYNQ_CTRL_CLOCK_DIV(i - vlynq_ldiv1));