mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-02-03 06:31:06 +02:00
* add console=tty0 to kernel command line.
* when press [S], enable the UART0 and UART1, uboot will delay 3 second wait input from serial console. * when press [S] + [M] + [POWER], will enalbe uart then boot from sd card. Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
This commit is contained in:
parent
73df02f0b7
commit
8ceec5f9a6
@ -57,11 +57,11 @@ static void gpio_init(void)
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*/
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if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){
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/* if pressed [S] */
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printf("[S] pressed, enable UART0\n");
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gd->boot_option = 5;
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printf("[S] pressed, enable UART\n");
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gd->boot_option |= BOOT_WITH_ENABLE_UART;
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__gpio_as_uart0();
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__gpio_as_uart1();
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} else {
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printf("[S] not pressed, disable UART0\n");
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__gpio_as_input(GPIO_KEYIN_8);
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__gpio_enable_pull(GPIO_KEYIN_8);
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}
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@ -86,8 +86,8 @@ static void gpio_init(void)
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__gpio_enable_pull(GPIO_USB_DETECT);
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if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) {
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printf("[M] pressed, boot from sd card\n");
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gd->boot_option = 1;
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printf("[M] pressed, boot from sd card %d\n");
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gd->boot_option |= BOOT_FROM_SDCARD;
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}
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}
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@ -97,7 +97,8 @@ static void cpm_init(void)
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__cpm_stop_cim();
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__cpm_stop_i2c();
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__cpm_stop_ssi();
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__cpm_stop_uart1();
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if (!(gd->boot_option & BOOT_WITH_ENABLE_UART))
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__cpm_stop_uart1();
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__cpm_stop_sadc();
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__cpm_stop_uhc();
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__cpm_stop_udc();
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@ -117,7 +118,7 @@ int checkboard (void)
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{
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printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %d MHz)\n",
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gd->cpu_clk/1000000);
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gd->cpu_clk / 1000000);
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return 0; /* success */
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}
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@ -24,7 +24,7 @@
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#define CONFIG_SYS_WHITE_ON_BLACK 1
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#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
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#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
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#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
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#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
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#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
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@ -73,7 +73,7 @@
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "QI# " /* Monitor Command Prompt */
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#define CONFIG_SYS_PROMPT "NanoNote# " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Print Buffer Size */
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@ -112,11 +112,11 @@
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#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
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/* ECC offset position in oob area, default value is 6 if it isn't defined */
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#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE 0xB8000000
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#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
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#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE 0xB8000000
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#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
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#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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@ -133,7 +133,7 @@
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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*/
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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/* Start NUB from this addr*/
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@ -5,8 +5,11 @@
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#define CONFIG_QI_LB60 1
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#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
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#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootwait"
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#define BOOT_FROM_SDCARD 1
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#define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */
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#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
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#define CONFIG_BOOTARGSFROMSD "mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootwait"
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#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
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#define CONFIG_BOOTCOMMANDFROMSD "mmc init; fatload mmc 0 0x80600000 uImage; bootm"
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@ -333,7 +333,6 @@ static void nand_load(int offs, int uboot_size, uchar *dst)
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}
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static void jz_nand_init(void) {
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/* Optimize the timing of nand */
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REG_EMC_SMCR1 = 0x094c4400;
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}
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@ -343,13 +342,7 @@ static void gpio_init(void)
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/*
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* Initialize SDRAM pins
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*/
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#if defined(CONFIG_JZ4720)
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__gpio_as_sdram_16bit_4720();
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#elif defined(CONFIG_JZ4725)
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__gpio_as_sdram_16bit_4725();
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#else
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__gpio_as_sdram_32bit();
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#endif
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/*
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* Initialize UART0 pins
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@ -359,22 +352,15 @@ static void gpio_init(void)
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static int is_usb_boot()
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{
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int keyU = 0;
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__gpio_as_input(KEY_U_IN);
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__gpio_enable_pull(KEY_U_IN);
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__gpio_as_output(KEY_U_OUT);
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__gpio_clear_pin(KEY_U_OUT);
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__gpio_as_input(KEY_U_IN);
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__gpio_enable_pull(KEY_U_IN);
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if (__gpio_get_pin(KEY_U_IN) == 0)
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return 1;
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__gpio_as_output(KEY_U_OUT);
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__gpio_clear_pin(KEY_U_OUT);
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keyU = __gpio_get_pin(KEY_U_IN);
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if (keyU)
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serial_puts("[U] not pressed\n");
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else
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serial_puts("[U] pressed\n");
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return !keyU;
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return 0;
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}
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void nand_boot(void)
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@ -384,22 +370,18 @@ void nand_boot(void)
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/*
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* Init hardware
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*/
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jz_nand_init();
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gpio_init();
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serial_init();
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serial_puts("\n\nNAND Secondary Program Loader\n\n");
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pll_init();
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serial_init();
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sdram_init();
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serial_puts("\n\nNAND Secondary Program Loader\n\n");
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#if defined(CONFIG_NANONOTE)
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if(is_usb_boot()) {
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serial_puts("enter USB BOOT mode\n");
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serial_puts("[U] pressed, goto USBBOOT mode\n");
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usb_boot();
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}
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#endif
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page_size = CONFIG_SYS_NAND_PAGE_SIZE;
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block_size = CONFIG_SYS_NAND_BLOCK_SIZE;
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page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
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@ -417,13 +399,9 @@ void nand_boot(void)
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serial_puts("Starting U-Boot ...\n");
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/*
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* Flush caches
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*/
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/* Flush caches */
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flush_cache_all();
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/*
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* Jump to U-Boot image
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*/
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/* Jump to U-Boot image */
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(*uboot)();
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}
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@ -5,11 +5,11 @@ From: Xiangfu Liu <xiangfu@sharism.cc>
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---
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Makefile | 10 +
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common/env_common.c | 2
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Makefile | 16 +
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common/env_common.c | 7 -
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common/lcd.c | 45 ++++
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common/main.c | 4
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cpu/mips/Makefile | 4
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common/main.c | 11 +
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cpu/mips/Makefile | 3
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cpu/mips/cache.S | 280 ++++++++++----------------
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cpu/mips/config.mk | 6 -
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cpu/mips/cpu.c | 75 +++++++
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@ -17,16 +17,16 @@ From: Xiangfu Liu <xiangfu@sharism.cc>
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drivers/mtd/nand/nand_base.c | 88 ++++++++
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examples/standalone/mips.lds | 2
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include/asm-mips/addrspace.h | 2
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include/asm-mips/global_data.h | 11 +
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include/asm-mips/global_data.h | 12 +
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include/lcd.h | 56 +++++
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lib_mips/board.c | 18 +-
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lib_mips/bootm.c | 7 +
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lib_mips/bootm.c | 12 +
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lib_mips/time.c | 4
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20 files changed, 800 insertions(+), 333 deletions(-)
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17 files changed, 778 insertions(+), 291 deletions(-)
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diff --git a/Makefile b/Makefile
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index f06a97c..a318eb4 100644
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index f06a97c..3d87cd1 100644
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--- a/Makefile
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+++ b/Makefile
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@@ -3439,6 +3439,22 @@ qemu_mips_config : unconfig
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@ -53,10 +53,11 @@ index f06a97c..a318eb4 100644
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#########################################################################
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diff --git a/common/env_common.c b/common/env_common.c
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index 439a4a9..6cfe30b 100644
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index 439a4a9..905d16a 100644
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--- a/common/env_common.c
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+++ b/common/env_common.c
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@@ -134,7 +134,10 @@ uchar default_environment[] = {
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@@ -133,8 +133,11 @@ uchar default_environment[] = {
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#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
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"pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0"
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#endif
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-#ifdef CONFIG_EXTRA_ENV_SETTINGS
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@ -176,33 +177,36 @@ index 4e31618..ddd5aa8 100644
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}
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diff --git a/common/main.c b/common/main.c
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index 10d8904..ff11ad7 100644
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index 10d8904..76641f3 100644
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--- a/common/main.c
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+++ b/common/main.c
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@@ -372,7 +372,9 @@ void main_loop (void)
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@@ -372,7 +372,11 @@ void main_loop (void)
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#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
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s = getenv ("bootdelay");
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bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
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-
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+#if defined(CONFIG_NANONOTE)
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+ DECLARE_GLOBAL_DATA_PTR;
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+ if (gd->boot_option == 5)
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+ bootdelay = gd->boot_option;
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+ if (gd->boot_option & BOOT_WITH_ENABLE_UART)
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+ bootdelay = 3;
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+# endif
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debug ("### main_loop entered: bootdelay=%d\n\n", bootdelay);
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# ifdef CONFIG_BOOT_RETRY_TIME
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@@ -393,7 +395,9 @@ void main_loop (void)
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@@ -393,7 +397,10 @@ void main_loop (void)
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}
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else
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#endif /* CONFIG_BOOTCOUNT_LIMIT */
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- s = getenv ("bootcmd");
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+ s = gd->boot_option == 1 ?
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+ getenv ("bootcmdfromsd"):
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+ getenv ("bootcmd") ;
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+ if (gd->boot_option & BOOT_FROM_SDCARD)
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+ s = getenv ("bootcmdfromsd");
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+ else
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+ s = getenv ("bootcmd");
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debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
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diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile
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index 28a1cbb..5207bc5 100644
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index 28a1cbb..afeb909 100644
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--- a/cpu/mips/Makefile
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+++ b/cpu/mips/Makefile
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@@ -33,6 +33,9 @@ SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o
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@ -687,7 +691,7 @@ index d5a1604..48e1cea 100644
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+}
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+#endif /* CONFIG_JzRISC */
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diff --git a/cpu/mips/start.S b/cpu/mips/start.S
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index 57db589..fa6e352 100644
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index 57db589..33c05b4 100644
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--- a/cpu/mips/start.S
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+++ b/cpu/mips/start.S
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@@ -23,32 +23,33 @@
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@ -1270,7 +1274,7 @@ index 57db589..fa6e352 100644
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+
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+#endif /* CONFIG_JZ4730 */
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diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
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index 426bb95..6e5fbd3 100644
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index 426bb95..23a1856 100644
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--- a/drivers/mtd/nand/nand_base.c
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+++ b/drivers/mtd/nand/nand_base.c
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@@ -109,6 +109,22 @@ static struct nand_ecclayout nand_oob_16 = {
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@ -1427,10 +1431,10 @@ index 3a1e6d6..2ee6920 100644
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cannot access physical memory directly from core */
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#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
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diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h
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index b2c4891..23f597e 100644
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index b2c4891..9f93fb4 100644
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--- a/include/asm-mips/global_data.h
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+++ b/include/asm-mips/global_data.h
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@@ -39,6 +39,17 @@
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@@ -39,6 +39,18 @@
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typedef struct global_data {
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bd_t *bd;
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unsigned long flags;
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@ -1442,8 +1446,9 @@ index b2c4891..23f597e 100644
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+ unsigned long mem_clk; /* Memory bus clock */
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+ unsigned long dev_clk; /* Device clock */
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+ unsigned long fb_base; /* base address of framebuffer */
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+ unsigned long boot_option; /* 1: boot from sd
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+ * 5: boot delay for 5 secs*/
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+#endif
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+#if defined(CONFIG_NANONOTE)
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+ unsigned long boot_option;
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+#endif
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unsigned long baudrate;
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unsigned long have_console; /* serial_init() was called */
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@ -1623,25 +1628,33 @@ index b2d113e..87cb12d 100644
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bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */
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#else
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diff --git a/lib_mips/bootm.c b/lib_mips/bootm.c
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index 54af24c..64bcad9 100644
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index 54af24c..b498ae8 100644
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--- a/lib_mips/bootm.c
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+++ b/lib_mips/bootm.c
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@@ -46,7 +46,9 @@ static void linux_env_set (char * env_name, char * env_val);
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@@ -46,10 +46,17 @@ static void linux_env_set (char * env_name, char * env_val);
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int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
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{
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void (*theKernel) (int, char **, char **, int *);
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- char *commandline = getenv ("bootargs");
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+ char *commandline = gd->boot_option == 1 ?
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+ getenv ("bootargsfromsd") :
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+ getenv ("bootargs");
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+ char *commandline;
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char env_buf[12];
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char *cp;
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@@ -98,6 +100,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
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+#if defined(CONFIG_NANONOTE)
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+ if (gd->boot_option & BOOT_FROM_SDCARD)
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+ commandline = getenv ("bootargsfromsd");
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+ else
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+#endif
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+ commandline = getenv ("bootargs");
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+
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if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
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return 1;
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@@ -98,6 +105,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
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}
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/* we assume that the kernel is in place */
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+ if (gd->boot_option == 1)
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+ if (gd->boot_option == BOOT_FROM_SDCARD)
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+ printf ("\n *** Booting from mircoSD ***\n");
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+
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printf ("\nStarting kernel ...\n\n");
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@ -1666,4 +1679,3 @@ index 07e356d..4654bf4 100644
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}
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+
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+#endif /* !CONFIG_JzRISC */
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