mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 06:53:21 +02:00
[brcm47xx] update tg3 driver
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33004 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
hauke
parent
7e86c89269
commit
8e1718f8e2
@ -16,35 +16,38 @@
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
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@@ -530,7 +532,8 @@ static void _tw32_flush(struct tg3 *tp,
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@@ -530,7 +532,9 @@ static void _tw32_flush(struct tg3 *tp,
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static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
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{
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tp->write32_mbox(tp, off, val);
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- if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
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+ if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
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+ (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)))
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+ (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
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+ !tg3_flag(tp, ICH_WORKAROUND)))
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tp->read32_mbox(tp, off);
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}
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@@ -540,7 +543,7 @@ static void tg3_write32_tx_mbox(struct t
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@@ -540,7 +544,8 @@ static void tg3_write32_tx_mbox(struct t
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writel(val, mbox);
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if (tg3_flag(tp, TXD_MBOX_HWBUG))
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writel(val, mbox);
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- if (tg3_flag(tp, MBOX_WRITE_REORDER))
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+ if (tg3_flag(tp, MBOX_WRITE_REORDER) || tg3_flag(tp, FLUSH_POSTED_WRITES))
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+ if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
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+ tg3_flag(tp, FLUSH_POSTED_WRITES))
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readl(mbox);
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}
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@@ -948,7 +951,7 @@ static void tg3_switch_clocks(struct tg3
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@@ -948,7 +953,8 @@ static void tg3_switch_clocks(struct tg3
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#define PHY_BUSY_LOOPS 5000
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-static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
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+static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
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+static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
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+ u32 *val)
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{
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u32 frame_val;
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unsigned int loops;
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@@ -962,7 +965,7 @@ static int tg3_readphy(struct tg3 *tp, i
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@@ -962,7 +968,7 @@ static int tg3_readphy(struct tg3 *tp, i
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*val = 0x0;
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@ -53,7 +56,7 @@
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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@@ -997,7 +1000,12 @@ static int tg3_readphy(struct tg3 *tp, i
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@@ -997,7 +1003,13 @@ static int tg3_readphy(struct tg3 *tp, i
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return ret;
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}
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@ -63,11 +66,12 @@
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+ return __tg3_readphy(tp, tp->phy_addr, reg, val);
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+}
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+
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+static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
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+static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
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+ u32 val)
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{
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u32 frame_val;
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unsigned int loops;
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@@ -1013,7 +1021,7 @@ static int tg3_writephy(struct tg3 *tp,
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@@ -1013,7 +1025,7 @@ static int tg3_writephy(struct tg3 *tp,
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udelay(80);
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}
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@ -76,7 +80,7 @@
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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@@ -1046,6 +1054,11 @@ static int tg3_writephy(struct tg3 *tp,
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@@ -1046,6 +1058,11 @@ static int tg3_writephy(struct tg3 *tp,
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return ret;
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}
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@ -88,7 +92,7 @@
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static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
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{
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int err;
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@@ -1608,6 +1621,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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@@ -1608,6 +1625,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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int i;
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u32 val;
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@ -100,7 +104,19 @@
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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/* Wait up to 20ms for init done. */
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for (i = 0; i < 200; i++) {
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@@ -3029,9 +3047,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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@@ -3015,6 +3037,11 @@ static int tg3_halt_cpu(struct tg3 *tp,
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tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
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udelay(10);
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} else {
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+ /* There is only an Rx CPU for the 5750 derivative in the
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+ * BCM4785. */
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+ if (tg3_flag(tp, IS_SSB_CORE))
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+ return 0;
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+
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for (i = 0; i < 10000; i++) {
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tw32(offset + CPU_STATE, 0xffffffff);
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tw32(offset + CPU_MODE, CPU_MODE_HALT);
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@@ -3029,9 +3056,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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return -ENODEV;
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}
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@ -116,7 +132,7 @@
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return 0;
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}
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@@ -3094,6 +3115,11 @@ static int tg3_load_5701_a0_firmware_fix
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@@ -3094,6 +3124,11 @@ static int tg3_load_5701_a0_firmware_fix
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const __be32 *fw_data;
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int err, i;
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@ -128,7 +144,7 @@
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fw_data = (void *)tp->fw->data;
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/* Firmware blob starts with version numbers, followed by
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@@ -3150,6 +3176,11 @@ static int tg3_load_tso_firmware(struct
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@@ -3150,6 +3185,11 @@ static int tg3_load_tso_firmware(struct
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unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
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int err, i;
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@ -140,21 +156,19 @@
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if (tg3_flag(tp, HW_TSO_1) ||
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tg3_flag(tp, HW_TSO_2) ||
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tg3_flag(tp, HW_TSO_3))
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@@ -3496,8 +3527,11 @@ static int tg3_power_down_prepare(struct
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@@ -3496,8 +3536,9 @@ static int tg3_power_down_prepare(struct
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tg3_frob_aux_power(tp, true);
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/* Workaround for unstable PLL clock */
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- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
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+ if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 &&
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+ (tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_3 &&
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+ /* !!! FIXME !!! */
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+ if ((!tg3_flag(tp, IS_SSB_CORE)) &&
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+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
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+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
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+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
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u32 val = tr32(0x7d00);
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val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
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@@ -4011,6 +4045,14 @@ relink:
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@@ -4011,6 +4052,14 @@ relink:
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if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
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tg3_phy_copper_begin(tp);
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@ -169,14 +183,41 @@
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tg3_readphy(tp, MII_BMSR, &bmsr);
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if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
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(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
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@@ -7833,6 +7875,14 @@ static int tg3_chip_reset(struct tg3 *tp
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@@ -4029,6 +4078,26 @@ relink:
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else
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tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
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+ /* In order for the 5750 core in BCM4785 chip to work properly
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+ * in RGMII mode, the Led Control Register must be set up.
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+ */
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+ if (tg3_flag(tp, RGMII_MODE)) {
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+ u32 led_ctrl = tr32(MAC_LED_CTRL);
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+ led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
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+
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+ if (tp->link_config.active_speed == SPEED_10)
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+ led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
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+ else if (tp->link_config.active_speed == SPEED_100)
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+ led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
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+ LED_CTRL_100MBPS_ON);
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+ else if (tp->link_config.active_speed == SPEED_1000)
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+ led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
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+ LED_CTRL_1000MBPS_ON);
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+
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+ tw32(MAC_LED_CTRL, led_ctrl);
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+ udelay(40);
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+ }
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+
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tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
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if (tp->link_config.active_duplex == DUPLEX_HALF)
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tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
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@@ -7833,6 +7902,14 @@ static int tg3_chip_reset(struct tg3 *tp
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tw32(0x5000, 0x400);
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}
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+ if (tg3_flag(tp, IS_SSB_CORE)) {
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+ /* BCM4785: In order to avoid repercussions from using potentially
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+ * defective internal ROM, stop the Rx RISC CPU, which is not
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+ * required. */
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+ /* BCM4785: In order to avoid repercussions from using
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+ * potentially defective internal ROM, stop the Rx RISC CPU,
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+ * which is not required. */
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+ tg3_stop_fw(tp);
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+ tg3_halt_cpu(tp, RX_CPU_BASE);
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+ }
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@ -184,7 +225,7 @@
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tw32(GRC_MODE, tp->grc_mode);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
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@@ -9247,6 +9297,11 @@ static void tg3_timer(unsigned long __op
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@@ -9247,6 +9324,11 @@ static void tg3_timer(unsigned long __op
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tg3_flag(tp, 57765_CLASS))
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tg3_chk_missed_msi(tp);
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@ -196,7 +237,7 @@
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if (!tg3_flag(tp, TAGGED_STATUS)) {
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/* All of this garbage is because when using non-tagged
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* IRQ status the mailbox/status_block protocol the chip
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@@ -10959,6 +11014,11 @@ static int tg3_test_nvram(struct tg3 *tp
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@@ -10959,6 +11041,11 @@ static int tg3_test_nvram(struct tg3 *tp
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if (tg3_flag(tp, NO_NVRAM))
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return 0;
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@ -208,7 +249,7 @@
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if (tg3_nvram_read(tp, 0, &magic) != 0)
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return -EIO;
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@@ -11916,11 +11976,11 @@ static int tg3_ioctl(struct net_device *
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@@ -11916,11 +12003,12 @@ static int tg3_ioctl(struct net_device *
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if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
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break; /* We have no PHY */
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@ -218,11 +259,12 @@
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spin_lock_bh(&tp->lock);
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- err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
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+ err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
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+ err = __tg3_readphy(tp, data->phy_id & 0x1f,
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+ data->reg_num & 0x1f, &mii_regval);
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spin_unlock_bh(&tp->lock);
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data->val_out = mii_regval;
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@@ -11932,11 +11992,11 @@ static int tg3_ioctl(struct net_device *
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@@ -11932,11 +12020,12 @@ static int tg3_ioctl(struct net_device *
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if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
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break; /* We have no PHY */
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@ -232,11 +274,12 @@
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spin_lock_bh(&tp->lock);
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- err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
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+ err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
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+ err = __tg3_writephy(tp, data->phy_id & 0x1f,
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+ data->reg_num & 0x1f, data->val_in);
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spin_unlock_bh(&tp->lock);
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return err;
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@@ -12670,6 +12730,13 @@ static void __devinit tg3_get_5720_nvram
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@@ -12670,6 +12759,13 @@ static void __devinit tg3_get_5720_nvram
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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static void __devinit tg3_nvram_init(struct tg3 *tp)
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{
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@ -250,7 +293,7 @@
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tw32_f(GRC_EEPROM_ADDR,
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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@@ -12936,6 +13003,9 @@ static int tg3_nvram_write_block(struct
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@@ -12936,6 +13032,9 @@ static int tg3_nvram_write_block(struct
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{
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int ret;
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@ -260,7 +303,29 @@
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if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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@@ -14382,6 +14452,11 @@ static int __devinit tg3_get_invariants(
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@@ -13394,10 +13493,19 @@ static int __devinit tg3_phy_probe(struc
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* subsys device table.
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*/
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p = tg3_lookup_by_subsys(tp);
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- if (!p)
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+ if (p) {
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+ tp->phy_id = p->phy_id;
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+ } else if (!tg3_flag(tp, IS_SSB_CORE)) {
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+ /* For now we saw the IDs 0xbc050cd0,
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+ * 0xbc050f80 and 0xbc050c30 on devices
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+ * connected to an BCM4785 and there are
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+ * probably more. Just assume that the phy is
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+ * supported when it is connected to a SSB core
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+ * for now.
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+ */
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return -ENODEV;
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+ }
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- tp->phy_id = p->phy_id;
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if (!tp->phy_id ||
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tp->phy_id == TG3_PHY_ID_BCM8002)
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tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
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@@ -14382,6 +14490,11 @@ static int __devinit tg3_get_invariants(
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}
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}
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@ -272,7 +337,7 @@
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/* Get eeprom hw config before calling tg3_set_power_state().
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* In particular, the TG3_FLAG_IS_NIC flag must be
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* determined before calling tg3_set_power_state() so that
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@@ -14798,6 +14873,10 @@ static int __devinit tg3_get_device_addr
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@@ -14798,6 +14911,10 @@ static int __devinit tg3_get_device_addr
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}
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if (!is_valid_ether_addr(&dev->dev_addr[0])) {
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@ -283,16 +348,17 @@
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#ifdef CONFIG_SPARC
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if (!tg3_get_default_macaddr_sparc(tp))
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return 0;
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@@ -15296,6 +15375,8 @@ static char * __devinit tg3_phy_string(s
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case TG3_PHY_ID_BCM5704: return "5704";
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case TG3_PHY_ID_BCM5705: return "5705";
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case TG3_PHY_ID_BCM5750: return "5750";
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+ case TG3_PHY_ID_BCM5750_2: return "5750-2";
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+ case TG3_PHY_ID_BCM5750_3: return "5750-3";
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case TG3_PHY_ID_BCM5752: return "5752";
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case TG3_PHY_ID_BCM5714: return "5714";
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case TG3_PHY_ID_BCM5780: return "5780";
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@@ -15506,6 +15587,13 @@ static int __devinit tg3_init_one(struct
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@@ -15082,7 +15199,8 @@ static int __devinit tg3_test_dma(struct
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if (tg3_flag(tp, 40BIT_DMA_BUG) &&
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
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tp->dma_rwctrl |= 0x8000;
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- else if (ccval == 0x6 || ccval == 0x7)
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+ else if ((ccval == 0x6 || ccval == 0x7) ||
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+ tg3_flag(tp, ONE_DMA_AT_ONCE))
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tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
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@@ -15506,6 +15624,17 @@ static int __devinit tg3_init_one(struct
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tp->msg_enable = tg3_debug;
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else
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tp->msg_enable = TG3_DEF_MSG_ENABLE;
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@ -300,43 +366,40 @@
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+ tg3_flag_set(tp, IS_SSB_CORE);
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+ if (ssb_gige_must_flush_posted_writes(pdev))
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+ tg3_flag_set(tp, FLUSH_POSTED_WRITES);
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+ if (ssb_gige_one_dma_at_once(pdev))
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+ tg3_flag_set(tp, ONE_DMA_AT_ONCE);
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+ if (ssb_gige_have_roboswitch(pdev))
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+ tg3_flag_set(tp, ROBOSWITCH);
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+ if (ssb_gige_is_rgmii(pdev))
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+ tg3_flag_set(tp, RGMII_MODE);
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+ }
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/* The word/byte swap controls here control register access byte
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* swapping. DMA data byte swapping is controlled in the GRC_MODE
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--- a/drivers/net/ethernet/broadcom/tg3.h
|
||||
+++ b/drivers/net/ethernet/broadcom/tg3.h
|
||||
@@ -2940,6 +2940,9 @@ enum TG3_FLAGS {
|
||||
@@ -2940,6 +2940,11 @@ enum TG3_FLAGS {
|
||||
TG3_FLAG_57765_PLUS,
|
||||
TG3_FLAG_57765_CLASS,
|
||||
TG3_FLAG_5717_PLUS,
|
||||
+ TG3_FLAG_IS_SSB_CORE,
|
||||
+ TG3_FLAG_FLUSH_POSTED_WRITES,
|
||||
+ TG3_FLAG_ROBOSWITCH,
|
||||
+ TG3_FLAG_ONE_DMA_AT_ONCE,
|
||||
+ TG3_FLAG_RGMII_MODE,
|
||||
|
||||
/* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
|
||||
TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
|
||||
@@ -3089,6 +3092,8 @@ struct tg3 {
|
||||
#define TG3_PHY_ID_BCM5704 0x60008190
|
||||
#define TG3_PHY_ID_BCM5705 0x600081a0
|
||||
#define TG3_PHY_ID_BCM5750 0x60008180
|
||||
+#define TG3_PHY_ID_BCM5750_2 0xbc050cd0
|
||||
+#define TG3_PHY_ID_BCM5750_3 0xbc050f80
|
||||
#define TG3_PHY_ID_BCM5752 0x60008100
|
||||
#define TG3_PHY_ID_BCM5714 0x60008340
|
||||
#define TG3_PHY_ID_BCM5780 0x60008350
|
||||
@@ -3126,7 +3131,8 @@ struct tg3 {
|
||||
(X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
|
||||
(X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
|
||||
(X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
|
||||
- (X) == TG3_PHY_ID_BCM8002)
|
||||
+ (X) == TG3_PHY_ID_BCM8002 || (X) == TG3_PHY_ID_BCM5750_2 || \
|
||||
+ (X) == TG3_PHY_ID_BCM5750_3)
|
||||
|
||||
u32 phy_flags;
|
||||
#define TG3_PHYFLG_IS_LOW_POWER 0x00000001
|
||||
--- a/include/linux/pci_ids.h
|
||||
+++ b/include/linux/pci_ids.h
|
||||
@@ -2120,6 +2120,7 @@
|
||||
#define PCI_DEVICE_ID_TIGON3_5754M 0x1672
|
||||
#define PCI_DEVICE_ID_TIGON3_5755M 0x1673
|
||||
#define PCI_DEVICE_ID_TIGON3_5756 0x1674
|
||||
+#define PCI_DEVICE_ID_TIGON3_5750 0x1676
|
||||
#define PCI_DEVICE_ID_TIGON3_5751 0x1677
|
||||
#define PCI_DEVICE_ID_TIGON3_5715 0x1678
|
||||
#define PCI_DEVICE_ID_TIGON3_5715S 0x1679
|
||||
--- a/include/linux/ssb/ssb_driver_gige.h
|
||||
+++ b/include/linux/ssb/ssb_driver_gige.h
|
||||
@@ -97,21 +97,12 @@ static inline bool ssb_gige_must_flush_p
|
||||
@ -374,13 +437,3 @@
|
||||
|
||||
#endif /* CONFIG_SSB_DRIVER_GIGE */
|
||||
#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
|
||||
--- a/include/linux/pci_ids.h
|
||||
+++ b/include/linux/pci_ids.h
|
||||
@@ -2120,6 +2120,7 @@
|
||||
#define PCI_DEVICE_ID_TIGON3_5754M 0x1672
|
||||
#define PCI_DEVICE_ID_TIGON3_5755M 0x1673
|
||||
#define PCI_DEVICE_ID_TIGON3_5756 0x1674
|
||||
+#define PCI_DEVICE_ID_TIGON3_5750 0x1676
|
||||
#define PCI_DEVICE_ID_TIGON3_5751 0x1677
|
||||
#define PCI_DEVICE_ID_TIGON3_5715 0x1678
|
||||
#define PCI_DEVICE_ID_TIGON3_5715S 0x1679
|
||||
|
||||
Loading…
Reference in New Issue
Block a user