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git://projects.qi-hardware.com/openwrt-xburst.git
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[ltq-dsl]
* add support for ar9 * add support for ase (vr9 support is still a todo) git-svn-id: svn://svn.openwrt.org/openwrt/trunk@28406 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
@@ -1,10 +1,33 @@
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/******************************************************************************
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**
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** FILE NAME : ifxmips_atm_ppe_common.h
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** PROJECT : UEIP
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** MODULES : ATM (ADSL)
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**
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** DATE : 1 AUG 2005
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** AUTHOR : Xu Liang
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** DESCRIPTION : ATM Driver (PPE Registers)
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 4 AUG 2005 Xu Liang Initiate Version
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** 23 OCT 2006 Xu Liang Add GPL header.
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** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
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*******************************************************************************/
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#ifndef IFXMIPS_ATM_PPE_COMMON_H
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#define IFXMIPS_ATM_PPE_COMMON_H
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#if defined(CONFIG_LANTIQ)
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#include "ifxmips_atm_ppe_danube.h"
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#define CONFIG_DANUBE
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#elif defined(CONFIG_DANUBE)
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#if defined(CONFIG_DANUBE)
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#include "ifxmips_atm_ppe_danube.h"
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#elif defined(CONFIG_AMAZON_SE)
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#include "ifxmips_atm_ppe_amazon_se.h"
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@@ -17,6 +40,7 @@
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#endif
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/*
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* Code/Data Memory (CDM) Interface Configuration Register
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*/
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@@ -207,24 +231,134 @@
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/*
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* RTHA/TTHA Registers
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*/
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#define SFSM_STATE0 PPE_REG_ADDR(0x0410)
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#define SFSM_STATE1 PPE_REG_ADDR(0x0411)
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#define SFSM_DBA0 PPE_REG_ADDR(0x0412)
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#define SFSM_DBA1 PPE_REG_ADDR(0x0413)
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#define SFSM_CBA0 PPE_REG_ADDR(0x0414)
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#define SFSM_CBA1 PPE_REG_ADDR(0x0415)
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#define SFSM_CFG0 PPE_REG_ADDR(0x0416)
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#define SFSM_CFG1 PPE_REG_ADDR(0x0417)
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#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C)
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#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D)
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#define FFSM_DBA0 PPE_REG_ADDR(0x0508)
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#define FFSM_DBA1 PPE_REG_ADDR(0x0509)
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#define FFSM_CFG0 PPE_REG_ADDR(0x050A)
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#define FFSM_CFG1 PPE_REG_ADDR(0x050B)
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#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E)
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#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F)
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#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514)
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#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515)
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#define RFBI_CFG PPE_REG_ADDR(0x0400)
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#define RBA_CFG0 PPE_REG_ADDR(0x0404)
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#define RBA_CFG1 PPE_REG_ADDR(0x0405)
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#define RCA_CFG0 PPE_REG_ADDR(0x0408)
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#define RCA_CFG1 PPE_REG_ADDR(0x0409)
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#define RDES_CFG0 PPE_REG_ADDR(0x040C)
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#define RDES_CFG1 PPE_REG_ADDR(0x040D)
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#define SFSM_STATE0 PPE_REG_ADDR(0x0410)
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#define SFSM_STATE1 PPE_REG_ADDR(0x0411)
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#define SFSM_DBA0 PPE_REG_ADDR(0x0412)
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#define SFSM_DBA1 PPE_REG_ADDR(0x0413)
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#define SFSM_CBA0 PPE_REG_ADDR(0x0414)
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#define SFSM_CBA1 PPE_REG_ADDR(0x0415)
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#define SFSM_CFG0 PPE_REG_ADDR(0x0416)
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#define SFSM_CFG1 PPE_REG_ADDR(0x0417)
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#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C)
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#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D)
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#define FFSM_DBA0 PPE_REG_ADDR(0x0508)
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#define FFSM_DBA1 PPE_REG_ADDR(0x0509)
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#define FFSM_CFG0 PPE_REG_ADDR(0x050A)
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#define FFSM_CFG1 PPE_REG_ADDR(0x050B)
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#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E)
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#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F)
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#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514)
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#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515)
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/*
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* PPE TC Logic Registers (partial)
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*/
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#define DREG_A_VERSION PPE_REG_ADDR(0x0D00)
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#define DREG_A_CFG PPE_REG_ADDR(0x0D01)
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#define DREG_AT_CTRL PPE_REG_ADDR(0x0D02)
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#define DREG_AT_CB_CFG0 PPE_REG_ADDR(0x0D03)
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#define DREG_AT_CB_CFG1 PPE_REG_ADDR(0x0D04)
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#define DREG_AR_CTRL PPE_REG_ADDR(0x0D08)
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#define DREG_AR_CB_CFG0 PPE_REG_ADDR(0x0D09)
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#define DREG_AR_CB_CFG1 PPE_REG_ADDR(0x0D0A)
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#define DREG_A_UTPCFG PPE_REG_ADDR(0x0D0E)
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#define DREG_A_STATUS PPE_REG_ADDR(0x0D0F)
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#define DREG_AT_CFG0 PPE_REG_ADDR(0x0D20)
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#define DREG_AT_CFG1 PPE_REG_ADDR(0x0D21)
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#define DREG_AT_FB_SIZE0 PPE_REG_ADDR(0x0D22)
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#define DREG_AT_FB_SIZE1 PPE_REG_ADDR(0x0D23)
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#define DREG_AT_CELL0 PPE_REG_ADDR(0x0D24)
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#define DREG_AT_CELL1 PPE_REG_ADDR(0x0D25)
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#define DREG_AT_IDLE_CNT0 PPE_REG_ADDR(0x0D26)
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#define DREG_AT_IDLE_CNT1 PPE_REG_ADDR(0x0D27)
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#define DREG_AT_IDLE0 PPE_REG_ADDR(0x0D28)
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#define DREG_AT_IDLE1 PPE_REG_ADDR(0x0D29)
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#define DREG_AR_CFG0 PPE_REG_ADDR(0x0D60)
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#define DREG_AR_CFG1 PPE_REG_ADDR(0x0D61)
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#define DREG_AR_CELL0 PPE_REG_ADDR(0x0D68)
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#define DREG_AR_CELL1 PPE_REG_ADDR(0x0D69)
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#define DREG_AR_IDLE_CNT0 PPE_REG_ADDR(0x0D6A)
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#define DREG_AR_IDLE_CNT1 PPE_REG_ADDR(0x0D6B)
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#define DREG_AR_AIIDLE_CNT0 PPE_REG_ADDR(0x0D6C)
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#define DREG_AR_AIIDLE_CNT1 PPE_REG_ADDR(0x0D6D)
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#define DREG_AR_BE_CNT0 PPE_REG_ADDR(0x0D6E)
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#define DREG_AR_BE_CNT1 PPE_REG_ADDR(0x0D6F)
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#define DREG_AR_HEC_CNT0 PPE_REG_ADDR(0x0D70)
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#define DREG_AR_HEC_CNT1 PPE_REG_ADDR(0x0D71)
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#define DREG_AR_IDLE0 PPE_REG_ADDR(0x0D74)
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#define DREG_AR_IDLE1 PPE_REG_ADDR(0x0D75)
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#define DREG_AR_CVN_CNT0 PPE_REG_ADDR(0x0DA4)
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#define DREG_AR_CVN_CNT1 PPE_REG_ADDR(0x0DA5)
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#define DREG_AR_CVNP_CNT0 PPE_REG_ADDR(0x0DA6)
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#define DREG_AR_CVNP_CNT1 PPE_REG_ADDR(0x0DA7)
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#define DREG_B0_LADR PPE_REG_ADDR(0x0DA8)
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#define DREG_B1_LADR PPE_REG_ADDR(0x0DA9)
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#define SFSM_DBA(i) ( (SFSM_dba * ) PPE_REG_ADDR(0x0412 + (i)))
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#define SFSM_CBA(i) ( (SFSM_cba * ) PPE_REG_ADDR(0x0414 + (i)))
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#define SFSM_CFG(i) ( (SFSM_cfg * ) PPE_REG_ADDR(0x0416 + (i)))
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#define SFSM_PGCNT(i) ( (SFSM_pgcnt * ) PPE_REG_ADDR(0x041C + (i)))
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#define FFSM_DBA(i) ( (FFSM_dba * ) PPE_REG_ADDR(0x0508 + (i)))
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#define FFSM_CFG(i) ( (FFSM_cfg * ) PPE_REG_ADDR(0x050A + (i)))
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#define FFSM_PGCNT(i) ( (FFSM_pgcnt * ) PPE_REG_ADDR(0x0514 + (i)))
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typedef struct {
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unsigned int res : 19;
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unsigned int dbase : 13;
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} SFSM_dba;
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typedef struct {
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unsigned int res : 19;
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unsigned int cbase : 13;
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} SFSM_cba;
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typedef struct {
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unsigned int res : 15;
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unsigned int endian : 1;
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unsigned int idlekeep: 1;
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unsigned int sen : 1;
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unsigned int res1 : 8;
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unsigned int pnum : 6;
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} SFSM_cfg;
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typedef struct {
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unsigned int res : 17;
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unsigned int pptr : 6;
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unsigned int dcmd : 1;
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unsigned int res1 : 2;
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unsigned int upage : 6;
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} SFSM_pgcnt;
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typedef struct {
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unsigned int res : 19;
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unsigned int dbase : 13;
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} FFSM_dba;
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typedef struct {
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unsigned int res : 12;
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unsigned int rstptr : 1;
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unsigned int clvpage : 1;
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unsigned int fidle : 1;
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unsigned int endian : 1;
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unsigned int res1 : 10;
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unsigned int pnum : 6;
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} FFSM_cfg;
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typedef struct {
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unsigned int res : 17;
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unsigned int ival : 6;
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unsigned int icmd : 1;
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unsigned int res1 : 2;
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unsigned int vpage : 6;
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} FFSM_pgcnt;
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