mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 13:11:09 +02:00
More SSB GigE fixes.
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10521 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
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parent
e693bef4a8
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90344b92f9
@ -1,7 +1,7 @@
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Index: linux-2.6.23.16/drivers/ssb/Kconfig
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===================================================================
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--- linux-2.6.23.16.orig/drivers/ssb/Kconfig 2008-02-20 18:32:01.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/Kconfig 2008-02-20 18:32:31.000000000 +0100
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--- linux-2.6.23.16.orig/drivers/ssb/Kconfig 2008-02-22 19:40:57.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/Kconfig 2008-02-22 19:42:52.000000000 +0100
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@@ -120,4 +120,13 @@ config SSB_DRIVER_EXTIF
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If unsure, say N
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@ -18,8 +18,8 @@ Index: linux-2.6.23.16/drivers/ssb/Kconfig
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endmenu
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Index: linux-2.6.23.16/drivers/ssb/Makefile
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===================================================================
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--- linux-2.6.23.16.orig/drivers/ssb/Makefile 2008-02-20 18:32:01.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/Makefile 2008-02-20 18:32:31.000000000 +0100
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--- linux-2.6.23.16.orig/drivers/ssb/Makefile 2008-02-22 19:40:57.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/Makefile 2008-02-22 19:42:52.000000000 +0100
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@@ -11,6 +11,7 @@ ssb-y += driver_chipcommon.o
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ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
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ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
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@ -31,8 +31,8 @@ Index: linux-2.6.23.16/drivers/ssb/Makefile
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Index: linux-2.6.23.16/drivers/ssb/driver_gige.c
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ linux-2.6.23.16/drivers/ssb/driver_gige.c 2008-02-20 18:32:31.000000000 +0100
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@@ -0,0 +1,268 @@
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+++ linux-2.6.23.16/drivers/ssb/driver_gige.c 2008-02-22 20:59:46.000000000 +0100
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@@ -0,0 +1,281 @@
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+/*
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+ * Sonics Silicon Backplane
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+ * Broadcom Gigabit Ethernet core driver
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@ -202,7 +202,7 @@ Index: linux-2.6.23.16/drivers/ssb/driver_gige.c
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+static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
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+{
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+ struct ssb_gige *dev;
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+ u32 base;
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+ u32 base, tmslow, tmshigh;
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+
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+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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+ if (!dev)
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@ -213,12 +213,11 @@ Index: linux-2.6.23.16/drivers/ssb/driver_gige.c
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+ dev->pci_controller.pci_ops = &dev->pci_ops;
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+ dev->pci_controller.io_resource = &dev->io_resource;
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+ dev->pci_controller.mem_resource = &dev->mem_resource;
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+ dev->pci_controller.mem_offset = 0x24000000;
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+ dev->pci_controller.io_map_base = 0x800;
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+ dev->pci_ops.read = ssb_gige_pci_read_config;
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+ dev->pci_ops.write = ssb_gige_pci_write_config;
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+
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+ dev->io_resource.name = "SSB GIGE I/O";
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+ dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
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+ dev->io_resource.start = 0x800;
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+ dev->io_resource.end = 0x8FF;
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+ dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
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@ -231,9 +230,9 @@ Index: linux-2.6.23.16/drivers/ssb/driver_gige.c
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+ gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
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+ gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
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+
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+ dev->mem_resource.name = "SSB GIGE memory";
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+ dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
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+ dev->mem_resource.start = base;
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+ dev->mem_resource.end = base + SSB_CORE_SIZE - 1;
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+ dev->mem_resource.end = base + 0x10000 - 1;
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+ dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
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+
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+ /* Enable the memory region. */
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@ -249,7 +248,21 @@ Index: linux-2.6.23.16/drivers/ssb/driver_gige.c
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+ */
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+ gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
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+
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+ //TODO
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+ /* Check if we have an RGMII or GMII PHY-bus.
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+ * On RGMII do not bypass the DLLs */
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+ tmslow = ssb_read32(sdev, SSB_TMSLOW);
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+ tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
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+ if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
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+ tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
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+ tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
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+ dev->has_rgmii = 1;
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+ } else {
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+ tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
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+ tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
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+ dev->has_rgmii = 0;
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+ }
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+ tmslow |= SSB_GIGE_TMSLOW_DLLEN;
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+ ssb_write32(sdev, SSB_TMSLOW, tmslow);
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+
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+ ssb_set_drvdata(sdev, dev);
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+ register_pci_controller(&dev->pci_controller);
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@ -304,16 +317,19 @@ Index: linux-2.6.23.16/drivers/ssb/driver_gige.c
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Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h 2008-02-20 18:32:31.000000000 +0100
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@@ -0,0 +1,70 @@
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+++ linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h 2008-02-22 20:47:58.000000000 +0100
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@@ -0,0 +1,178 @@
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+#ifndef LINUX_SSB_DRIVER_GIGE_H_
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+#define LINUX_SSB_DRIVER_GIGE_H_
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+
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+#include <linux/ssb/ssb.h>
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+#include <linux/pci.h>
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+#include <linux/spinlock.h>
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+
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+
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+#ifdef CONFIG_SSB_DRIVER_GIGE
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+
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+
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+#define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
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+#define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
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+#define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
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@ -324,11 +340,29 @@ Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h
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+#define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
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+#define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
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+
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+/* TM Status High flags */
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+#define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
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+/* TM Status Low flags */
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+#define SSB_GIGE_TMSLOW_TXBYPASS 0x00080000 /* TX bypass (no delay) */
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+#define SSB_GIGE_TMSLOW_RXBYPASS 0x00100000 /* RX bypass (no delay) */
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+#define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
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+
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+/* Boardflags (low) */
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+#define SSB_GIGE_BFL_ROBOSWITCH 0x0010
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+
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+
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+#define SSB_GIGE_MEM_RES_NAME "SSB Broadcom 47xx GigE memory"
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+#define SSB_GIGE_IO_RES_NAME "SSB Broadcom 47xx GigE I/O"
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+
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+struct ssb_gige {
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+ struct ssb_device *dev;
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+
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+ spinlock_t lock;
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+
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+ /* True, if the device has an RGMII bus.
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+ * False, if the device has a GMII bus. */
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+ bool has_rgmii;
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+
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+ /* The PCI controller device. */
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+ struct pci_controller pci_controller;
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+ struct pci_ops pci_ops;
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@ -336,6 +370,68 @@ Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h
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+ struct resource io_resource;
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+};
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+
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+/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
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+static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
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+{
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+ return (pdev->resource[0].name &&
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+ strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
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+}
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+
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+/* Convert a pci_dev pointer to a ssb_gige pointer. */
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+static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
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+{
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+ if (!pdev_is_ssb_gige_core(pdev))
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+ return NULL;
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+ return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
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+}
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+
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+/* Returns whether the PHY is connected by an RGMII bus. */
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+static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
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+{
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+ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
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+ return (dev ? dev->has_rgmii : 0);
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+}
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+
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+/* Returns whether we have a Roboswitch. */
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+static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
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+{
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+ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
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+ if (dev)
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+ return !!(dev->dev->bus->sprom.boardflags_lo &
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+ SSB_GIGE_BFL_ROBOSWITCH);
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+ return 0;
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+}
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+
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+/* Returns whether we can only do one DMA at once. */
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+static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
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+{
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+ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
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+ if (dev)
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+ return ((dev->dev->bus->chip_id == 0x4785) &&
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+ (dev->dev->bus->chip_rev < 2));
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+ return 0;
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+}
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+
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+/* Returns whether we must flush posted writes. */
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+static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
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+{
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+ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
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+ if (dev)
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+ return (dev->dev->bus->chip_id == 0x4785);
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+ return 0;
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+}
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+
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+extern char * nvram_get(const char *name); //FIXME
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+/* Get the device MAC address */
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+static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
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+{
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+#ifdef CONFIG_BCM947XX
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+ char *res = nvram_get("et0macaddr"); //FIXME
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+ if (res)
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+ memcpy(macaddr, res, 6);
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+#endif
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+}
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+
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+extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
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+ struct pci_dev *pdev);
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+extern int ssb_gige_map_irq(struct ssb_device *sdev,
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@ -374,12 +470,37 @@ Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h
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+{
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+}
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+
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+static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
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+{
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+ return 0;
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+}
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+static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
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+{
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+ return NULL;
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+}
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+static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
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+{
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+ return 0;
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+}
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+static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
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+{
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+ return 0;
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+}
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+static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
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+{
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+ return 0;
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+}
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+static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
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+{
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+ return 0;
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+}
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+
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+#endif /* CONFIG_SSB_DRIVER_GIGE */
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+#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
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Index: linux-2.6.23.16/drivers/ssb/driver_pcicore.c
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===================================================================
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--- linux-2.6.23.16.orig/drivers/ssb/driver_pcicore.c 2008-02-20 18:32:01.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/driver_pcicore.c 2008-02-20 18:32:31.000000000 +0100
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--- linux-2.6.23.16.orig/drivers/ssb/driver_pcicore.c 2008-02-22 19:40:57.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/driver_pcicore.c 2008-02-22 19:42:52.000000000 +0100
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@@ -60,74 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock);
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/* Core to access the external PCI config space. Can only have one. */
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static struct ssb_pcicore *extpci_core;
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@ -550,8 +671,8 @@ Index: linux-2.6.23.16/drivers/ssb/driver_pcicore.c
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u32 val;
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Index: linux-2.6.23.16/drivers/ssb/embedded.c
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===================================================================
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--- linux-2.6.23.16.orig/drivers/ssb/embedded.c 2008-02-20 18:32:01.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/embedded.c 2008-02-20 18:32:31.000000000 +0100
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--- linux-2.6.23.16.orig/drivers/ssb/embedded.c 2008-02-22 19:40:57.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/embedded.c 2008-02-22 19:42:52.000000000 +0100
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@@ -10,6 +10,9 @@
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#include <linux/ssb/ssb.h>
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@ -655,8 +776,8 @@ Index: linux-2.6.23.16/drivers/ssb/embedded.c
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+}
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Index: linux-2.6.23.16/include/linux/ssb/ssb.h
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===================================================================
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--- linux-2.6.23.16.orig/include/linux/ssb/ssb.h 2008-02-20 18:32:01.000000000 +0100
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+++ linux-2.6.23.16/include/linux/ssb/ssb.h 2008-02-20 18:32:31.000000000 +0100
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--- linux-2.6.23.16.orig/include/linux/ssb/ssb.h 2008-02-22 19:40:57.000000000 +0100
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+++ linux-2.6.23.16/include/linux/ssb/ssb.h 2008-02-22 19:42:52.000000000 +0100
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@@ -422,5 +422,12 @@ extern int ssb_bus_powerup(struct ssb_bu
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extern u32 ssb_admatch_base(u32 adm);
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extern u32 ssb_admatch_size(u32 adm);
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@ -672,8 +793,8 @@ Index: linux-2.6.23.16/include/linux/ssb/ssb.h
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#endif /* LINUX_SSB_H_ */
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Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h
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===================================================================
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--- linux-2.6.23.16.orig/include/linux/ssb/ssb_driver_pci.h 2008-02-20 18:32:01.000000000 +0100
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+++ linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h 2008-02-20 18:32:31.000000000 +0100
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--- linux-2.6.23.16.orig/include/linux/ssb/ssb_driver_pci.h 2008-02-22 19:40:57.000000000 +0100
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+++ linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h 2008-02-22 19:42:52.000000000 +0100
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@@ -1,6 +1,11 @@
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#ifndef LINUX_SSB_PCICORE_H_
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#define LINUX_SSB_PCICORE_H_
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@ -715,8 +836,8 @@ Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h
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#endif /* LINUX_SSB_PCICORE_H_ */
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Index: linux-2.6.23.16/drivers/ssb/main.c
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===================================================================
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--- linux-2.6.23.16.orig/drivers/ssb/main.c 2008-02-20 18:32:01.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/main.c 2008-02-20 18:32:31.000000000 +0100
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--- linux-2.6.23.16.orig/drivers/ssb/main.c 2008-02-22 19:40:57.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/main.c 2008-02-22 19:42:52.000000000 +0100
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@@ -14,6 +14,7 @@
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#include <linux/io.h>
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#include <linux/ssb/ssb.h>
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@ -777,8 +898,8 @@ Index: linux-2.6.23.16/drivers/ssb/main.c
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}
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Index: linux-2.6.23.16/drivers/ssb/ssb_private.h
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===================================================================
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--- linux-2.6.23.16.orig/drivers/ssb/ssb_private.h 2008-02-20 18:32:01.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/ssb_private.h 2008-02-20 18:32:31.000000000 +0100
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--- linux-2.6.23.16.orig/drivers/ssb/ssb_private.h 2008-02-22 19:40:57.000000000 +0100
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+++ linux-2.6.23.16/drivers/ssb/ssb_private.h 2008-02-22 19:42:52.000000000 +0100
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@@ -118,6 +118,8 @@ extern u32 ssb_calc_clock_rate(u32 pllty
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extern int ssb_devices_freeze(struct ssb_bus *bus);
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extern int ssb_devices_thaw(struct ssb_bus *bus);
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@ -788,3 +909,252 @@ Index: linux-2.6.23.16/drivers/ssb/ssb_private.h
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/* b43_pci_bridge.c */
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#ifdef CONFIG_SSB_PCIHOST
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Index: linux-2.6.23.16/drivers/net/tg3.c
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===================================================================
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--- linux-2.6.23.16.orig/drivers/net/tg3.c 2008-02-22 19:40:57.000000000 +0100
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+++ linux-2.6.23.16/drivers/net/tg3.c 2008-02-23 20:02:58.000000000 +0100
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@@ -38,6 +38,7 @@
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#include <linux/workqueue.h>
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#include <linux/prefetch.h>
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#include <linux/dma-mapping.h>
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||||
+#include <linux/ssb/ssb_driver_gige.h>
|
||||
|
||||
#include <net/checksum.h>
|
||||
#include <net/ip.h>
|
||||
@@ -410,8 +411,9 @@ static void _tw32_flush(struct tg3 *tp,
|
||||
static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
|
||||
{
|
||||
tp->write32_mbox(tp, off, val);
|
||||
- if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
|
||||
- !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
|
||||
+ if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
|
||||
+ (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
|
||||
+ !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
|
||||
tp->read32_mbox(tp, off);
|
||||
}
|
||||
|
||||
@@ -1988,6 +1990,14 @@ static int tg3_setup_copper_phy(struct t
|
||||
tp->link_config.active_duplex = current_duplex;
|
||||
}
|
||||
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
|
||||
+ current_link_up = 1;
|
||||
+ current_speed = SPEED_1000; //FIXME
|
||||
+ current_duplex = DUPLEX_FULL;
|
||||
+ tp->link_config.active_speed = current_speed;
|
||||
+ tp->link_config.active_duplex = current_duplex;
|
||||
+ }
|
||||
+
|
||||
if (current_link_up == 1 &&
|
||||
(tp->link_config.active_duplex == DUPLEX_FULL) &&
|
||||
(tp->link_config.autoneg == AUTONEG_ENABLE)) {
|
||||
@@ -4813,6 +4823,11 @@ static int tg3_poll_fw(struct tg3 *tp)
|
||||
int i;
|
||||
u32 val;
|
||||
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||
+ /* We don't use firmware. */
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
|
||||
/* Wait up to 20ms for init done. */
|
||||
for (i = 0; i < 200; i++) {
|
||||
@@ -5040,6 +5055,14 @@ static int tg3_chip_reset(struct tg3 *tp
|
||||
tw32(0x5000, 0x400);
|
||||
}
|
||||
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||
+ /* BCM4785: In order to avoid repercussions from using potentially
|
||||
+ * defective internal ROM, stop the Rx RISC CPU, which is not
|
||||
+ * required. */
|
||||
+ tg3_stop_fw(tp);
|
||||
+ tg3_halt_cpu(tp, RX_CPU_BASE);
|
||||
+ }
|
||||
+
|
||||
tw32(GRC_MODE, tp->grc_mode);
|
||||
|
||||
if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
|
||||
@@ -5308,9 +5331,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
- /* Clear firmware's nvram arbitration. */
|
||||
- if (tp->tg3_flags & TG3_FLAG_NVRAM)
|
||||
- tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
|
||||
+ if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
|
||||
+ /* Clear firmware's nvram arbitration. */
|
||||
+ if (tp->tg3_flags & TG3_FLAG_NVRAM)
|
||||
+ tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -5391,6 +5417,11 @@ static int tg3_load_5701_a0_firmware_fix
|
||||
struct fw_info info;
|
||||
int err, i;
|
||||
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||
+ /* We don't use firmware. */
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
info.text_base = TG3_FW_TEXT_ADDR;
|
||||
info.text_len = TG3_FW_TEXT_LEN;
|
||||
info.text_data = &tg3FwText[0];
|
||||
@@ -5949,6 +5980,11 @@ static int tg3_load_tso_firmware(struct
|
||||
unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
|
||||
int err, i;
|
||||
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||
+ /* We don't use firmware. */
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
|
||||
return 0;
|
||||
|
||||
@@ -6850,6 +6886,11 @@ static void tg3_timer(unsigned long __op
|
||||
|
||||
spin_lock(&tp->lock);
|
||||
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
|
||||
+ /* BCM4785: Flush posted writes from GbE to host memory. */
|
||||
+ tr32(HOSTCC_MODE);
|
||||
+ }
|
||||
+
|
||||
if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
|
||||
/* All of this garbage is because when using non-tagged
|
||||
* IRQ status the mailbox/status_block protocol the chip
|
||||
@@ -8432,6 +8473,11 @@ static int tg3_test_nvram(struct tg3 *tp
|
||||
u32 *buf, csum, magic;
|
||||
int i, j, err = 0, size;
|
||||
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||
+ /* We don't have NVRAM. */
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
|
||||
return -EIO;
|
||||
|
||||
@@ -9571,6 +9617,12 @@ static void __devinit tg3_get_5906_nvram
|
||||
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
|
||||
static void __devinit tg3_nvram_init(struct tg3 *tp)
|
||||
{
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
|
||||
+ /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
|
||||
+ tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
tw32_f(GRC_EEPROM_ADDR,
|
||||
(EEPROM_ADDR_FSM_RESET |
|
||||
(EEPROM_DEFAULT_CLOCK_PERIOD <<
|
||||
@@ -9706,6 +9758,9 @@ static int tg3_nvram_read(struct tg3 *tp
|
||||
{
|
||||
int ret;
|
||||
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
|
||||
return tg3_nvram_read_using_eeprom(tp, offset, val);
|
||||
|
||||
@@ -9938,6 +9993,9 @@ static int tg3_nvram_write_block(struct
|
||||
{
|
||||
int ret;
|
||||
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
|
||||
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
|
||||
~GRC_LCLCTRL_GPIO_OUTPUT1);
|
||||
@@ -10804,7 +10862,6 @@ static int __devinit tg3_get_invariants(
|
||||
tp->write32 = tg3_write_flush_reg32;
|
||||
}
|
||||
|
||||
-
|
||||
if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
|
||||
(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
|
||||
tp->write32_tx_mbox = tg3_write32_tx_mbox;
|
||||
@@ -10840,6 +10897,11 @@ static int __devinit tg3_get_invariants(
|
||||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
|
||||
tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
|
||||
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
|
||||
+ tp->write32_tx_mbox = tg3_write_flush_reg32;
|
||||
+ tp->write32_rx_mbox = tg3_write_flush_reg32;
|
||||
+ }
|
||||
+
|
||||
/* Get eeprom hw config before calling tg3_set_power_state().
|
||||
* In particular, the TG3_FLG2_IS_NIC flag must be
|
||||
* determined before calling tg3_set_power_state() so that
|
||||
@@ -11184,6 +11246,10 @@ static int __devinit tg3_get_device_addr
|
||||
}
|
||||
|
||||
if (!is_valid_ether_addr(&dev->dev_addr[0])) {
|
||||
+ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
|
||||
+ ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
|
||||
+ }
|
||||
+ if (!is_valid_ether_addr(&dev->dev_addr[0])) {
|
||||
#ifdef CONFIG_SPARC64
|
||||
if (!tg3_get_default_macaddr_sparc(tp))
|
||||
return 0;
|
||||
@@ -11675,6 +11741,7 @@ static char * __devinit tg3_phy_string(s
|
||||
case PHY_ID_BCM5704: return "5704";
|
||||
case PHY_ID_BCM5705: return "5705";
|
||||
case PHY_ID_BCM5750: return "5750";
|
||||
+ case PHY_ID_BCM5750_2: return "5750-2";
|
||||
case PHY_ID_BCM5752: return "5752";
|
||||
case PHY_ID_BCM5714: return "5714";
|
||||
case PHY_ID_BCM5780: return "5780";
|
||||
@@ -11859,6 +11926,13 @@ static int __devinit tg3_init_one(struct
|
||||
tp->msg_enable = tg3_debug;
|
||||
else
|
||||
tp->msg_enable = TG3_DEF_MSG_ENABLE;
|
||||
+ if (pdev_is_ssb_gige_core(pdev)) {
|
||||
+ tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
|
||||
+ if (ssb_gige_must_flush_posted_writes(pdev))
|
||||
+ tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
|
||||
+ if (ssb_gige_have_roboswitch(pdev))
|
||||
+ tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
|
||||
+ }
|
||||
|
||||
/* The word/byte swap controls here control register access byte
|
||||
* swapping. DMA data byte swapping is controlled in the GRC_MODE
|
||||
Index: linux-2.6.23.16/drivers/net/tg3.h
|
||||
===================================================================
|
||||
--- linux-2.6.23.16.orig/drivers/net/tg3.h 2008-02-22 19:40:57.000000000 +0100
|
||||
+++ linux-2.6.23.16/drivers/net/tg3.h 2008-02-23 19:35:15.000000000 +0100
|
||||
@@ -2279,6 +2279,10 @@ struct tg3 {
|
||||
#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
|
||||
#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
|
||||
#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
|
||||
+ u32 tg3_flags3;
|
||||
+#define TG3_FLG3_IS_SSB_CORE 0x00000001
|
||||
+#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00000002
|
||||
+#define TG3_FLG3_ROBOSWITCH 0x00000004
|
||||
|
||||
struct timer_list timer;
|
||||
u16 timer_counter;
|
||||
@@ -2333,6 +2337,7 @@ struct tg3 {
|
||||
#define PHY_ID_BCM5714 0x60008340
|
||||
#define PHY_ID_BCM5780 0x60008350
|
||||
#define PHY_ID_BCM5755 0xbc050cc0
|
||||
+#define PHY_ID_BCM5750_2 0xbc050cd0
|
||||
#define PHY_ID_BCM5787 0xbc050ce0
|
||||
#define PHY_ID_BCM5756 0xbc050ed0
|
||||
#define PHY_ID_BCM5906 0xdc00ac40
|
||||
@@ -2364,7 +2369,8 @@ struct tg3 {
|
||||
(X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
|
||||
(X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
|
||||
(X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
|
||||
- (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002)
|
||||
+ (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002 || \
|
||||
+ (X) == PHY_ID_BCM5750_2)
|
||||
|
||||
struct tg3_hw_stats *hw_stats;
|
||||
dma_addr_t stats_mapping;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user