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git://projects.qi-hardware.com/openwrt-xburst.git
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[ramips] make ramips ethernet use a register mapping table
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33547 3c298f89-4303-0410-b956-a3cf2f4a3e73
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98837afb76
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90960d25b1
@ -47,9 +47,47 @@ static inline void rt305x_esw_exit(void) { }
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#define RADEBUG(fmt, args...) do {} while (0)
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#endif
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enum raeth_reg {
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RAETH_REG_PDMA_GLO_CFG = 0,
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RAETH_REG_PDMA_RST_CFG,
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RAETH_REG_DLY_INT_CFG,
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RAETH_REG_TX_BASE_PTR0,
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RAETH_REG_TX_MAX_CNT0,
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RAETH_REG_TX_CTX_IDX0,
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RAETH_REG_RX_BASE_PTR0,
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RAETH_REG_RX_MAX_CNT0,
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RAETH_REG_RX_CALC_IDX0,
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RAETH_REG_FE_INT_ENABLE,
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RAETH_REG_FE_INT_STATUS,
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RAETH_REG_COUNT
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};
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static const u32 ramips_reg_table[RAETH_REG_COUNT] = {
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[RAETH_REG_PDMA_GLO_CFG] = RAMIPS_PDMA_GLO_CFG,
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[RAETH_REG_PDMA_RST_CFG] = RAMIPS_PDMA_RST_CFG,
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[RAETH_REG_DLY_INT_CFG] = RAMIPS_DLY_INT_CFG,
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[RAETH_REG_TX_BASE_PTR0] = RAMIPS_TX_BASE_PTR0,
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[RAETH_REG_TX_MAX_CNT0] = RAMIPS_TX_MAX_CNT0,
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[RAETH_REG_TX_CTX_IDX0] = RAMIPS_TX_CTX_IDX0,
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[RAETH_REG_RX_BASE_PTR0] = RAMIPS_RX_BASE_PTR0,
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[RAETH_REG_RX_MAX_CNT0] = RAMIPS_RX_MAX_CNT0,
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[RAETH_REG_RX_CALC_IDX0] = RAMIPS_RX_CALC_IDX0,
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[RAETH_REG_FE_INT_ENABLE] = RAMIPS_FE_INT_ENABLE,
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[RAETH_REG_FE_INT_STATUS] = RAMIPS_FE_INT_STATUS,
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};
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static struct net_device * ramips_dev;
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static void __iomem *ramips_fe_base = 0;
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static inline u32 get_reg_offset(enum raeth_reg reg)
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{
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const u32 *table;
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table = ramips_reg_table;
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return table[reg];
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}
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static inline void
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ramips_fe_wr(u32 val, unsigned reg)
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{
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@ -62,22 +100,34 @@ ramips_fe_rr(unsigned reg)
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return __raw_readl(ramips_fe_base + reg);
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}
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static inline void
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ramips_fe_twr(u32 val, enum raeth_reg reg)
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{
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ramips_fe_wr(val, get_reg_offset(reg));
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}
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static inline u32
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ramips_fe_trr(enum raeth_reg reg)
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{
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return ramips_fe_rr(get_reg_offset(reg));
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}
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static inline void
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ramips_fe_int_disable(u32 mask)
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{
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ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) & ~mask,
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RAMIPS_FE_INT_ENABLE);
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ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) & ~mask,
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RAETH_REG_FE_INT_ENABLE);
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/* flush write */
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ramips_fe_rr(RAMIPS_FE_INT_ENABLE);
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ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
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}
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static inline void
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ramips_fe_int_enable(u32 mask)
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{
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ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) | mask,
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RAMIPS_FE_INT_ENABLE);
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ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) | mask,
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RAETH_REG_FE_INT_ENABLE);
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/* flush write */
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ramips_fe_rr(RAMIPS_FE_INT_ENABLE);
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ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
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}
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static inline void
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@ -642,15 +692,15 @@ err_cleanup:
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static void
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ramips_setup_dma(struct raeth_priv *re)
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{
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ramips_fe_wr(re->tx_desc_dma, RAMIPS_TX_BASE_PTR0);
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ramips_fe_wr(NUM_TX_DESC, RAMIPS_TX_MAX_CNT0);
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ramips_fe_wr(0, RAMIPS_TX_CTX_IDX0);
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ramips_fe_wr(RAMIPS_PST_DTX_IDX0, RAMIPS_PDMA_RST_CFG);
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ramips_fe_twr(re->tx_desc_dma, RAETH_REG_TX_BASE_PTR0);
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ramips_fe_twr(NUM_TX_DESC, RAETH_REG_TX_MAX_CNT0);
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ramips_fe_twr(0, RAETH_REG_TX_CTX_IDX0);
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ramips_fe_twr(RAMIPS_PST_DTX_IDX0, RAETH_REG_PDMA_RST_CFG);
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ramips_fe_wr(re->rx_desc_dma, RAMIPS_RX_BASE_PTR0);
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ramips_fe_wr(NUM_RX_DESC, RAMIPS_RX_MAX_CNT0);
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ramips_fe_wr((NUM_RX_DESC - 1), RAMIPS_RX_CALC_IDX0);
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ramips_fe_wr(RAMIPS_PST_DRX_IDX0, RAMIPS_PDMA_RST_CFG);
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ramips_fe_twr(re->rx_desc_dma, RAETH_REG_RX_BASE_PTR0);
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ramips_fe_twr(NUM_RX_DESC, RAETH_REG_RX_MAX_CNT0);
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ramips_fe_twr((NUM_RX_DESC - 1), RAETH_REG_RX_CALC_IDX0);
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ramips_fe_twr(RAMIPS_PST_DRX_IDX0, RAETH_REG_PDMA_RST_CFG);
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}
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static int
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@ -680,7 +730,7 @@ ramips_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
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DMA_TO_DEVICE);
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spin_lock(&re->page_lock);
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tx = ramips_fe_rr(RAMIPS_TX_CTX_IDX0);
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tx = ramips_fe_trr(RAETH_REG_TX_CTX_IDX0);
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tx_next = (tx + 1) % NUM_TX_DESC;
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txi = &re->tx_info[tx];
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@ -700,7 +750,7 @@ ramips_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
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txd->txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
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dev->stats.tx_packets++;
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dev->stats.tx_bytes += skb->len;
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ramips_fe_wr(tx_next, RAMIPS_TX_CTX_IDX0);
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ramips_fe_twr(tx_next, RAETH_REG_TX_CTX_IDX0);
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netdev_sent_queue(dev, skb->len);
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spin_unlock(&re->page_lock);
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return NETDEV_TX_OK;
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@ -720,7 +770,7 @@ ramips_eth_rx_hw(unsigned long ptr)
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int rx;
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int max_rx = 16;
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rx = ramips_fe_rr(RAMIPS_RX_CALC_IDX0);
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rx = ramips_fe_trr(RAETH_REG_RX_CALC_IDX0);
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while (max_rx) {
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struct raeth_rx_info *rxi;
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@ -768,7 +818,7 @@ ramips_eth_rx_hw(unsigned long ptr)
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}
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rxd->rxd2 = RX_DMA_LSO;
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ramips_fe_wr(rx, RAMIPS_RX_CALC_IDX0);
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ramips_fe_twr(rx, RAETH_REG_RX_CALC_IDX0);
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max_rx--;
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}
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@ -825,13 +875,13 @@ ramips_eth_irq(int irq, void *dev)
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struct raeth_priv *re = netdev_priv(dev);
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unsigned int status;
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status = ramips_fe_rr(RAMIPS_FE_INT_STATUS);
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status &= ramips_fe_rr(RAMIPS_FE_INT_ENABLE);
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status = ramips_fe_trr(RAETH_REG_FE_INT_STATUS);
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status &= ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
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if (!status)
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return IRQ_NONE;
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ramips_fe_wr(status, RAMIPS_FE_INT_STATUS);
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ramips_fe_twr(status, RAETH_REG_FE_INT_STATUS);
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if (status & RAMIPS_RX_DLY_INT) {
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ramips_fe_int_disable(RAMIPS_RX_DLY_INT);
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@ -867,10 +917,10 @@ ramips_eth_open(struct net_device *dev)
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ramips_hw_set_macaddr(dev->dev_addr);
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ramips_setup_dma(re);
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ramips_fe_wr((ramips_fe_rr(RAMIPS_PDMA_GLO_CFG) & 0xff) |
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ramips_fe_twr((ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) & 0xff) |
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(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN |
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RAMIPS_TX_DMA_EN | RAMIPS_PDMA_SIZE_4DWORDS),
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RAMIPS_PDMA_GLO_CFG);
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RAETH_REG_PDMA_GLO_CFG);
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ramips_fe_wr((ramips_fe_rr(RAMIPS_FE_GLO_CFG) &
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~(RAMIPS_US_CYC_CNT_MASK << RAMIPS_US_CYC_CNT_SHIFT)) |
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((re->plat->sys_freq / RAMIPS_US_CYC_CNT_DIVISOR) << RAMIPS_US_CYC_CNT_SHIFT),
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@ -882,8 +932,8 @@ ramips_eth_open(struct net_device *dev)
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ramips_phy_start(re);
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ramips_fe_wr(RAMIPS_DELAY_INIT, RAMIPS_DLY_INT_CFG);
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ramips_fe_wr(RAMIPS_TX_DLY_INT | RAMIPS_RX_DLY_INT, RAMIPS_FE_INT_ENABLE);
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ramips_fe_twr(RAMIPS_DELAY_INIT, RAETH_REG_DLY_INT_CFG);
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ramips_fe_twr(RAMIPS_TX_DLY_INT | RAMIPS_RX_DLY_INT, RAETH_REG_FE_INT_ENABLE);
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ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) &
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~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff),
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RAMIPS_GDMA1_FWD_CFG);
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@ -907,12 +957,12 @@ ramips_eth_stop(struct net_device *dev)
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{
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struct raeth_priv *re = netdev_priv(dev);
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ramips_fe_wr(ramips_fe_rr(RAMIPS_PDMA_GLO_CFG) &
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ramips_fe_twr(ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) &
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~(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | RAMIPS_TX_DMA_EN),
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RAMIPS_PDMA_GLO_CFG);
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RAETH_REG_PDMA_GLO_CFG);
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/* disable all interrupts in the hw */
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ramips_fe_wr(0, RAMIPS_FE_INT_ENABLE);
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ramips_fe_twr(0, RAETH_REG_FE_INT_ENABLE);
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ramips_phy_stop(re);
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free_irq(dev->irq, dev);
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