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update brcm-2.4 to 2.4.35.4, integrate new broadcom system code, update broadcom-wl to a contributed version (v4.150.10.5) - no bcm57xx support yet, will follow shortly

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10137 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
2008-01-06 19:28:07 +00:00
parent b59f896089
commit 90fba37c49
165 changed files with 20348 additions and 10073 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
target/linux/brcm-2.4/files/arch/mips/bcm947xx/Makefile
View File

@@ -9,8 +9,8 @@ O_TARGET := bcm947xx.o
export-objs := export.o
obj-y := prom.o setup.o time.o sbmips.o gpio.o
obj-y += nvram.o nvram_linux.o sflash.o
obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
obj-y += nvram.o nvram_linux.o cfe_env.o hndpmu.o
obj-y += sbutils.o utils.o bcmsrom.o hndchipc.o
obj-$(CONFIG_PCI) += sbpci.o pcibios.o
obj-y += export.o

2858
target/linux/brcm-2.4/files/arch/mips/bcm947xx/bcmsrom.c
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File diff suppressed because it is too large Load Diff

247
target/linux/brcm-2.4/files/arch/mips/bcm947xx/bcmutils.c
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@@ -1,247 +0,0 @@
/*
* Misc useful OS-independent routines.
*
* Copyright 2006, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
* $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
*/
#include <typedefs.h>
#include <bcmdefs.h>
#include <stdarg.h>
#include <bcmutils.h>
#include <osl.h>
#include <sbutils.h>
#include <bcmnvram.h>
#include <bcmendian.h>
#include <bcmdevs.h>
unsigned char bcm_ctype[] = {
_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
_BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
_BCM_C, /* 8-15 */
_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
_BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
_BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
_BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
_BCM_U|_BCM_X, _BCM_U, /* 64-71 */
_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
_BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
_BCM_L|_BCM_X, _BCM_L, /* 96-103 */
_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
_BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
_BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
_BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
_BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
};
ulong
bcm_strtoul(char *cp, char **endp, uint base)
{
ulong result, value;
bool minus;
minus = FALSE;
while (bcm_isspace(*cp))
cp++;
if (cp[0] == '+')
cp++;
else if (cp[0] == '-') {
minus = TRUE;
cp++;
}
if (base == 0) {
if (cp[0] == '0') {
if ((cp[1] == 'x') || (cp[1] == 'X')) {
base = 16;
cp = &cp[2];
} else {
base = 8;
cp = &cp[1];
}
} else
base = 10;
} else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
cp = &cp[2];
}
result = 0;
while (bcm_isxdigit(*cp) &&
(value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
result = result*base + value;
cp++;
}
if (minus)
result = (ulong)(result * -1);
if (endp)
*endp = (char *)cp;
return (result);
}
uchar
bcm_toupper(uchar c)
{
if (bcm_islower(c))
c -= 'a'-'A';
return (c);
}
char*
bcm_ether_ntoa(struct ether_addr *ea, char *buf)
{
sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
return (buf);
}
/*
* Search the name=value vars for a specific one and return its value.
* Returns NULL if not found.
*/
char*
getvar(char *vars, char *name)
{
char *s;
int len;
len = strlen(name);
/* first look in vars[] */
for (s = vars; s && *s;) {
/* CSTYLED */
if ((memcmp(s, name, len) == 0) && (s[len] == '='))
return (&s[len+1]);
while (*s++)
;
}
/* then query nvram */
return (nvram_get(name));
}
/*
* Search the vars for a specific one and return its value as
* an integer. Returns 0 if not found.
*/
int
getintvar(char *vars, char *name)
{
char *val;
if ((val = getvar(vars, name)) == NULL)
return (0);
return (bcm_strtoul(val, NULL, 0));
}
/*******************************************************************************
* crc8
*
* Computes a crc8 over the input data using the polynomial:
*
* x^8 + x^7 +x^6 + x^4 + x^2 + 1
*
* The caller provides the initial value (either CRC8_INIT_VALUE
* or the previous returned value) to allow for processing of
* discontiguous blocks of data. When generating the CRC the
* caller is responsible for complementing the final return value
* and inserting it into the byte stream. When checking, a final
* return value of CRC8_GOOD_VALUE indicates a valid CRC.
*
* Reference: Dallas Semiconductor Application Note 27
* Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
* ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
* ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
*
* ****************************************************************************
*/
static uint8 crc8_table[256] = {
0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
};
#define CRC_INNER_LOOP(n, c, x) \
(c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
uint8
hndcrc8(
uint8 *pdata, /* pointer to array of data to process */
uint nbytes, /* number of input data bytes to process */
uint8 crc /* either CRC8_INIT_VALUE or previous return value */
)
{
/* hard code the crc loop instead of using CRC_INNER_LOOP macro
* to avoid the undefined and unnecessary (uint8 >> 8) operation.
*/
while (nbytes-- > 0)
crc = crc8_table[(crc ^ *pdata++) & 0xff];
return crc;
}

233
target/linux/brcm-2.4/files/arch/mips/bcm947xx/cfe_env.c Normal file
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@@ -0,0 +1,233 @@
/*
* NVRAM variable manipulation (Linux kernel half)
*
* Copyright 2001-2003, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id$
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <typedefs.h>
#include <osl.h>
#include <bcmendian.h>
#define NVRAM_SIZE (0x1ff0)
static char _nvdata[NVRAM_SIZE] __initdata;
static char _valuestr[256] __initdata;
/*
* TLV types. These codes are used in the "type-length-value"
* encoding of the items stored in the NVRAM device (flash or EEPROM)
*
* The layout of the flash/nvram is as follows:
*
* <type> <length> <data ...> <type> <length> <data ...> <type_end>
*
* The type code of "ENV_TLV_TYPE_END" marks the end of the list.
* The "length" field marks the length of the data section, not
* including the type and length fields.
*
* Environment variables are stored as follows:
*
* <type_env> <length> <flags> <name> = <value>
*
* If bit 0 (low bit) is set, the length is an 8-bit value.
* If bit 0 (low bit) is clear, the length is a 16-bit value
*
* Bit 7 set indicates "user" TLVs. In this case, bit 0 still
* indicates the size of the length field.
*
* Flags are from the constants below:
*
*/
#define ENV_LENGTH_16BITS 0x00 /* for low bit */
#define ENV_LENGTH_8BITS 0x01
#define ENV_TYPE_USER 0x80
#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
/*
* The actual TLV types we support
*/
#define ENV_TLV_TYPE_END 0x00
#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
/*
* Environment variable flags
*/
#define ENV_FLG_NORMAL 0x00 /* normal read/write */
#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
/* *********************************************************************
* _nvram_read(buffer,offset,length)
*
* Read data from the NVRAM device
*
* Input parameters:
* buffer - destination buffer
* offset - offset of data to read
* length - number of bytes to read
*
* Return value:
* number of bytes read, or <0 if error occured
********************************************************************* */
static int
_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
{
int i;
if (offset > NVRAM_SIZE)
return -1;
for ( i = 0; i < length; i++) {
buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
}
return length;
}
static char*
_strnchr(const char *dest,int c,size_t cnt)
{
while (*dest && (cnt > 0)) {
if (*dest == c) return (char *) dest;
dest++;
cnt--;
}
return NULL;
}
/*
* Core support API: Externally visible.
*/
/*
* Get the value of an NVRAM variable
* @param name name of variable to get
* @return value of variable or NULL if undefined
*/
char*
cfe_env_get(unsigned char *nv_buf, char* name)
{
int size;
unsigned char *buffer;
unsigned char *ptr;
unsigned char *envval;
unsigned int reclen;
unsigned int rectype;
int offset;
int flg;
size = NVRAM_SIZE;
buffer = &_nvdata[0];
ptr = buffer;
offset = 0;
/* Read the record type and length */
if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
goto error;
}
while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
/* Adjust pointer for TLV type */
rectype = *(ptr);
offset++;
size--;
/*
* Read the length. It can be either 1 or 2 bytes
* depending on the code
*/
if (rectype & ENV_LENGTH_8BITS) {
/* Read the record type and length - 8 bits */
if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
goto error;
}
reclen = *(ptr);
size--;
offset++;
}
else {
/* Read the record type and length - 16 bits, MSB first */
if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
goto error;
}
reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
size -= 2;
offset += 2;
}
if (reclen > size)
break; /* should not happen, bad NVRAM */
switch (rectype) {
case ENV_TLV_TYPE_ENV:
/* Read the TLV data */
if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
goto error;
flg = *ptr++;
envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
if (envval) {
*envval++ = '\0';
memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
_valuestr[(reclen-1)-(envval-ptr)] = '\0';
#if 0
printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
#endif
if(!strcmp(ptr, name)){
return _valuestr;
}
if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
return _valuestr;
}
break;
default:
/* Unknown TLV type, skip it. */
break;
}
/*
* Advance to next TLV
*/
size -= (int)reclen;
offset += reclen;
/* Read the next record type */
ptr = buffer;
if (_nvram_read(nv_buf, ptr,offset,1) != 1)
goto error;
}
error:
return NULL;
}

33
target/linux/brcm-2.4/files/arch/mips/bcm947xx/compressed/Makefile
View File

@@ -1,33 +0,0 @@
#
# Makefile for Broadcom BCM947XX boards
#
# Copyright 2001-2003, Broadcom Corporation
# All Rights Reserved.
#
# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
#
# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
#
OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
SYSTEM ?= $(TOPDIR)/vmlinux
all: vmlinuz
# Don't build dependencies, this may die if $(CC) isn't gcc
dep:
# Create a gzipped version named vmlinuz for compatibility
vmlinuz: piggy
gzip -c9 $< > $@
piggy: $(SYSTEM)
$(OBJCOPY) $(OBJCOPY_ARGS) $< $@
mrproper: clean
clean:
rm -f vmlinuz piggy

19
target/linux/brcm-2.4/files/arch/mips/bcm947xx/export.c
View File

@@ -6,8 +6,10 @@
_export(bcm947xx_sbh)
_export(sb_alp_clock)
_export(sb_attach)
_export(sb_kattach)
_export(sb_backplane64)
_export(sb_boardtype)
_export(sb_boardvendor)
_export(sb_btcgpiowar)
@@ -24,6 +26,7 @@ _export(sb_core_disable)
_export(sb_core_reset)
_export(sb_core_tofixup)
_export(sb_coreflags)
_export(sb_coreflags_wo)
_export(sb_coreflagshi)
_export(sb_coreidx)
_export(sb_coreregs)
@@ -39,26 +42,30 @@ _export(sb_gpioled)
_export(sb_gpioin)
_export(sb_gpioout)
_export(sb_gpioouten)
_export(sb_gpiopull)
_export(sb_gpiotimerval)
_export(sb_irq)
_export(sb_iscoreup)
_export(sb_pci_setup)
_export(sb_pci_sleep)
_export(sb_pci_down)
_export(sb_pci_up)
_export(sb_pcirev)
_export(sb_pcmcia_init)
_export(sb_pcmciarev)
_export(sb_pmu_paref_ldo_enable)
_export(sb_pmu_rcal)
_export(sb_pmu_set_ldo_voltage)
_export(sb_deregister_intr_callback)
_export(sb_register_intr_callback)
_export(sb_setcore)
_export(sb_setcoreidx)
_export(sb_war16165)
_export(sb_war32414_forceHT)
_export(sb_war42780_clkreq)
_export(sb_osh)
_export(getvar)
_export(getintvar)
_export(bcm_strtoul)
_export(bcm_ctype)
_export(bcm_toupper)
_export(bcm_ether_ntoa)
_export(nvram_get)
_export(nvram_getall)

3
target/linux/brcm-2.4/files/arch/mips/bcm947xx/gpio.c
View File

@@ -20,7 +20,6 @@
#include <typedefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <sbutils.h>
#include <bcmdevs.h>
@@ -122,7 +121,7 @@ gpio_init(void)
{
int i;
if (!(gpio_sbh = sb_kattach()))
if (!(gpio_sbh = sb_kattach(SB_OSH)))
return -ENODEV;
sb_gpiosetcore(gpio_sbh);

386
target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndchipc.c
View File

@@ -1,7 +1,7 @@
/*
* BCM47XX support code for some chipcommon (old extif) facilities (uart)
* BCM47XX support code for some chipcommon facilities (uart, jtagm)
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,28 +9,52 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#include <typedefs.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <sbutils.h>
#include <bcmdevs.h>
#include <bcmnvram.h>
#include <sbconfig.h>
#include <sbextif.h>
#include <sbchipc.h>
#include <sbextif.h>
#include <hndchipc.h>
#include <hndcpu.h>
/*
* Returns TRUE if an external UART exists at the given base
* register.
/* debug/trace */
#define CC_ERROR(args)
#ifdef BCMDBG
#define CC_MSG(args) printf args
#else
#define CC_MSG(args)
#endif /* BCMDBG */
/* interested chipcommon interrupt source
* - GPIO
* - EXTIF
* - ECI
* - PMU
* - UART
*/
static bool
BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
{
#define MAX_CC_INT_SOURCE 5
/* chipc secondary isr info */
typedef struct {
uint intmask; /* int mask */
cc_isr_fn isr; /* secondary isr handler */
void *cbdata; /* pointer to private data */
} cc_isr_info_t;
static cc_isr_info_t cc_isr_desc[MAX_CC_INT_SOURCE];
/* chip common intmask */
static uint32 cc_intmask = 0;
static bool BCMINITFN(serial_exists) (osl_t * osh, uint8 * regs) {
uint8 save_mcr, status1;
save_mcr = R_REG(osh, &regs[UART_MCR]);
@@ -41,118 +65,276 @@ BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
return (status1 == 0x90);
}
static void __init sb_extif_serial_init(sb_t * sbh, void *regs,
sb_serial_init_fn add)
{
osl_t *osh = sb_osh(sbh);
extifregs_t *eir = (extifregs_t *) regs;
sbconfig_t *sb;
ulong base;
uint irq;
int i, n;
/* Determine external UART register base */
sb = (sbconfig_t *) ((ulong) eir + SBCONFIGOFF);
base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
/* Determine IRQ */
irq = sb_irq(sbh);
/* Disable GPIO interrupt initially */
W_REG(osh, &eir->gpiointpolarity, 0);
W_REG(osh, &eir->gpiointmask, 0);
/* Search for external UARTs */
n = 2;
for (i = 0; i < 2; i++) {
regs = (void *)REG_MAP(base + (i * 8), 8);
if (serial_exists(osh, regs)) {
/* Set GPIO 1 to be the external UART IRQ */
W_REG(osh, &eir->gpiointmask, 2);
/* XXXDetermine external UART clock */
if (add)
add(regs, irq, 13500000, 0);
}
}
/* Add internal UART if enabled */
if (R_REG(osh, &eir->corecontrol) & CC_UE)
if (add)
add((void *)&eir->uartdata, irq, sb_clock(sbh), 2);
}
/*
* Initializes UART access. The callback function will be called once
* per found UART.
*/
void
BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
uint reg_shift))
{
void BCMINITFN(sb_serial_init) (sb_t * sbh, sb_serial_init_fn add) {
osl_t *osh;
void *regs;
ulong base;
chipcregs_t *cc;
uint32 rev, cap, pll, baud_base, div;
uint irq;
int i, n;
osh = sb_osh(sbh);
if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
extifregs_t *eir = (extifregs_t *) regs;
sbconfig_t *sb;
regs = sb_setcore(sbh, SB_EXTIF, 0);
if (regs) {
sb_extif_serial_init(sbh, regs, add);
return;
}
/* Determine external UART register base */
sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0);
ASSERT(cc);
/* Determine IRQ */
irq = sb_irq(sbh);
/* Determine core revision and capabilities */
rev = sbh->ccrev;
cap = sbh->cccaps;
pll = cap & CC_CAP_PLL_MASK;
/* Disable GPIO interrupt initially */
W_REG(osh, &eir->gpiointpolarity, 0);
W_REG(osh, &eir->gpiointmask, 0);
/* Determine IRQ */
irq = sb_irq(sbh);
/* Search for external UARTs */
n = 2;
for (i = 0; i < 2; i++) {
regs = (void *) REG_MAP(base + (i * 8), 8);
if (serial_exists(osh, regs)) {
/* Set GPIO 1 to be the external UART IRQ */
W_REG(osh, &eir->gpiointmask, 2);
/* XXXDetermine external UART clock */
if (add)
add(regs, irq, 13500000, 0);
}
}
/* Add internal UART if enabled */
if (R_REG(osh, &eir->corecontrol) & CC_UE)
if (add)
add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
} else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
chipcregs_t *cc = (chipcregs_t *) regs;
uint32 rev, cap, pll, baud_base, div;
/* Determine core revision and capabilities */
rev = sb_corerev(sbh);
cap = R_REG(osh, &cc->capabilities);
pll = cap & CAP_PLL_MASK;
/* Determine IRQ */
irq = sb_irq(sbh);
if (pll == PLL_TYPE1) {
/* PLL clock */
baud_base = sb_clock_rate(pll,
R_REG(osh, &cc->clockcontrol_n),
R_REG(osh, &cc->clockcontrol_m2));
div = 1;
} else {
if (pll == PLL_TYPE1) {
/* PLL clock */
baud_base = sb_clock_rate(pll,
R_REG(osh, &cc->clockcontrol_n),
R_REG(osh, &cc->clockcontrol_m2));
div = 1;
} else {
/* 5354 chip common uart uses a constant clock
* frequency of 25MHz */
if (sb_corerev(sbh) == 20) {
/* Set the override bit so we don't divide it */
W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
baud_base = 25000000;
} else if (rev >= 11 && rev != 15) {
/* Fixed ALP clock */
if (rev >= 11 && rev != 15) {
baud_base = 20000000;
div = 1;
/* Set the override bit so we don't divide it */
W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
}
baud_base = sb_alp_clock(sbh);
div = 1;
/* Turn off UART clock before switching clock source */
if (rev >= 21)
AND_REG(osh, &cc->corecontrol, ~CC_UARTCLKEN);
/* Set the override bit so we don't divide it */
OR_REG(osh, &cc->corecontrol, CC_UARTCLKO);
if (rev >= 21)
OR_REG(osh, &cc->corecontrol, CC_UARTCLKEN);
} else if (rev >= 3) {
/* Internal backplane clock */
else if (rev >= 3) {
baud_base = sb_clock(sbh);
div = 2; /* Minimum divisor */
W_REG(osh, &cc->clkdiv,
((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
}
baud_base = sb_clock(sbh);
div = 2; /* Minimum divisor */
W_REG(osh, &cc->clkdiv,
((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
} else {
/* Fixed internal backplane clock */
else {
baud_base = 88000000;
div = 48;
}
/* Clock source depends on strapping if UartClkOverride is unset */
if ((rev > 0) &&
((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
/* Internal divided backplane clock */
baud_base /= div;
} else {
/* Assume external clock of 1.8432 MHz */
baud_base = 1843200;
}
}
baud_base = 88000000;
div = 48;
}
/* Add internal UARTs */
n = cap & CAP_UARTS_MASK;
for (i = 0; i < n; i++) {
/* Register offset changed after revision 0 */
if (rev)
regs = (void *)((ulong) &cc->uart0data + (i * 256));
else
regs = (void *)((ulong) &cc->uart0data + (i * 8));
if (add)
add(regs, irq, baud_base, 0);
/* Clock source depends on strapping if UartClkOverride is unset */
if ((rev > 0)
&& ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
if ((cap & CC_CAP_UCLKSEL) == CC_CAP_UINTCLK) {
/* Internal divided backplane clock */
baud_base /= div;
} else {
/* Assume external clock of 1.8432 MHz */
baud_base = 1843200;
}
}
}
/* Add internal UARTs */
n = cap & CC_CAP_UARTS_MASK;
for (i = 0; i < n; i++) {
/* Register offset changed after revision 0 */
if (rev)
regs = (void *)((ulong) & cc->uart0data + (i * 256));
else
regs = (void *)((ulong) & cc->uart0data + (i * 8));
if (add)
add(regs, irq, baud_base, 0);
}
}
#if 0
/*
* Initialize jtag master and return handle for
* jtag_rwreg. Returns NULL on failure.
*/
void *sb_jtagm_init(sb_t * sbh, uint clkd, bool exttap)
{
void *regs;
if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
chipcregs_t *cc = (chipcregs_t *) regs;
uint32 tmp;
/*
* Determine jtagm availability from
* core revision and capabilities.
*/
/*
* Corerev 10 has jtagm, but the only chip
* with it does not have a mips, and
* the layout of the jtagcmd register is
* different. We'll only accept >= 11.
*/
if (sbh->ccrev < 11)
return (NULL);
if ((sbh->cccaps & CC_CAP_JTAGP) == 0)
return (NULL);
/* Set clock divider if requested */
if (clkd != 0) {
tmp = R_REG(osh, &cc->clkdiv);
tmp =
(tmp & ~CLKD_JTAG) | ((clkd << CLKD_JTAG_SHIFT) &
CLKD_JTAG);
W_REG(osh, &cc->clkdiv, tmp);
}
/* Enable jtagm */
tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
W_REG(osh, &cc->jtagctrl, tmp);
}
return (regs);
}
void sb_jtagm_disable(osl_t * osh, void *h)
{
chipcregs_t *cc = (chipcregs_t *) h;
W_REG(osh, &cc->jtagctrl, R_REG(osh, &cc->jtagctrl) & ~JCTRL_EN);
}
/*
* Read/write a jtag register. Assumes a target with
* 8 bit IR and 32 bit DR.
*/
#define IRWIDTH 8 /* Default Instruction Register width */
#define DRWIDTH 32 /* Default Data Register width */
uint32 jtag_rwreg(osl_t * osh, void *h, uint32 ir, uint32 dr)
{
chipcregs_t *cc = (chipcregs_t *) h;
uint32 tmp;
W_REG(osh, &cc->jtagir, ir);
W_REG(osh, &cc->jtagdr, dr);
tmp = JCMD_START | JCMD_ACC_IRDR |
((IRWIDTH - 1) << JCMD_IRW_SHIFT) | (DRWIDTH - 1);
W_REG(osh, &cc->jtagcmd, tmp);
while (((tmp = R_REG(osh, &cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
/* OSL_DELAY(1); */
}
tmp = R_REG(osh, &cc->jtagdr);
return (tmp);
}
#endif
/*
* Interface to register chipc secondary isr
*/
bool
BCMINITFN(sb_cc_register_isr) (sb_t * sbh, cc_isr_fn isr, uint32 ccintmask,
void *cbdata) {
bool done = FALSE;
chipcregs_t *regs;
uint origidx;
uint i;
/* Save the current core index */
origidx = sb_coreidx(sbh);
regs = sb_setcore(sbh, SB_CC, 0);
ASSERT(regs);
for (i = 0; i < MAX_CC_INT_SOURCE; i++) {
if (cc_isr_desc[i].isr == NULL) {
cc_isr_desc[i].isr = isr;
cc_isr_desc[i].cbdata = cbdata;
cc_isr_desc[i].intmask = ccintmask;
done = TRUE;
break;
}
}
if (done) {
cc_intmask = R_REG(sb_osh(sbh), &regs->intmask);
cc_intmask |= ccintmask;
W_REG(sb_osh(sbh), &regs->intmask, cc_intmask);
}
/* restore original coreidx */
sb_setcoreidx(sbh, origidx);
return done;
}
/*
* chipc primary interrupt handler
*/
void sb_cc_isr(sb_t * sbh, chipcregs_t * regs)
{
uint32 ccintstatus;
uint32 intstatus;
uint32 i;
/* prior to rev 21 chipc interrupt means uart and gpio */
if (sbh->ccrev >= 21)
ccintstatus = R_REG(sb_osh(sbh), &regs->intstatus) & cc_intmask;
else
ccintstatus = (CI_UART | CI_GPIO);
for (i = 0; i < MAX_CC_INT_SOURCE; i++) {
if ((cc_isr_desc[i].isr != NULL) &&
(intstatus = (cc_isr_desc[i].intmask & ccintstatus))) {
(cc_isr_desc[i].isr) (cc_isr_desc[i].cbdata, intstatus);
}
}
}

1257
target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndpmu.c Normal file
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File diff suppressed because it is too large Load Diff

2
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdefs.h
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@@ -101,6 +101,8 @@ extern bool bcmreclaimed;
*/
#define BCMDONGLEHDRSZ 8
/* Max. nvram variable table size */
#define MAXSZ_NVRAM_VARS 4096
#endif /* _bcmdefs_h_ */

243
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs.h
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@@ -1,22 +1,20 @@
/*
* Broadcom device-specific manifest constants.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
* $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
* $Id$
*/
#ifndef _BCMDEVS_H
#define _BCMDEVS_H
#include "bcm4710.h"
/* Known PCI vendor Id's */
/* PCI vendor IDs */
#define VENDOR_EPIGRAM 0xfeda
#define VENDOR_BROADCOM 0x14e4
#define VENDOR_3COM 0x10b7
@@ -25,24 +23,63 @@
#define VENDOR_DELL 0x1028
#define VENDOR_HP 0x0e11
#define VENDOR_APPLE 0x106b
#define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */
#define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */
#define VENDOR_TI 0x104c /* Texas Instruments */
/* PCI Device Id's */
/* PCMCIA vendor IDs */
#define VENDOR_BROADCOM_PCMCIA 0x02d0
/* SDIO vendor IDs */
#define VENDOR_BROADCOM_SDIO 0x00BF
/* PCI Device IDs */
#define BCM4210_DEVICE_ID 0x1072 /* never used */
#define BCM4211_DEVICE_ID 0x4211
#define BCM4230_DEVICE_ID 0x1086 /* never used */
#define BCM4231_DEVICE_ID 0x4231
#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
#define BCM4211_DEVICE_ID 0x4211
#define BCM4231_DEVICE_ID 0x4231
#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
#define BCM4328_D11DUAL_ID 0x4314 /* 4328 802.11a/g id */
#define BCM4328_D11G_ID 0x4315 /* 4328 802.11g 2.4Ghz band id */
#define BCM4328_D11A_ID 0x4316 /* 4328 802.11a 5Ghz band id */
#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
#define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */
#define BCM4325_D11G_ID 0x431c /* 4325 802.11g 2.4Ghz band id */
#define BCM4325_D11A_ID 0x431d /* 4325 802.11a 5Ghz band id */
#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
#define BCM4306_UART_ID 0x4322 /* 4306 uart */
#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
#define BCM4306_D11G_ID2 0x4325
#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */
#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
#define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */
#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
#define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */
#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
#define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */
#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
@@ -57,114 +94,83 @@
#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
#define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */
#define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */
#define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */
#define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */
/* Chip IDs */
#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
#define BCM4306_D11G_ID2 0x4325
#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
#define BCM4306_UART_ID 0x4322 /* 4306 uart */
#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
#define BCM4309_PKG_ID 1 /* 4309 package id */
#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
#define BCM4303_PKG_ID 2 /* 4303 package id */
#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
#define BCM4312_CHIP_ID 0x4312 /* 4312 chip common chipid */
#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
#define BCM4328_CHIP_ID 0x4328 /* 4328 chip common chipid */
#define BCM4325_CHIP_ID 0x4325 /* 4325 chip common chipid */
#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
#define BCM5354_CHIP_ID 0x5354 /* bcm5354 chipcommon chipid */
#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
/* Package IDs */
#define BCM4303_PKG_ID 2 /* 4303 package id */
#define BCM4309_PKG_ID 1 /* 4309 package id */
#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
#define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */
#define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */
#define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */
#define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */
#define BCM5354E_PKG_ID 1 /* 5354E package id */
#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
/* PCMCIA vendor Id's */
#define VENDOR_BROADCOM_PCMCIA 0x02d0
/* SDIO vendor Id's */
#define VENDOR_BROADCOM_SDIO 0x00BF
#define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */
#define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */
/* boardflags */
#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
#define BFL_FEM 0x0800 /* This board supports the Front End Module */
#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
#define BFL_HGPA 0x2000 /* This board has a high gain PA */
#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
#define BFL_BTCOEXIST 0x00000001 /* This board implements Bluetooth coexistance */
#define BFL_PACTRL 0x00000002 /* This board has gpio 9 controlling the PA */
#define BFL_AIRLINEMODE 0x00000004 /* This board implements gpio13 radio disable indication */
#define BFL_ADCDIV 0x00000008 /* This board has the rssi ADC divider */
#define BFL_ENETROBO 0x00000010 /* This board has robo switch or core */
#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
#define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
#define BFL_ENETADM 0x00000080 /* This board has ADMtek switch */
#define BFL_ENETVLAN 0x00000100 /* This board has vlan capability */
#define BFL_AFTERBURNER 0x00000200 /* This board supports Afterburner mode */
#define BFL_NOPCI 0x00000400 /* This board leaves PCI floating */
#define BFL_FEM 0x00000800 /* This board supports the Front End Module */
#define BFL_EXTLNA 0x00001000 /* This board has an external LNA */
#define BFL_HGPA 0x00002000 /* This board has a high gain PA */
#define BFL_BTCMOD 0x00004000 /* This board' BTCOEXIST is in the alternate gpios */
#define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */
#define BFL_NOPA 0x00010000 /* This board has no PA */
#define BFL_RSSIINV 0x00020000 /* This board's RSSI uses positive slope */
#define BFL_PAREF 0x00040000 /* This board uses the PARef LDO */
#define BFL_3TSWITCH 0x00080000 /* This board uses a triple throw switch shared with BT */
#define BFL_PHASESHIFTER 0x00100000 /* This board can support phase shifter */
#define BFL_BUCKBOOST 0x00200000 /* This board has buck/booster */
/* boardflags2 */
#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
#define BFL2_DEPRECIATED_STUB 0x00000002 /* This board flag is depreciated */
#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits enabling TX Power Control */
#define BFL2_2X4_DIV 0x00000008 /* This board supports the 2X4 diversity switch */
#define BFL2_5G_PWRGAIN 0x00000010 /* This board supports 5G band power gain */
#define BFL2_PCIEWAR_OVR 0x00000020 /* This board overrides ASPM and Clkreq settings */
#define BFL2_CAESERS_BRD 0x00000040 /* This board is Dell Caeser's brd (unused by sw) */
/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
@@ -172,6 +178,9 @@
#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
#define BOARD_GPIO_ANT0_SEL 0x100 /* With BFL2_2X4_DIV */
#define BOARD_GPIO_ANT1_SEL 0x200 /* With BFL2_2X4_DIV */
#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
@@ -184,7 +193,6 @@
#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
/* Reference Board Types */
#define BU4710_BOARD 0x0400
#define VSIM4710_BOARD 0x0401
#define QT4710_BOARD 0x0402
@@ -259,6 +267,7 @@
/* BCM63XX boards */
#define BCM96338_BOARD 0x6338
#define BCM96348_BOARD 0x6348
#define BCM96358_BOARD 0x6358
/* Another mp4306 with SiGe */
#define BCM94306P_BOARD 0x044c
@@ -333,6 +342,18 @@
#define CB2_4321_BOARD 0x046d
#define MC4321_BOARD 0x046e
/* 4328 boards */
#define BU4328_BOARD 0x0481
#define BCM4328SDG_BOARD 0x0482
#define BCM4328SDAG_BOARD 0x0483
#define BCM4328UG_BOARD 0x0484
#define BCM4328UAG_BOARD 0x0485
#define BCM4328PC_BOARD 0x0486
#define BCM4328CF_BOARD 0x0487
/* 4325 boards */
#define BU4325_BOARD 0x0490
/* # of GPIO pins */
#define GPIO_NUMPINS 16
@@ -358,6 +379,10 @@
#define BCM2062_IDCODE 0x02062000
#define BCM2062A0_IDCODE 0x0206217f
#define BCM2063_ID 0x2063
#define BCM2063_IDCODE 0x02063000
#define BCM2063A0_IDCODE 0x0206317f
/* parts of an idcode: */
#define IDCODE_MFG_MASK 0x00000fff
#define IDCODE_MFG_SHIFT 0

4
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmendian.h
View File

@@ -1,7 +1,7 @@
/*
* local version of endian.h - byte order defines
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _BCMENDIAN_H_

51
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmnvram.h
View File

@@ -1,7 +1,7 @@
/*
* NVRAM variable manipulation
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
* $Id$
*/
#ifndef _bcmnvram_h_
@@ -35,10 +35,19 @@ struct nvram_tuple {
};
/*
* Initialize NVRAM access. May be unnecessary or undefined on certain
* platforms.
* Get default value for an NVRAM variable
*/
extern int nvram_init(void *sbh);
extern char *nvram_default_get(const char *name);
/*
* Append a chunk of nvram variables to the global list
*/
extern int nvram_append(void *sb, char *vars, uint varsz);
/*
* Check for reset button press for restoring factory defaults.
*/
extern bool nvram_reset(void *sbh);
/*
* Disable NVRAM access. May be unnecessary or undefined on certain
@@ -59,8 +68,6 @@ extern char * nvram_get(const char *name);
* as input
*/
extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
/*
* Get the value of an NVRAM variable.
@@ -69,16 +76,6 @@ extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
*/
#define nvram_safe_get(name) (nvram_get(name) ? : "")
#define nvram_safe_unset(name) ({ \
if(nvram_get(name)) \
nvram_unset(name); \
})
#define nvram_safe_set(name, value) ({ \
if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
nvram_set(name, value); \
})
/*
* Match an NVRAM variable.
* @param name name of variable to match
@@ -139,15 +136,24 @@ extern int nvram_commit(void);
* @param count size of buffer in bytes
* @return 0 on success and errno on failure
*/
extern int nvram_getall(char *buf, int count);
extern int nvram_getall(char *nvram_buf, int count);
extern int file2nvram(char *filename, char *varname);
extern int nvram2file(char *varname, char *filename);
/*
* returns the crc value of the nvram
* @param nvh nvram header pointer
*/
extern uint8 nvram_calc_crc(struct nvram_header * nvh);
extern char* getvar(char *vars, const char *name);
extern int getintvar(char *vars, const char *name);
#endif /* _LANGUAGE_ASSEMBLY */
/* The NVRAM version number stored as an NVRAM variable */
#define NVRAM_SOFTWARE_VERSION "1"
#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
#define NVRAM_CLEAR_MAGIC 0x0
#define NVRAM_CLEAR_MAGIC 0x0
#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
#define NVRAM_VERSION 1
#define NVRAM_HEADER_SIZE 20
@@ -156,4 +162,7 @@ extern int nvram2file(char *varname, char *filename);
#define NVRAM_MAX_VALUE_LEN 255
#define NVRAM_MAX_PARAM_LEN 64
#define NVRAM_CRC_START_POSITION 9 /* magic, len, crc8 to be skipped */
#define NVRAM_CRC_VER_MASK 0xffffff00 /* for crc_ver_init */
#endif /* _bcmnvram_h_ */

216
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmsrom.h
View File

@@ -1,7 +1,7 @@
/*
* Misc useful routines to access NIC local SROM/OTP .
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,14 +9,93 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
* $Id$
*/
#ifndef _bcmsrom_h_
#define _bcmsrom_h_
/* Maximum srom: 4 Kilobits == 512 bytes */
#define SROM_MAX 512
#define SROM_MAX 512
#define SROM_WORDS 64
#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */
#define SROM_SSID 2
#define SROM_WL1LHMAXP 29
#define SROM_WL1LPAB0 30
#define SROM_WL1LPAB1 31
#define SROM_WL1LPAB2 32
#define SROM_WL1HPAB0 33
#define SROM_WL1HPAB1 34
#define SROM_WL1HPAB2 35
#define SROM_MACHI_IL0 36
#define SROM_MACMID_IL0 37
#define SROM_MACLO_IL0 38
#define SROM_MACHI_ET0 39
#define SROM_MACMID_ET0 40
#define SROM_MACLO_ET0 41
#define SROM_MACHI_ET1 42
#define SROM_MACMID_ET1 43
#define SROM_MACLO_ET1 44
#define SROM3_MACHI 37
#define SROM3_MACMID 38
#define SROM3_MACLO 39
#define SROM_BXARSSI2G 40
#define SROM_BXARSSI5G 41
#define SROM_TRI52G 42
#define SROM_TRI5GHL 43
#define SROM_RXPO52G 45
#define SROM2_ENETPHY 45
#define SROM_AABREV 46
/* Fields in AABREV */
#define SROM_BR_MASK 0x00ff
#define SROM_CC_MASK 0x0f00
#define SROM_CC_SHIFT 8
#define SROM_AA0_MASK 0x3000
#define SROM_AA0_SHIFT 12
#define SROM_AA1_MASK 0xc000
#define SROM_AA1_SHIFT 14
#define SROM_WL0PAB0 47
#define SROM_WL0PAB1 48
#define SROM_WL0PAB2 49
#define SROM_LEDBH10 50
#define SROM_LEDBH32 51
#define SROM_WL10MAXP 52
#define SROM_WL1PAB0 53
#define SROM_WL1PAB1 54
#define SROM_WL1PAB2 55
#define SROM_ITT 56
#define SROM_BFL 57
#define SROM_BFL2 28
#define SROM3_BFL2 61
#define SROM_AG10 58
#define SROM_CCODE 59
#define SROM_OPO 60
#define SROM3_LEDDC 62
#define SROM_CRCREV 63
/* SROM Rev 4: Reallocate the software part of the srom to accomodate
* MIMO features. It assumes up to two PCIE functions and 440 bytes
@@ -35,18 +114,30 @@
#define SROM4_BFL1 35
#define SROM4_BFL2 36
#define SROM4_BFL3 37
#define SROM5_BFL0 37
#define SROM5_BFL1 38
#define SROM5_BFL2 39
#define SROM5_BFL3 40
#define SROM4_MACHI 38
#define SROM4_MACMID 39
#define SROM4_MACLO 40
#define SROM5_MACHI 41
#define SROM5_MACMID 42
#define SROM5_MACLO 43
#define SROM4_CCODE 41
#define SROM4_REGREV 42
#define SROM5_CCODE 34
#define SROM5_REGREV 35
#define SROM4_LEDBH10 43
#define SROM4_LEDBH32 44
#define SROM5_LEDBH10 59
#define SROM5_LEDBH32 60
#define SROM4_LEDDC 45
#define SROM5_LEDDC 45
#define SROM4_AA 46
#define SROM4_AA2G_MASK 0x00ff
@@ -62,6 +153,14 @@
#define SROM4_TXPID5GL 53
#define SROM4_TXPID5GH 55
#define SROM4_TXRXC 61
#define SROM4_TXCHAIN_MASK 0x000f
#define SROM4_TXCHAIN_SHIFT 0
#define SROM4_RXCHAIN_MASK 0x00f0
#define SROM4_RXCHAIN_SHIFT 4
#define SROM4_SWITCH_MASK 0xff00
#define SROM4_SWITCH_SHIFT 8
/* Per-path fields */
#define MAX_PATH 4
#define SROM4_PATH0 64
@@ -95,14 +194,117 @@
#define SROM4_5G_MCSPO 173
#define SROM4_5GL_MCSPO 181
#define SROM4_5GH_MCSPO 189
#define SROM4_CCDPO 197
#define SROM4_CDDPO 197
#define SROM4_STBCPO 198
#define SROM4_BW40PO 199
#define SROM4_BWDUPPO 200
extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
#define SROM4_CRCREV 219
extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
/*SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
* This is acombined srom for both MIMO and SISO boards, usable in
* the .130 4Kilobit OTP with hardware redundancy.
*/
#define SROM8_SIGN 64
#define SROM8_BREV 65
#define SROM8_BFL0 66
#define SROM8_BFL1 67
#define SROM8_BFL2 68
#define SROM8_BFL3 69
#define SROM8_MACHI 70
#define SROM8_MACMID 71
#define SROM8_MACLO 72
#define SROM8_CCODE 73
#define SROM8_REGREV 74
#define SROM8_LEDBH10 75
#define SROM8_LEDBH32 76
#define SROM8_LEDDC 77
#define SROM8_AA 78
#define SROM8_AG10 79
#define SROM8_AG32 80
#define SROM8_TXRXC 81
#define SROM8_BXARSSI2G 82
#define SROM8_BXARSSI5G 83
#define SROM8_TRI52G 84
#define SROM8_TRI5GHL 85
#define SROM8_RXPO52G 86
/* Per-path offsets & fields */
#define SROM8_PATH0 96
#define SROM8_PATH1 112
#define SROM8_PATH2 128
#define SROM8_PATH3 144
#define SROM8_2G_ITT_MAXP 0
#define SROM8_2G_PA 1
#define SROM8_5G_ITT_MAXP 4
#define SROM8_5GLH_MAXP 5
#define SROM8_5G_PA 6
#define SROM8_5GL_PA 9
#define SROM8_5GH_PA 12
/* All the miriad power offsets */
#define SROM8_2G_CCKPO 160
#define SROM8_2G_OFDMPO 161
#define SROM8_5G_OFDMPO 163
#define SROM8_5GL_OFDMPO 165
#define SROM8_5GH_OFDMPO 167
#define SROM8_2G_MCSPO 169
#define SROM8_5G_MCSPO 177
#define SROM8_5GL_MCSPO 185
#define SROM8_5GH_MCSPO 193
#define SROM8_CDDPO 201
#define SROM8_STBCPO 202
#define SROM8_BW40PO 203
#define SROM8_BWDUPPO 204
/* SISO PA parameters are in the path0 spaces */
#define SROM8_SISO 96
/* Legacy names for SISO PA paramters */
#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
#define SROM8_CRCREV 219
/* Prototypes */
extern int srom_var_init(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
char **vars, uint *count);
extern int srom_read(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
uint byteoff, uint nbytes, uint16 *buf);
extern int srom_write(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
uint byteoff, uint nbytes, uint16 *buf);
extern int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt,
char **vars, uint *count);
#endif /* _bcmsrom_h_ */

433
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmutils.h
View File

@@ -1,433 +0,0 @@
/*
* Misc useful os-independent macros and functions.
*
* Copyright 2006, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
* $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
*/
#ifndef _bcmutils_h_
#define _bcmutils_h_
/* ** driver-only section ** */
#ifdef BCMDRIVER
#define _BCM_U 0x01 /* upper */
#define _BCM_L 0x02 /* lower */
#define _BCM_D 0x04 /* digit */
#define _BCM_C 0x08 /* cntrl */
#define _BCM_P 0x10 /* punct */
#define _BCM_S 0x20 /* white space (space/lf/tab) */
#define _BCM_X 0x40 /* hex digit */
#define _BCM_SP 0x80 /* hard space (0x20) */
#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
extern unsigned char bcm_ctype[];
#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
/*
* Spin at most 'us' microseconds while 'exp' is true.
* Caller should explicitly test 'exp' when this completes
* and take appropriate error action if 'exp' is still true.
*/
#define SPINWAIT(exp, us) { \
uint countdown = (us) + 9; \
while ((exp) && (countdown >= 10)) {\
OSL_DELAY(10); \
countdown -= 10; \
} \
}
struct ether_addr {
uint8 octet[6];
} __attribute__((packed));
/* string */
extern uchar bcm_toupper(uchar c);
extern ulong bcm_strtoul(char *cp, char **endp, uint base);
extern char *bcmstrstr(char *haystack, char *needle);
extern char *bcmstrcat(char *dest, const char *src);
extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
/* ethernet address */
extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
/* variable access */
extern char *getvar(char *vars, char *name);
extern int getintvar(char *vars, char *name);
extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
#ifdef BCMPERFSTATS
extern void bcm_perf_enable(void);
extern void bcmstats(char *fmt);
extern void bcmlog(char *fmt, uint a1, uint a2);
extern void bcmdumplog(char *buf, int size);
extern int bcmdumplogent(char *buf, uint idx);
#else
#define bcm_perf_enable()
#define bcmstats(fmt)
#define bcmlog(fmt, a1, a2)
#define bcmdumplog(buf, size) *buf = '\0'
#define bcmdumplogent(buf, idx) -1
#endif /* BCMPERFSTATS */
extern char *bcm_nvram_vars(uint *length);
extern int bcm_nvram_cache(void *sbh);
/* Support for sharing code across in-driver iovar implementations.
* The intent is that a driver use this structure to map iovar names
* to its (private) iovar identifiers, and the lookup function to
* find the entry. Macros are provided to map ids and get/set actions
* into a single number space for a switch statement.
*/
/* iovar structure */
typedef struct bcm_iovar {
const char *name; /* name for lookup and display */
uint16 varid; /* id for switch */
uint16 flags; /* driver-specific flag bits */
uint16 type; /* base type of argument */
uint16 minlen; /* min length for buffer vars */
} bcm_iovar_t;
/* varid definitions are per-driver, may use these get/set bits */
/* IOVar action bits for id mapping */
#define IOV_GET 0 /* Get an iovar */
#define IOV_SET 1 /* Set an iovar */
/* Varid to actionid mapping */
#define IOV_GVAL(id) ((id)*2)
#define IOV_SVAL(id) (((id)*2)+IOV_SET)
#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
/* flags are per-driver based on driver attributes */
/* Base type definitions */
#define IOVT_VOID 0 /* no value (implictly set only) */
#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
#define IOVT_INT8 2 /* integer values are range-checked */
#define IOVT_UINT8 3 /* unsigned int 8 bits */
#define IOVT_INT16 4 /* int 16 bits */
#define IOVT_UINT16 5 /* unsigned int 16 bits */
#define IOVT_INT32 6 /* int 32 bits */
#define IOVT_UINT32 7 /* unsigned int 32 bits */
#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
#endif /* #ifdef BCMDRIVER */
/* ** driver/apps-shared section ** */
#define BCME_STRLEN 64 /* Max string length for BCM errors */
#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
/*
* error codes could be added but the defined ones shouldn't be changed/deleted
* these error codes are exposed to the user code
* when ever a new error code is added to this list
* please update errorstring table with the related error string and
* update osl files with os specific errorcode map
*/
#define BCME_OK 0 /* Success */
#define BCME_ERROR -1 /* Error generic */
#define BCME_BADARG -2 /* Bad Argument */
#define BCME_BADOPTION -3 /* Bad option */
#define BCME_NOTUP -4 /* Not up */
#define BCME_NOTDOWN -5 /* Not down */
#define BCME_NOTAP -6 /* Not AP */
#define BCME_NOTSTA -7 /* Not STA */
#define BCME_BADKEYIDX -8 /* BAD Key Index */
#define BCME_RADIOOFF -9 /* Radio Off */
#define BCME_NOTBANDLOCKED -10 /* Not band locked */
#define BCME_NOCLK -11 /* No Clock */
#define BCME_BADRATESET -12 /* BAD Rate valueset */
#define BCME_BADBAND -13 /* BAD Band */
#define BCME_BUFTOOSHORT -14 /* Buffer too short */
#define BCME_BUFTOOLONG -15 /* Buffer too long */
#define BCME_BUSY -16 /* Busy */
#define BCME_NOTASSOCIATED -17 /* Not Associated */
#define BCME_BADSSIDLEN -18 /* Bad SSID len */
#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
#define BCME_BADCHAN -20 /* Bad Channel */
#define BCME_BADADDR -21 /* Bad Address */
#define BCME_NORESOURCE -22 /* Not Enough Resources */
#define BCME_UNSUPPORTED -23 /* Unsupported */
#define BCME_BADLEN -24 /* Bad length */
#define BCME_NOTREADY -25 /* Not Ready */
#define BCME_EPERM -26 /* Not Permitted */
#define BCME_NOMEM -27 /* No Memory */
#define BCME_ASSOCIATED -28 /* Associated */
#define BCME_RANGE -29 /* Not In Range */
#define BCME_NOTFOUND -30 /* Not Found */
#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
#define BCME_LAST BCME_DONGLE_DOWN
/* These are collection of BCME Error strings */
#define BCMERRSTRINGTABLE { \
"OK", \
"Undefined error", \
"Bad Argument", \
"Bad Option", \
"Not up", \
"Not down", \
"Not AP", \
"Not STA", \
"Bad Key Index", \
"Radio Off", \
"Not band locked", \
"No clock", \
"Bad Rate valueset", \
"Bad Band", \
"Buffer too short", \
"Buffer too long", \
"Busy", \
"Not Associated", \
"Bad SSID len", \
"Out of Range Channel", \
"Bad Channel", \
"Bad Address", \
"Not Enough Resources", \
"Unsupported", \
"Bad length", \
"Not Ready", \
"Not Permitted", \
"No Memory", \
"Associated", \
"Not In Range", \
"Not Found", \
"WME Not Enabled", \
"TSPEC Not Found", \
"ACM Not Supported", \
"Not WME Association", \
"SDIO Bus Error", \
"Dongle Not Accessible" \
}
#ifndef ABS
#define ABS(a) (((a) < 0)?-(a):(a))
#endif /* ABS */
#ifndef MIN
#define MIN(a, b) (((a) < (b))?(a):(b))
#endif /* MIN */
#ifndef MAX
#define MAX(a, b) (((a) > (b))?(a):(b))
#endif /* MAX */
#define CEIL(x, y) (((x) + ((y)-1)) / (y))
#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
#define VALID_MASK(mask) !((mask) & ((mask) + 1))
#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
/* bit map related macros */
#ifndef setbit
#ifndef NBBY /* the BSD family defines NBBY */
#define NBBY 8 /* 8 bits per byte */
#endif /* #ifndef NBBY */
#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
#define isset(a, i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
#define isclr(a, i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
#endif /* setbit */
#define NBITS(type) (sizeof(type) * 8)
#define NBITVAL(nbits) (1 << (nbits))
#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
#define NBITMASK(nbits) MAXBITVAL(nbits)
#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
/* basic mux operation - can be optimized on several architectures */
#define MUX(pred, true, false) ((pred) ? (true) : (false))
/* modulo inc/dec - assumes x E [0, bound - 1] */
#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
/* modulo inc/dec, bound = 2^k */
#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
/* modulo add/sub - assumes x, y E [0, bound - 1] */
#define MODADD(x, y, bound) \
MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
#define MODSUB(x, y, bound) \
MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
/* module add/sub, bound = 2^k */
#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
/* crc defines */
#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
/* bcm_format_flags() bit description structure */
typedef struct bcm_bit_desc {
uint32 bit;
char* name;
} bcm_bit_desc_t;
/* tag_ID/length/value_buffer tuple */
typedef struct bcm_tlv {
uint8 id;
uint8 len;
uint8 data[1];
} bcm_tlv_t;
/* Check that bcm_tlv_t fits into the given buflen */
#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
/* buffer length for ethernet address from bcm_ether_ntoa() */
#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
/* unaligned load and store macros */
#ifdef IL_BIGENDIAN
static INLINE uint32
load32_ua(uint8 *a)
{
return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
}
static INLINE void
store32_ua(uint8 *a, uint32 v)
{
a[0] = (v >> 24) & 0xff;
a[1] = (v >> 16) & 0xff;
a[2] = (v >> 8) & 0xff;
a[3] = v & 0xff;
}
static INLINE uint16
load16_ua(uint8 *a)
{
return ((a[0] << 8) | a[1]);
}
static INLINE void
store16_ua(uint8 *a, uint16 v)
{
a[0] = (v >> 8) & 0xff;
a[1] = v & 0xff;
}
#else
static INLINE uint32
load32_ua(uint8 *a)
{
return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
}
static INLINE void
store32_ua(uint8 *a, uint32 v)
{
a[3] = (v >> 24) & 0xff;
a[2] = (v >> 16) & 0xff;
a[1] = (v >> 8) & 0xff;
a[0] = v & 0xff;
}
static INLINE uint16
load16_ua(uint8 *a)
{
return ((a[1] << 8) | a[0]);
}
static INLINE void
store16_ua(uint8 *a, uint16 v)
{
a[1] = (v >> 8) & 0xff;
a[0] = v & 0xff;
}
#endif /* IL_BIGENDIAN */
/* externs */
/* crc */
extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
/* format/print */
extern void printfbig(char *buf);
/* IE parsing */
extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
/* bcmerror */
extern const char *bcmerrorstr(int bcmerror);
/* multi-bool data type: set of bools, mbool is true if any is set */
typedef uint32 mbool;
#define mboolset(mb, bit) (mb |= bit) /* set one bool */
#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
/* power conversion */
extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
extern uint8 bcm_mw_to_qdbm(uint16 mw);
/* generic datastruct to help dump routines */
struct fielddesc {
char *nameandfmt;
uint32 offset;
uint32 len;
};
/* Buffer structure for collecting string-formatted data
* using bcm_bprintf() API.
* Use bcm_binit() to initialize before use
*/
struct bcmstrbuf
{
char *buf; /* pointer to current position in origbuf */
uint size; /* current (residual) size in bytes */
char *origbuf; /* unmodified pointer to orignal buffer */
uint origsize; /* unmodified orignal buffer size in bytes */
};
extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str,
char *buf, uint32 bufsize);
extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
#endif /* _bcmutils_h_ */

31
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndchipc.h Normal file
View File

@@ -0,0 +1,31 @@
/*
* HND SiliconBackplane chipcommon support.
*
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id$
*/
#ifndef _hndchipc_h_
#define _hndchipc_h_
typedef void (*sb_serial_init_fn)(void *regs, uint irq, uint baud_base, uint reg_shift);
extern void sb_serial_init(sb_t *sbh, sb_serial_init_fn add);
extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
extern void sb_jtagm_disable(osl_t *osh, void *h);
extern uint32 jtag_rwreg(osl_t *osh, void *h, uint32 ir, uint32 dr);
typedef void (*cc_isr_fn)(void* cbdata, uint32 ccintst);
extern bool sb_cc_register_isr(sb_t *sbh, cc_isr_fn isr, uint32 ccintmask, void *cbdata);
extern void sb_cc_isr(sb_t *sbh, chipcregs_t *regs);
#endif /* _hndchipc_h_ */

10
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndcpu.h
View File

@@ -1,7 +1,7 @@
/*
* HND SiliconBackplane MIPS/ARM cores software interface.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _hndcpu_h_
@@ -17,12 +17,14 @@
#if defined(mips)
#include <hndmips.h>
#elif defined(__ARM_ARCH_4T__)
#elif defined(__arm__) || defined(__thumb__) || defined(__thumb2__)
#include <hndarm.h>
#endif
extern uint sb_irq(sb_t *sbh);
extern uint32 sb_cpu_clock(sb_t *sbh);
extern void sb_cpu_wait(void);
extern void hnd_cpu_wait(sb_t *sbh);
extern void hnd_cpu_jumpto(void *addr);
extern void hnd_cpu_reset(sb_t *sbh);
#endif /* _hndcpu_h_ */

7
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h
View File

@@ -1,7 +1,7 @@
/*
* HND SiliconBackplane MIPS core software interface.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _hndmips_h_
@@ -22,6 +22,7 @@ extern uint32 sb_memc_get_ncdl(sb_t *sbh);
#if defined(BCMPERFSTATS)
/* enable counting - exclusive version. Only one set of counters allowed at a time */
extern void hndmips_perf_cyclecount_enable(void);
extern void hndmips_perf_instrcount_enable(void);
extern void hndmips_perf_icachecount_enable(void);
extern void hndmips_perf_dcachecount_enable(void);
@@ -40,6 +41,6 @@ extern void hndmips_perf_icache_miss_enable(void);
extern uint32 hndmips_perf_read_instrcount(void);
extern uint32 hndmips_perf_read_cache_miss(void);
extern uint32 hndmips_perf_read_cache_hit(void);
#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
#endif
#endif /* _hndmips_h_ */

9
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpci.h
View File

@@ -1,8 +1,8 @@
/*
* HND SiliconBackplane PCI core software interface.
*
* $Id: hndpci.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
* Copyright 2006, Broadcom Corporation
* $Id$
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -25,6 +25,9 @@ extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint of
extern void sbpci_ban(uint16 core);
extern int sbpci_init(sb_t *sbh);
extern int sbpci_init_pci(sb_t *sbh);
extern void sbpci_check(sb_t *sbh);
extern void sbpci_init_cores(sb_t *sbh);
extern void sbpci_arb_park(sb_t *sbh, uint parkid);
#define PCI_PARK_NVRAM 0xff
#endif /* _hndpci_h_ */

37
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpmu.h Normal file
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@@ -0,0 +1,37 @@
/*
* HND SiliconBackplane PMU support.
*
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id$
*/
#ifndef _hndpmu_h_
#define _hndpmu_h_
#define SET_LDO_VOLTAGE_LDO1 1
#define SET_LDO_VOLTAGE_LDO2 2
#define SET_LDO_VOLTAGE_LDO3 3
#define SET_LDO_VOLTAGE_PAREF 4
extern void sb_pmu_init(sb_t *sbh, osl_t *osh);
extern void sb_pmu_pll_init(sb_t *sbh, osl_t *osh, uint32 xtalfreq);
extern void sb_pmu_res_init(sb_t *sbh, osl_t *osh);
extern uint32 sb_pmu_force_ilp(sb_t *sbh, osl_t *osh, bool force);
extern uint32 sb_pmu_cpu_clock(sb_t *sbh, osl_t *osh);
extern uint32 sb_pmu_alp_clock(sb_t *sbh, osl_t *osh);
extern void sb_pmu_set_switcher_voltage(sb_t *sbh, osl_t *osh, uint8 bb_voltage, uint8 rf_voltage);
extern void sb_pmu_set_ldo_voltage(sb_t *sbh, osl_t *osh, uint8 ldo, uint8 voltage);
extern void sb_pmu_paref_ldo_enable(sb_t *sbh, osl_t *osh, bool enable);
extern uint16 sb_pmu_fast_pwrup_delay(sb_t *sbh, osl_t *osh);
extern void sb_pmu_otp_power(sb_t *sbh, osl_t *osh, bool on);
extern void sb_pmu_rcal(sb_t *sbh, osl_t *osh);
#endif /* _hndpmu_h_ */

33
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linux_gpio.h Normal file
View File

@@ -0,0 +1,33 @@
/*
* Linux Broadcom BCM47xx GPIO char driver
*
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id$
*/
#ifndef _linux_gpio_h_
#define _linux_gpio_h_
struct gpio_ioctl {
uint32 mask;
uint32 val;
};
#define GPIO_IOC_MAGIC 'G'
/* reserve/release a gpio to the caller */
#define GPIO_IOC_RESERVE _IOWR(GPIO_IOC_MAGIC, 1, struct gpio_ioctl)
#define GPIO_IOC_RELEASE _IOWR(GPIO_IOC_MAGIC, 2, struct gpio_ioctl)
/* ioctls to read/write the gpio registers */
#define GPIO_IOC_OUT _IOWR(GPIO_IOC_MAGIC, 3, struct gpio_ioctl)
#define GPIO_IOC_IN _IOWR(GPIO_IOC_MAGIC, 4, struct gpio_ioctl)
#define GPIO_IOC_OUTEN _IOWR(GPIO_IOC_MAGIC, 5, struct gpio_ioctl)
#endif /* _linux_gpio_h_ */

40
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linuxver.h
View File

@@ -2,7 +2,7 @@
* Linux-specific abstractions to gain some independence from linux kernel versions.
* Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -10,14 +10,19 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: linuxver.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _linuxver_h_
#define _linuxver_h_
#include <linux/config.h>
#include <linux/version.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
#include <linux/config.h>
#else
#include <linux/autoconf.h>
#endif
#include <linux/module.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
@@ -28,15 +33,6 @@
#endif
#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
#if defined(MODULE) && defined(MODVERSIONS)
#include <linux/modversions.h>
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
#include <linux/moduleparam.h>
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
#define module_param_string(_name_, _string_, _size_, _perm_) \
@@ -77,6 +73,13 @@
#endif
#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func)
#else
#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func, _data)
typedef void (*work_func_t)(void *work);
#endif /* < 2.6.20 */
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
/* Some distributions have their own 2.6.x compatibility layers */
#ifndef IRQ_NONE
@@ -110,6 +113,12 @@ cs_error(client_handle_t handle, int func, int ret)
}
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15))
typedef struct pcmcia_device dev_link_t;
#endif
#endif /* CONFIG_PCMCIA */
#ifndef __exit
@@ -414,4 +423,11 @@ pci_restore_state(struct pci_dev *dev, u32 *buffer)
#define af_packet_priv data
#endif
/* suspend args */
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 11)
#define DRV_SUSPEND_STATE_TYPE pm_message_t
#else
#define DRV_SUSPEND_STATE_TYPE uint32
#endif
#endif /* _linuxver_h_ */

6
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/mipsinc.h
View File

@@ -1,7 +1,7 @@
/*
* HND Run Time Environment for standalone MIPS programs.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _MISPINC_H
@@ -69,6 +69,7 @@
#define C0_CTEXT $4
#define C0_PGMASK $5
#define C0_WIRED $6
#define C0_INFO $7
#define C0_BADVADDR $8
#define C0_COUNT $9
#define C0_TLBHI $10
@@ -145,6 +146,7 @@ symbol: .frame sp, 0, ra
#define C0_CTEXT 4 /* CP0: Context */
#define C0_PGMASK 5 /* CP0: TLB PageMask */
#define C0_WIRED 6 /* CP0: TLB Wired */
#define C0_INFO 7 /* CP0: Info */
#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
#define C0_COUNT 9 /* CP0: Count */
#define C0_TLBHI 10 /* CP0: TLB EntryHi */

82
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/osl.h
View File

@@ -4,26 +4,66 @@
#include <linux/delay.h>
#include <typedefs.h>
#include <linuxver.h>
#include <bcmutils.h>
#include <pcicfg.h>
#define ASSERT(n)
#ifndef ABS
#define ABS(a) (((a) < 0)?-(a):(a))
#endif /* ABS */
#ifndef MIN
#define MIN(a, b) (((a) < (b))?(a):(b))
#endif /* MIN */
#ifndef MAX
#define MAX(a, b) (((a) > (b))?(a):(b))
#endif /* MAX */
#define CEIL(x, y) (((x) + ((y)-1)) / (y))
#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
#define VALID_MASK(mask) !((mask) & ((mask) + 1))
#ifndef OFFSETOF
#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
#endif /* OFFSETOF */
#ifndef ARRAYSIZE
#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
#endif
/*
* Spin at most 'us' microseconds while 'exp' is true.
* Caller should explicitly test 'exp' when this completes
* and take appropriate error action if 'exp' is still true.
*/
#define SPINWAIT(exp, us) { \
uint countdown = (us) + 9; \
while ((exp) && (countdown >= 10)) {\
OSL_DELAY(10); \
countdown -= 10; \
} \
}
typedef void (*pktfree_cb_fn_t)(void *ctx, void *pkt, unsigned int status);
/* Pkttag flag should be part of public information */
typedef struct {
bool pkttag;
uint pktalloced; /* Number of allocated packet buffers */
void *tx_fn;
void *tx_ctx;
uint pktalloced; /* Number of allocated packet buffers */
bool mmbus; /* Bus supports memory-mapped register accesses */
pktfree_cb_fn_t tx_fn; /* Callback function for PKTFREE */
void *tx_ctx; /* Context to the callback function */
} osl_pubinfo_t;
struct osl_info {
osl_pubinfo_t pub;
uint magic;
void *pdev;
uint malloced;
uint failed;
void *dbgmem_list;
osl_pubinfo_t pub;
uint magic;
void *pdev;
uint malloced;
uint failed;
uint bustype;
void *dbgmem_list;
};
typedef struct osl_info osl_t;
@@ -101,8 +141,8 @@ typedef struct osl_info osl_t;
#define MFREE(osh, addr, size) kfree((addr))
#define MALLOCED(osh) (0)
#define osl_delay OSL_DELAY
static inline void OSL_DELAY(uint usec)
#define OSL_DELAY _osl_delay
static inline void _osl_delay(uint usec)
{
uint d;
@@ -128,10 +168,10 @@ bcm_mdelay(uint ms)
#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
#define OSL_PCI_READ_CONFIG(osh, offset, size) \
osl_pci_read_config((osh), (offset), (size))
_osl_pci_read_config((osh), (offset), (size))
static inline uint32
osl_pci_read_config(osl_t *osh, uint offset, uint size)
_osl_pci_read_config(osl_t *osh, uint offset, uint size)
{
uint val;
uint retry = PCI_CFG_RETRY;
@@ -146,9 +186,9 @@ osl_pci_read_config(osl_t *osh, uint offset, uint size)
}
#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
osl_pci_write_config((osh), (offset), (size), (val))
_osl_pci_write_config((osh), (offset), (size), (val))
static inline void
osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
_osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
{
uint retry = PCI_CFG_RETRY;
@@ -156,24 +196,24 @@ osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
pci_write_config_dword(osh->pdev, offset, val);
if (offset != PCI_BAR0_WIN)
break;
if (osl_pci_read_config(osh, offset, size) == val)
if (_osl_pci_read_config(osh, offset, size) == val)
break;
} while (retry--);
}
/* return bus # for the pci device pointed by osh->pdev */
#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
#define OSL_PCI_BUS(osh) _osl_pci_bus(osh)
static inline uint
osl_pci_bus(osl_t *osh)
_osl_pci_bus(osl_t *osh)
{
return ((struct pci_dev *)osh->pdev)->bus->number;
}
/* return slot # for the pci device pointed by osh->pdev */
#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
#define OSL_PCI_SLOT(osh) _osl_pci_slot(osh)
static inline uint
osl_pci_slot(osl_t *osh)
_osl_pci_slot(osl_t *osh)
{
return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
}

19
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h
View File

@@ -1,7 +1,7 @@
/*
* pcicfg.h: PCI configuration constants and structures.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $
* $Id$
*/
#ifndef _h_pcicfg_
@@ -170,6 +170,14 @@ typedef struct _pci_config_regs {
#undef PCI_CLASS_DOCK
#endif /* __NetBSD__ */
#ifdef EFI
#undef PCI_CLASS_BRIDGE
#undef PCI_CLASS_OLD
#undef PCI_CLASS_DISPLAY
#undef PCI_CLASS_SERIAL
#undef PCI_CLASS_SATELLITE
#endif /* EFI */
/* Classes and subclasses */
typedef enum {
@@ -406,6 +414,11 @@ typedef struct _pciconfig_cap_pwrmgmt {
unsigned char data;
} pciconfig_cap_pwrmgmt;
#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
/* Data structure to define the PCIE capability */
typedef struct _pciconfig_cap_pcie {
unsigned char capID;
@@ -463,7 +476,7 @@ typedef struct _pcie_enhanced_caphdr {
* 8KB window, so their address is the "regular"
* address plus 4K
*/
#define PCI_BAR0_WINSZ 8192 /* bar0 window size */
#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */

501
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbchipc.h
View File

@@ -5,8 +5,8 @@
* jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
* gpio interface, extbus, and support for serial and parallel flashes.
*
* $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
* Copyright 2006, Broadcom Corporation
* $Id$
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -19,7 +19,6 @@
#ifndef _SBCHIPC_H
#define _SBCHIPC_H
#ifndef _LANGUAGE_ASSEMBLY
/* cpp contortions to concatenate w/arg prescan */
@@ -29,6 +28,7 @@
#define PAD _XSTR(__LINE__)
#endif /* PAD */
typedef volatile struct {
uint32 chipid; /* 0x0 */
uint32 capabilities;
@@ -62,20 +62,26 @@ typedef volatile struct {
/* Silicon backplane configuration broadcast control */
uint32 broadcastaddress; /* 0x50 */
uint32 broadcastdata;
uint32 PAD[2];
/* gpio - cleared only by power-on-reset */
uint32 gpiopullup; /* 0x58, corerev >= 20 */
uint32 gpiopulldown; /* 0x5c, corerev >= 20 */
uint32 gpioin; /* 0x60 */
uint32 gpioout;
uint32 gpioouten;
uint32 gpiocontrol;
uint32 gpiointpolarity;
uint32 gpiointmask;
uint32 PAD[2];
/* GPIO events corerev >= 11 */
uint32 gpioevent;
uint32 gpioeventintmask;
/* Watchdog timer */
uint32 watchdog; /* 0x80 */
uint32 PAD[1];
/* GPIO events corerev >= 11 */
uint32 gpioeventintpolarity;
/* GPIO based LED powersave registers corerev >= 16 */
uint32 gpiotimerval; /* 0x88 */
@@ -114,10 +120,31 @@ typedef volatile struct {
uint32 prog_waitcount;
uint32 flash_config;
uint32 flash_waitcount;
uint32 PAD[44];
uint32 PAD[4];
/* Clock control and hardware workarounds */
uint32 clk_ctl_st;
/* Enhanced Coexistance Interface (ECI) registers (corerev >= 21) */
uint32 eci_output; /* 0x140 */
uint32 eci_control;
uint32 eci_inputlo;
uint32 eci_inputmi;
uint32 eci_inputhi;
uint32 eci_inputintpolaritylo;
uint32 eci_inputintpolaritymi;
uint32 eci_inputintpolarityhi;
uint32 eci_intmasklo;
uint32 eci_intmaskmi;
uint32 eci_intmaskhi;
uint32 eci_eventlo;
uint32 eci_eventmi;
uint32 eci_eventhi;
uint32 eci_eventmasklo;
uint32 eci_eventmaskmi;
uint32 eci_eventmaskhi;
uint32 PAD[23];
/* Clock control and hardware workarounds (corerev >= 20) */
uint32 clk_ctl_st; /* 0x1e0 */
uint32 hw_war;
uint32 PAD[70];
@@ -140,12 +167,47 @@ typedef volatile struct {
uint8 uart1lsr;
uint8 uart1msr;
uint8 uart1scratch;
uint32 PAD[126];
/* PMU registers (corerev >= 20) */
uint32 pmucontrol; /* 0x600 */
uint32 pmucapabilities;
uint32 pmustatus;
uint32 res_state;
uint32 res_pending;
uint32 pmutimer;
uint32 min_res_mask;
uint32 max_res_mask;
uint32 res_table_sel;
uint32 res_dep_mask;
uint32 res_updn_timer;
uint32 res_timer;
uint32 clkstretch;
uint32 pmuwatchdog;
uint32 PAD[2];
uint32 res_req_timer_sel;
uint32 res_req_timer;
uint32 res_req_mask;
uint32 PAD;
uint32 chipcontrol_addr;
uint32 chipcontrol_data;
uint32 regcontrol_addr;
uint32 regcontrol_data;
uint32 pllcontrol_addr;
uint32 pllcontrol_data;
uint32 PAD[102];
uint16 otp[512];
} chipcregs_t;
#endif /* _LANGUAGE_ASSEMBLY */
/* corecontrol */
#define CC_UE (1 << 0) /* uart enable */
#define CC_CHIPID 0
#define CC_CAPABILITIES 4
#define CC_OTPST 0x10
#define CC_CHIPST 0x2c
#define CC_JTAGCMD 0x30
#define CC_JTAGIR 0x34
#define CC_JTAGDR 0x38
@@ -158,7 +220,18 @@ typedef volatile struct {
#define CC_CLKC_M3 0xa0
#define CC_CLKDIV 0xa4
#define CC_SYS_CLK_CTL 0xc0
#define CC_OTP 0x800
#define CC_CLK_CTL_ST SB_CLK_CTL_ST
#define PMU_CTL 0x600
#define PMU_CAP 0x604
#define PMU_ST 0x608
#define PMU_TIMER 0x614
#define PMU_MIN_RES_MASK 0x618
#define PMU_MAX_RES_MASK 0x61c
#define PMU_REG_CONTROL_ADDR 0x658
#define PMU_REG_CONTROL_DATA 0x65C
#define PMU_PLL_CONTROL_ADDR 0x660
#define PMU_PLL_CONTROL_DATA 0x664
#define CC_OTP 0x800 /* OTP address space */
/* chipid */
#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
@@ -170,24 +243,26 @@ typedef volatile struct {
#define CID_CC_SHIFT 24
/* capabilities */
#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
#define CAP_PWR_CTL 0x00040000 /* Power control */
#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
#define CAP_ROM 0x00800000 /* Internal boot rom active */
#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
#define CC_CAP_UARTS_MASK 0x00000003 /* Number of uarts */
#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
#define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
#define CC_CAP_PWR_CTL 0x00040000 /* Power control */
#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
#define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */
/* PLL type */
#define PLL_NONE 0x00000000
@@ -199,39 +274,72 @@ typedef volatile struct {
#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
/* ALP clock on pre-PMU chips */
#define ALP_CLOCK 20000000
/* HT clock */
#define HT_CLOCK 80000000
/* watchdog clock */
#define WATCHDOG_CLOCK_5354 32000 /* Hz */
/* corecontrol */
#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
#define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */
/* chipcontrol */
#define CHIPCTRL_4321A0_DEFAULT 0x3a4
#define CHIPCTRL_4321A1_DEFAULT 0x0a4
/* Fields in the otpstatus register */
#define OTPS_PROGFAIL 0x80000000
#define OTPS_PROTECT 0x00000007
#define OTPS_HW_PROTECT 0x00000001
#define OTPS_SW_PROTECT 0x00000002
#define OTPS_CID_PROTECT 0x00000004
/* Fields in the otpstatus register in rev >= 21 */
#define OTPS_OL_MASK 0x000000ff
#define OTPS_OL_MFG 0x00000001 /* manuf row is locked */
#define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */
#define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */
#define OTPS_OL_GU 0x00000008 /* general use region is locked */
#define OTPS_GUP_MASK 0x00000f00
#define OTPS_GUP_SHIFT 8
#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
#define OTPS_READY 0x00001000
#define OTPS_RV(x) (1 << (16 + (x)))
/* Fields in the otpcontrol register */
#define OTPC_RECWAIT 0xff000000
#define OTPC_PROGWAIT 0x00ffff00
#define OTPC_PRW_SHIFT 8
#define OTPC_MAXFAIL 0x00000038
#define OTPC_VSEL 0x00000006
#define OTPC_SELVL 0x00000001
/* Fields in the otpcontrol register in rev >= 21 */
#define OTPC_PROGSEL 0x00000001
#define OTPC_PCOUNT_MASK 0x0000000e
#define OTPC_PCOUNT_SHIFT 1
#define OTPC_VSEL_MASK 0x000000f0
#define OTPC_VSEL_SHIFT 4
#define OTPC_TMM_MASK 0x00000700
#define OTPC_TMM_SHIFT 8
#define OTPC_ODM 0x00000800
#define OTPC_PROGEN 0x80000000
/* Fields in otpprog */
#define OTPP_COL_MASK 0x000000ff
#define OTPP_ROW_MASK 0x0000ff00
#define OTPP_ROW_SHIFT 8
#define OTPP_READERR 0x10000000
#define OTPP_VALUE 0x20000000
#define OTPP_VALUE_SHIFT 29
#define OTPP_READ 0x40000000
#define OTPP_START 0x80000000
#define OTPP_BUSY 0x80000000
/* Fields in otpprog in rev >= 21 */
#define OTPP_COL_MASK 0x000000ff
#define OTPP_COL_SHIFT 0
#define OTPP_ROW_MASK 0x0000ff00
#define OTPP_ROW_SHIFT 8
#define OTPP_OC_MASK 0x0f000000
#define OTPP_OC_SHIFT 24
#define OTPP_READERR 0x10000000
#define OTPP_VALUE_MASK 0x20000000
#define OTPP_VALUE_SHIFT 29
#define OTPP_START_BUSY 0x80000000
/* Opcodes for OTPP_OC field */
#define OTPPOC_READ 0
#define OTPPOC_BIT_PROG 1
#define OTPPOC_VERIFY 3
#define OTPPOC_INIT 4
#define OTPPOC_SET 5
#define OTPPOC_RESET 6
#define OTPPOC_OCST 7
#define OTPPOC_ROW_LOCK 8
#define OTPPOC_PRESCN_TEST 9
/* jtagcmd */
#define JCMD_START 0x80000000
@@ -272,7 +380,12 @@ typedef volatile struct {
/* intstatus/intmask */
#define CI_GPIO 0x00000001 /* gpio intr */
#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
#define CI_EI 0x00000002 /* extif intr (corerev >= 3) */
#define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */
#define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */
#define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */
#define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */
#define CI_UART 0x00000040 /* uart intr (corerev >= 21) */
#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
/* slow_clk_ctl */
@@ -306,6 +419,43 @@ typedef volatile struct {
#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
#define SYCC_CD_SHIFT 16
/* pcmcia_iowait */
#define PI_W0_MASK 0x0000003f /* waitcount0 */
#define PI_W1_MASK 0x00001f00 /* waitcount1 */
#define PI_W1_SHIFT 8
#define PI_W2_MASK 0x001f0000 /* waitcount2 */
#define PI_W2_SHIFT 16
#define PI_W3_MASK 0x1f000000 /* waitcount3 */
#define PI_W3_SHIFT 24
/* prog_waitcount */
#define PW_W0_MASK 0x0000001f /* waitcount0 */
#define PW_W1_MASK 0x00001f00 /* waitcount1 */
#define PW_W1_SHIFT 8
#define PW_W2_MASK 0x001f0000 /* waitcount2 */
#define PW_W2_SHIFT 16
#define PW_W3_MASK 0x1f000000 /* waitcount3 */
#define PW_W3_SHIFT 24
#define PW_W0 0x0000000c
#define PW_W1 0x00000a00
#define PW_W2 0x00020000
#define PW_W3 0x01000000
/* watchdog */
#define WATCHDOG_CLOCK 48000000 /* Hz */
/* Fields in pmucontrol */
#define PCTL_ILP_DIV_MASK 0xffff0000
#define PCTL_ILP_DIV_SHIFT 16
#define PCTL_NOILP_ON_WAIT 0x00000200
#define PCTL_HT_REQ_EN 0x00000100
#define PCTL_ALP_REQ_EN 0x00000080
#define PCTL_XTALFREQ_MASK 0x0000007c
#define PCTL_XTALFREQ_SHIFT 2
#define PCTL_ILP_DIV_EN 0x00000002
#define PCTL_LPO_SEL 0x00000001
/* gpiotimerval */
#define GPIO_ONTIME_SHIFT 16
@@ -377,9 +527,10 @@ typedef volatile struct {
#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
#define CC_CFG_EM_IDE 0x0006 /* IDE */
#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
#define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */
#define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */
#define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */
#define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */
/* ExtBus address space */
#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
@@ -396,6 +547,7 @@ typedef volatile struct {
/* Start/busy bit in flashcontrol */
#define SFLASH_OPCODE 0x000000ff
#define SFLASH_ACTION 0x00000700
#define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
#define SFLASH_START 0x80000000
#define SFLASH_BUSY SFLASH_START
@@ -419,6 +571,7 @@ typedef volatile struct {
#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
#define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */
/* Status register bits for ST flashes */
#define SFLASH_ST_WIP 0x01 /* Write In Progress */
@@ -456,31 +609,6 @@ typedef volatile struct {
#define SFLASH_AT_ID_MASK 0x38
#define SFLASH_AT_ID_SHIFT 3
/* OTP regions */
#define OTP_HW_REGION OTPS_HW_PROTECT
#define OTP_SW_REGION OTPS_SW_PROTECT
#define OTP_CID_REGION OTPS_CID_PROTECT
/* OTP regions (Byte offsets from otp size) */
#define OTP_SWLIM_OFF (-8)
#define OTP_CIDBASE_OFF 0
#define OTP_CIDLIM_OFF 8
/* Predefined OTP words (Word offset from otp size) */
#define OTP_BOUNDARY_OFF (-4)
#define OTP_HWSIGN_OFF (-3)
#define OTP_SWSIGN_OFF (-2)
#define OTP_CIDSIGN_OFF (-1)
#define OTP_CID_OFF 0
#define OTP_PKG_OFF 1
#define OTP_FID_OFF 2
#define OTP_RSV_OFF 3
#define OTP_LIM_OFF 4
#define OTP_SIGNATURE 0x578a
#define OTP_MAGIC 0x4e56
/*
* These are the UART port assignments, expressed as offsets from the base
* register. These assignments should hold for any serial port based on
@@ -507,10 +635,223 @@ typedef volatile struct {
#define UART_LSR_RXRDY 0x01 /* Receiver ready */
#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
/* Interrupt Identity Register (IIR) bits */
#define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */
#define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */
#define UART_IIR_MDM_CHG 0x0 /* Modem status changed */
#define UART_IIR_NOINT 0x1 /* No interrupt pending */
#define UART_IIR_THRE 0x2 /* THR empty */
#define UART_IIR_RCVD_DATA 0x4 /* Received data available */
#define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */
#define UART_IIR_CHAR_TIME 0xc /* Character time */
/* Interrupt Enable Register (IER) bits */
#define UART_IER_EDSSI 8 /* enable modem status interrupt */
#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
#define UART_IER_ERBFI 1 /* enable data available interrupt */
/* pmustatus */
#define PST_INTPEND 0x0040
#define PST_SBCLKST 0x0030
#define PST_ALPAVAIL 0x0008
#define PST_HTAVAIL 0x0004
#define PST_RESINIT 0x0003
/* pmucapabilities */
#define PCAP_REV_MASK 0x000000ff
/* PMU Resource Request Timer registers */
/* This is based on PmuRev0 */
#define PRRT_TIME_MASK 0x03ff
#define PRRT_INTEN 0x0400
#define PRRT_REQ_ACTIVE 0x0800
#define PRRT_ALP_REQ 0x1000
#define PRRT_HT_REQ 0x2000
/* PMU resource bit position */
#define PMURES_BIT(bit) (1 << (bit))
/* PMU corerev and chip specific PLL controls.
* PMU<rev>_PLL<num>_XXXX where <rev> is PMU corerev and <num> is an arbitary number
* to differentiate different PLLs controlled by the same PMU rev.
*/
/* pllcontrol registers */
/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
#define PMU0_PLL0_PLLCTL0 0
#define PMU0_PLL0_PC0_PDIV_MASK 1
#define PMU0_PLL0_PC0_PDIV_FREQ 25000
#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
#define PMU0_PLL0_PC0_DIV_ARM_BASE 8
/* PC0_DIV_ARM for PLLOUT_ARM */
#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
#define PMU0_PLL0_PLLCTL1 1
#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
#define PMU0_PLL0_PC1_STOP_MOD 0x00000040
/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
#define PMU0_PLL0_PLLCTL2 2
#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
/* Chip specific PMU resources. */
#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
#define RES4328_ILP_REQUEST 4 /* 0x00010 */
#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
#define RES4328_ROM_SWITCH 7 /* 0x00080 */
#define RES4328_PA_REF_LDO 8 /* 0x00100 */
#define RES4328_RADIO_LDO 9 /* 0x00200 */
#define RES4328_AFE_LDO 10 /* 0x00400 */
#define RES4328_PLL_LDO 11 /* 0x00800 */
#define RES4328_BG_FILTBYP 12 /* 0x01000 */
#define RES4328_TX_FILTBYP 13 /* 0x02000 */
#define RES4328_RX_FILTBYP 14 /* 0x04000 */
#define RES4328_XTAL_PU 15 /* 0x08000 */
#define RES4328_XTAL_EN 16 /* 0x10000 */
#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
#define RES4328_BB_PLL_PU 19 /* 0x80000 */
#define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */
#define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */
#define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */
#define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
#define RES5354_ILP_REQUEST 4 /* 0x00010 */
#define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */
#define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */
#define RES5354_ROM_SWITCH 7 /* 0x00080 */
#define RES5354_PA_REF_LDO 8 /* 0x00100 */
#define RES5354_RADIO_LDO 9 /* 0x00200 */
#define RES5354_AFE_LDO 10 /* 0x00400 */
#define RES5354_PLL_LDO 11 /* 0x00800 */
#define RES5354_BG_FILTBYP 12 /* 0x01000 */
#define RES5354_TX_FILTBYP 13 /* 0x02000 */
#define RES5354_RX_FILTBYP 14 /* 0x04000 */
#define RES5354_XTAL_PU 15 /* 0x08000 */
#define RES5354_XTAL_EN 16 /* 0x10000 */
#define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */
#define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */
#define RES5354_BB_PLL_PU 19 /* 0x80000 */
/* pllcontrol registers */
/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypsss_sdmod */
#define PMU1_PLL0_PLLCTL0 0
#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
#define PMU1_PLL0_PC0_P1DIV_SHIFT 20
#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
#define PMU1_PLL0_PC0_P2DIV_SHIFT 24
/* m<x>div */
#define PMU1_PLL0_PLLCTL1 1
#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
#define PMU1_PLL0_PC1_M1DIV_SHIFT 0
#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
#define PMU1_PLL0_PC1_M2DIV_SHIFT 8
#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
#define PMU1_PLL0_PC1_M3DIV_SHIFT 16
#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
#define PMU1_PLL0_PC1_M4DIV_SHIFT 24
/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
#define PMU1_PLL0_PLLCTL2 2
#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
#define PMU1_PLL0_PC2_M5DIV_SHIFT 0
#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
#define PMU1_PLL0_PC2_M6DIV_SHIFT 8
#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
/* ndiv_frac */
#define PMU1_PLL0_PLLCTL3 3
#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
/* pll_ctrl */
#define PMU1_PLL0_PLLCTL4 4
/* pll_ctrl, vco_rng, clkdrive_ch<x> */
#define PMU1_PLL0_PLLCTL5 5
#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
#define RES4325_CBUCK_BURST 1 /* 0x00000002 */
#define RES4325_CBUCK_PWM 2 /* 0x00000004 */
#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
#define RES4325_ILP_REQUEST 6 /* 0x00000040 */
#define RES4325_ABUCK_BURST 7 /* 0x00000080 */
#define RES4325_ABUCK_PWM 8 /* 0x00000100 */
#define RES4325_LNLDO1_PU 9 /* 0x00000200 */
#define RES4325_LNLDO2_PU 10 /* 0x00000400 */
#define RES4325_LNLDO3_PU 11 /* 0x00000800 */
#define RES4325_LNLDO4_PU 12 /* 0x00001000 */
#define RES4325_XTAL_PU 13 /* 0x00002000 */
#define RES4325_ALP_AVAIL 14 /* 0x00004000 */
#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
#define RES4325_HT_AVAIL 21 /* 0x00200000 */
/* Chip specific ChipStatus register bits */
#define CST4325_SPROM_OTP_SEL_MASK 0x00000003
#define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
#define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
#define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
#define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
#define CST4325_SDIO_USB_MODE_MASK 0x00000004
#define CST4325_SDIO_USB_MODE_SHIFT 2
#define CST4325_RCAL_VALID_MASK 0x00000008
#define CST4325_RCAL_VALID_SHIFT 3
#define CST4325_RCAL_VALUE_MASK 0x000001f0
#define CST4325_RCAL_VALUE_SHIFT 4
#define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */
#define CST4325_PMUTOP_2B_SHIFT 9
#define RES4312_SWITCHER_BURST 0 /* 0x00000001 */
#define RES4312_SWITCHER_PWM 1 /* 0x00000002 */
#define RES4312_PA_REF_LDO 2 /* 0x00000004 */
#define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */
#define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */
#define RES4312_RADIO_LDO 5 /* 0x00000020 */
#define RES4312_ILP_REQUEST 6 /* 0x00000040 */
#define RES4312_BG_FILTBYP 7 /* 0x00000080 */
#define RES4312_TX_FILTBYP 8 /* 0x00000100 */
#define RES4312_RX_FILTBYP 9 /* 0x00000200 */
#define RES4312_XTAL_PU 10 /* 0x00000400 */
#define RES4312_ALP_AVAIL 11 /* 0x00000800 */
#define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */
#define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */
#define RES4312_HT_AVAIL 14 /* 0x00004000 */
/*
* Maximum delay for the PMU state transition.
* This is an upper bound intended for spinwaits etc.
*/
#define PMU_MAX_TRANSITION_DLY 15000
#endif /* _SBCHIPC_H */

51
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h
View File

@@ -1,7 +1,7 @@
/*
* Broadcom SiliconBackplane hardware register definitions.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,11 +9,12 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _SBCONFIG_H
#define _SBCONFIG_H
#include "linuxver.h"
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
@@ -36,13 +37,13 @@
#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
#define SB_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
#define SB_ROM 0x20000000 /* ARM ROM */
#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */
#define SB_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
#define SB_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
#define SB_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
@@ -196,7 +197,7 @@ typedef volatile struct _sbconfig {
#define SBTMH_INT 0x2 /* interrupt */
#define SBTMH_BUSY 0x4 /* busy */
#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
#define SBTMH_FL_MASK 0x0fff0000 /* core-specific flags */
#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
#define SBTMH_GCR 0x20000000 /* gated clock request */
#define SBTMH_BISTF 0x40000000 /* bist failed */
@@ -323,7 +324,6 @@ typedef volatile struct _sbconfig {
#define SB_ILINE100 0x80a /* iline100 core */
#define SB_IPSEC 0x80b /* ipsec core */
#define SB_PCMCIA 0x80d /* pcmcia core */
#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */
#define SB_SOCRAM 0x80e /* internal memory core */
#define SB_MEMC 0x80f /* memc sdram core */
#define SB_EXTIF 0x811 /* external interface core */
@@ -342,11 +342,32 @@ typedef volatile struct _sbconfig {
#define SB_MIMO 0x821 /* MIMO phy core */
#define SB_SRAMC 0x822 /* SRAM controller core */
#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
#define SB_ARM11 0x824 /* ARM 1176 core */
#define SB_ARM7 0x825 /* ARM 7tdmi core */
#define SB_ARM7S 0x825 /* ARM7tdmi-s core */
#define SB_SDIOD 0x829 /* SDIO device core */
#define SB_ARMCM3 0x82a /* ARM Cortex M3 core */
#define SB_OCP 0x830 /* OCP2OCP bridge core */
#define SB_SC 0x831 /* shared common core */
#define SB_AHB 0x832 /* OCP2AHB bridge core */
#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
/* Not an enumeration space register, but common to all cores to
* communicate w/PMU regarding Silicon Backplane clocking.
*/
#define SB_CLK_CTL_ST 0x1e0 /* clock control and status */
/* clk_ctl_st register */
#define CCS_FORCEALP 0x00000001 /* force ALP request */
#define CCS_FORCEHT 0x00000002 /* force HT request */
#define CCS_FORCEILP 0x00000004 /* force ILP request */
#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
#define CCS_HTAVAIL 0x00020000 /* HT is available */
#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
/* Not really related to Silicon Backplane, but a couple of software
* conventions for the use the flash space:
*/
@@ -359,11 +380,11 @@ typedef volatile struct _sbconfig {
#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
#define BISZ_TXTST_IDX 1 /* 1: text start */
#define BISZ_TXTEND_IDX 2 /* 2: text start */
#define BISZ_DATAST_IDX 3 /* 3: text start */
#define BISZ_DATAEND_IDX 4 /* 4: text start */
#define BISZ_BSSST_IDX 5 /* 5: text start */
#define BISZ_BSSEND_IDX 6 /* 6: text start */
#define BISZ_TXTEND_IDX 2 /* 2: text end */
#define BISZ_DATAST_IDX 3 /* 3: data start */
#define BISZ_DATAEND_IDX 4 /* 4: data end */
#define BISZ_BSSST_IDX 5 /* 5: bss start */
#define BISZ_BSSEND_IDX 6 /* 6: bss end */
#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
#endif /* _SBCONFIG_H */

9
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbextif.h
View File

@@ -161,15 +161,6 @@ typedef volatile struct {
#define PA_W3_MASK 0x1f000000 /* waitcount3 */
#define PA_W3_SHIFT 24
/* pcmcia_iowait */
#define PI_W0_MASK 0x3f /* waitcount0 */
#define PI_W1_MASK 0x1f00 /* waitcount1 */
#define PI_W1_SHIFT 8
#define PI_W2_MASK 0x1f0000 /* waitcount2 */
#define PI_W2_SHIFT 16
#define PI_W3_MASK 0x1f000000 /* waitcount3 */
#define PI_W3_SHIFT 24
/* prog_waitcount */
#define PW_W0_MASK 0x0000001f /* waitcount0 */
#define PW_W1_MASK 0x00001f00 /* waitcount1 */

4
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbhndmips.h
View File

@@ -7,7 +7,7 @@
* interface. The core revision is stored in the SB ID register in SB
* configuration space.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -15,7 +15,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sbhndmips.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _sbhndmips_h_

4
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbmemc.h
View File

@@ -1,7 +1,7 @@
/*
* BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sbmemc.h,v 1.6 2006/03/02 12:33:44 honor Exp $
* $Id$
*/
#ifndef _SBMEMC_H

11
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpci.h
View File

@@ -1,7 +1,7 @@
/*
* HND SiliconBackplane PCI core hardware definitions.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _sbpci_h_
@@ -68,8 +68,11 @@ typedef struct sbpciregs {
#define PCI_PARKID_EXT0 0 /* External master 0 */
#define PCI_PARKID_EXT1 1 /* External master 1 */
#define PCI_PARKID_EXT2 2 /* External master 2 */
#define PCI_PARKID_INT 3 /* Internal master */
#define PCI_PARKID_LAST 4 /* Last active master */
#define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */
#define PCI_PARKID_INT 3 /* Internal master (rev < 11) */
#define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */
#define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */
#define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */
/* Interrupt status/mask */
#define PCI_INTA 0x01 /* PCI INTA# is asserted */

53
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcie.h
View File

@@ -1,7 +1,7 @@
/*
* BCM43XX SiliconBackplane PCIE core hardware definitions.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sbpcie.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _SBPCIE_H
@@ -38,11 +38,17 @@
#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
/* different register spaces to access thr'u pcie indirect access */
#define PCIE_CONFIGREGS 1 /* Access to config space */
#define PCIE_PCIEREGS 2 /* Access to pcie registers */
/* SB side: PCIE core and host control registers */
typedef struct sbpcieregs {
uint32 PAD[3];
uint32 biststatus; /* bist Status: 0x00C */
uint32 PAD[6];
uint32 gpiosel; /* PCIE gpio sel: 0x010 */
uint32 gpioouten; /* PCIE gpio outen: 0x14 */
uint32 PAD[4];
uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
uint32 PAD[54];
uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
@@ -58,11 +64,12 @@ typedef struct sbpcieregs {
uint32 mdiocontrol; /* controls the mdio access: 0x128 */
uint32 mdiodata; /* Data to the mdio access: 0x12c */
/* pcie protocol phy/dllp/tlp register access mechanism */
uint32 pcieaddr; /* address of the internal registeru: 0x130 */
uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
/* pcie protocol phy/dllp/tlp register indirect access mechanism */
uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */
uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
uint32 PAD[434];
uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
uint32 PAD[433];
uint16 sprom[36]; /* SPROM shadow Area */
} sbpcieregs_t;
@@ -136,6 +143,7 @@ typedef struct sbpcieregs {
#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
#define PCIE_DLLP_TESTREG 0x14C /* Test */
#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
#define PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
/* PCIE protocol TLP diagnostic registers */
#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
@@ -192,9 +200,38 @@ typedef struct sbpcieregs {
#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
/* SERDES registers */
/* SERDES RX registers */
#define SERDES_RX_CTRL 1 /* Rx cntrl */
#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
#define SERDES_RX_CDR 6 /* CDR */
#define SERDES_RX_CDRBW 7 /* CDR BW */
/* SERDES RX control register */
#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
/* SERDES PLL registers */
#define SERDES_PLL_CTRL 1 /* PLL control reg */
#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
/* SPROM offsets */
#define SRSH_ASPM_OFFSET 4 /* word 4 */
#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */
#define SRSH_CLKREQ_OFFSET 20 /* word 20 */
#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */
/* Linkcontrol reg offset in PCIE Cap */
#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */
#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
#define PCIE_ASPM_ENAB 0x03 /* ASPM L0s & L1 in linkctrl */
#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
/* Status reg PCIE_PLP_STATUSREG */
#define PCIE_PLP_POLARITYINV_STAT 0x10
#endif /* _SBPCIE_H */

44
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcmcia.h
View File

@@ -1,7 +1,7 @@
/*
* BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _SBPCMCIA_H
@@ -75,6 +75,8 @@
#define SROM_DATAH (0x073a / 2)
#define SROM_ADDRL (0x073c / 2)
#define SROM_ADDRH (0x073e / 2)
#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */
#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */
/* Values for srom_cs: */
#define SROM_IDLE 0
@@ -84,16 +86,30 @@
#define SROM_WDS 7
#define SROM_DONE 8
/* Fields in srom_info: */
#define SRI_SZ_MASK 0x03
#define SRI_BLANK 0x04
#define SRI_OTP 0x80
/* CIS stuff */
/* The CIS stops where the FCRs start */
#define CIS_SIZE PCMCIA_FCR
/* CIS tuple length field max */
#define CIS_TUPLE_LEN_MAX 0xff
/* Standard tuples we know about */
#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */
#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
#define CISTPL_FUNCID 0x21 /* Function identification */
#define CISTPL_FUNCE 0x22 /* Function extensions */
#define CISTPL_CFTABLE 0x1b /* Config table entry */
#define CISTPL_END 0xff /* End of the CIS tuple chain */
/* Function identifier provides context for the function extentions tuple */
/* Function extensions for LANs */
@@ -135,7 +151,29 @@
#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
#define HNBU_PAPARMS5G 0x0e /* 5G PA params */
#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */
#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */
#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch,
* 2 bytes, rev 3.
*/
#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch,
* 2 bytes, rev 3.
*/
#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */
#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */
#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */
#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */
#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */
#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */
#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */
#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */
#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */
#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */
#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */
#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8
* plus extra info appended.
*/
/* sbtmstatelow */
#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */

15
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h
View File

@@ -1,7 +1,7 @@
/*
* BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
* $Id$
*/
#ifndef _SBSDRAM_H
@@ -26,16 +26,7 @@ typedef volatile struct sbsdramregs {
uint32 pad2;
} sbsdramregs_t;
/* SDRAM simulation */
#ifdef RAMSZ
#define SDRAMSZ RAMSZ
#else
#define SDRAMSZ (4 * 1024 * 1024)
#endif
extern uchar sdrambuf[SDRAMSZ];
#endif /* _LANGUAGE_ASSEMBLY */
#endif /* !_LANGUAGE_ASSEMBLY */
/* SDRAM initialization control (initcontrol) register bits */
#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */

44
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsocram.h
View File

@@ -1,7 +1,7 @@
/*
* BCM47XX Sonics SiliconBackplane embedded ram core
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,21 +9,21 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _SBSOCRAM_H
#define _SBSOCRAM_H
#define SR_COREINFO 0x00
#define SR_BWALLOC 0x04
#define SR_BISTSTAT 0x0c
#define SR_BANKINDEX 0x10
#define SR_BANKSTBYCTL 0x14
#ifndef _LANGUAGE_ASSEMBLY
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif /* PAD */
/* Memcsocram core registers */
typedef volatile struct sbsocramregs {
uint32 coreinfo;
@@ -32,13 +32,28 @@ typedef volatile struct sbsocramregs {
uint32 biststat;
uint32 bankidx;
uint32 standbyctrl;
uint32 PAD[116];
uint32 pwrctl; /* corerev >= 2 */
} sbsocramregs_t;
#endif
#endif /* _LANGUAGE_ASSEMBLY */
/* Register offsets */
#define SR_COREINFO 0x00
#define SR_BWALLOC 0x04
#define SR_BISTSTAT 0x0c
#define SR_BANKINDEX 0x10
#define SR_BANKSTBYCTL 0x14
#define SR_PWRCTL 0x1e8
/* Coreinfo register */
#define SRCI_PT_MASK 0x30000
#define SRCI_PT_MASK 0x00030000
#define SRCI_PT_SHIFT 16
/* corerev >= 3 */
#define SRCI_LSS_MASK 0x00f00000
#define SRCI_LSS_SHIFT 20
#define SRCI_LRS_MASK 0x0f000000
#define SRCI_LRS_SHIFT 24
/* In corerev 0, the memory size is 2 to the power of the
* base plus 16 plus to the contents of the memsize field plus 1.
@@ -61,4 +76,11 @@ typedef volatile struct sbsocramregs {
#define SRCI_SRBSZ_SHIFT 0
#define SR_BSZ_BASE 14
/* Standby control register */
#define SRSC_SBYOVR_MASK 0x80000000
#define SRSC_SBYOVR_SHIFT 31
#define SRSC_SBYOVRVAL_MASK 0x60000000
#define SRSC_SBYOVRVAL_SHIFT 29
#endif /* _SBSOCRAM_H */

277
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsprom.h Normal file
View File

@@ -0,0 +1,277 @@
/*
* SPROM format definitions for the Broadcom 47xx and 43xx chip family.
*
* $Id$
* Copyright(c) 2002 Broadcom Corporation
*/
#ifndef _SBSPROM_H
#define _SBSPROM_H
#include "typedefs.h"
#include "bcmdevs.h"
/* A word is this many bytes */
#define SRW 2
/* offset into PCI config space for write enable bit */
#define CFG_SROM_WRITABLE_OFFSET 0x88
#define SROM_WRITEABLE 0x10
/* enumeration space consists of N contiguous 4Kbyte core register sets */
#define SBCORES_BASE 0x18000000
#define SBCORES_EACH 0x1000
/* offset from BAR0 for srom space */
#define SROM_BASE 4096
/* number of 2-byte words in srom */
#define SROM_SIZE 64
#define SROM_BYTES (SROM_SIZE * SRW)
#define MAX_FN 4
/* Word 0, Hardware control */
#define SROM_HWCTL 0
#define HW_FUNMSK 0x000f
#define HW_FCLK 0x0200
#define HW_CBM 0x0400
#define HW_PIMSK 0xf000
#define HW_PISHIFT 12
#define HW_4301PISHIFT 13
#define HW_PI4402 0x2
#define HW_FUN4401 0x0001
#define HW_FCLK4402 0x0000
/* Word 1, common-power/boot-rom */
#define SROM_COMMPW 1
/* boot rom present bit */
#define BR_PRESSHIFT 8
/* 15:9 for n; boot rom size is 2^(14 + n) bytes */
#define BR_SIZESHIFT 9
/* Word 2, SubsystemId */
#define SROM_SSID 2
/* Word 3, VendorId */
#define SROM_VID 3
/* Function 0 info, function info length */
#define SROM_FN0 4
#define SROM_FNSZ 8
/* Within each function: */
/* Word 0, deviceID */
#define SRFN_DID 0
/* Words 1-2, ClassCode */
#define SRFN_CCL 1
/* Word 2, D0 Power */
#define SRFN_CCHD0 2
/* Word 3, PME and D1D2D3 power */
#define SRFN_PMED123 3
#define PME_IL 0
#define PME_ENET0 1
#define PME_ENET1 2
#define PME_CODEC 3
#define PME_4402_ENET 0
#define PME_4402_CODEC 1
#define PME_4301_WL 2
#define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME)
/* Word 4, Bar1 enable, pme reports */
#define SRFN_B1PMER 4
#define B1E 1
#define B1SZMSK 0xe
#define B1SZSH 1
#define PMERMSK 0x0ff0
#define PME 0x0010
#define PMERD0 0x0020
#define PMERD1 0x0040
#define PMERD2 0x0080
#define PMERD3H 0x0100
#define PMERD3CA 0x0200
#define PMERD3CV 0x0400
#define IGNCLKRR 0x0800
#define B0LMSK 0xf000
/* Words 4-5, Bar0 Sonics value */
#define SRFN_B0H 5
/* Words 6-7, CIS Pointer */
#define SRFN_CISL 6
#define SRFN_CISH 7
/* Words 36-38: iLine MAC address */
#define SROM_I_MACHI 36
#define SROM_I_MACMID 37
#define SROM_I_MACLO 38
/* Words 36-38: wireless0 MAC address on 43xx */
#define SROM_W0_MACHI 36
#define SROM_W0_MACMID 37
#define SROM_W0_MACLO 38
/* Words 39-41: enet0 MAC address */
#define SROM_E0_MACHI 39
#define SROM_E0_MACMID 40
#define SROM_E0_MACLO 41
/* Words 42-44: enet1 MAC address */
#define SROM_E1_MACHI 42
#define SROM_E1_MACMID 43
#define SROM_E1_MACLO 44
/* Words 42-44: wireless1 MAC address on 4309 */
#define SROM_W1_MACHI 42
#define SROM_W1_MACMID 43
#define SROM_W1_MACLO 44
#define SROM_EPHY 45
/* Word 46: BdRev & Antennas0/1 & ccLock for 430x */
#define SROM_REV_AA_LOCK 46
/* Words 47-51 wl0 PA bx */
#define SROM_WL0_PAB0 47
#define SROM_WL0_PAB1 48
#define SROM_WL0_PAB2 49
#define SROM_WL0_PAB3 50
#define SROM_WL0_PAB4 51
/* Word 52: wl0/wl1 MaxPower */
#define SROM_WL_MAXPWR 52
/* Words 53-55 wl1 PA bx */
#define SROM_WL1_PAB0 53
#define SROM_WL1_PAB1 54
#define SROM_WL1_PAB2 55
/* Woprd 56: itt */
#define SROM_ITT 56
/* Words 59-62: OEM Space */
#define SROM_WL_OEM 59
#define SROM_OEM_SIZE 4
/* Contents for the srom */
#define BU4710_SSID 0x0400
#define VSIM4710_SSID 0x0401
#define QT4710_SSID 0x0402
#define BU4610_SSID 0x0403
#define VSIM4610_SSID 0x0404
#define BU4307_SSID 0x0405
#define BCM94301CB_SSID 0x0406
#define BCM94301MP_SSID 0x0407
#define BCM94307MP_SSID 0x0408
#define AP4307_SSID 0x0409
#define BU4309_SSID 0x040a
#define BCM94309CB_SSID 0x040b
#define BCM94309MP_SSID 0x040c
#define AP4309_SSID 0x040d
#define BU4402_SSID 0x4402
#define CLASS_OTHER 0x8000
#define CLASS_ETHER 0x0000
#define CLASS_NET 0x0002
#define CLASS_COMM 0x0007
#define CLASS_MODEM 0x0300
#define CLASS_MIPS 0x3000
#define CLASS_PROC 0x000b
#define CLASS_FLASH 0x0100
#define CLASS_MEM 0x0005
#define CLASS_SERIALBUS 0x000c
#define CLASS_OHCI 0x0310
/* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */
#define MACHI 0x90
#define MACMID_BU4710I 0x4c17
#define MACMID_BU4710E0 0x4c18
#define MACMID_BU4710E1 0x4c19
#define MACMID_94710R1I 0x4c1a
#define MACMID_94710R1E0 0x4c1b
#define MACMID_94710R1E1 0x4c1c
#define MACMID_94710R4I 0x4c1d
#define MACMID_94710R4E0 0x4c1e
#define MACMID_94710R4E1 0x4c1f
#define MACMID_94710DEVI 0x4c20
#define MACMID_94710DEVE0 0x4c21
#define MACMID_94710DEVE1 0x4c22
#define MACMID_BU4402 0x4c23
#define MACMID_BU4610I 0x4c24
#define MACMID_BU4610E0 0x4c25
#define MACMID_BU4610E1 0x4c26
#define MACMID_BU4307W 0x4c27
#define MACMID_BU4307E 0x4c28
#define MACMID_94301CB 0x4c29
#define MACMID_94301MP 0x4c2a
#define MACMID_94307MPW 0x4c2b
#define MACMID_94307MPE 0x4c2c
#define MACMID_AP4307W 0x4c2d
#define MACMID_AP4307E 0x4c2e
#define MACMID_BU4309W0 0x4c2f
#define MACMID_BU4309W1 0x4c30
#define MACMID_BU4309E 0x4c31
#define MACMID_94309CBW0 0x4c32
#define MACMID_94309CBW1 0x4c33
#define MACMID_94309MPW0 0x4c34
#define MACMID_94309MPW1 0x4c35
#define MACMID_94309MPE 0x4c36
#define MACMID_BU4401 0x4c37
/* Enet phy settings one or two singles or a dual */
/* Bits 4-0 : MII address for enet0 (0x1f for not there */
/* Bits 9-5 : MII address for enet1 (0x1f for not there */
/* Bit 14 : Mdio for enet0 */
/* Bit 15 : Mdio for enet1 */
/* bu4710 with only one phy on enet1 with address 7: */
#define SROM_EPHY_ONE 0x80ff
/* bu4710 with two individual phys, at 6 and 7, */
/* each mdio connected to its own mac: */
#define SROM_EPHY_TWO 0x80e6
/* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */
#define SROM_EPHY_DUAL 0x0001
/* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */
#define SROM_EPHY_R1 0x0010
/* r4 board with a single phy on enet0 at address 5 and a switch */
/* chip on enet1 (speciall case: 0x1e */
#define SROM_EPHY_R4 0x83e5
/* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */
#define SROM_EPHY_INTERNAL 0x0001
/* 4307 uses an external phy at phyaddr 0; want mdcport == coreunit == 0 */
#define SROM_EPHY_ZERO 0x0000
#define SROM_VERS 0x0001
#endif /* _SBSPROM_H */

75
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbutils.h
View File

@@ -2,7 +2,7 @@
* Misc utility routines for accessing chip-specific features
* of Broadcom HNBU SiliconBackplane-based chips.
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -10,14 +10,14 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
* $Id$
*/
#ifndef _sbutils_h_
#define _sbutils_h_
/*
* Datastructure to export all chip specific common variables
* Data structure to export all chip specific common variables
* public (read-only) portion of sbutils handle returned by
* sb_attach()/sb_kattach()
*/
@@ -29,15 +29,22 @@ struct sb_pub {
uint buscorerev; /* buscore rev */
uint buscoreidx; /* buscore index */
int ccrev; /* chip common core rev */
uint32 cccaps; /* chip common capabilities */
int pmurev; /* pmu core rev */
uint32 pmucaps; /* pmu capabilities */
uint boardtype; /* board type */
uint boardvendor; /* board vendor */
uint boardflags; /* board flags */
uint chip; /* chip number */
uint chiprev; /* chip revision */
uint chippkg; /* chip package option */
uint32 chipst; /* chip status */
uint sonicsrev; /* sonics backplane rev */
bool pr42780; /* whether PCIE 42780 WAR applies to this chip */
bool pr32414; /* whether 432414 WAR applis to the chip */
};
typedef const struct sb_pub sb_t;
typedef const struct sb_pub sb_t;
/*
* Many of the routines below take an 'sbh' handle as their first arg.
@@ -48,10 +55,11 @@ typedef const struct sb_pub sb_t;
*/
#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
/* exported externs */
extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
void *sdh, char **vars, uint *varsz);
extern sb_t *sb_kattach(void);
extern sb_t *sb_kattach(osl_t *osh);
extern void sb_detach(sb_t *sbh);
extern uint sb_chip(sb_t *sbh);
extern uint sb_chiprev(sb_t *sbh);
@@ -67,16 +75,20 @@ extern uint sb_buscoretype(sb_t *sbh);
extern uint sb_buscorerev(sb_t *sbh);
extern uint sb_corelist(sb_t *sbh, uint coreid[]);
extern uint sb_coreid(sb_t *sbh);
extern uint sb_flag(sb_t *sbh);
extern uint sb_coreidx(sb_t *sbh);
extern uint sb_coreunit(sb_t *sbh);
extern uint sb_corevendor(sb_t *sbh);
extern uint sb_corerev(sb_t *sbh);
extern void *sb_osh(sb_t *sbh);
extern void sb_setosh(sb_t *sbh, osl_t *osh);
extern uint sb_corereg(sb_t *sbh, uint coreidx, uint regoff, uint mask, uint val);
extern void *sb_coreregs(sb_t *sbh);
extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
extern void sb_coreflags_wo(sb_t *sbh, uint32 mask, uint32 val);
extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
extern bool sb_iscoreup(sb_t *sbh);
extern uint sb_findcoreidx(sb_t *sbh, uint coreid, uint coreunit);
extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
extern int sb_corebist(sb_t *sbh);
@@ -88,6 +100,7 @@ extern void sb_core_tofixup(sb_t *sbh);
extern void sb_core_disable(sb_t *sbh, uint32 bits);
extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
extern uint32 sb_clock(sb_t *sbh);
extern uint32 sb_alp_clock(sb_t *sbh);
extern void sb_pci_setup(sb_t *sbh, uint coremask);
extern void sb_pcmcia_init(sb_t *sbh);
extern void sb_watchdog(sb_t *sbh, uint ticks);
@@ -101,6 +114,17 @@ extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
extern uint32 sb_gpiopull(sb_t *sbh, bool updown, uint32 mask, uint32 val);
extern uint32 sb_gpioevent(sb_t *sbh, uint regtype, uint32 mask, uint32 val);
extern uint32 sb_gpio_int_enable(sb_t *sbh, bool enable);
/* GPIO event handlers */
typedef void (*gpio_handler_t)(uint32 stat, void *arg);
extern void *sb_gpio_handler_register(sb_t *sbh, uint32 event,
bool level, gpio_handler_t cb, void *arg);
extern void sb_gpio_handler_unregister(sb_t *sbh, void* gpioh);
extern void sb_gpio_handler_process(sb_t *sbh);
extern void sb_clkctl_init(sb_t *sbh);
extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
@@ -108,7 +132,9 @@ extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
void *intrsenabled_fn, void *intr_arg);
extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
extern void sb_deregister_intr_callback(sb_t *sbh);
extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to, uint idx);
extern uint16 sb_d11_devid(sb_t *sbh);
extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
uint8 *pciheader);
@@ -119,7 +145,19 @@ extern bool sb_backplane64(sb_t *sbh);
extern void sb_btcgpiowar(sb_t *sbh);
#if defined(BCMDBG_ASSERT)
extern bool sb_taclear(sb_t *sbh);
#endif
#ifdef BCMDBG
extern void sb_dump(sb_t *sbh, struct bcmstrbuf *b);
extern void sb_dumpregs(sb_t *sbh, struct bcmstrbuf *b);
extern void sb_view(sb_t *sbh);
extern void sb_viewall(sb_t *sbh);
extern void sb_clkctl_dump(sb_t *sbh, struct bcmstrbuf *b);
extern uint8 sb_pcieL1plldown(sb_t *sbh);
extern uint32 sb_pcielcreg(sb_t *sbh, uint32 mask, uint32 val);
#endif
extern bool sb_deviceremoved(sb_t *sbh);
extern uint32 sb_socram_size(sb_t *sbh);
@@ -130,6 +168,20 @@ extern uint32 sb_socram_size(sb_t *sbh);
* Return 0 on success, nonzero otherwise.
*/
extern int sb_devpath(sb_t *sbh, char *path, int size);
/* Read variable with prepending the devpath to the name */
extern char *sb_getdevpathvar(sb_t *sbh, const char *name);
extern int sb_getdevpathintvar(sb_t *sbh, const char *name);
extern uint8 sb_pcieclkreq(sb_t *sbh, uint32 mask, uint32 val);
extern void sb_war42780_clkreq(sb_t *sbh, bool clkreq);
extern void sb_pci_sleep(sb_t *sbh);
extern void sb_pci_down(sb_t *sbh);
extern void sb_pci_up(sb_t *sbh);
/* Wake-on-wireless-LAN (WOWL) */
extern bool sb_pci_pmecap(sb_t *sbh);
extern bool sb_pci_pmeclr(sb_t *sbh);
extern void sb_pci_pmeen(sb_t *sbh);
/* clkctl xtal what flags */
#define XTAL 0x1 /* primary crystal oscillator (2050) */
@@ -143,7 +195,16 @@ extern int sb_devpath(sb_t *sbh, char *path, int size);
/* GPIO usage priorities */
#define GPIO_DRV_PRIORITY 0 /* Driver */
#define GPIO_APP_PRIORITY 1 /* Application */
#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
/* GPIO pull up/down */
#define GPIO_PULLUP 0
#define GPIO_PULLDN 1
/* GPIO event regtype */
#define GPIO_REGEVT 0 /* GPIO register event */
#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
/* device path */
#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */

20
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sflash.h
View File

@@ -1,7 +1,7 @@
/*
* Broadcom SiliconBackplane chipcommon serial flash interface
*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -9,7 +9,7 @@
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sflash.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
* $Id$
*/
#ifndef _sflash_h_
@@ -17,6 +17,7 @@
#include <typedefs.h>
#include <sbchipc.h>
#include <sbutils.h>
struct sflash {
uint blocksize; /* Block size */
@@ -26,11 +27,14 @@ struct sflash {
};
/* Utility functions */
extern int sflash_poll(chipcregs_t *cc, uint offset);
extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
extern int sflash_erase(chipcregs_t *cc, uint offset);
extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
extern struct sflash * sflash_init(chipcregs_t *cc);
extern int sflash_poll(sb_t *sbh, chipcregs_t *cc, uint offset);
extern int sflash_read(sb_t *sbh, chipcregs_t *cc,
uint offset, uint len, uchar *buf);
extern int sflash_write(sb_t *sbh, chipcregs_t *cc,
uint offset, uint len, const uchar *buf);
extern int sflash_erase(sb_t *sbh, chipcregs_t *cc, uint offset);
extern int sflash_commit(sb_t *sbh, chipcregs_t *cc,
uint offset, uint len, const uchar *buf);
extern struct sflash *sflash_init(sb_t *sbh, chipcregs_t *cc);
#endif /* _sflash_h_ */

12
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/trxhdr.h
View File

@@ -1,7 +1,7 @@
/*
* TRX image file header format.
*
* Copyright 2005, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
@@ -10,16 +10,16 @@
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id$
*/
*/
#include <typedefs.h>
#define TRX_MAGIC 0x30524448 /* "HDR0" */
#define TRX_VERSION 1
#define TRX_MAX_LEN 0x3A0000
#define TRX_NO_HEADER 1 /* Do not write TRX header */
#define TRX_VERSION 1 /* Version 1 */
#define TRX_MAX_LEN 0x7A0000 /* Max length */
#define TRX_NO_HEADER 1 /* Do not write TRX header */
#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
#define TRX_MAX_OFFSET 3
#define TRX_MAX_OFFSET 3 /* Max number of individual files */
struct trx_header {
uint32 magic; /* "HDR0" */

37
target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/typedefs.h
View File

@@ -1,12 +1,12 @@
/*
* Copyright 2006, Broadcom Corporation
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
* $Id: typedefs.h,v 1.1.1.12 2006/04/08 06:13:40 honor Exp $
* $Id$
*/
#ifndef _TYPEDEFS_H_
@@ -69,10 +69,13 @@ typedef unsigned char bool; /* consistent w/BOOL */
#endif /* ! __cplusplus */
/* use the Windows ULONG_PTR type when compiling for 64 bit */
#if defined(_WIN64)
#if defined(_WIN64) && !defined(EFI)
#include <basetsd.h>
#define TYPEDEF_UINTPTR
typedef ULONG_PTR uintptr;
typedef ULONG_PTR uintptr;
#elif defined(__x86_64__)
#define TYPEDEF_UINTPTR
typedef unsigned long long int uintptr;
#endif
@@ -80,6 +83,10 @@ typedef ULONG_PTR uintptr;
#define _NEED_SIZE_T_
#endif
#if defined(EFI) && !defined(_WIN64)
#define _NEED_SIZE_T_
#endif
#if defined(_NEED_SIZE_T_)
typedef long unsigned int size_t;
#endif
@@ -104,14 +111,20 @@ typedef unsigned __int64 uint64;
#endif
#if defined(linux)
#ifdef linux
#define TYPEDEF_UINT
#define TYPEDEF_USHORT
#define TYPEDEF_ULONG
#endif
#ifdef __KERNEL__
#include <linux/version.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19))
#define TYPEDEF_BOOL
#endif /* >= 2.6.19 */
#endif /* __KERNEL__ */
#endif /* linux */
#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
!defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__)
!defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__) && !defined(__IOPOS__)
#define TYPEDEF_UINT
#define TYPEDEF_USHORT
#endif
@@ -137,7 +150,7 @@ typedef unsigned __int64 uint64;
#endif /* __ICL */
#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
!defined(__DJGPP__)
!defined(__DJGPP__) && !defined(__IOPOS__)
/* pick up ushort & uint from standard types.h */
#if defined(linux) && defined(__KERNEL__)
@@ -150,7 +163,7 @@ typedef unsigned __int64 uint64;
#endif
#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
#endif
#if defined(MACOSX)
@@ -320,7 +333,7 @@ typedef float64 float_t;
#define INLINE __inline
#elif __GNUC__
#elif defined(__GNUC__)
#define INLINE __inline__
@@ -353,8 +366,8 @@ typedef float64 float_t;
#endif /* USE_TYPEDEF_DEFAULTS */
/*
* Including the bcmdefs.h here, to make sure everyone including typedefs.h
* gets this automatically
* Including the bcmdefs.h here, to make sure everyone including typedefs.h
* gets this automatically
*/
#include "bcmdefs.h"

54
target/linux/brcm-2.4/files/arch/mips/bcm947xx/nvram.c
View File

@@ -15,7 +15,6 @@
#include <osl.h>
#include <bcmendian.h>
#include <bcmnvram.h>
#include <bcmutils.h>
#include <sbsdram.h>
extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
@@ -244,10 +243,10 @@ BCMINITFN(_nvram_commit)(struct nvram_header *header)
header->config_refresh |= SDRAM_REFRESH << 16;
header->config_ncdl = 0;
} else {
header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
header->crc_ver_init |= (simple_strtoul(init, NULL, 0) & 0xffff) << 16;
header->config_refresh = simple_strtoul(config, NULL, 0) & 0xffff;
header->config_refresh |= (simple_strtoul(refresh, NULL, 0) & 0xffff) << 16;
header->config_ncdl = simple_strtoul(ncdl, NULL, 0);
}
/* Clear data area */
@@ -276,7 +275,7 @@ BCMINITFN(_nvram_commit)(struct nvram_header *header)
tmp.crc_ver_init = htol32(header->crc_ver_init);
tmp.config_refresh = htol32(header->config_refresh);
tmp.config_ncdl = htol32(header->config_ncdl);
crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, 0xff);
/* Continue CRC8 over data bytes */
crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
@@ -313,3 +312,46 @@ BCMINITFN(_nvram_exit)(void)
{
BCMINIT(nvram_free)();
}
/*
* Search the name=value vars for a specific one and return its value.
* Returns NULL if not found.
*/
char*
getvar(char *vars, const char *name)
{
char *s;
int len;
len = strlen(name);
/* first look in vars[] */
for (s = vars; s && *s;) {
/* CSTYLED */
if ((memcmp(s, name, len) == 0) && (s[len] == '='))
return (&s[len+1]);
while (*s++)
;
}
/* then query nvram */
return (nvram_get(name));
}
/*
* Search the vars for a specific one and return its value as
* an integer. Returns 0 if not found.
*/
int
getintvar(char *vars, const char *name)
{
char *val;
if ((val = getvar(vars, name)) == NULL)
return (0);
return (simple_strtoul(val, NULL, 0));
}

12
target/linux/brcm-2.4/files/arch/mips/bcm947xx/nvram_linux.c
View File

@@ -33,7 +33,6 @@
#include <osl.h>
#include <bcmendian.h>
#include <bcmnvram.h>
#include <bcmutils.h>
#include <sbconfig.h>
#include <sbchipc.h>
#include <sbutils.h>
@@ -53,6 +52,9 @@ static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
extern void *bcm947xx_sbh;
extern spinlock_t bcm947xx_sbh_lock;
static int cfe_env;
extern char *cfe_env_get(char *nv_buf, const char *name);
/* Convenience */
#define sbh bcm947xx_sbh
#define sbh_lock bcm947xx_sbh_lock
@@ -72,14 +74,14 @@ early_nvram_init(void)
if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
base = KSEG1ADDR(SB_FLASH2);
switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
switch (readl(&cc->capabilities) & CC_CAP_FLASH_MASK) {
case PFLASH:
lim = SB_FLASH2_SZ;
break;
case SFLASH_ST:
case SFLASH_AT:
if ((info = sflash_init(cc)) == NULL)
if ((info = sflash_init(sbh,cc)) == NULL)
return;
lim = info->size;
break;
@@ -105,6 +107,7 @@ early_nvram_init(void)
break;
*dst++ = *src++;
}
cfe_env = 1;
return;
}
@@ -154,6 +157,9 @@ early_nvram_get(const char *name)
if (!nvram_buf[0])
early_nvram_init();
if (cfe_env)
return cfe_env_get(nvram_buf, name);
/* Look for name=value and return value */
var = &nvram_buf[sizeof(struct nvram_header)];
end = nvram_buf + sizeof(nvram_buf) - 2;

22
target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c
View File

@@ -25,7 +25,6 @@
#include <typedefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <sbconfig.h>
#include <sbutils.h>
#include <hndpci.h>
@@ -134,7 +133,7 @@ pcibios_init(void)
{
ulong flags;
if (!(sbh = sb_kattach()))
if (!(sbh = sb_kattach(SB_OSH)))
panic("sb_kattach failed");
spin_lock_init(&sbh_lock);
@@ -312,6 +311,25 @@ pcibios_enable_device(struct pci_dev *dev, int mask)
writel(0x7FF, (ulong)regs + 0x200);
udelay(1);
}
/* PRxxxx: War for 5354 failures. */
if (sb_corerev(sbh) == 1) {
uint32 tmp;
/* Change Flush control reg */
tmp = readl((uintptr)regs + 0x400);
tmp &= ~8;
writel(tmp, (uintptr)regs + 0x400);
tmp = readl((uintptr)regs + 0x400);
printk("USB20H fcr: 0x%x\n", tmp);
/* Change Shim control reg */
tmp = readl((uintptr)regs + 0x304);
tmp &= ~0x100;
writel(tmp, (uintptr)regs + 0x304);
tmp = readl((uintptr)regs + 0x304);
printk("USB20H shim cr: 0x%x\n", tmp);
}
} else
sb_core_reset(sbh, 0, 0);

849
target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbmips.c
View File

File diff suppressed because it is too large Load Diff

267
target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbpci.c
View File

@@ -17,7 +17,6 @@
#include <pcicfg.h>
#include <bcmdevs.h>
#include <sbconfig.h>
#include <bcmutils.h>
#include <sbutils.h>
#include <sbpci.h>
#include <bcmendian.h>
@@ -31,7 +30,7 @@
#define PCI_MSG(args) printf args
#else
#define PCI_MSG(args)
#endif /* BCMDBG_PCI */
#endif /* BCMDBG_PCI */
/* Can free sbpci_init() memory after boot */
#ifndef linux
@@ -40,11 +39,11 @@
/* Emulated configuration space */
typedef struct {
int n;
uint size0;
uint size1;
uint size2;
uint size3;
int n;
uint size0;
uint size1;
uint size2;
uint size3;
} sb_bar_cfg_t;
static pci_config_regs sb_config_regs[SB_MAXCORES];
static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
@@ -86,10 +85,9 @@ static uint8 pci_hbslot = 0;
*/
/* Assume one-hot slot wiring */
#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
static uint32
config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
static uint32 config_cmd(sb_t * sbh, uint bus, uint dev, uint func, uint off)
{
uint coreidx;
sbpciregs_t *regs;
@@ -112,21 +110,21 @@ config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
uint32 win;
/* Slide the PCI window to the appropriate slot */
win = (SBTOPCI_CFG0 | ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
win =
(SBTOPCI_CFG0 |
((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
W_REG(osh, &regs->sbtopci1, win);
addr = SB_PCI_CFG |
((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
(func << PCICFG_FUN_SHIFT) |
(off & ~3);
((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
(func << PCICFG_FUN_SHIFT) | (off & ~3);
}
} else {
/* Type 1 transaction */
W_REG(osh, &regs->sbtopci1, SBTOPCI_CFG1);
addr = SB_PCI_CFG |
(bus << PCICFG_BUS_SHIFT) |
(dev << PCICFG_SLOT_SHIFT) |
(func << PCICFG_FUN_SHIFT) |
(off & ~3);
(bus << PCICFG_BUS_SHIFT) |
(dev << PCICFG_SLOT_SHIFT) |
(func << PCICFG_FUN_SHIFT) | (off & ~3);
}
sb_setcoreidx(sbh, coreidx);
@@ -145,8 +143,8 @@ config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
* the register address where value in 'val' is read.
*/
static bool
sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
uint32 **addr, uint32 *val)
sb_pcihb_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
uint32 ** addr, uint32 * val)
{
sbpciregs_t *regs;
osl_t *osh;
@@ -162,9 +160,9 @@ sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
/* read pci config when core rev >= 8 */
coreidx = sb_coreidx(sbh);
regs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
*addr = (uint32 *)&regs->pcicfg[func][off >> 2];
*addr = (uint32 *) & regs->pcicfg[func][off >> 2];
*val = R_REG(osh, *addr);
ret = TRUE;
}
@@ -174,30 +172,30 @@ sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
}
int
extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
extpci_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
void *buf, int len)
{
uint32 addr = 0, *reg = NULL, val;
int ret = 0;
/*
* Set value to -1 when:
* flag 'pci_disabled' is true;
* value of 'addr' is zero;
* REG_MAP() fails;
* BUSPROBE() fails;
* flag 'pci_disabled' is true;
* value of 'addr' is zero;
* REG_MAP() fails;
* BUSPROBE() fails;
*/
if (pci_disabled)
val = 0xffffffff;
else if (bus == 1 && dev == pci_hbslot && func == 0 &&
sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
;
sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val)) ;
else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
((reg = (uint32 *)REG_MAP(addr, len)) == 0) ||
(BUSPROBE(val, reg) != 0))
((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
(BUSPROBE(val, reg) != 0))
val = 0xffffffff;
PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
__FUNCTION__, val, reg, addr, len, off, buf));
__FUNCTION__, val, reg, addr, len, off, buf));
val >>= 8 * (off & 3);
if (len == 4)
@@ -216,7 +214,8 @@ extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf
}
int
extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
extpci_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
void *buf, int len)
{
osl_t *osh;
uint32 addr = 0, *reg = NULL, val;
@@ -226,19 +225,18 @@ extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *bu
/*
* Ignore write attempt when:
* flag 'pci_disabled' is true;
* value of 'addr' is zero;
* REG_MAP() fails;
* BUSPROBE() fails;
* flag 'pci_disabled' is true;
* value of 'addr' is zero;
* REG_MAP() fails;
* BUSPROBE() fails;
*/
if (pci_disabled)
return 0;
else if (bus == 1 && dev == pci_hbslot && func == 0 &&
sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
;
sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val)) ;
else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
(BUSPROBE(val, reg) != 0))
((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
(BUSPROBE(val, reg) != 0))
goto done;
if (len == 4)
@@ -258,7 +256,7 @@ extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *bu
W_REG(osh, reg, val);
done:
done:
if (reg && addr)
REG_UNMAP(reg);
@@ -287,8 +285,8 @@ done:
/* Sync the emulation registers and the real PCI config registers. */
static void
sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
uint off, uint len)
sb_pcid_read_config(sb_t * sbh, uint coreidx, sb_pci_cfg_t * cfg,
uint off, uint len)
{
osl_t *osh;
uint oldidx;
@@ -308,21 +306,23 @@ sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
sb_setcoreidx(sbh, coreidx);
if (sb_iscoreup(sbh)) {
if (len == 4)
*(uint32 *)((ulong)cfg->emu + off) =
htol32(R_REG(osh, (uint32 *)((ulong)cfg->pci + off)));
*(uint32 *) ((ulong) cfg->emu + off) =
htol32(R_REG
(osh, (uint32 *) ((ulong) cfg->pci + off)));
else if (len == 2)
*(uint16 *)((ulong)cfg->emu + off) =
htol16(R_REG(osh, (uint16 *)((ulong)cfg->pci + off)));
*(uint16 *) ((ulong) cfg->emu + off) =
htol16(R_REG
(osh, (uint16 *) ((ulong) cfg->pci + off)));
else if (len == 1)
*(uint8 *)((ulong)cfg->emu + off) =
R_REG(osh, (uint8 *)((ulong)cfg->pci + off));
*(uint8 *) ((ulong) cfg->emu + off) =
R_REG(osh, (uint8 *) ((ulong) cfg->pci + off));
}
sb_setcoreidx(sbh, oldidx);
}
static void
sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
uint off, uint len)
sb_pcid_write_config(sb_t * sbh, uint coreidx, sb_pci_cfg_t * cfg,
uint off, uint len)
{
osl_t *osh;
uint oldidx;
@@ -342,14 +342,14 @@ sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
sb_setcoreidx(sbh, coreidx);
if (sb_iscoreup(sbh)) {
if (len == 4)
W_REG(osh, (uint32 *)((ulong)cfg->pci + off),
ltoh32(*(uint32 *)((ulong)cfg->emu + off)));
W_REG(osh, (uint32 *) ((ulong) cfg->pci + off),
ltoh32(*(uint32 *) ((ulong) cfg->emu + off)));
else if (len == 2)
W_REG(osh, (uint16 *)((ulong)cfg->pci + off),
ltoh16(*(uint16 *)((ulong)cfg->emu + off)));
W_REG(osh, (uint16 *) ((ulong) cfg->pci + off),
ltoh16(*(uint16 *) ((ulong) cfg->emu + off)));
else if (len == 1)
W_REG(osh, (uint8 *)((ulong)cfg->pci + off),
*(uint8 *)((ulong)cfg->emu + off));
W_REG(osh, (uint8 *) ((ulong) cfg->pci + off),
*(uint8 *) ((ulong) cfg->emu + off));
}
sb_setcoreidx(sbh, oldidx);
}
@@ -358,16 +358,18 @@ sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
* Functions for accessing translated SB configuration space
*/
static int
sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
sb_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, void *buf,
int len)
{
pci_config_regs *cfg;
if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
if (dev >= SB_MAXCORES || func >= MAXFUNCS
|| (off + len) > sizeof(pci_config_regs))
return -1;
cfg = sb_pci_cfg[dev][func].emu;
ASSERT(ISALIGNED(off, len));
ASSERT(ISALIGNED((uintptr)buf, len));
ASSERT(ISALIGNED((uintptr) buf, len));
/* use special config space if the device does not exist */
if (!cfg)
@@ -377,11 +379,11 @@ sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, in
sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
if (len == 4)
*((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
*((uint32 *) buf) = ltoh32(*((uint32 *) ((ulong) cfg + off)));
else if (len == 2)
*((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
*((uint16 *) buf) = ltoh16(*((uint16 *) ((ulong) cfg + off)));
else if (len == 1)
*((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
*((uint8 *) buf) = *((uint8 *) ((ulong) cfg + off));
else
return -1;
@@ -389,7 +391,8 @@ sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, in
}
static int
sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
sb_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, void *buf,
int len)
{
uint coreidx;
void *regs;
@@ -397,14 +400,15 @@ sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, i
osl_t *osh;
sb_bar_cfg_t *bar;
if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
if (dev >= SB_MAXCORES || func >= MAXFUNCS
|| (off + len) > sizeof(pci_config_regs))
return -1;
cfg = sb_pci_cfg[dev][func].emu;
if (!cfg)
return -1;
ASSERT(ISALIGNED(off, len));
ASSERT(ISALIGNED((uintptr)buf, len));
ASSERT(ISALIGNED((uintptr) buf, len));
osh = sb_osh(sbh);
@@ -418,33 +422,37 @@ sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, i
/* Highest numbered address match register */
if (off == OFFSETOF(pci_config_regs, base[0]))
cfg->base[0] = ~(bar->size0 - 1);
else if (off == OFFSETOF(pci_config_regs, base[1]) && bar->n >= 1)
else if (off == OFFSETOF(pci_config_regs, base[1])
&& bar->n >= 1)
cfg->base[1] = ~(bar->size1 - 1);
else if (off == OFFSETOF(pci_config_regs, base[2]) && bar->n >= 2)
else if (off == OFFSETOF(pci_config_regs, base[2])
&& bar->n >= 2)
cfg->base[2] = ~(bar->size2 - 1);
else if (off == OFFSETOF(pci_config_regs, base[3]) && bar->n >= 3)
else if (off == OFFSETOF(pci_config_regs, base[3])
&& bar->n >= 3)
cfg->base[3] = ~(bar->size3 - 1);
}
sb_setcoreidx(sbh, coreidx);
}
else if (len == 4)
*((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
} else if (len == 4)
*((uint32 *) ((ulong) cfg + off)) = htol32(*((uint32 *) buf));
else if (len == 2)
*((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
*((uint16 *) ((ulong) cfg + off)) = htol16(*((uint16 *) buf));
else if (len == 1)
*((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
*((uint8 *) ((ulong) cfg + off)) = *((uint8 *) buf);
else
return -1;
/* sync emulation with real PCI config if necessary */
if (sb_pci_cfg[dev][func].pci)
sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off,
len);
return 0;
}
int
sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
sbpci_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
void *buf, int len)
{
if (bus == 0)
return sb_read_config(sbh, bus, dev, func, off, buf, len);
@@ -453,7 +461,8 @@ sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
}
int
sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
sbpci_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
void *buf, int len)
{
if (bus == 0)
return sb_write_config(sbh, bus, dev, func, off, buf, len);
@@ -461,8 +470,7 @@ sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf
return extpci_write_config(sbh, bus, dev, func, off, buf, len);
}
void
sbpci_ban(uint16 core)
void sbpci_ban(uint16 core)
{
if (pci_banned < ARRAYSIZE(pci_ban))
pci_ban[pci_banned++] = core;
@@ -473,8 +481,7 @@ sbpci_ban(uint16 core)
* Otherwise return -1 to indicate there is no PCI core and return 1
* to indicate PCI core is disabled.
*/
int __init
sbpci_init_pci(sb_t *sbh)
int __init sbpci_init_pci(sb_t * sbh)
{
uint chip, chiprev, chippkg, host;
uint32 boardflags;
@@ -499,8 +506,8 @@ sbpci_init_pci(sb_t *sbh)
if ((chip == 0x4310) && (chiprev == 0))
pci_disabled = TRUE;
sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
sb = (sbconfig_t *) ((ulong) pci + SBCONFIGOFF);
boardflags = (uint32) getintvar(NULL, "boardflags");
@@ -511,8 +518,7 @@ sbpci_init_pci(sb_t *sbh)
*/
if (((chip == BCM4712_CHIP_ID) &&
((chippkg == BCM4712SMALL_PKG_ID) ||
(chippkg == BCM4712MID_PKG_ID))) ||
(boardflags & BFL_NOPCI))
(chippkg == BCM4712MID_PKG_ID))) || (boardflags & BFL_NOPCI))
pci_disabled = TRUE;
/* Enable the core */
@@ -550,13 +556,13 @@ sbpci_init_pci(sb_t *sbh)
}
/* Reset the external PCI bus and enable the clock */
W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
OSL_DELAY(150); /* delay > 100 us */
W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
OSL_DELAY(150); /* delay > 100 us */
W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
/* Use internal arbiter and park REQ/GRNT at external master 0 */
W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
OSL_DELAY(1); /* delay 1 us */
OSL_DELAY(1); /* delay 1 us */
if (sb_corerev(sbh) >= 8) {
val = getintvar(NULL, "parkid");
ASSERT(val <= PCI_PARKID_LAST);
@@ -571,7 +577,8 @@ sbpci_init_pci(sb_t *sbh)
/* GPIO 1 resets the CardBus device on bcm94710ap */
sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
W_REG(osh, &pci->sprom[0], R_REG(osh, &pci->sprom[0]) | 0x400);
W_REG(osh, &pci->sprom[0],
R_REG(osh, &pci->sprom[0]) | 0x400);
}
/* 64 MB I/O access window */
@@ -583,13 +590,14 @@ sbpci_init_pci(sb_t *sbh)
/* Host bridge slot # nvram overwrite */
if ((hbslot = nvram_get("pcihbslot"))) {
pci_hbslot = bcm_strtoul(hbslot, NULL, 0);
pci_hbslot = simple_strtoul(hbslot, NULL, 0);
ASSERT(pci_hbslot < PCI_MAX_DEVICES);
}
/* Enable PCI bridge BAR0 prefetch and burst */
val = 6;
sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val,
sizeof(val));
/* Enable PCI interrupts */
W_REG(osh, &pci->intmask, PCI_INTA);
@@ -602,7 +610,8 @@ sbpci_init_pci(sb_t *sbh)
* Get the PCI region address and size information.
*/
static void __init
sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar)
sbpci_init_regions(sb_t * sbh, uint func, pci_config_regs * cfg,
sb_bar_cfg_t * bar)
{
osl_t *osh;
uint16 coreid;
@@ -610,26 +619,26 @@ sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar
sbconfig_t *sb;
uint32 base;
osh = sb_osh(sbh);
coreid = sb_coreid(sbh);
regs = sb_coreregs(sbh);
sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
osh = sb_osh(sbh);
coreid = sb_coreid(sbh);
regs = sb_coreregs(sbh);
sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF);
switch (coreid) {
case SB_USB20H:
base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
cfg->base[1] = 0;
cfg->base[2] = 0;
cfg->base[3] = 0;
cfg->base[4] = 0;
cfg->base[5] = 0;
bar->n = 1;
bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
bar->size1 = 0;
bar->size2 = 0;
bar->size3 = 0;
bar->n = 1;
bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
bar->size1 = 0;
bar->size2 = 0;
bar->size3 = 0;
break;
default:
cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
@@ -638,11 +647,13 @@ sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar
cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
cfg->base[4] = 0;
cfg->base[5] = 0;
bar->n = (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
bar->n =
(R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >>
SBIDL_AR_SHIFT;
bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
break;
}
}
@@ -651,8 +662,7 @@ sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar
* Construct PCI config spaces for SB cores so that they
* can be accessed as if they were PCI devices.
*/
static void __init
sbpci_init_cores(sb_t *sbh)
static void __init sbpci_init_cores(sb_t * sbh)
{
uint chiprev, coreidx, i;
sbconfig_t *sb;
@@ -679,11 +689,11 @@ sbpci_init_cores(sb_t *sbh)
memset(&sb_pci_null, -1, sizeof(sb_pci_null));
cfg = sb_config_regs;
bar = sb_bar_cfg;
for (dev = 0; dev < SB_MAXCORES; dev ++) {
for (dev = 0; dev < SB_MAXCORES; dev++) {
/* Check if the core exists */
if (!(regs = sb_setcoreidx(sbh, dev)))
continue;
sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF);
/* Check if this core is banned */
coreid = sb_coreid(sbh);
@@ -701,8 +711,9 @@ sbpci_init_cores(sb_t *sbh)
}
/* Convert core id to pci id */
if (sb_corepciid(sbh, func, &vendor, &device, &class, &subclass,
&progif, &header))
if (sb_corepciid
(sbh, func, &vendor, &device, &class, &subclass,
&progif, &header))
continue;
/*
@@ -712,13 +723,16 @@ sbpci_init_cores(sb_t *sbh)
*/
switch (device) {
case BCM47XX_GIGETH_ID:
pci = (pci_config_regs *)((uint32)regs + 0x800);
pci =
(pci_config_regs *) ((uint32) regs + 0x800);
break;
case BCM47XX_SATAXOR_ID:
pci = (pci_config_regs *)((uint32)regs + 0x400);
pci =
(pci_config_regs *) ((uint32) regs + 0x400);
break;
case BCM47XX_ATA100_ID:
pci = (pci_config_regs *)((uint32)regs + 0x800);
pci =
(pci_config_regs *) ((uint32) regs + 0x800);
break;
default:
pci = NULL;
@@ -734,22 +748,23 @@ sbpci_init_cores(sb_t *sbh)
cfg->header_type = header;
sbpci_init_regions(sbh, func, cfg, bar);
/* Save core interrupt flag */
cfg->int_pin = R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
cfg->int_pin =
R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
/* Save core interrupt assignment */
cfg->int_line = sb_irq(sbh);
/* Indicate there is no SROM */
*((uint32 *) &cfg->sprom_control) = 0xffffffff;
*((uint32 *) & cfg->sprom_control) = 0xffffffff;
/* Point to the PCI config spaces */
sb_pci_cfg[dev][func].emu = cfg;
sb_pci_cfg[dev][func].pci = pci;
sb_pci_cfg[dev][func].bar = bar;
cfg ++;
bar ++;
cfg++;
bar++;
}
}
done:
done:
sb_setcoreidx(sbh, coreidx);
}
@@ -758,11 +773,9 @@ done:
* Must propagate sbpci_init_pci() return value to the caller to let
* them know the PCI core initialization status.
*/
int __init
sbpci_init(sb_t *sbh)
int __init sbpci_init(sb_t * sbh)
{
int status = sbpci_init_pci(sbh);
sbpci_init_cores(sbh);
return status;
}

2771
target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbutils.c
View File

File diff suppressed because it is too large Load Diff

3
target/linux/brcm-2.4/files/arch/mips/bcm947xx/setup.c
View File

@@ -48,7 +48,6 @@
#include <typedefs.h>
#include <osl.h>
#include <sbutils.h>
#include <bcmutils.h>
#include <bcmnvram.h>
#include <sbhndmips.h>
#include <hndmips.h>
@@ -170,7 +169,7 @@ brcm_setup(void)
char *value;
/* Get global SB handle */
sbh = sb_kattach();
sbh = sb_kattach(SB_OSH);
/* Initialize clocks and interrupts */
sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);

422
target/linux/brcm-2.4/files/arch/mips/bcm947xx/sflash.c
View File

@@ -1,422 +0,0 @@
/*
* Broadcom SiliconBackplane chipcommon serial flash interface
*
* Copyright 2006, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
*
* $Id: sflash.c,v 1.1.1.13 2006/02/27 03:43:16 honor Exp $
*/
#include <osl.h>
#include <typedefs.h>
#include <sbconfig.h>
#include <sbchipc.h>
#include <mipsinc.h>
#include <bcmutils.h>
#include <bcmdevs.h>
#include <sflash.h>
/* Private global state */
static struct sflash sflash;
/* Issue a serial flash command */
static INLINE void
sflash_cmd(chipcregs_t *cc, uint opcode)
{
W_REG(NULL, &cc->flashcontrol, SFLASH_START | opcode);
while (R_REG(NULL, &cc->flashcontrol) & SFLASH_BUSY);
}
/* Initialize serial flash access */
struct sflash *
sflash_init(chipcregs_t *cc)
{
uint32 id, id2;
bzero(&sflash, sizeof(sflash));
sflash.type = R_REG(NULL, &cc->capabilities) & CAP_FLASH_MASK;
switch (sflash.type) {
case SFLASH_ST:
/* Probe for ST chips */
sflash_cmd(cc, SFLASH_ST_DP);
sflash_cmd(cc, SFLASH_ST_RES);
id = R_REG(NULL, &cc->flashdata);
switch (id) {
case 0x11:
/* ST M25P20 2 Mbit Serial Flash */
sflash.blocksize = 64 * 1024;
sflash.numblocks = 4;
break;
case 0x12:
/* ST M25P40 4 Mbit Serial Flash */
sflash.blocksize = 64 * 1024;
sflash.numblocks = 8;
break;
case 0x13:
/* ST M25P80 8 Mbit Serial Flash */
sflash.blocksize = 64 * 1024;
sflash.numblocks = 16;
break;
case 0x14:
/* ST M25P16 16 Mbit Serial Flash */
sflash.blocksize = 64 * 1024;
sflash.numblocks = 32;
break;
case 0x15:
/* ST M25P32 32 Mbit Serial Flash */
sflash.blocksize = 64 * 1024;
sflash.numblocks = 64;
break;
case 0x16:
/* ST M25P64 64 Mbit Serial Flash */
sflash.blocksize = 64 * 1024;
sflash.numblocks = 128;
break;
case 0xbf:
W_REG(NULL, &cc->flashaddress, 1);
sflash_cmd(cc, SFLASH_ST_RES);
id2 = R_REG(NULL, &cc->flashdata);
if (id2 == 0x44) {
/* SST M25VF80 4 Mbit Serial Flash */
sflash.blocksize = 64 * 1024;
sflash.numblocks = 8;
}
break;
}
break;
case SFLASH_AT:
/* Probe for Atmel chips */
sflash_cmd(cc, SFLASH_AT_STATUS);
id = R_REG(NULL, &cc->flashdata) & 0x3c;
switch (id) {
case 0xc:
/* Atmel AT45DB011 1Mbit Serial Flash */
sflash.blocksize = 256;
sflash.numblocks = 512;
break;
case 0x14:
/* Atmel AT45DB021 2Mbit Serial Flash */
sflash.blocksize = 256;
sflash.numblocks = 1024;
break;
case 0x1c:
/* Atmel AT45DB041 4Mbit Serial Flash */
sflash.blocksize = 256;
sflash.numblocks = 2048;
break;
case 0x24:
/* Atmel AT45DB081 8Mbit Serial Flash */
sflash.blocksize = 256;
sflash.numblocks = 4096;
break;
case 0x2c:
/* Atmel AT45DB161 16Mbit Serial Flash */
sflash.blocksize = 512;
sflash.numblocks = 4096;
break;
case 0x34:
/* Atmel AT45DB321 32Mbit Serial Flash */
sflash.blocksize = 512;
sflash.numblocks = 8192;
break;
case 0x3c:
/* Atmel AT45DB642 64Mbit Serial Flash */
sflash.blocksize = 1024;
sflash.numblocks = 8192;
break;
}
break;
}
sflash.size = sflash.blocksize * sflash.numblocks;
return sflash.size ? &sflash : NULL;
}
/* Read len bytes starting at offset into buf. Returns number of bytes read. */
int
sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
{
int cnt;
uint32 *from, *to;
if (!len)
return 0;
if ((offset + len) > sflash.size)
return -22;
if ((len >= 4) && (offset & 3))
cnt = 4 - (offset & 3);
else if ((len >= 4) && ((uint32)buf & 3))
cnt = 4 - ((uint32)buf & 3);
else
cnt = len;
from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
to = (uint32 *)buf;
if (cnt < 4) {
bcopy(from, to, cnt);
return cnt;
}
while (cnt >= 4) {
*to++ = *from++;
cnt -= 4;
}
return (len - cnt);
}
/* Poll for command completion. Returns zero when complete. */
int
sflash_poll(chipcregs_t *cc, uint offset)
{
if (offset >= sflash.size)
return -22;
switch (sflash.type) {
case SFLASH_ST:
/* Check for ST Write In Progress bit */
sflash_cmd(cc, SFLASH_ST_RDSR);
return R_REG(NULL, &cc->flashdata) & SFLASH_ST_WIP;
case SFLASH_AT:
/* Check for Atmel Ready bit */
sflash_cmd(cc, SFLASH_AT_STATUS);
return !(R_REG(NULL, &cc->flashdata) & SFLASH_AT_READY);
}
return 0;
}
/* Write len bytes starting at offset into buf. Returns number of bytes
* written. Caller should poll for completion.
*/
int
sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
{
struct sflash *sfl;
int ret = 0;
bool is4712b0;
uint32 page, byte, mask;
if (!len)
return 0;
if ((offset + len) > sflash.size)
return -22;
sfl = &sflash;
switch (sfl->type) {
case SFLASH_ST:
mask = R_REG(NULL, &cc->chipid);
is4712b0 = (((mask & CID_ID_MASK) == BCM4712_CHIP_ID) &&
((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
/* Enable writes */
sflash_cmd(cc, SFLASH_ST_WREN);
if (is4712b0) {
mask = 1 << 14;
W_REG(NULL, &cc->flashaddress, offset);
W_REG(NULL, &cc->flashdata, *buf++);
/* Set chip select */
OR_REG(NULL, &cc->gpioout, mask);
/* Issue a page program with the first byte */
sflash_cmd(cc, SFLASH_ST_PP);
ret = 1;
offset++;
len--;
while (len > 0) {
if ((offset & 255) == 0) {
/* Page boundary, drop cs and return */
AND_REG(NULL, &cc->gpioout, ~mask);
if (!sflash_poll(cc, offset)) {
/* Flash rejected command */
return -11;
}
return ret;
} else {
/* Write single byte */
sflash_cmd(cc, *buf++);
}
ret++;
offset++;
len--;
}
/* All done, drop cs if needed */
if ((offset & 255) != 1) {
/* Drop cs */
AND_REG(NULL, &cc->gpioout, ~mask);
if (!sflash_poll(cc, offset)) {
/* Flash rejected command */
return -12;
}
}
} else {
ret = 1;
W_REG(NULL, &cc->flashaddress, offset);
W_REG(NULL, &cc->flashdata, *buf);
/* Page program */
sflash_cmd(cc, SFLASH_ST_PP);
}
break;
case SFLASH_AT:
mask = sfl->blocksize - 1;
page = (offset & ~mask) << 1;
byte = offset & mask;
/* Read main memory page into buffer 1 */
if (byte || (len < sfl->blocksize)) {
W_REG(NULL, &cc->flashaddress, page);
sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
/* 250 us for AT45DB321B */
SPINWAIT(sflash_poll(cc, offset), 1000);
ASSERT(!sflash_poll(cc, offset));
}
/* Write into buffer 1 */
for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
W_REG(NULL, &cc->flashaddress, byte++);
W_REG(NULL, &cc->flashdata, *buf++);
sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
}
/* Write buffer 1 into main memory page */
W_REG(NULL, &cc->flashaddress, page);
sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
break;
}
return ret;
}
/* Erase a region. Returns number of bytes scheduled for erasure.
* Caller should poll for completion.
*/
int
sflash_erase(chipcregs_t *cc, uint offset)
{
struct sflash *sfl;
if (offset >= sflash.size)
return -22;
sfl = &sflash;
switch (sfl->type) {
case SFLASH_ST:
sflash_cmd(cc, SFLASH_ST_WREN);
W_REG(NULL, &cc->flashaddress, offset);
sflash_cmd(cc, SFLASH_ST_SE);
return sfl->blocksize;
case SFLASH_AT:
W_REG(NULL, &cc->flashaddress, offset << 1);
sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
return sfl->blocksize;
}
return 0;
}
/*
* writes the appropriate range of flash, a NULL buf simply erases
* the region of flash
*/
int
sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
{
struct sflash *sfl;
uchar *block = NULL, *cur_ptr, *blk_ptr;
uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
uint blk_offset, blk_len, copied;
int bytes, ret = 0;
/* Check address range */
if (len <= 0)
return 0;
sfl = &sflash;
if ((offset + len) > sfl->size)
return -1;
blocksize = sfl->blocksize;
mask = blocksize - 1;
/* Allocate a block of mem */
if (!(block = MALLOC(NULL, blocksize)))
return -1;
while (len) {
/* Align offset */
cur_offset = offset & ~mask;
cur_length = blocksize;
cur_ptr = block;
remainder = blocksize - (offset & mask);
if (len < remainder)
cur_retlen = len;
else
cur_retlen = remainder;
/* buf == NULL means erase only */
if (buf) {
/* Copy existing data into holding block if necessary */
if ((offset & mask) || (len < blocksize)) {
blk_offset = cur_offset;
blk_len = cur_length;
blk_ptr = cur_ptr;
/* Copy entire block */
while (blk_len) {
copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
blk_offset += copied;
blk_len -= copied;
blk_ptr += copied;
}
}
/* Copy input data into holding block */
memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
}
/* Erase block */
if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
goto done;
while (sflash_poll(cc, (uint) cur_offset));
/* buf == NULL means erase only */
if (!buf) {
offset += cur_retlen;
len -= cur_retlen;
continue;
}
/* Write holding block */
while (cur_length > 0) {
if ((bytes = sflash_write(cc,
(uint) cur_offset,
(uint) cur_length,
(uchar *) cur_ptr)) < 0) {
ret = bytes;
goto done;
}
while (sflash_poll(cc, (uint) cur_offset));
cur_offset += bytes;
cur_length -= bytes;
cur_ptr += bytes;
}
offset += cur_retlen;
len -= cur_retlen;
buf += cur_retlen;
}
ret = len;
done:
if (block)
MFREE(NULL, block, blocksize);
return ret;
}

14
target/linux/brcm-2.4/files/arch/mips/bcm947xx/time.c
View File

@@ -23,11 +23,12 @@
#include <osl.h>
#include <bcmnvram.h>
#include <sbconfig.h>
#include <sbextif.h>
#include <sbutils.h>
#include <sbchipc.h>
#include <hndmips.h>
#include <mipsinc.h>
#include <hndcpu.h>
#include <bcmdevs.h>
/* Global SB handle */
extern void *bcm947xx_sbh;
@@ -39,13 +40,11 @@ extern spinlock_t bcm947xx_sbh_lock;
extern int panic_timeout;
static int watchdog = 0;
static u8 *mcr = NULL;
void __init
bcm947xx_time_init(void)
{
unsigned int hz;
extifregs_t *eir;
/*
* Use deterministic values for initial counter interrupt
@@ -83,8 +82,13 @@ bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
timer_interrupt(irq, dev_id, regs);
/* Set the watchdog timer to reset after the specified number of ms */
if (watchdog > 0)
sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
if (watchdog > 0) {
if (sb_chip(sbh) == BCM5354_CHIP_ID)
sb_watchdog(sbh, WATCHDOG_CLOCK_5354 / 1000 * watchdog);
else
sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
}
}
static struct irqaction bcm947xx_timer_irqaction = {

105
target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.c Normal file
View File

@@ -0,0 +1,105 @@
/*
* Driver O/S-independent utility routines
*
* Copyright 2007, Broadcom Corporation
* All Rights Reserved.
*
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
* $Id$
*/
#include <typedefs.h>
#include <bcmdefs.h>
#include <stdarg.h>
#include <osl.h>
#include <sbutils.h>
#include <bcmendian.h>
#include "utils.h"
/*******************************************************************************
* crc8
*
* Computes a crc8 over the input data using the polynomial:
*
* x^8 + x^7 +x^6 + x^4 + x^2 + 1
*
* The caller provides the initial value (either CRC8_INIT_VALUE
* or the previous returned value) to allow for processing of
* discontiguous blocks of data. When generating the CRC the
* caller is responsible for complementing the final return value
* and inserting it into the byte stream. When checking, a final
* return value of CRC8_GOOD_VALUE indicates a valid CRC.
*
* Reference: Dallas Semiconductor Application Note 27
* Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
* ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
* ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
*
* ****************************************************************************
*/
static const uint8 crc8_table[256] = {
0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
};
#define CRC_INNER_LOOP(n, c, x) \
(c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
uint8 hndcrc8 (uint8 * pdata, /* pointer to array of data to process */
uint nbytes, /* number of input data bytes to process */
uint8 crc /* either CRC8_INIT_VALUE or previous return value */
)
{
/* hard code the crc loop instead of using CRC_INNER_LOOP macro
* to avoid the undefined and unnecessary (uint8 >> 8) operation.
*/
while (nbytes-- > 0)
crc = crc8_table[(crc ^ *pdata++) & 0xff];
return crc;
}
char *
bcm_ether_ntoa (struct ether_addr *ea, char *buf)
{
snprintf (buf, 18, "%02x:%02x:%02x:%02x:%02x:%02x",
ea->octet[0] & 0xff, ea->octet[1] & 0xff, ea->octet[2] & 0xff,
ea->octet[3] & 0xff, ea->octet[4] & 0xff, ea->octet[5] & 0xff);
return (buf);
}

65
target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.h Normal file
View File

@@ -0,0 +1,65 @@
#ifndef __bcm_utils_h
#define __bcm_utils_h
#define BCME_STRLEN 64 /* Max string length for BCM errors */
#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
/*
* error codes could be added but the defined ones shouldn't be changed/deleted
* these error codes are exposed to the user code
* when ever a new error code is added to this list
* please update errorstring table with the related error string and
* update osl files with os specific errorcode map
*/
#define BCME_OK 0 /* Success */
#define BCME_ERROR -1 /* Error generic */
#define BCME_BADARG -2 /* Bad Argument */
#define BCME_BADOPTION -3 /* Bad option */
#define BCME_NOTUP -4 /* Not up */
#define BCME_NOTDOWN -5 /* Not down */
#define BCME_NOTAP -6 /* Not AP */
#define BCME_NOTSTA -7 /* Not STA */
#define BCME_BADKEYIDX -8 /* BAD Key Index */
#define BCME_RADIOOFF -9 /* Radio Off */
#define BCME_NOTBANDLOCKED -10 /* Not band locked */
#define BCME_NOCLK -11 /* No Clock */
#define BCME_BADRATESET -12 /* BAD Rate valueset */
#define BCME_BADBAND -13 /* BAD Band */
#define BCME_BUFTOOSHORT -14 /* Buffer too short */
#define BCME_BUFTOOLONG -15 /* Buffer too long */
#define BCME_BUSY -16 /* Busy */
#define BCME_NOTASSOCIATED -17 /* Not Associated */
#define BCME_BADSSIDLEN -18 /* Bad SSID len */
#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
#define BCME_BADCHAN -20 /* Bad Channel */
#define BCME_BADADDR -21 /* Bad Address */
#define BCME_NORESOURCE -22 /* Not Enough Resources */
#define BCME_UNSUPPORTED -23 /* Unsupported */
#define BCME_BADLEN -24 /* Bad length */
#define BCME_NOTREADY -25 /* Not Ready */
#define BCME_EPERM -26 /* Not Permitted */
#define BCME_NOMEM -27 /* No Memory */
#define BCME_ASSOCIATED -28 /* Associated */
#define BCME_RANGE -29 /* Not In Range */
#define BCME_NOTFOUND -30 /* Not Found */
#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
#define BCME_VERSION -37 /* Incorrect version */
#define BCME_LAST BCME_VERSION
/* buffer length for ethernet address from bcm_ether_ntoa() */
#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
struct ether_addr {
unsigned char octet[6];
};
extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
#endif /* __bcm_utils_h */