mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
update brcm-2.4 to 2.4.35.4, integrate new broadcom system code, update broadcom-wl to a contributed version (v4.150.10.5) - no bcm57xx support yet, will follow shortly
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10137 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
@@ -5,8 +5,8 @@
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* jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
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* gpio interface, extbus, and support for serial and parallel flashes.
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*
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* $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
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* Copyright 2006, Broadcom Corporation
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* $Id$
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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@@ -19,7 +19,6 @@
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#ifndef _SBCHIPC_H
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#define _SBCHIPC_H
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#ifndef _LANGUAGE_ASSEMBLY
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/* cpp contortions to concatenate w/arg prescan */
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@@ -29,6 +28,7 @@
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#define PAD _XSTR(__LINE__)
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#endif /* PAD */
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typedef volatile struct {
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uint32 chipid; /* 0x0 */
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uint32 capabilities;
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@@ -62,20 +62,26 @@ typedef volatile struct {
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/* Silicon backplane configuration broadcast control */
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uint32 broadcastaddress; /* 0x50 */
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uint32 broadcastdata;
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uint32 PAD[2];
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/* gpio - cleared only by power-on-reset */
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uint32 gpiopullup; /* 0x58, corerev >= 20 */
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uint32 gpiopulldown; /* 0x5c, corerev >= 20 */
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uint32 gpioin; /* 0x60 */
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uint32 gpioout;
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uint32 gpioouten;
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uint32 gpiocontrol;
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uint32 gpiointpolarity;
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uint32 gpiointmask;
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uint32 PAD[2];
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/* GPIO events corerev >= 11 */
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uint32 gpioevent;
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uint32 gpioeventintmask;
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/* Watchdog timer */
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uint32 watchdog; /* 0x80 */
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uint32 PAD[1];
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/* GPIO events corerev >= 11 */
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uint32 gpioeventintpolarity;
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/* GPIO based LED powersave registers corerev >= 16 */
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uint32 gpiotimerval; /* 0x88 */
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@@ -114,10 +120,31 @@ typedef volatile struct {
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uint32 prog_waitcount;
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uint32 flash_config;
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uint32 flash_waitcount;
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uint32 PAD[44];
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uint32 PAD[4];
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/* Clock control and hardware workarounds */
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uint32 clk_ctl_st;
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/* Enhanced Coexistance Interface (ECI) registers (corerev >= 21) */
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uint32 eci_output; /* 0x140 */
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uint32 eci_control;
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uint32 eci_inputlo;
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uint32 eci_inputmi;
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uint32 eci_inputhi;
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uint32 eci_inputintpolaritylo;
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uint32 eci_inputintpolaritymi;
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uint32 eci_inputintpolarityhi;
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uint32 eci_intmasklo;
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uint32 eci_intmaskmi;
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uint32 eci_intmaskhi;
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uint32 eci_eventlo;
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uint32 eci_eventmi;
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uint32 eci_eventhi;
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uint32 eci_eventmasklo;
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uint32 eci_eventmaskmi;
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uint32 eci_eventmaskhi;
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uint32 PAD[23];
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/* Clock control and hardware workarounds (corerev >= 20) */
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uint32 clk_ctl_st; /* 0x1e0 */
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uint32 hw_war;
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uint32 PAD[70];
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@@ -140,12 +167,47 @@ typedef volatile struct {
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uint8 uart1lsr;
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uint8 uart1msr;
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uint8 uart1scratch;
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uint32 PAD[126];
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/* PMU registers (corerev >= 20) */
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uint32 pmucontrol; /* 0x600 */
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uint32 pmucapabilities;
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uint32 pmustatus;
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uint32 res_state;
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uint32 res_pending;
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uint32 pmutimer;
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uint32 min_res_mask;
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uint32 max_res_mask;
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uint32 res_table_sel;
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uint32 res_dep_mask;
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uint32 res_updn_timer;
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uint32 res_timer;
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uint32 clkstretch;
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uint32 pmuwatchdog;
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uint32 PAD[2];
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uint32 res_req_timer_sel;
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uint32 res_req_timer;
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uint32 res_req_mask;
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uint32 PAD;
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uint32 chipcontrol_addr;
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uint32 chipcontrol_data;
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uint32 regcontrol_addr;
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uint32 regcontrol_data;
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uint32 pllcontrol_addr;
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uint32 pllcontrol_data;
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uint32 PAD[102];
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uint16 otp[512];
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} chipcregs_t;
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#endif /* _LANGUAGE_ASSEMBLY */
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/* corecontrol */
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#define CC_UE (1 << 0) /* uart enable */
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#define CC_CHIPID 0
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#define CC_CAPABILITIES 4
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#define CC_OTPST 0x10
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#define CC_CHIPST 0x2c
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#define CC_JTAGCMD 0x30
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#define CC_JTAGIR 0x34
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#define CC_JTAGDR 0x38
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@@ -158,7 +220,18 @@ typedef volatile struct {
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#define CC_CLKC_M3 0xa0
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#define CC_CLKDIV 0xa4
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#define CC_SYS_CLK_CTL 0xc0
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#define CC_OTP 0x800
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#define CC_CLK_CTL_ST SB_CLK_CTL_ST
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#define PMU_CTL 0x600
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#define PMU_CAP 0x604
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#define PMU_ST 0x608
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#define PMU_TIMER 0x614
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#define PMU_MIN_RES_MASK 0x618
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#define PMU_MAX_RES_MASK 0x61c
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#define PMU_REG_CONTROL_ADDR 0x658
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#define PMU_REG_CONTROL_DATA 0x65C
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#define PMU_PLL_CONTROL_ADDR 0x660
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#define PMU_PLL_CONTROL_DATA 0x664
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#define CC_OTP 0x800 /* OTP address space */
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/* chipid */
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#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
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@@ -170,24 +243,26 @@ typedef volatile struct {
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#define CID_CC_SHIFT 24
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/* capabilities */
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#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
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#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
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#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
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#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
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#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
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#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
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#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
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#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
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#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
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#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
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#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
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#define CAP_PWR_CTL 0x00040000 /* Power control */
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#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
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#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
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#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
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#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
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#define CAP_ROM 0x00800000 /* Internal boot rom active */
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#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
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#define CC_CAP_UARTS_MASK 0x00000003 /* Number of uarts */
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#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
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#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
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#define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
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#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
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#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
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#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
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#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
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#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
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#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
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#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
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#define CC_CAP_PWR_CTL 0x00040000 /* Power control */
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#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
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#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
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#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
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#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
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#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
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#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
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#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
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#define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */
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/* PLL type */
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#define PLL_NONE 0x00000000
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@@ -199,39 +274,72 @@ typedef volatile struct {
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#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
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#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
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/* ALP clock on pre-PMU chips */
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#define ALP_CLOCK 20000000
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/* HT clock */
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#define HT_CLOCK 80000000
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/* watchdog clock */
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#define WATCHDOG_CLOCK_5354 32000 /* Hz */
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/* corecontrol */
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#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
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#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
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#define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */
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/* chipcontrol */
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#define CHIPCTRL_4321A0_DEFAULT 0x3a4
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#define CHIPCTRL_4321A1_DEFAULT 0x0a4
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/* Fields in the otpstatus register */
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#define OTPS_PROGFAIL 0x80000000
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#define OTPS_PROTECT 0x00000007
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#define OTPS_HW_PROTECT 0x00000001
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#define OTPS_SW_PROTECT 0x00000002
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#define OTPS_CID_PROTECT 0x00000004
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/* Fields in the otpstatus register in rev >= 21 */
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#define OTPS_OL_MASK 0x000000ff
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#define OTPS_OL_MFG 0x00000001 /* manuf row is locked */
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#define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */
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#define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */
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#define OTPS_OL_GU 0x00000008 /* general use region is locked */
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#define OTPS_GUP_MASK 0x00000f00
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#define OTPS_GUP_SHIFT 8
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#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
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#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
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#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
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#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
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#define OTPS_READY 0x00001000
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#define OTPS_RV(x) (1 << (16 + (x)))
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/* Fields in the otpcontrol register */
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#define OTPC_RECWAIT 0xff000000
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#define OTPC_PROGWAIT 0x00ffff00
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#define OTPC_PRW_SHIFT 8
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#define OTPC_MAXFAIL 0x00000038
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#define OTPC_VSEL 0x00000006
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#define OTPC_SELVL 0x00000001
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/* Fields in the otpcontrol register in rev >= 21 */
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#define OTPC_PROGSEL 0x00000001
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#define OTPC_PCOUNT_MASK 0x0000000e
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#define OTPC_PCOUNT_SHIFT 1
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#define OTPC_VSEL_MASK 0x000000f0
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#define OTPC_VSEL_SHIFT 4
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#define OTPC_TMM_MASK 0x00000700
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#define OTPC_TMM_SHIFT 8
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#define OTPC_ODM 0x00000800
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#define OTPC_PROGEN 0x80000000
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/* Fields in otpprog */
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#define OTPP_COL_MASK 0x000000ff
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#define OTPP_ROW_MASK 0x0000ff00
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#define OTPP_ROW_SHIFT 8
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#define OTPP_READERR 0x10000000
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#define OTPP_VALUE 0x20000000
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#define OTPP_VALUE_SHIFT 29
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#define OTPP_READ 0x40000000
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#define OTPP_START 0x80000000
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#define OTPP_BUSY 0x80000000
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/* Fields in otpprog in rev >= 21 */
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#define OTPP_COL_MASK 0x000000ff
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#define OTPP_COL_SHIFT 0
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#define OTPP_ROW_MASK 0x0000ff00
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#define OTPP_ROW_SHIFT 8
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#define OTPP_OC_MASK 0x0f000000
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#define OTPP_OC_SHIFT 24
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#define OTPP_READERR 0x10000000
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#define OTPP_VALUE_MASK 0x20000000
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#define OTPP_VALUE_SHIFT 29
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#define OTPP_START_BUSY 0x80000000
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/* Opcodes for OTPP_OC field */
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#define OTPPOC_READ 0
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#define OTPPOC_BIT_PROG 1
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#define OTPPOC_VERIFY 3
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#define OTPPOC_INIT 4
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#define OTPPOC_SET 5
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#define OTPPOC_RESET 6
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#define OTPPOC_OCST 7
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#define OTPPOC_ROW_LOCK 8
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#define OTPPOC_PRESCN_TEST 9
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/* jtagcmd */
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#define JCMD_START 0x80000000
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@@ -272,7 +380,12 @@ typedef volatile struct {
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/* intstatus/intmask */
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#define CI_GPIO 0x00000001 /* gpio intr */
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#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
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#define CI_EI 0x00000002 /* extif intr (corerev >= 3) */
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#define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */
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#define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */
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#define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */
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#define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */
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#define CI_UART 0x00000040 /* uart intr (corerev >= 21) */
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#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
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/* slow_clk_ctl */
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@@ -306,6 +419,43 @@ typedef volatile struct {
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#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
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#define SYCC_CD_SHIFT 16
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/* pcmcia_iowait */
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#define PI_W0_MASK 0x0000003f /* waitcount0 */
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#define PI_W1_MASK 0x00001f00 /* waitcount1 */
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#define PI_W1_SHIFT 8
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#define PI_W2_MASK 0x001f0000 /* waitcount2 */
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#define PI_W2_SHIFT 16
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#define PI_W3_MASK 0x1f000000 /* waitcount3 */
|
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#define PI_W3_SHIFT 24
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|
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/* prog_waitcount */
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#define PW_W0_MASK 0x0000001f /* waitcount0 */
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#define PW_W1_MASK 0x00001f00 /* waitcount1 */
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#define PW_W1_SHIFT 8
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#define PW_W2_MASK 0x001f0000 /* waitcount2 */
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#define PW_W2_SHIFT 16
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||||
#define PW_W3_MASK 0x1f000000 /* waitcount3 */
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||||
#define PW_W3_SHIFT 24
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||||
|
||||
#define PW_W0 0x0000000c
|
||||
#define PW_W1 0x00000a00
|
||||
#define PW_W2 0x00020000
|
||||
#define PW_W3 0x01000000
|
||||
|
||||
/* watchdog */
|
||||
#define WATCHDOG_CLOCK 48000000 /* Hz */
|
||||
|
||||
/* Fields in pmucontrol */
|
||||
#define PCTL_ILP_DIV_MASK 0xffff0000
|
||||
#define PCTL_ILP_DIV_SHIFT 16
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||||
#define PCTL_NOILP_ON_WAIT 0x00000200
|
||||
#define PCTL_HT_REQ_EN 0x00000100
|
||||
#define PCTL_ALP_REQ_EN 0x00000080
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||||
#define PCTL_XTALFREQ_MASK 0x0000007c
|
||||
#define PCTL_XTALFREQ_SHIFT 2
|
||||
#define PCTL_ILP_DIV_EN 0x00000002
|
||||
#define PCTL_LPO_SEL 0x00000001
|
||||
|
||||
/* gpiotimerval */
|
||||
#define GPIO_ONTIME_SHIFT 16
|
||||
|
||||
@@ -377,9 +527,10 @@ typedef volatile struct {
|
||||
#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
|
||||
#define CC_CFG_EM_IDE 0x0006 /* IDE */
|
||||
#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
|
||||
#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
|
||||
#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
|
||||
#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
|
||||
#define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */
|
||||
#define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */
|
||||
#define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */
|
||||
#define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */
|
||||
|
||||
/* ExtBus address space */
|
||||
#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
|
||||
@@ -396,6 +547,7 @@ typedef volatile struct {
|
||||
/* Start/busy bit in flashcontrol */
|
||||
#define SFLASH_OPCODE 0x000000ff
|
||||
#define SFLASH_ACTION 0x00000700
|
||||
#define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
|
||||
#define SFLASH_START 0x80000000
|
||||
#define SFLASH_BUSY SFLASH_START
|
||||
|
||||
@@ -419,6 +571,7 @@ typedef volatile struct {
|
||||
#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
|
||||
#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
|
||||
#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
|
||||
#define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */
|
||||
|
||||
/* Status register bits for ST flashes */
|
||||
#define SFLASH_ST_WIP 0x01 /* Write In Progress */
|
||||
@@ -456,31 +609,6 @@ typedef volatile struct {
|
||||
#define SFLASH_AT_ID_MASK 0x38
|
||||
#define SFLASH_AT_ID_SHIFT 3
|
||||
|
||||
/* OTP regions */
|
||||
#define OTP_HW_REGION OTPS_HW_PROTECT
|
||||
#define OTP_SW_REGION OTPS_SW_PROTECT
|
||||
#define OTP_CID_REGION OTPS_CID_PROTECT
|
||||
|
||||
/* OTP regions (Byte offsets from otp size) */
|
||||
#define OTP_SWLIM_OFF (-8)
|
||||
#define OTP_CIDBASE_OFF 0
|
||||
#define OTP_CIDLIM_OFF 8
|
||||
|
||||
/* Predefined OTP words (Word offset from otp size) */
|
||||
#define OTP_BOUNDARY_OFF (-4)
|
||||
#define OTP_HWSIGN_OFF (-3)
|
||||
#define OTP_SWSIGN_OFF (-2)
|
||||
#define OTP_CIDSIGN_OFF (-1)
|
||||
|
||||
#define OTP_CID_OFF 0
|
||||
#define OTP_PKG_OFF 1
|
||||
#define OTP_FID_OFF 2
|
||||
#define OTP_RSV_OFF 3
|
||||
#define OTP_LIM_OFF 4
|
||||
|
||||
#define OTP_SIGNATURE 0x578a
|
||||
#define OTP_MAGIC 0x4e56
|
||||
|
||||
/*
|
||||
* These are the UART port assignments, expressed as offsets from the base
|
||||
* register. These assignments should hold for any serial port based on
|
||||
@@ -507,10 +635,223 @@ typedef volatile struct {
|
||||
#define UART_LSR_RXRDY 0x01 /* Receiver ready */
|
||||
#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
|
||||
|
||||
/* Interrupt Identity Register (IIR) bits */
|
||||
#define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */
|
||||
#define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */
|
||||
#define UART_IIR_MDM_CHG 0x0 /* Modem status changed */
|
||||
#define UART_IIR_NOINT 0x1 /* No interrupt pending */
|
||||
#define UART_IIR_THRE 0x2 /* THR empty */
|
||||
#define UART_IIR_RCVD_DATA 0x4 /* Received data available */
|
||||
#define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */
|
||||
#define UART_IIR_CHAR_TIME 0xc /* Character time */
|
||||
|
||||
/* Interrupt Enable Register (IER) bits */
|
||||
#define UART_IER_EDSSI 8 /* enable modem status interrupt */
|
||||
#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
|
||||
#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
|
||||
#define UART_IER_ERBFI 1 /* enable data available interrupt */
|
||||
|
||||
/* pmustatus */
|
||||
#define PST_INTPEND 0x0040
|
||||
#define PST_SBCLKST 0x0030
|
||||
#define PST_ALPAVAIL 0x0008
|
||||
#define PST_HTAVAIL 0x0004
|
||||
#define PST_RESINIT 0x0003
|
||||
|
||||
/* pmucapabilities */
|
||||
#define PCAP_REV_MASK 0x000000ff
|
||||
|
||||
/* PMU Resource Request Timer registers */
|
||||
/* This is based on PmuRev0 */
|
||||
#define PRRT_TIME_MASK 0x03ff
|
||||
#define PRRT_INTEN 0x0400
|
||||
#define PRRT_REQ_ACTIVE 0x0800
|
||||
#define PRRT_ALP_REQ 0x1000
|
||||
#define PRRT_HT_REQ 0x2000
|
||||
|
||||
/* PMU resource bit position */
|
||||
#define PMURES_BIT(bit) (1 << (bit))
|
||||
|
||||
/* PMU corerev and chip specific PLL controls.
|
||||
* PMU<rev>_PLL<num>_XXXX where <rev> is PMU corerev and <num> is an arbitary number
|
||||
* to differentiate different PLLs controlled by the same PMU rev.
|
||||
*/
|
||||
/* pllcontrol registers */
|
||||
/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
|
||||
#define PMU0_PLL0_PLLCTL0 0
|
||||
#define PMU0_PLL0_PC0_PDIV_MASK 1
|
||||
#define PMU0_PLL0_PC0_PDIV_FREQ 25000
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_BASE 8
|
||||
|
||||
/* PC0_DIV_ARM for PLLOUT_ARM */
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
|
||||
#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
|
||||
|
||||
/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
|
||||
#define PMU0_PLL0_PLLCTL1 1
|
||||
#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
|
||||
#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
|
||||
#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
|
||||
#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
|
||||
#define PMU0_PLL0_PC1_STOP_MOD 0x00000040
|
||||
|
||||
/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
|
||||
#define PMU0_PLL0_PLLCTL2 2
|
||||
#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
|
||||
#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
|
||||
|
||||
/* Chip specific PMU resources. */
|
||||
#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
|
||||
#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
|
||||
#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
|
||||
#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
|
||||
#define RES4328_ILP_REQUEST 4 /* 0x00010 */
|
||||
#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
|
||||
#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
|
||||
#define RES4328_ROM_SWITCH 7 /* 0x00080 */
|
||||
#define RES4328_PA_REF_LDO 8 /* 0x00100 */
|
||||
#define RES4328_RADIO_LDO 9 /* 0x00200 */
|
||||
#define RES4328_AFE_LDO 10 /* 0x00400 */
|
||||
#define RES4328_PLL_LDO 11 /* 0x00800 */
|
||||
#define RES4328_BG_FILTBYP 12 /* 0x01000 */
|
||||
#define RES4328_TX_FILTBYP 13 /* 0x02000 */
|
||||
#define RES4328_RX_FILTBYP 14 /* 0x04000 */
|
||||
#define RES4328_XTAL_PU 15 /* 0x08000 */
|
||||
#define RES4328_XTAL_EN 16 /* 0x10000 */
|
||||
#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
|
||||
#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
|
||||
#define RES4328_BB_PLL_PU 19 /* 0x80000 */
|
||||
|
||||
#define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */
|
||||
#define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */
|
||||
#define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */
|
||||
#define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
|
||||
#define RES5354_ILP_REQUEST 4 /* 0x00010 */
|
||||
#define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */
|
||||
#define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */
|
||||
#define RES5354_ROM_SWITCH 7 /* 0x00080 */
|
||||
#define RES5354_PA_REF_LDO 8 /* 0x00100 */
|
||||
#define RES5354_RADIO_LDO 9 /* 0x00200 */
|
||||
#define RES5354_AFE_LDO 10 /* 0x00400 */
|
||||
#define RES5354_PLL_LDO 11 /* 0x00800 */
|
||||
#define RES5354_BG_FILTBYP 12 /* 0x01000 */
|
||||
#define RES5354_TX_FILTBYP 13 /* 0x02000 */
|
||||
#define RES5354_RX_FILTBYP 14 /* 0x04000 */
|
||||
#define RES5354_XTAL_PU 15 /* 0x08000 */
|
||||
#define RES5354_XTAL_EN 16 /* 0x10000 */
|
||||
#define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */
|
||||
#define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */
|
||||
#define RES5354_BB_PLL_PU 19 /* 0x80000 */
|
||||
|
||||
/* pllcontrol registers */
|
||||
/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypsss_sdmod */
|
||||
#define PMU1_PLL0_PLLCTL0 0
|
||||
#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
|
||||
#define PMU1_PLL0_PC0_P1DIV_SHIFT 20
|
||||
#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
|
||||
#define PMU1_PLL0_PC0_P2DIV_SHIFT 24
|
||||
|
||||
/* m<x>div */
|
||||
#define PMU1_PLL0_PLLCTL1 1
|
||||
#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
|
||||
#define PMU1_PLL0_PC1_M1DIV_SHIFT 0
|
||||
#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
|
||||
#define PMU1_PLL0_PC1_M2DIV_SHIFT 8
|
||||
#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
|
||||
#define PMU1_PLL0_PC1_M3DIV_SHIFT 16
|
||||
#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
|
||||
#define PMU1_PLL0_PC1_M4DIV_SHIFT 24
|
||||
|
||||
/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
|
||||
#define PMU1_PLL0_PLLCTL2 2
|
||||
#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
|
||||
#define PMU1_PLL0_PC2_M5DIV_SHIFT 0
|
||||
#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
|
||||
#define PMU1_PLL0_PC2_M6DIV_SHIFT 8
|
||||
#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
|
||||
#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
|
||||
#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
|
||||
#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
|
||||
|
||||
/* ndiv_frac */
|
||||
#define PMU1_PLL0_PLLCTL3 3
|
||||
#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
|
||||
#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
|
||||
|
||||
/* pll_ctrl */
|
||||
#define PMU1_PLL0_PLLCTL4 4
|
||||
|
||||
/* pll_ctrl, vco_rng, clkdrive_ch<x> */
|
||||
#define PMU1_PLL0_PLLCTL5 5
|
||||
#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
|
||||
#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
|
||||
|
||||
#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
|
||||
#define RES4325_CBUCK_BURST 1 /* 0x00000002 */
|
||||
#define RES4325_CBUCK_PWM 2 /* 0x00000004 */
|
||||
#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
|
||||
#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
|
||||
#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
|
||||
#define RES4325_ILP_REQUEST 6 /* 0x00000040 */
|
||||
#define RES4325_ABUCK_BURST 7 /* 0x00000080 */
|
||||
#define RES4325_ABUCK_PWM 8 /* 0x00000100 */
|
||||
#define RES4325_LNLDO1_PU 9 /* 0x00000200 */
|
||||
#define RES4325_LNLDO2_PU 10 /* 0x00000400 */
|
||||
#define RES4325_LNLDO3_PU 11 /* 0x00000800 */
|
||||
#define RES4325_LNLDO4_PU 12 /* 0x00001000 */
|
||||
#define RES4325_XTAL_PU 13 /* 0x00002000 */
|
||||
#define RES4325_ALP_AVAIL 14 /* 0x00004000 */
|
||||
#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
|
||||
#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
|
||||
#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
|
||||
#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
|
||||
#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
|
||||
#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
|
||||
#define RES4325_HT_AVAIL 21 /* 0x00200000 */
|
||||
|
||||
/* Chip specific ChipStatus register bits */
|
||||
#define CST4325_SPROM_OTP_SEL_MASK 0x00000003
|
||||
#define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
|
||||
#define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
|
||||
#define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
|
||||
#define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
|
||||
#define CST4325_SDIO_USB_MODE_MASK 0x00000004
|
||||
#define CST4325_SDIO_USB_MODE_SHIFT 2
|
||||
#define CST4325_RCAL_VALID_MASK 0x00000008
|
||||
#define CST4325_RCAL_VALID_SHIFT 3
|
||||
#define CST4325_RCAL_VALUE_MASK 0x000001f0
|
||||
#define CST4325_RCAL_VALUE_SHIFT 4
|
||||
#define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */
|
||||
#define CST4325_PMUTOP_2B_SHIFT 9
|
||||
|
||||
#define RES4312_SWITCHER_BURST 0 /* 0x00000001 */
|
||||
#define RES4312_SWITCHER_PWM 1 /* 0x00000002 */
|
||||
#define RES4312_PA_REF_LDO 2 /* 0x00000004 */
|
||||
#define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */
|
||||
#define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */
|
||||
#define RES4312_RADIO_LDO 5 /* 0x00000020 */
|
||||
#define RES4312_ILP_REQUEST 6 /* 0x00000040 */
|
||||
#define RES4312_BG_FILTBYP 7 /* 0x00000080 */
|
||||
#define RES4312_TX_FILTBYP 8 /* 0x00000100 */
|
||||
#define RES4312_RX_FILTBYP 9 /* 0x00000200 */
|
||||
#define RES4312_XTAL_PU 10 /* 0x00000400 */
|
||||
#define RES4312_ALP_AVAIL 11 /* 0x00000800 */
|
||||
#define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */
|
||||
#define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */
|
||||
#define RES4312_HT_AVAIL 14 /* 0x00004000 */
|
||||
|
||||
/*
|
||||
* Maximum delay for the PMU state transition.
|
||||
* This is an upper bound intended for spinwaits etc.
|
||||
*/
|
||||
#define PMU_MAX_TRANSITION_DLY 15000
|
||||
|
||||
#endif /* _SBCHIPC_H */
|
||||
|
||||
Reference in New Issue
Block a user