mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-24 20:53:22 +02:00
ocf: update to version 20120127
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32672 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
luka
parent
8ad915e157
commit
94a17b96c4
@ -26,7 +26,6 @@ config OCF_CRYPTODEV
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config OCF_CRYPTOSOFT
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tristate "cryptosoft (software crypto engine)"
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select CRYPTO_MANAGER
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depends on OCF_OCF
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help
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A software driver for the OCF framework that uses
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@ -105,6 +105,7 @@ patch:
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patch=ocf-linux-base.patch; \
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patch24=ocf-linux-24.patch; \
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patch26=ocf-linux-26.patch; \
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patch3=ocf-linux-3.patch; \
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( \
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find . -name Makefile; \
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find . -name Config.in; \
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@ -116,6 +117,8 @@ patch:
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done > $$patch; \
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cat $$patchbase/patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \
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cat $$patchbase/patches/linux-2.6.38-ocf.patch $$patch > $$patch26; \
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cat $$patchbase/patches/linux-3.2.1-ocf.patch $$patch > $$patch3; \
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#
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# this target probably does nothing for anyone but me - davidm
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@ -1,246 +0,0 @@
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###########################
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README - ocf-linux-20100530
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###########################
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This README provides instructions for getting ocf-linux compiled and
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operating in a generic linux environment. Other information on the project
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can be found at the home page:
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http://ocf-linux.sourceforge.net/
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Embedded systems and applications requiring userspace acceleration will need
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to patch the kernel source to get full OCF support. See "Adding OCF to
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linux source" below. Otherwise the "OCF Quickstart" that follows is the
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easiest way to get started.
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If your goal is to accelerate Openswan on Ubuntu or CentOS, you may find
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that the required binaries are already available on openswan.org:
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ftp://ftp.openswan.org/ocf/
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ftp://ftp.openswan.org/openswan/binaries/ubuntu/
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#####################################################
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OCF Quickstart for Ubuntu/Others (including Openswan)
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#####################################################
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This section provides instructions on how to quickly add kernel only support
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for OCF to a GNU/Linux system. It is only suitable for in-kernel use such as
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Openswan MAST/KLIPS.
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If the target is an embedded system, or, userspace acceleration of
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applications such as OpenVPN and OpenSSL, the section below titled
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"Adding OCF to linux source" is more appropriate.
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Before building kernel only support for OCF ensure that the appropriate
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linux-headers package is installed:
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cd ocf
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make ocf_modules
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sudo make ocf_install
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OCF_DIR=`pwd` # remember where OCF sources were built
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At this point the ocf, cryptosoft, ocfnull, hifn7751 and ocf-bench modules
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should have been built and installed. The OCF installation can be tested
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with the following commands:
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modprobe ocf
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modprobe cryptosoft
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modprobe ocf-bench
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dmesg | tail -5
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The final modprobe of ocf-bench will fail, this is intentional as ocf-bench
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is a short lived module that tests in-kernel performance of OCF. If
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everything worked correctly the "dmesg | tail -5" should include a line
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like:
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[ 583.128741] OCF: 45133 requests of 1488 bytes in 251 jiffies (535.122 Mbps)
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This shows the in-kernel performance of OCF using the cryptosoft driver.
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For addition driver load options, see "How to load the OCF modules" below.
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If the intention is to run an OCF accelerated Openswan (KLIPS/MAST) then use
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these steps to compile openswan downloaded from openswan.org (2.6.34 or later).
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tar xf openswan-2.6.34.tar.gz
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cd openswan-2.6.34
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make programs
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make KERNELSRC=/lib/modules/`uname -r`/build \
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KBUILD_EXTRA_SYMBOLS=$OCF_DIR/Module.symvers \
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MODULE_DEF_INCLUDE=`pwd`/packaging/ocf/config-all.hmodules \
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MODULE_DEFCONFIG=`pwd`/packaging/ocf/defconfig \
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module
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sudo make KERNELSRC=/lib/modules/`uname -r`/build \
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KBUILD_EXTRA_SYMBOLS=$OCF_DIR/Module.symvers \
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MODULE_DEF_INCLUDE=`pwd`/packaging/ocf/config-all.hmodules \
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MODULE_DEFCONFIG=`pwd`/packaging/ocf/defconfig \
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install minstall
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The rest of this document is only required for more complex build
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requirements.
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##########################
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Adding OCF to linux source
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##########################
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It is recommended that OCF be built as modules as it increases the
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flexibility and ease of debugging the system.
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Ensure that the system has /dev/crypto for userspace access to OCF:
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mknod /dev/crypto c 10 70
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Generate the kernel patches and apply the appropriate one.
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cd ocf
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make patch
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This will provide three files:
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linux-2.4.*-ocf.patch
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linux-2.6.*-ocf.patch
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ocf-linux-base.patch
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If either of the first two patches applies to the targets kernel, then one
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of the following as required:
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cd linux-2.X.Y; patch -p1 < linux-2.4.*-ocf.patch
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cd linux-2.6.Y; patch -p1 < linux-2.6.*-ocf.patch
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Otherwise, locate the appropriate kernel patch in the patches directory and
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apply that as well as the ocf-linux-base.patch using '-p1'.
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When using a linux-2.4 system on a non-x86 platform, the following may be
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required to build cryptosoft:
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cp linux-2.X.x/include/asm-i386/kmap_types.h linux-2.X.x/include/asm-YYY
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When using cryptosoft, for simplicity, enable all the crypto support in the
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kernel except for the test driver. Likewise for the OCF options. Do not
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enable OCF crypto drivers for HW that is not present (for example the ixp4xx
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driver will not compile on non-Xscale systems).
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Make sure that cryptodev.h from the ocf directory is installed as
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crypto/cryptodev.h in an include directory that is used for building
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applications for the target platform. For example on a host system that
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might be:
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/usr/include/crypto/cryptodev.h
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Patch the openssl-0.9.8r code the openssl-0.9.8r.patch from the patches
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directory. There are many older patch versions in the patches directory
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if required.
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The openssl patches provide the following functionality:
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* enables --with-cryptodev for non BSD systems
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* adds -cpu option to openssl speed for calculating CPU load under linux
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* fixes null pointer in openssl speed multi thread output.
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* fixes test keys to work with linux crypto's more stringent key checking.
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* adds MD5/SHA acceleration (Ronen Shitrit), only enabled with the
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--with-cryptodev-digests option
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* fixes bug in engine code caching.
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Build the crypto-tools directory for the target to obtain a userspace
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testing tool call cryptotest.
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###########################
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How to load the OCF modules
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###########################
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First insert the base modules (cryptodev is optional, it is only used
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for userspace acceleration):
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modprobe ocf
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modprobe cryptodev
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Load the software OCF driver with:
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modprobe cryptosoft
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and zero or more of the OCF HW drivers with:
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modprobe safe
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modprobe hifn7751
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modprobe ixp4xx
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...
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All the drivers take a debug option to enable verbose debug so that
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OCF operation may be observed via "dmesg" or the console. For debug
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load the modules as:
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modprobe ocf crypto_debug=1
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modprobe cryptodev cryptodev_debug=1
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modprobe cryptosoft swcr_debug=1
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More than one OCF crypto driver may be loaded but then there is no
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guarantee as to which will be used (other than a preference for HW
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drivers over SW drivers by most applications).
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It is also possible to enable debug at run time on linux-2.6 systems
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with the following:
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echo 1 > /sys/module/ocf/parameters/crypto_debug
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echo 1 > /sys/module/cryptodev/parameters/cryptodev_debug
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echo 1 > /sys/module/cryptosoft/parameters/swcr_debug
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echo 1 > /sys/module/hifn7751/parameters/hifn_debug
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echo 1 > /sys/module/safe/parameters/safe_debug
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echo 1 > /sys/module/ixp4xx/parameters/ixp_debug
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...
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The ocf-bench driver accepts the following parameters:
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request_q_len - Maximum number of outstanding requests to OCF
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request_num - run for at least this many requests
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request_size - size of each request (multiple of 16 bytes recommended)
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request_batch - enable OCF request batching
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request_cbimm - enable OCF immediate callback on completion
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For example:
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modprobe ocf-bench request_size=1024 request_cbimm=0
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#######################
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Testing the OCF support
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#######################
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run "cryptotest", it should do a short test for a couple of
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des packets. If it does everything is working.
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If this works, then ssh will use the driver when invoked as:
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ssh -c 3des username@host
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to see for sure that it is operating, enable debug as defined above.
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To get a better idea of performance run:
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cryptotest 100 4096
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There are more options to cryptotest, see the help.
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It is also possible to use openssl to test the speed of the crypto
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drivers.
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openssl speed -evp des -engine cryptodev -elapsed
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openssl speed -evp des3 -engine cryptodev -elapsed
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openssl speed -evp aes128 -engine cryptodev -elapsed
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and multiple threads (10) with:
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openssl speed -evp des -engine cryptodev -elapsed -multi 10
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openssl speed -evp des3 -engine cryptodev -elapsed -multi 10
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openssl speed -evp aes128 -engine cryptodev -elapsed -multi 10
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for public key testing you can try:
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cryptokeytest
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openssl speed -engine cryptodev rsa -elapsed
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openssl speed -engine cryptodev dsa -elapsed
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#############################
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#
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# David McCullough
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# david_mccullough@mcafee.com
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#
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#############################
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@ -592,7 +592,7 @@ c7108_process(void *arg, struct cryptop *crp, int hint)
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i < skb_shinfo(skb)->nr_frags &&
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sg_num < SCATTERLIST_MAX; i++) {
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if (skip < skb_shinfo(skb)->frags[i].size) {
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//sg[sg_num].page = skb_frag_page(&kb_shinfo(skb)->frags[i]);
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//sg[sg_num].page = skb_frag_page(&skb_shinfo(skb)->frags[i]);
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//sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip;
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len = skb_shinfo(skb)->frags[i].size - skip;
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if (len + sg_len > crd->crd_len)
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@ -636,6 +636,8 @@ c7108_process(void *arg, struct cryptop *crp, int hint)
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sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip));
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sg_num = 1;
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}
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if (sg_num > 0)
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sg_mark_end(&sg[sg_num-1]);
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switch (sw->xfm_type) {
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@ -143,7 +143,6 @@ EXPORT_SYMBOL(cuio_copyback);
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EXPORT_SYMBOL(cuio_copydata);
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EXPORT_SYMBOL(cuio_getptr);
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static void
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skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len)
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{
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11
target/linux/generic/files/crypto/ocf/cryptocteon/README.txt
Normal file
11
target/linux/generic/files/crypto/ocf/cryptocteon/README.txt
Normal file
@ -0,0 +1,11 @@
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You will need the CRYPTO package installed to build this driver, and
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potentially the ADK.
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cavium_crypto sourced from:
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||||
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adk/components/source/cavium_ipsec_kame/cavium_ipsec.c
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and significantly modified to suit use with OCF. All original
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copyright/ownership headers retained.
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@ -497,7 +497,8 @@ octo_process(device_t dev, struct cryptop *crp, int hint)
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offset_in_page(crp->crp_buf));
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sg_num = 1;
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}
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if (sg_num > 0)
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sg_mark_end(&sg[sg_num-1]);
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/*
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* setup a new explicit key
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@ -814,6 +814,8 @@ static void swcr_process_req(struct swcr_req *req)
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sg_len, offset_in_page(crp->crp_buf + skip));
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sg_num = 1;
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}
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if (sg_num > 0)
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sg_mark_end(&req->sg[sg_num-1]);
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switch (sw->sw_type & SW_TYPE_ALG_AMASK) {
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|
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|
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78
target/linux/generic/files/crypto/ocf/ep80579/environment.mk
Normal file
78
target/linux/generic/files/crypto/ocf/ep80579/environment.mk
Normal file
@ -0,0 +1,78 @@
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###########################################################################
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||||
#
|
||||
# This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
# redistributing this file, you may do so under either license.
|
||||
#
|
||||
# GPL LICENSE SUMMARY
|
||||
#
|
||||
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of version 2 of the GNU General Public License as
|
||||
# published by the Free Software Foundation.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful, but
|
||||
# WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
# The full GNU General Public License is included in this distribution
|
||||
# in the file called LICENSE.GPL.
|
||||
#
|
||||
# Contact Information:
|
||||
# Intel Corporation
|
||||
#
|
||||
# BSD LICENSE
|
||||
#
|
||||
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# * Neither the name of Intel Corporation nor the names of its
|
||||
# contributors may be used to endorse or promote products derived
|
||||
# from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
#
|
||||
# version: Security.L.1.0.130
|
||||
#
|
||||
###########################################################################
|
||||
|
||||
|
||||
ICP_LAC_API=$(ICP_ROOT)/Acceleration/include/lac
|
||||
ICP_BTR_API=$(ICP_ROOT)/Acceleration/include/btr
|
||||
ICP_API_DIR=$(ICP_ROOT)/Acceleration/include
|
||||
ICP_OCF_SHIM_DIR?=$(KERNEL_SOURCE_ROOT)/crypto/ocf/
|
||||
ifeq ($(wildcard $(ICP_OCF_SHIM_DIR)),)
|
||||
ICP_OCF_SHIM_DIR?=$(ROOTDIR)/modules/ocf/
|
||||
endif
|
||||
|
||||
ICP_OS_LEVEL?=kernel_space
|
||||
|
||||
ICP_OS?=linux_2.6
|
||||
|
||||
ICP_CORE?=ia
|
||||
|
||||
@ -0,0 +1,69 @@
|
||||
###################
|
||||
# @par
|
||||
# This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
# redistributing this file, you may do so under either license.
|
||||
#
|
||||
# GPL LICENSE SUMMARY
|
||||
#
|
||||
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of version 2 of the GNU General Public License as
|
||||
# published by the Free Software Foundation.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful, but
|
||||
# WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
# The full GNU General Public License is included in this distribution
|
||||
# in the file called LICENSE.GPL.
|
||||
#
|
||||
# Contact Information:
|
||||
# Intel Corporation
|
||||
#
|
||||
# BSD LICENSE
|
||||
#
|
||||
# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# * Neither the name of Intel Corporation nor the names of its
|
||||
# contributors may be used to endorse or promote products derived
|
||||
# from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
#
|
||||
# version: Security.L.1.0.130
|
||||
###################
|
||||
|
||||
#specific include directories in kernel space
|
||||
INCLUDES+=#e.g. -I$(OSAL_DIR)/include \
|
||||
|
||||
#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include
|
||||
EXTRA_CFLAGS += $(INCLUDES) -O2 -Wall
|
||||
EXTRA_LDFLAGS +=-whole-archive
|
||||
|
||||
@ -434,10 +434,8 @@ hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent)
|
||||
if (pci_enable_device(dev) < 0)
|
||||
return(-ENODEV);
|
||||
|
||||
#ifdef HAVE_PCI_SET_MWI
|
||||
if (pci_set_mwi(dev))
|
||||
return(-ENODEV);
|
||||
#endif
|
||||
|
||||
if (!dev->irq) {
|
||||
printk("hifn: found device with no IRQ assigned. check BIOS settings!");
|
||||
|
||||
@ -208,10 +208,8 @@ hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent)
|
||||
if (pci_enable_device(dev) < 0)
|
||||
return(-ENODEV);
|
||||
|
||||
#ifdef HAVE_PCI_SET_MWI
|
||||
if (pci_set_mwi(dev))
|
||||
return(-ENODEV);
|
||||
#endif
|
||||
|
||||
if (!dev->irq) {
|
||||
printk("hifn: found device with no IRQ assigned. check BIOS settings!");
|
||||
@ -385,7 +383,6 @@ static struct pci_device_id hipp_pci_tbl[] = {
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
|
||||
{ PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155,
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
|
||||
{ 0 }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, hipp_pci_tbl);
|
||||
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.4
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -92,6 +92,11 @@ extern int cesaReqResources;
|
||||
#define CESA_OCF_MAX_SES 128
|
||||
#define CESA_Q_SIZE 64
|
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
|
||||
#define FRAG_PAGE(f) (f).p
|
||||
#else
|
||||
#define FRAG_PAGE(f) (f)
|
||||
#endif
|
||||
|
||||
/* data structures */
|
||||
struct cesa_ocf_data {
|
||||
@ -415,7 +420,7 @@ cesa_ocf_process(device_t dev, struct cryptop *crp, int hint)
|
||||
for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) {
|
||||
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
|
||||
p_buf_info->bufSize = frag->size;
|
||||
p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset;
|
||||
p_buf_info->bufVirtPtr = page_address(FRAG_PAGE(frag->page)) + frag->page_offset;
|
||||
p_buf_info++;
|
||||
}
|
||||
p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1;
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.4
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,163 @@
|
||||
/*******************************************************************************
|
||||
Copyright (C) Marvell International Ltd. and its affiliates
|
||||
|
||||
This software file (the "File") is owned and distributed by Marvell
|
||||
International Ltd. and/or its affiliates ("Marvell") under the following
|
||||
alternative licensing terms. Once you have made an election to distribute the
|
||||
File under one of the following license alternatives, please (i) delete this
|
||||
introductory statement regarding license alternatives, (ii) delete the two
|
||||
license alternatives that you have not elected to use and (iii) preserve the
|
||||
Marvell copyright notice above.
|
||||
|
||||
********************************************************************************
|
||||
Marvell Commercial License Option
|
||||
|
||||
If you received this File from Marvell and you have entered into a commercial
|
||||
license agreement (a "Commercial License") with Marvell, the File is licensed
|
||||
to you under the terms of the applicable Commercial License.
|
||||
|
||||
********************************************************************************
|
||||
Marvell GPL License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File in accordance with the terms and conditions of the General
|
||||
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
|
||||
available along with the File in the license.txt file or by writing to the Free
|
||||
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
|
||||
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
|
||||
|
||||
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
|
||||
DISCLAIMED. The GPL License provides additional details about this warranty
|
||||
disclaimer.
|
||||
********************************************************************************
|
||||
Marvell BSD License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File under the following licensing terms.
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of Marvell nor the names of its contributors may be
|
||||
used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#define MV_ASMLANGUAGE
|
||||
#include "mvOsAsm.h"
|
||||
#include "mvDeviceId.h"
|
||||
#include "mvCtrlEnvRegs.h"
|
||||
#include "mvCpuIfRegs.h"
|
||||
#include "mvCtrlEnvAsm.h"
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* mvCpuIfPreInit - Make early initialization of CPU interface.
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* The function will initialize the CPU interface parameters that must
|
||||
* be initialize before any BUS activity towards the DDR interface,
|
||||
* which means it must be executed from ROM. Because of that, the function
|
||||
* is implemented in assembly code.
|
||||
* The function configure the following CPU config register parameters:
|
||||
* 1) CPU2MbusLTickDrv
|
||||
* 2) CPU2MbusLTickSample.
|
||||
* NOTE: This function must be called AFTER the internal register
|
||||
* base is modified to INTER_REGS_BASE.
|
||||
*
|
||||
* INPUT:
|
||||
* None.
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* None.
|
||||
*
|
||||
* r11 holds return function address.
|
||||
*******************************************************************************/
|
||||
#define MV88F6281_PCKG_OPT 2
|
||||
#define MV88F6192_PCKG_OPT 1
|
||||
#define MV88F6180_PCKG_OPT 0
|
||||
|
||||
.globl _mvCpuIfPreInit
|
||||
_mvCpuIfPreInit:
|
||||
|
||||
mov r11, LR /* Save link register */
|
||||
|
||||
/* Read device ID */
|
||||
MV_CTRL_MODEL_GET_ASM(r4, r5);
|
||||
|
||||
/* goto calcConfigReg if device is 6281 */
|
||||
ldr r5, =MV88F6281_PCKG_OPT
|
||||
cmp r4, r5
|
||||
beq calcConfigReg
|
||||
|
||||
/* goto calcConfigReg if device is 6192/6190 */
|
||||
ldr r5, =MV88F6192_PCKG_OPT
|
||||
cmp r4, r5
|
||||
beq calcConfigReg
|
||||
|
||||
/* Else 6180 */
|
||||
/* Get the "sample on reset" register */
|
||||
MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
|
||||
ldr r5, =MSAR_CPUCLCK_MASK_6180
|
||||
and r5, r4, r5
|
||||
mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180
|
||||
|
||||
ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3
|
||||
cmp r5, #CPU_2_DDR_CLK_1x3_1
|
||||
beq setConfigReg
|
||||
|
||||
ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4
|
||||
cmp r5, #CPU_2_DDR_CLK_1x4_1
|
||||
beq setConfigReg
|
||||
b setConfigReg
|
||||
|
||||
calcConfigReg:
|
||||
/* Get the "sample on reset" register */
|
||||
MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
|
||||
ldr r5, =MSAR_DDRCLCK_RTIO_MASK
|
||||
and r5, r4, r5
|
||||
mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS
|
||||
|
||||
ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3
|
||||
cmp r5, #CPU_2_DDR_CLK_1x3
|
||||
beq setConfigReg
|
||||
|
||||
ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4
|
||||
cmp r5, #CPU_2_DDR_CLK_1x4
|
||||
beq setConfigReg
|
||||
|
||||
/* Else */
|
||||
ldr r4, =0
|
||||
|
||||
setConfigReg:
|
||||
/* Read CPU Config register */
|
||||
MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG)
|
||||
ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK)
|
||||
and r7, r7, r5 /* Clear register fields */
|
||||
orr r7, r7, r4 /* Set the values according to the findings */
|
||||
MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG)
|
||||
|
||||
done:
|
||||
mov PC, r11 /* r11 is saved link register */
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.5
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.3
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.3
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,988 @@
|
||||
/*******************************************************************************
|
||||
Copyright (C) Marvell International Ltd. and its affiliates
|
||||
|
||||
This software file (the "File") is owned and distributed by Marvell
|
||||
International Ltd. and/or its affiliates ("Marvell") under the following
|
||||
alternative licensing terms. Once you have made an election to distribute the
|
||||
File under one of the following license alternatives, please (i) delete this
|
||||
introductory statement regarding license alternatives, (ii) delete the two
|
||||
license alternatives that you have not elected to use and (iii) preserve the
|
||||
Marvell copyright notice above.
|
||||
|
||||
********************************************************************************
|
||||
Marvell Commercial License Option
|
||||
|
||||
If you received this File from Marvell and you have entered into a commercial
|
||||
license agreement (a "Commercial License") with Marvell, the File is licensed
|
||||
to you under the terms of the applicable Commercial License.
|
||||
|
||||
********************************************************************************
|
||||
Marvell GPL License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File in accordance with the terms and conditions of the General
|
||||
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
|
||||
available along with the File in the license.txt file or by writing to the Free
|
||||
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
|
||||
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
|
||||
|
||||
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
|
||||
DISCLAIMED. The GPL License provides additional details about this warranty
|
||||
disclaimer.
|
||||
********************************************************************************
|
||||
Marvell BSD License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File under the following licensing terms.
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of Marvell nor the names of its contributors may be
|
||||
used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#define MV_ASMLANGUAGE
|
||||
#include "mvSysHwConfig.h"
|
||||
#include "mvOsAsm.h"
|
||||
#include "mvBoardEnvSpec.h"
|
||||
#include "mvCpuIfRegs.h"
|
||||
#include "mvDramIfConfig.h"
|
||||
#include "mvDramIfRegs.h"
|
||||
#include "pex/mvPexRegs.h"
|
||||
#include "pci/mvPciRegs.h"
|
||||
#include "mvCtrlEnvSpec.h"
|
||||
#include "mvCtrlEnvAsm.h"
|
||||
#include "cpu/mvCpuArm.h"
|
||||
#include "mvCommon.h"
|
||||
|
||||
/* defines */
|
||||
|
||||
#if !defined(MV_INC_BOARD_DDIM)
|
||||
.globl dramBoot1
|
||||
dramBoot1:
|
||||
.word 0
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
*
|
||||
*
|
||||
*
|
||||
*******************************************************************************/
|
||||
#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG)
|
||||
|
||||
/* PEX_PCI and PRPMC boards 256 MB*/
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001
|
||||
#define STATIC_SDRAM_CONFIG 0x03248400
|
||||
#define STATIC_SDRAM_MODE 0x62
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x4041000
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x00000020
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x0
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
|
||||
#define STATIC_SDRAM_EXT_MODE 0x0
|
||||
|
||||
#elif defined(DB_FPGA)
|
||||
|
||||
/* FPGA DC boards 256 MB*/
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001
|
||||
#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */
|
||||
#define STATIC_SDRAM_MODE 0x22
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x03041000
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x00000020
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x0
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
|
||||
#define STATIC_SDRAM_EXT_MODE 0x1
|
||||
|
||||
#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER)
|
||||
|
||||
/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001
|
||||
#define STATIC_SDRAM_CONFIG 0x03158400
|
||||
#define STATIC_SDRAM_MODE 0x452
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x06041000
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x00000020
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601
|
||||
#define STATIC_SDRAM_EXT_MODE 0x00000440
|
||||
|
||||
|
||||
#elif defined(RD_88F6183AP)
|
||||
|
||||
/* DDR2 1 devices 512Mbit by 16 bit */
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001
|
||||
#define STATIC_SDRAM_CONFIG 0x1f154400
|
||||
#define STATIC_SDRAM_MODE 0x432
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x04041000
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x00000020
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601
|
||||
#define STATIC_SDRAM_EXT_MODE 0x00000440
|
||||
|
||||
/* 6082L MARVELL DIMM */
|
||||
#elif defined(DB_88F6082LBP)
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001
|
||||
#define STATIC_SDRAM_CONFIG 0x7f158400
|
||||
#define STATIC_SDRAM_MODE 0x432
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x04041040
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x00000020
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01
|
||||
#define STATIC_SDRAM_EXT_MODE 0x00000440
|
||||
|
||||
#elif defined(RD_88W8660_AP82S)
|
||||
|
||||
/* Shark RD */
|
||||
|
||||
#if defined(MV_DRAM_32M)
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x00000010
|
||||
#elif defined(MV_DRAM_16M)
|
||||
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x00000000
|
||||
|
||||
#else
|
||||
#error "NO DDR size selected"
|
||||
#endif
|
||||
|
||||
#define STATIC_SDRAM_CONFIG 0x03144400
|
||||
#define STATIC_SDRAM_MODE 0x62
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x4041000
|
||||
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x0
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
|
||||
#define STATIC_SDRAM_EXT_MODE 0x0
|
||||
|
||||
#elif defined(RD_88W8660)
|
||||
|
||||
/* Shark RD */
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001
|
||||
#define STATIC_SDRAM_CONFIG 0x03144400
|
||||
#define STATIC_SDRAM_MODE 0x62
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x4041000
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x00000010
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x0
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
|
||||
#define STATIC_SDRAM_EXT_MODE 0x0
|
||||
|
||||
#else /* NAS */
|
||||
|
||||
|
||||
#if defined(RD_88F5182)
|
||||
|
||||
#if defined(MV_88F5082)
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x20
|
||||
#else
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x20
|
||||
#endif
|
||||
|
||||
#elif defined(RD_88F5182_3)
|
||||
|
||||
#if defined(MV_88F5082)
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x20
|
||||
#else
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x20
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x0
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(MV_88F5082)
|
||||
#define STATIC_SDRAM_CONFIG 0x3144400
|
||||
#else
|
||||
#define STATIC_SDRAM_CONFIG 0x3148400
|
||||
#endif
|
||||
#define STATIC_SDRAM_MODE 0x62
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x4041000
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x40c
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x0
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
|
||||
#define STATIC_SDRAM_EXT_MODE 0x0
|
||||
|
||||
#endif
|
||||
|
||||
.globl _mvDramIfStaticInit
|
||||
_mvDramIfStaticInit:
|
||||
|
||||
mov r11, LR /* Save link register */
|
||||
mov r10, r2
|
||||
|
||||
/* If we boot from NAND jump to DRAM sddress */
|
||||
|
||||
mov r5, #1
|
||||
ldr r6, =dramBoot1
|
||||
str r5, [r6] /* We started executing from DRAM */
|
||||
|
||||
ldr r6, dramBoot1
|
||||
cmp r6, #0
|
||||
bne 1f
|
||||
|
||||
|
||||
/* set all dram windows to 0 */
|
||||
mov r6, #0
|
||||
MV_REG_WRITE_ASM(r6, r5, 0x1504)
|
||||
MV_REG_WRITE_ASM(r6, r5, 0x150c)
|
||||
MV_REG_WRITE_ASM(r6, r5, 0x1514)
|
||||
MV_REG_WRITE_ASM(r6, r5, 0x151c)
|
||||
|
||||
/* set all dram configuration in temp registers */
|
||||
ldr r6, = STATIC_SDRAM0_BANK0_SIZE
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0)
|
||||
ldr r6, = STATIC_SDRAM_CONFIG
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1)
|
||||
ldr r6, = STATIC_SDRAM_MODE
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2)
|
||||
ldr r6, = STATIC_DUNIT_CTRL_LOW
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3)
|
||||
ldr r6, = STATIC_SDRAM_ADDR_CTRL
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4)
|
||||
ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5)
|
||||
ldr r6, = STATIC_SDRAM_TIME_CTRL_HI
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
|
||||
ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7)
|
||||
ldr r6, = STATIC_SDRAM_ODT_CTRL_HI
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8)
|
||||
ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9)
|
||||
ldr r6, = STATIC_SDRAM_EXT_MODE
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10)
|
||||
|
||||
mov sp, #0
|
||||
bl _mvDramIfConfig
|
||||
1:
|
||||
mov r2, r10
|
||||
mov PC, r11 /* r11 is saved link register */
|
||||
|
||||
#else /* #if !defined(MV_INC_BOARD_DDIM) */
|
||||
|
||||
.globl dramBoot1
|
||||
dramBoot1:
|
||||
.word 0
|
||||
|
||||
/*******************************************************************************
|
||||
* mvDramIfBasicInit - Basic initialization of DRAM interface
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* The function will initialize the DRAM for basic usage. The function
|
||||
* will use the TWSI assembly API to extract DIMM parameters according
|
||||
* to which DRAM interface will be initialized.
|
||||
* The function referes to the following DRAM parameters:
|
||||
* 1) DIMM is registered or not.
|
||||
* 2) DIMM width detection.
|
||||
* 3) DIMM density.
|
||||
*
|
||||
* INPUT:
|
||||
* r3 - required size for initial DRAM.
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* None.
|
||||
*
|
||||
* Note:
|
||||
* r4 holds I2C EEPROM address
|
||||
* r5 holds SDRAM register base address
|
||||
* r7 holds returned values
|
||||
* r8 holds SDRAM various configuration registers value.
|
||||
* r11 holds return function address.
|
||||
*******************************************************************************/
|
||||
/* Setting the offsets of the I2C registers */
|
||||
#define NUM_OF_ROWS_OFFSET 3
|
||||
#define NUM_OF_COLS_OFFSET 4
|
||||
#define NUM_OF_RANKS 5
|
||||
#define SDRAM_WIDTH_OFFSET 13
|
||||
#define NUM_OF_BANKS_OFFSET 17
|
||||
#define SUPPORTED_CL_OFFSET 18
|
||||
#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */
|
||||
#define SDRAM_MODULES_ATTR_OFFSET 21
|
||||
|
||||
#define DRAM_DEV_DENSITY_128M 0x080
|
||||
#define DRAM_DEV_DENSITY_256M 0x100
|
||||
#define DRAM_DEV_DENSITY_512M 0x200
|
||||
.globl _mvDramIfBasicInit
|
||||
.extern _i2cInit
|
||||
|
||||
_mvDramIfBasicInit:
|
||||
|
||||
mov r11, LR /* Save link register */
|
||||
|
||||
mov r5, #1
|
||||
ldr r8, =dramBoot1
|
||||
str r5, [r8] /* We started executing from DRAM */
|
||||
|
||||
/* If we boot from NAND jump to DRAM sddress */
|
||||
ldr r8, dramBoot1
|
||||
cmp r8, #0
|
||||
movne pc, r11
|
||||
|
||||
|
||||
|
||||
bl _i2cInit /* Initialize TWSI master */
|
||||
|
||||
/* Get default SDRAM Config values */
|
||||
MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
|
||||
bic r8, r8, #SDRAM_DCFG_MASK
|
||||
|
||||
|
||||
/* Read device ID */
|
||||
MV_CTRL_MODEL_GET_ASM(r4, r5);
|
||||
|
||||
/* Return if OrionN */
|
||||
ldr r5, =MV_5180_DEV_ID
|
||||
cmp r4, r5
|
||||
beq cat_through_end
|
||||
|
||||
/* Return if Orion1 */
|
||||
ldr r5, =MV_5181_DEV_ID
|
||||
cmp r4, r5
|
||||
beq cat_through_end
|
||||
|
||||
/* Return if Nas */
|
||||
ldr r5, =MV_5182_DEV_ID
|
||||
cmp r4, r5
|
||||
beq cat_through_end
|
||||
|
||||
/* Return if Shark */
|
||||
ldr r5, =MV_8660_DEV_ID
|
||||
cmp r4, r5
|
||||
beq cat_through_end
|
||||
|
||||
/* goto calcConfigReg if bigger than Orion2*/
|
||||
ldr r5, =MV_5281_DEV_ID
|
||||
cmp r4, r5
|
||||
bne cat_through
|
||||
|
||||
cat_through:
|
||||
/* set cat through - for better performance - in orion2 b0 and higher*/
|
||||
orr r8, r8, #SDRAM_CATTHR_EN
|
||||
|
||||
cat_through_end:
|
||||
|
||||
|
||||
/* Get registered/non registered info from DIMM */
|
||||
bl _is_Registered
|
||||
beq nonRegistered
|
||||
|
||||
setRegistered:
|
||||
orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */
|
||||
|
||||
nonRegistered:
|
||||
/* Get SDRAM width */
|
||||
bl _get_width
|
||||
|
||||
orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */
|
||||
cmp r7, #16
|
||||
beq setConfigReg
|
||||
|
||||
orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */
|
||||
cmp r7, #8
|
||||
beq setConfigReg
|
||||
|
||||
/* This is an error. return */
|
||||
b exit_ddrAutoConfig
|
||||
|
||||
setConfigReg:
|
||||
mov r8, r6
|
||||
ldr r6, =SDRAM_CONFIG_DV
|
||||
orr r8, r8, r6 /* Add default settings */
|
||||
mov r6, r8 /* Do not swap r8 content */
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG)
|
||||
|
||||
/* Set maximum CL supported by DIMM */
|
||||
bl _get_CAL
|
||||
|
||||
/* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */
|
||||
clz r6, r7
|
||||
rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */
|
||||
|
||||
/* Check the DDR version */
|
||||
tst r8, #SDRAM_DTYPE_DDR2
|
||||
bne casDdr2
|
||||
|
||||
casDdr1:
|
||||
ldr r7, =3 /* stBurstDel field value */
|
||||
ldr r8, =0x52 /* Assuming MAX CL = 1.5 */
|
||||
cmp r6, #1 /* If CL = 1.5 break */
|
||||
beq setModeReg
|
||||
|
||||
ldr r7, =3 /* stBurstDel field value */
|
||||
ldr r8, =0x22 /* Assuming MAX CL = 2 */
|
||||
cmp r6, #2 /* If CL = 2 break */
|
||||
beq setModeReg
|
||||
|
||||
ldr r7, =4 /* stBurstDel field value */
|
||||
ldr r8, =0x62 /* Assuming MAX CL = 2.5 */
|
||||
cmp r6, #3 /* If CL = 2.5 break */
|
||||
beq setModeReg
|
||||
|
||||
ldr r7, =4 /* stBurstDel field value */
|
||||
ldr r8, =0x32 /* Assuming MAX CL = 3 */
|
||||
cmp r6, #4 /* If CL = 3 break */
|
||||
beq setModeReg
|
||||
|
||||
ldr r7, =5 /* stBurstDel field value */
|
||||
ldr r8, =0x42 /* Assuming MAX CL = 4 */
|
||||
cmp r6, #6 /* If CL = 4 break */
|
||||
b setModeReg
|
||||
|
||||
b exit_ddrAutoConfig /* This is an error !! */
|
||||
|
||||
casDdr2:
|
||||
ldr r7, =4 /* stBurstDel field value */
|
||||
ldr r8, =0x32 /* Assuming MAX CL = 3 */
|
||||
cmp r6, #3 /* If CL = 3 break */
|
||||
beq casDdr2Cont
|
||||
|
||||
ldr r7, =5 /* stBurstDel field value */
|
||||
ldr r8, =0x42 /* Assuming MAX CL = 4 */
|
||||
cmp r6, #4 /* If CL = 4 break */
|
||||
beq casDdr2Cont
|
||||
|
||||
/* CL 5 currently unsupported. We use CL 4 instead */
|
||||
ldr r7, =5 /* stBurstDel field value */
|
||||
ldr r8, =0x42 /* Assuming MAX CL = 5 */
|
||||
cmp r6, #5 /* If CL = 5 break */
|
||||
beq casDdr2Cont
|
||||
|
||||
b exit_ddrAutoConfig /* This is an error !! */
|
||||
casDdr2Cont:
|
||||
/* Write recovery for auto-precharge relevant only in DDR2 */
|
||||
orr r8, r8, #0x400 /* Default value */
|
||||
|
||||
setModeReg:
|
||||
/* The CPU must not attempt to change the SDRAM Mode register setting */
|
||||
/* prior to DRAM controller completion of the DRAM initialization */
|
||||
/* sequence. To guarantee this restriction, it is recommended that */
|
||||
/* the CPU sets the SDRAM Operation register to NOP command, performs */
|
||||
/* read polling until the register is back in Normal operation value, */
|
||||
/* and then sets SDRAM Mode register to it's new value. */
|
||||
|
||||
/* write 'nop' to SDRAM operation */
|
||||
mov r6, #0x5 /* 'NOP' command */
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
|
||||
|
||||
/* poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll1:
|
||||
ldr r6, [r5]
|
||||
cmp r6, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll1
|
||||
|
||||
/* Now its safe to write new value to SDRAM Mode register */
|
||||
MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG)
|
||||
|
||||
/* Make the Dunit write the DRAM its new mode */
|
||||
mov r6, #0x3 /* Mode Register Set command */
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
|
||||
|
||||
/* poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll2:
|
||||
ldr r6, [r5]
|
||||
cmp r6, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll2
|
||||
|
||||
/* Set Dunit control register according to max CL detected */
|
||||
/* If we use registered DIMM, add 1 to stBurstDel */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG)
|
||||
tst r6, #SDRAM_REGISTERED
|
||||
beq setDunitReg
|
||||
add r7, r7, #1
|
||||
|
||||
setDunitReg:
|
||||
ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV
|
||||
orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
|
||||
|
||||
|
||||
/* DIMM density configuration*/
|
||||
/* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */
|
||||
Density:
|
||||
bl _getDensity
|
||||
mov r8, r7
|
||||
mov r8, r8, LSR #20 /* Move density 20 bits to the right */
|
||||
/* For example 0x10000000 --> 0x1000 */
|
||||
|
||||
mov r6, #0x00
|
||||
cmp r8, #DRAM_DEV_DENSITY_128M
|
||||
beq densCont
|
||||
|
||||
mov r6, #0x10
|
||||
cmp r8, #DRAM_DEV_DENSITY_256M
|
||||
beq densCont
|
||||
|
||||
mov r6, #0x20
|
||||
cmp r8, #DRAM_DEV_DENSITY_512M
|
||||
beq densCont
|
||||
|
||||
/* This is an error. return */
|
||||
b exit_ddrAutoConfig
|
||||
|
||||
densCont:
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG)
|
||||
|
||||
/* Config DDR2 registers (Extended mode, ODTs and pad calibration) */
|
||||
MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
|
||||
tst r8, #SDRAM_DTYPE_DDR2
|
||||
beq _extModeODTEnd
|
||||
|
||||
|
||||
/* Set DDR Extended Mode register for working with CS[0] */
|
||||
/* write 'nop' to SDRAM operation */
|
||||
mov r6, #0x5 /* 'NOP' command */
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
|
||||
|
||||
/* poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll3:
|
||||
ldr r6, [r5]
|
||||
cmp r6, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll3
|
||||
|
||||
/* Now its safe to write new value to SDRAM Extended Mode register */
|
||||
ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG)
|
||||
|
||||
/* Make the Dunit write the DRAM its new extended mode */
|
||||
mov r6, #0x4 /* Extended Mode Register Set command */
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
|
||||
|
||||
/* poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll4:
|
||||
ldr r6, [r5]
|
||||
cmp r6, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll4
|
||||
|
||||
/* ODT configuration is done for single bank CS[0] only */
|
||||
/* Config DDR2 On Die Termination (ODT) registers */
|
||||
ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV
|
||||
MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG)
|
||||
|
||||
ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV
|
||||
MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
|
||||
|
||||
ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV
|
||||
MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG)
|
||||
|
||||
|
||||
/* we will check what device we are running and perform
|
||||
Initialization according to device value */
|
||||
|
||||
_extModeODTEnd:
|
||||
|
||||
/* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */
|
||||
/* Does Not Work for Address/Control and Data Pads. */
|
||||
/* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */
|
||||
|
||||
/* Read device ID */
|
||||
MV_CTRL_MODEL_GET_ASM(r6, r5);
|
||||
/* Read device revision */
|
||||
MV_CTRL_REV_GET_ASM(r8, r5);
|
||||
|
||||
/* Continue if OrionN */
|
||||
ldr r5, =MV_5180_DEV_ID
|
||||
cmp r6, r5
|
||||
bne 1f
|
||||
b glMem2End
|
||||
1:
|
||||
|
||||
/* Continue if Orion1 and device revision B1 */
|
||||
ldr r5, =MV_5181_DEV_ID
|
||||
cmp r6, r5
|
||||
bne 1f
|
||||
|
||||
cmp r8, #MV_5181_B1_REV
|
||||
bge glMem2End
|
||||
b glMem2Start
|
||||
1:
|
||||
|
||||
/* Orion NAS */
|
||||
ldr r5, =MV_5182_DEV_ID
|
||||
cmp r6, r5
|
||||
beq glMem2Start
|
||||
|
||||
/* Orion Shark */
|
||||
ldr r5, =MV_8660_DEV_ID
|
||||
cmp r6, r5
|
||||
beq glMem2Start
|
||||
|
||||
b glMem2End
|
||||
|
||||
glMem2Start:
|
||||
|
||||
/* DDR SDRAM Address/Control Pads Calibration */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
|
||||
/* Set Bit [31] to make the register writable */
|
||||
orr r8, r6, #SDRAM_WR_EN
|
||||
|
||||
MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
|
||||
bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
|
||||
bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */
|
||||
bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */
|
||||
bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */
|
||||
|
||||
/* Get the final N locked value of driving strength [22:17] */
|
||||
mov r5, r6
|
||||
mov r5, r5, LSL #9
|
||||
mov r5, r5, LSR #26 /* r5[5:0]<DrvN> = r6[22:17]<LockN> */
|
||||
orr r5, r5, r5, LSL #6 /* r5[11:6]<DrvP> = r5[5:0]<DrvN> */
|
||||
|
||||
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
|
||||
orr r6, r6, r5
|
||||
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
|
||||
|
||||
/* DDR SDRAM Data Pads Calibration */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
|
||||
|
||||
/* Set Bit [31] to make the register writable */
|
||||
orr r8, r6, #SDRAM_WR_EN
|
||||
|
||||
MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG)
|
||||
|
||||
bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
|
||||
bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */
|
||||
bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */
|
||||
bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */
|
||||
|
||||
/* Get the final N locked value of driving strength [22:17] */
|
||||
mov r5, r6
|
||||
mov r5, r5, LSL #9
|
||||
mov r5, r5, LSR #26
|
||||
orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17]<LockN> */
|
||||
|
||||
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
|
||||
orr r6, r6, r5
|
||||
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
|
||||
|
||||
glMem2End:
|
||||
/* Implement Guideline (GL# MEM-3) Drive Strength Value */
|
||||
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
|
||||
|
||||
/* Get SDRAM Config value */
|
||||
MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
|
||||
|
||||
/* Get DIMM type */
|
||||
tst r8, #SDRAM_DTYPE_DDR2
|
||||
beq ddr1StrengthVal
|
||||
|
||||
ddr2StrengthVal:
|
||||
ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
|
||||
ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV
|
||||
b setDrvStrength
|
||||
ddr1StrengthVal:
|
||||
ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
|
||||
ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV
|
||||
|
||||
setDrvStrength:
|
||||
/* DDR SDRAM Address/Control Pads Calibration */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
|
||||
orr r6, r6, #SDRAM_WR_EN /* Make register writeable */
|
||||
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
HTOLL(r6,r5)
|
||||
|
||||
bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
|
||||
bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK
|
||||
orr r6, r4, r6 /* Set default value for DDR */
|
||||
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
|
||||
|
||||
/* DDR SDRAM Data Pads Calibration */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
|
||||
|
||||
orr r6, r6, #SDRAM_WR_EN /* Make register writeable */
|
||||
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
|
||||
HTOLL(r6,r5)
|
||||
|
||||
bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
|
||||
bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK
|
||||
orr r6, r8, r6 /* Set default value for DDR */
|
||||
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
|
||||
|
||||
|
||||
/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
|
||||
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
|
||||
/* Get the "sample on reset" register for the DDR frequancy */
|
||||
|
||||
#if defined(MV_RUN_FROM_FLASH)
|
||||
/* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
|
||||
ldr r7, = _cpuARMDDRCLK
|
||||
ldr r4, =_start
|
||||
ldr r4, [r4]
|
||||
sub r7, r7, r4
|
||||
ldr r4, = Lrom_start_of_data
|
||||
ldr r4, [r4]
|
||||
add r7, r4, r7
|
||||
#else
|
||||
/* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
|
||||
ldr r7, = _cpuARMDDRCLK
|
||||
ldr r4, =_start
|
||||
sub r7, r7, r4
|
||||
add r7, r7, #CFG_MONITOR_BASE
|
||||
#endif
|
||||
/* Get the "sample on reset" register for the DDR frequancy */
|
||||
MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
|
||||
ldr r5, =MSAR_ARMDDRCLCK_MASK
|
||||
and r5, r4, r5
|
||||
#if 0 /* YOTAM TO BE FIX */
|
||||
mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS
|
||||
#endif
|
||||
|
||||
/* Read device ID */
|
||||
MV_CTRL_MODEL_GET_ASM(r6, r8);
|
||||
|
||||
/* Continue if TC90 */
|
||||
ldr r8, =MV_1281_DEV_ID
|
||||
cmp r6, r6
|
||||
beq armClkMsb
|
||||
|
||||
/* Continue if Orion2 */
|
||||
ldr r8, =MV_5281_DEV_ID
|
||||
cmp r6, r8
|
||||
#if 0 /* YOTAM TO BE FIX */
|
||||
bne 1f
|
||||
#endif
|
||||
|
||||
armClkMsb:
|
||||
#if 0 /* YOTAM TO BE FIX */
|
||||
tst r4, #MSAR_ARMDDRCLCK_H_MASK
|
||||
beq 1f
|
||||
orr r5, r5, #BIT4
|
||||
1:
|
||||
ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE
|
||||
mul r5, r4, r5
|
||||
add r7, r7, r5
|
||||
add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF
|
||||
ldr r5, [r7]
|
||||
#endif
|
||||
|
||||
/* Get SDRAM Config value */
|
||||
MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG)
|
||||
|
||||
/* Get DIMM type */
|
||||
tst r8, #SDRAM_DTYPE_DDR2
|
||||
beq ddr1FtdllVal
|
||||
|
||||
ddr2FtdllVal:
|
||||
ldr r4, =FTDLL_DDR2_250MHZ
|
||||
ldr r7, =_250MHz
|
||||
cmp r5, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR2_200MHZ
|
||||
ldr r7, =_200MHz
|
||||
cmp r5, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR2_166MHZ
|
||||
ldr r7, =_166MHz
|
||||
cmp r5, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR2_133MHZ
|
||||
b setFtdllReg
|
||||
|
||||
ddr1FtdllVal:
|
||||
ldr r4, =FTDLL_DDR1_200MHZ
|
||||
ldr r7, =_200MHz
|
||||
cmp r5, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR1_166MHZ
|
||||
ldr r7, =_166MHz
|
||||
cmp r5, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR1_133MHZ
|
||||
ldr r7, =_133MHz
|
||||
cmp r5, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =0
|
||||
|
||||
setFtdllReg:
|
||||
|
||||
#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)
|
||||
MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
|
||||
orr r8, r8, r4
|
||||
MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
|
||||
bic r8, r8, #1
|
||||
MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
|
||||
#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/
|
||||
|
||||
|
||||
setTimingReg:
|
||||
/* Set default Timing parameters */
|
||||
MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
|
||||
tst r8, #SDRAM_DTYPE_DDR2
|
||||
bne ddr2TimeParam
|
||||
|
||||
ddr1TimeParam:
|
||||
ldr r6, =DDR1_TIMING_LOW_DV
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG)
|
||||
ldr r6, =DDR1_TIMING_HIGH_DV
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG)
|
||||
b timeParamDone
|
||||
|
||||
ddr2TimeParam:
|
||||
ldr r6, =DDR2_TIMING_LOW_DV
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG)
|
||||
ldr r6, =DDR2_TIMING_HIGH_DV
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG)
|
||||
|
||||
timeParamDone:
|
||||
/* Open CS[0] window to requested size and enable it. Disable other */
|
||||
/* windows */
|
||||
ldr r6, =SCBAR_BASE_MASK
|
||||
sub r3, r3, #1
|
||||
and r3, r3, r6
|
||||
orr r3, r3, #1 /* Enable bank */
|
||||
MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0))
|
||||
ldr r6, =0
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1))
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2))
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3))
|
||||
|
||||
exit_ddrAutoConfig:
|
||||
mov PC, r11 /* r11 is saved link register */
|
||||
|
||||
|
||||
/***************************************************************************************/
|
||||
/* r4 holds I2C EEPROM address
|
||||
* r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value
|
||||
* r8 holds SDRAM various configuration registers value.
|
||||
* r13 holds Link register
|
||||
*/
|
||||
/**************************/
|
||||
_getDensity:
|
||||
mov r13, LR /* Save link register */
|
||||
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */
|
||||
bl _i2cRead
|
||||
mov r8, r7 /* r8 save number of rows */
|
||||
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */
|
||||
bl _i2cRead
|
||||
add r8, r8, r7 /* r8 = number of rows + number of col */
|
||||
|
||||
mov r7, #0x1
|
||||
mov r8, r7, LSL r8 /* r8 = (1 << r8) */
|
||||
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */
|
||||
bl _i2cRead
|
||||
mul r8, r7, r8
|
||||
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */
|
||||
bl _i2cRead
|
||||
mul r7, r8, r7
|
||||
|
||||
mov PC, r13
|
||||
|
||||
/**************************/
|
||||
_get_width:
|
||||
mov r13, LR /* Save link register */
|
||||
|
||||
/* Get SDRAM width (SPD offset 13) */
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #SDRAM_WIDTH_OFFSET
|
||||
bl _i2cRead /* result in r7 */
|
||||
|
||||
mov PC, r13
|
||||
|
||||
/**************************/
|
||||
_get_CAL:
|
||||
mov r13, LR /* Save link register */
|
||||
|
||||
/* Set maximum CL supported by DIMM */
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */
|
||||
bl _i2cRead
|
||||
|
||||
mov PC, r13
|
||||
|
||||
/**************************/
|
||||
/* R8 - sdram configuration register.
|
||||
* Return value in flag if no-registered then Z-flag is set
|
||||
*/
|
||||
_is_Registered:
|
||||
mov r13, LR /* Save link register */
|
||||
|
||||
/* Get registered/non registered info from DIMM */
|
||||
tst r8, #SDRAM_DTYPE_DDR2
|
||||
bne regDdr2
|
||||
|
||||
regDdr1:
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #SDRAM_MODULES_ATTR_OFFSET
|
||||
bl _i2cRead /* result in r7 */
|
||||
tst r7, #0x2
|
||||
b exit
|
||||
regDdr2:
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #DIMM_TYPE_INFO_OFFSET
|
||||
bl _i2cRead /* result in r7 */
|
||||
tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */
|
||||
/* or Mini-RDIMM (0x10) */
|
||||
exit:
|
||||
mov PC, r13
|
||||
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,668 @@
|
||||
/*******************************************************************************
|
||||
Copyright (C) Marvell International Ltd. and its affiliates
|
||||
|
||||
This software file (the "File") is owned and distributed by Marvell
|
||||
International Ltd. and/or its affiliates ("Marvell") under the following
|
||||
alternative licensing terms. Once you have made an election to distribute the
|
||||
File under one of the following license alternatives, please (i) delete this
|
||||
introductory statement regarding license alternatives, (ii) delete the two
|
||||
license alternatives that you have not elected to use and (iii) preserve the
|
||||
Marvell copyright notice above.
|
||||
|
||||
********************************************************************************
|
||||
Marvell Commercial License Option
|
||||
|
||||
If you received this File from Marvell and you have entered into a commercial
|
||||
license agreement (a "Commercial License") with Marvell, the File is licensed
|
||||
to you under the terms of the applicable Commercial License.
|
||||
|
||||
********************************************************************************
|
||||
Marvell GPL License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File in accordance with the terms and conditions of the General
|
||||
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
|
||||
available along with the File in the license.txt file or by writing to the Free
|
||||
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
|
||||
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
|
||||
|
||||
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
|
||||
DISCLAIMED. The GPL License provides additional details about this warranty
|
||||
disclaimer.
|
||||
********************************************************************************
|
||||
Marvell BSD License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File under the following licensing terms.
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of Marvell nor the names of its contributors may be
|
||||
used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* mvDramIfBasicAsm.s
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* Memory full detection and best timing configuration is done in
|
||||
* C code. C runtime environment requires a stack. This module API
|
||||
* initialize DRAM interface chip select 0 for basic functionality for
|
||||
* the use of stack.
|
||||
* The module API assumes DRAM information is stored in I2C EEPROM reside
|
||||
* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM
|
||||
* internal data structure is assumed to be orgenzied in common DRAM
|
||||
* vendor SPD structure.
|
||||
* NOTE: DFCDL values are assumed to be already initialized prior to
|
||||
* this module API activity.
|
||||
*
|
||||
*
|
||||
* DEPENDENCIES:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/* includes */
|
||||
#define MV_ASMLANGUAGE
|
||||
#include "mvOsAsm.h"
|
||||
#include "mvSysHwConfig.h"
|
||||
#include "mvDramIfRegs.h"
|
||||
#include "mvDramIfConfig.h"
|
||||
#include "mvCpuIfRegs.h"
|
||||
#include "pex/mvPexRegs.h"
|
||||
#include "pci/mvPciRegs.h"
|
||||
#include "mvCtrlEnvSpec.h"
|
||||
#include "mvCtrlEnvAsm.h"
|
||||
#include "cpu/mvCpuArm.h"
|
||||
#include "mvCommon.h"
|
||||
|
||||
/* defines */
|
||||
|
||||
/* locals */
|
||||
.data
|
||||
.globl _mvDramIfConfig
|
||||
|
||||
.text
|
||||
|
||||
/*******************************************************************************
|
||||
* _mvDramIfConfig - Basic DRAM interface initialization.
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* The function will initialize the following DRAM parameters using the
|
||||
* values prepared by mvDramIfDetect routine. Values are located
|
||||
* in predefined registers.
|
||||
*
|
||||
* INPUT:
|
||||
* None.
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
_mvDramIfConfig:
|
||||
|
||||
/* Save register on stack */
|
||||
cmp sp, #0
|
||||
beq no_stack_s
|
||||
save_on_stack:
|
||||
stmdb sp!, {r1, r2, r3, r4, r7, r11}
|
||||
no_stack_s:
|
||||
|
||||
/* 1) Write to SDRAM coniguration register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 2) Write Dunit control low register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 3) Write SDRAM address control register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 4) Write SDRAM bank 0 size register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0))
|
||||
str r4, [r1]
|
||||
|
||||
/* 5) Write SDRAM open pages control register */
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG)
|
||||
ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV
|
||||
str r4, [r1]
|
||||
|
||||
/* 6) Write SDRAM timing Low register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 7) Write SDRAM timing High register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 8) Write SDRAM mode register */
|
||||
/* The CPU must not attempt to change the SDRAM Mode register setting */
|
||||
/* prior to DRAM controller completion of the DRAM initialization */
|
||||
/* sequence. To guarantee this restriction, it is recommended that */
|
||||
/* the CPU sets the SDRAM Operation register to NOP command, performs */
|
||||
/* read polling until the register is back in Normal operation value, */
|
||||
/* and then sets SDRAM Mode register to it’s new value. */
|
||||
|
||||
/* 8.1 write 'nop' to SDRAM operation */
|
||||
mov r4, #0x5 /* 'NOP' command */
|
||||
MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG)
|
||||
|
||||
/* 8.2 poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll1:
|
||||
ldr r4, [r1]
|
||||
cmp r4, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll1
|
||||
|
||||
/* 8.3 Now its safe to write new value to SDRAM Mode register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 8.4 Make the Dunit write the DRAM its new mode */
|
||||
mov r4, #0x3 /* Mode Register Set command */
|
||||
MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
|
||||
|
||||
/* 8.5 poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll2:
|
||||
ldr r4, [r1]
|
||||
cmp r4, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll2
|
||||
|
||||
#ifndef DB_FPGA
|
||||
/* Config DDR2 registers (Extended mode, ODTs and pad calibration) */
|
||||
MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG)
|
||||
tst r4, #SDRAM_DTYPE_DDR2
|
||||
beq _extModeODTEnd
|
||||
#endif /* DB_FPGA */
|
||||
|
||||
/* 9) Write SDRAM Extended mode register This operation should be */
|
||||
/* done for each memory bank */
|
||||
/* write 'nop' to SDRAM operation */
|
||||
mov r4, #0x5 /* 'NOP' command */
|
||||
MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
|
||||
|
||||
/* poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll3:
|
||||
ldr r4, [r1]
|
||||
cmp r4, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll3
|
||||
|
||||
/* Now its safe to write new value to SDRAM Extended Mode register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* Go over each of the Banks */
|
||||
ldr r3, =0 /* r3 = DRAM bank Num */
|
||||
|
||||
extModeLoop:
|
||||
/* Set the SDRAM Operation Control to each of the DRAM banks */
|
||||
mov r2, r3 /* Do not swap the bank counter value */
|
||||
MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG)
|
||||
|
||||
/* Make the Dunit write the DRAM its new mode */
|
||||
mov r4, #0x4 /* Extended Mode Register Set command */
|
||||
MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
|
||||
|
||||
/* poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll4:
|
||||
ldr r4, [r1]
|
||||
cmp r4, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll4
|
||||
#ifndef DB_FPGA
|
||||
add r3, r3, #1
|
||||
cmp r3, #4 /* 4 = Number of banks */
|
||||
bne extModeLoop
|
||||
|
||||
extModeEnd:
|
||||
/* Config DDR2 On Die Termination (ODT) registers */
|
||||
/* Write SDRAM DDR2 ODT control low register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* Write SDRAM DDR2 ODT control high register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* Write SDRAM DDR2 Dunit ODT control register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG)
|
||||
str r4, [r1]
|
||||
|
||||
#endif /* DB_FPGA */
|
||||
_extModeODTEnd:
|
||||
#ifndef DB_FPGA
|
||||
/* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */
|
||||
/* Does Not Work for Address/Control and Data Pads. */
|
||||
/* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */
|
||||
|
||||
/* Read device ID */
|
||||
MV_CTRL_MODEL_GET_ASM(r3, r1);
|
||||
/* Read device revision */
|
||||
MV_CTRL_REV_GET_ASM(r2, r1);
|
||||
|
||||
/* Continue if OrionN */
|
||||
ldr r1, =MV_5180_DEV_ID
|
||||
cmp r3, r1
|
||||
bne 1f
|
||||
b glMem2End
|
||||
1:
|
||||
/* Continue if Orion1 and device revision B1 */
|
||||
ldr r1, =MV_5181_DEV_ID
|
||||
cmp r3, r1
|
||||
bne 1f
|
||||
|
||||
cmp r2, #MV_5181_B1_REV
|
||||
bge glMem2End
|
||||
b glMem2Start
|
||||
1:
|
||||
|
||||
/* Orion NAS */
|
||||
ldr r1, =MV_5182_DEV_ID
|
||||
cmp r3, r1
|
||||
beq glMem2Start
|
||||
|
||||
/* Orion NAS */
|
||||
ldr r1, =MV_5082_DEV_ID
|
||||
cmp r3, r1
|
||||
beq glMem2Start
|
||||
|
||||
/* Orion Shark */
|
||||
ldr r1, =MV_8660_DEV_ID
|
||||
cmp r3, r1
|
||||
beq glMem2Start
|
||||
|
||||
b glMem2End
|
||||
|
||||
glMem2Start:
|
||||
|
||||
/* DDR SDRAM Address/Control Pads Calibration */
|
||||
MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
|
||||
/* Set Bit [31] to make the register writable */
|
||||
orr r2, r3, #SDRAM_WR_EN
|
||||
|
||||
MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
|
||||
bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
|
||||
bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */
|
||||
bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */
|
||||
bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */
|
||||
|
||||
/* Get the final N locked value of driving strength [22:17] */
|
||||
mov r1, r3
|
||||
mov r1, r1, LSL #9
|
||||
mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
|
||||
orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
|
||||
|
||||
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
|
||||
orr r3, r3, r1
|
||||
|
||||
MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
|
||||
|
||||
/* DDR SDRAM Data Pads Calibration */
|
||||
MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
|
||||
|
||||
/* Set Bit [31] to make the register writable */
|
||||
orr r2, r3, #SDRAM_WR_EN
|
||||
|
||||
MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG)
|
||||
|
||||
bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
|
||||
bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */
|
||||
bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */
|
||||
bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */
|
||||
|
||||
/* Get the final N locked value of driving strength [22:17] */
|
||||
mov r1, r3
|
||||
mov r1, r1, LSL #9
|
||||
mov r1, r1, LSR #26
|
||||
orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
|
||||
|
||||
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
|
||||
orr r3, r3, r1
|
||||
|
||||
MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
|
||||
|
||||
glMem2End:
|
||||
|
||||
|
||||
/* Implement Guideline (GL# MEM-3) Drive Strength Value */
|
||||
/* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */
|
||||
/* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */
|
||||
|
||||
/* Get SDRAM Config value */
|
||||
MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG)
|
||||
|
||||
/* Get DIMM type */
|
||||
tst r2, #SDRAM_DTYPE_DDR2
|
||||
beq ddr1StrengthVal
|
||||
|
||||
ddr2StrengthVal:
|
||||
ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
|
||||
ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV
|
||||
b setDrvStrength
|
||||
ddr1StrengthVal:
|
||||
ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
|
||||
ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV
|
||||
|
||||
setDrvStrength:
|
||||
/* DDR SDRAM Address/Control Pads Calibration */
|
||||
MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
|
||||
orr r3, r3, #SDRAM_WR_EN /* Make register writeable */
|
||||
|
||||
MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
HTOLL(r3,r1)
|
||||
|
||||
bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
|
||||
bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK
|
||||
orr r3, r4, r3 /* Set default value for DDR */
|
||||
|
||||
MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
||||
|
||||
|
||||
/* DDR SDRAM Data Pads Calibration */
|
||||
MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
|
||||
|
||||
orr r3, r3, #SDRAM_WR_EN /* Make register writeable */
|
||||
|
||||
MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
|
||||
HTOLL(r3,r1)
|
||||
|
||||
bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
|
||||
bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK
|
||||
orr r3, r2, r3 /* Set default value for DDR */
|
||||
|
||||
MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
|
||||
|
||||
#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)
|
||||
/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
|
||||
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */
|
||||
/* 88F5082, 88F5181L, 88F6082/L */
|
||||
|
||||
/* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
|
||||
ldr r7, = _cpuARMDDRCLK
|
||||
ldr r4, =_start
|
||||
sub r7, r7, r4
|
||||
add r7, r7, #CFG_MONITOR_BASE
|
||||
|
||||
/* Get the "sample on reset" register for the DDR frequancy */
|
||||
MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET)
|
||||
ldr r1, =MSAR_ARMDDRCLCK_MASK
|
||||
and r1, r4, r1
|
||||
#if 0 /* YOTAM TO BE FIX */
|
||||
mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS
|
||||
#endif
|
||||
|
||||
/* Read device ID */
|
||||
MV_CTRL_MODEL_GET_ASM(r3, r2);
|
||||
|
||||
/* Continue if TC90 */
|
||||
ldr r2, =MV_1281_DEV_ID
|
||||
cmp r3, r2
|
||||
beq armClkMsb
|
||||
|
||||
/* Continue if Orion2 */
|
||||
ldr r2, =MV_5281_DEV_ID
|
||||
cmp r3, r2
|
||||
#if 0 /* YOTAM TO BE FIX */
|
||||
bne 1f
|
||||
#endif
|
||||
|
||||
armClkMsb:
|
||||
#if 0 /* YOTAM TO BE FIX */
|
||||
tst r4, #MSAR_ARMDDRCLCK_H_MASK
|
||||
beq 1f
|
||||
orr r1, r1, #BIT4
|
||||
1:
|
||||
ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE
|
||||
mul r1, r4, r1
|
||||
add r7, r7, r1
|
||||
add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF
|
||||
ldr r1, [r7]
|
||||
#endif
|
||||
|
||||
/* Get SDRAM Config value */
|
||||
MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG)
|
||||
|
||||
/* Get DIMM type */
|
||||
tst r2, #SDRAM_DTYPE_DDR2
|
||||
beq ddr1FtdllVal
|
||||
|
||||
ddr2FtdllVal:
|
||||
ldr r2, =MV_5281_DEV_ID
|
||||
cmp r3, r2
|
||||
bne 2f
|
||||
MV_CTRL_REV_GET_ASM(r3, r2)
|
||||
cmp r3, #MV_5281_D0_REV
|
||||
beq orin2_d0_ddr2_ftdll_val
|
||||
cmp r3, #MV_5281_D1_REV
|
||||
beq orin2_d1_ddr2_ftdll_val
|
||||
cmp r3, #MV_5281_D2_REV
|
||||
beq orin2_d1_ddr2_ftdll_val
|
||||
b ddr2_default_val
|
||||
|
||||
/* Set Orion 2 D1 ftdll values for DDR2 */
|
||||
orin2_d1_ddr2_ftdll_val:
|
||||
ldr r4, =FTDLL_DDR2_250MHZ_5281_D1
|
||||
ldr r7, =_250MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR2_200MHZ_5281_D1
|
||||
ldr r7, =_200MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR2_166MHZ_5281_D0
|
||||
ldr r7, =_166MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
b ddr2_default_val
|
||||
|
||||
/* Set Orion 2 D0 ftdll values for DDR2 */
|
||||
orin2_d0_ddr2_ftdll_val:
|
||||
ldr r4, =FTDLL_DDR2_250MHZ_5281_D0
|
||||
ldr r7, =_250MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR2_200MHZ_5281_D0
|
||||
ldr r7, =_200MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR2_166MHZ_5281_D0
|
||||
ldr r7, =_166MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
b ddr2_default_val
|
||||
2:
|
||||
ldr r2, =MV_5182_DEV_ID
|
||||
cmp r3, r2
|
||||
bne 3f
|
||||
|
||||
/* Set Orion nas ftdll values for DDR2 */
|
||||
orin_nas_ftdll_val:
|
||||
ldr r4, =FTDLL_DDR2_166MHZ_5182
|
||||
ldr r7, =_166MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
|
||||
/* default values for all other devices */
|
||||
3:
|
||||
ddr2_default_val:
|
||||
ldr r4, =FTDLL_DDR2_250MHZ
|
||||
ldr r7, =_250MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR2_200MHZ
|
||||
ldr r7, =_200MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR2_166MHZ
|
||||
ldr r7, =_166MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR2_133MHZ
|
||||
ldr r7, =_133MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =0
|
||||
b setFtdllReg
|
||||
|
||||
ddr1FtdllVal:
|
||||
ldr r2, =MV_5281_DEV_ID
|
||||
cmp r3, r2
|
||||
bne 2f
|
||||
MV_CTRL_REV_GET_ASM(r3, r2)
|
||||
cmp r3, #MV_5281_D0_REV
|
||||
bge orin2_ddr1_ftdll_val
|
||||
b ddr1_default_val
|
||||
|
||||
/* Set Orion 2 D0 and above ftdll values for DDR1 */
|
||||
orin2_ddr1_ftdll_val:
|
||||
ldr r4, =FTDLL_DDR1_200MHZ_5281_D0
|
||||
ldr r7, =_200MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
ldr r4, =FTDLL_DDR1_166MHZ_5281_D0
|
||||
ldr r7, =_166MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
b ddr1_default_val
|
||||
2:
|
||||
ldr r2, =MV_5181_DEV_ID
|
||||
cmp r3, r2
|
||||
bne 3f
|
||||
MV_CTRL_REV_GET_ASM(r3, r2)
|
||||
cmp r3, #MV_5181_B1_REV
|
||||
bge orin1_ddr1_ftdll_val
|
||||
b ddr1_default_val
|
||||
|
||||
/* Set Orion 1 ftdll values for DDR1 */
|
||||
orin1_ddr1_ftdll_val:
|
||||
ldr r4, =FTDLL_DDR1_166MHZ_5181_B1
|
||||
ldr r7, =_166MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
3:
|
||||
ddr1_default_val:
|
||||
ldr r4, =FTDLL_DDR1_133MHZ
|
||||
ldr r7, =_133MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
|
||||
ldr r4, =FTDLL_DDR1_166MHZ
|
||||
ldr r7, =_166MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
|
||||
ldr r4, =FTDLL_DDR1_200MHZ
|
||||
ldr r7, =_200MHz
|
||||
cmp r1, r7
|
||||
beq setFtdllReg
|
||||
|
||||
ldr r4, =0
|
||||
|
||||
setFtdllReg:
|
||||
|
||||
MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG)
|
||||
HTOLL(r4,r1)
|
||||
bic r4, r4, #1
|
||||
MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG)
|
||||
|
||||
#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */
|
||||
#endif /* DB_FPGA */
|
||||
|
||||
restoreTmpRegs:
|
||||
/* Restore the registers we used to save the DDR detect values */
|
||||
|
||||
ldr r4, =DRAM_BUF_REG0_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0)
|
||||
|
||||
ldr r4, =DRAM_BUF_REG1_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1)
|
||||
|
||||
ldr r4, =DRAM_BUF_REG2_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2)
|
||||
|
||||
ldr r4, =DRAM_BUF_REG3_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3)
|
||||
|
||||
ldr r4, =DRAM_BUF_REG4_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4)
|
||||
|
||||
ldr r4, =DRAM_BUF_REG5_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5)
|
||||
|
||||
ldr r4, =DRAM_BUF_REG6_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6)
|
||||
|
||||
ldr r4, =DRAM_BUF_REG7_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7)
|
||||
|
||||
ldr r4, =DRAM_BUF_REG8_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8)
|
||||
|
||||
ldr r4, =DRAM_BUF_REG9_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9)
|
||||
|
||||
ldr r4, =DRAM_BUF_REG10_DV
|
||||
MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10)
|
||||
|
||||
|
||||
/* Restore registers */
|
||||
/* Save register on stack */
|
||||
cmp sp, #0
|
||||
beq no_stack_l
|
||||
load_from_stack:
|
||||
ldmia sp!, {r1, r2, r3, r4, r7, r11}
|
||||
no_stack_l:
|
||||
|
||||
mov pc, lr
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.4
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,986 @@
|
||||
/*******************************************************************************
|
||||
Copyright (C) Marvell International Ltd. and its affiliates
|
||||
|
||||
This software file (the "File") is owned and distributed by Marvell
|
||||
International Ltd. and/or its affiliates ("Marvell") under the following
|
||||
alternative licensing terms. Once you have made an election to distribute the
|
||||
File under one of the following license alternatives, please (i) delete this
|
||||
introductory statement regarding license alternatives, (ii) delete the two
|
||||
license alternatives that you have not elected to use and (iii) preserve the
|
||||
Marvell copyright notice above.
|
||||
|
||||
********************************************************************************
|
||||
Marvell Commercial License Option
|
||||
|
||||
If you received this File from Marvell and you have entered into a commercial
|
||||
license agreement (a "Commercial License") with Marvell, the File is licensed
|
||||
to you under the terms of the applicable Commercial License.
|
||||
|
||||
********************************************************************************
|
||||
Marvell GPL License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File in accordance with the terms and conditions of the General
|
||||
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
|
||||
available along with the File in the license.txt file or by writing to the Free
|
||||
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
|
||||
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
|
||||
|
||||
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
|
||||
DISCLAIMED. The GPL License provides additional details about this warranty
|
||||
disclaimer.
|
||||
********************************************************************************
|
||||
Marvell BSD License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File under the following licensing terms.
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of Marvell nor the names of its contributors may be
|
||||
used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#define _ASMLANGUAGE
|
||||
#define MV_ASMLANGUAGE
|
||||
#include "mvSysHwConfig.h"
|
||||
#include "mvOsAsm.h"
|
||||
#include "boardEnv/mvBoardEnvSpec.h"
|
||||
#include "ctrlEnv/sys/mvCpuIfRegs.h"
|
||||
#include "mvDramIfConfig.h"
|
||||
#include "mvDramIfRegs.h"
|
||||
#include "pex/mvPexRegs.h"
|
||||
#include "ctrlEnv/mvCtrlEnvSpec.h"
|
||||
#include "ctrlEnv/mvCtrlEnvAsm.h"
|
||||
#include "mvCommon.h"
|
||||
|
||||
/* defines */
|
||||
|
||||
#if defined(MV_STATIC_DRAM_ON_BOARD)
|
||||
.globl dramBoot1
|
||||
dramBoot1:
|
||||
.word 0
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
*
|
||||
*
|
||||
*
|
||||
*******************************************************************************/
|
||||
#if defined(DB_MV78XX0) || defined(DB_MV88F632X)
|
||||
/* DDR2 boards 512MB 333MHz */
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
|
||||
#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */
|
||||
#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
|
||||
#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */
|
||||
#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
|
||||
#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
|
||||
#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
|
||||
|
||||
#elif defined(RD_MV78XX0_AMC)
|
||||
/* On board DDR2 512MB 400MHz CL5 */
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
|
||||
#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */
|
||||
#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
|
||||
#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
|
||||
#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
|
||||
#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
|
||||
#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
|
||||
|
||||
#elif defined(RD_MV78XX0_H3C)
|
||||
/* DDR2 boards 512MB 333MHz */
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
|
||||
#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */
|
||||
#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
|
||||
#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
|
||||
#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
|
||||
#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
|
||||
#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
|
||||
|
||||
#elif defined(RD_MV78XX0_PCAC)
|
||||
/* DDR2 boards 256MB 200MHz */
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */
|
||||
#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */
|
||||
#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
|
||||
#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
|
||||
#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
|
||||
#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
|
||||
#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
|
||||
|
||||
#else
|
||||
/* DDR2 MV88F6281 boards 256MB 400MHz */
|
||||
#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */
|
||||
#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */
|
||||
#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */
|
||||
#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */
|
||||
#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */
|
||||
#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */
|
||||
#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */
|
||||
#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */
|
||||
#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */
|
||||
#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
|
||||
#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */
|
||||
#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */
|
||||
#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
|
||||
#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
|
||||
#endif /* MV78XX0 */
|
||||
|
||||
.globl _mvDramIfStaticInit
|
||||
_mvDramIfStaticInit:
|
||||
|
||||
mov r11, LR /* Save link register */
|
||||
mov r10, r2
|
||||
|
||||
#ifdef MV78XX0
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
|
||||
orr r6, r6, #BIT4 /* Enable 2T mode */
|
||||
bic r6, r6, #BIT6 /* clear ctrlPos */
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
|
||||
#endif
|
||||
|
||||
/*DDR SDRAM Initialization Control */
|
||||
ldr r6, =DSICR_INIT_EN
|
||||
MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
|
||||
2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
|
||||
and r6, r6, #DSICR_INIT_EN
|
||||
cmp r6, #0
|
||||
bne 2b
|
||||
|
||||
/* If we boot from NAND jump to DRAM address */
|
||||
mov r5, #1
|
||||
ldr r6, =dramBoot1
|
||||
str r5, [r6] /* We started executing from DRAM */
|
||||
|
||||
ldr r6, dramBoot1
|
||||
cmp r6, #0
|
||||
bne 1f
|
||||
|
||||
/* set all dram windows to 0 */
|
||||
mov r6, #0
|
||||
MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0))
|
||||
MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1))
|
||||
MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2))
|
||||
MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3))
|
||||
ldr r6, = STATIC_SDRAM0_BANK0_SIZE
|
||||
MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0))
|
||||
|
||||
|
||||
/* set all dram configuration in temp registers */
|
||||
ldr r6, = STATIC_SDRAM0_BANK0_SIZE
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0)
|
||||
ldr r6, = STATIC_SDRAM_CONFIG
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1)
|
||||
ldr r6, = STATIC_SDRAM_MODE
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2)
|
||||
ldr r6, = STATIC_DUNIT_CTRL_LOW
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3)
|
||||
ldr r6, = STATIC_SDRAM_ADDR_CTRL
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4)
|
||||
ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5)
|
||||
ldr r6, = STATIC_SDRAM_TIME_CTRL_HI
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
|
||||
ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7)
|
||||
ldr r6, = STATIC_SDRAM_ODT_CTRL_HI
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8)
|
||||
ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9)
|
||||
ldr r6, = STATIC_SDRAM_EXT_MODE
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10)
|
||||
ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11)
|
||||
ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12)
|
||||
#ifndef MV_NAND_BOOT
|
||||
ldr r6, = STATIC_DUNIT_CTRL_HI
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13)
|
||||
#endif
|
||||
|
||||
ldr sp,=0
|
||||
bl _mvDramIfConfig
|
||||
ldr r0, =0
|
||||
#ifdef MV78XX0
|
||||
bl _mvDramIfEccMemInit
|
||||
#endif
|
||||
1:
|
||||
mov r2, r10
|
||||
mov PC, r11 /* r11 is saved link register */
|
||||
|
||||
#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */
|
||||
|
||||
.globl dramBoot1
|
||||
dramBoot1:
|
||||
.word 0
|
||||
|
||||
/*******************************************************************************
|
||||
* mvDramIfBasicInit - Basic initialization of DRAM interface
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* The function will initialize the DRAM for basic usage. The function
|
||||
* will use the TWSI assembly API to extract DIMM parameters according
|
||||
* to which DRAM interface will be initialized.
|
||||
* The function referes to the following DRAM parameters:
|
||||
* 1) DIMM is registered or not.
|
||||
* 2) DIMM width detection.
|
||||
* 3) DIMM density.
|
||||
*
|
||||
* INPUT:
|
||||
* r3 - required size for initial DRAM.
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* None.
|
||||
*
|
||||
* Note:
|
||||
* r4 holds I2C EEPROM address
|
||||
* r5 holds SDRAM register base address
|
||||
* r7 holds returned values
|
||||
* r8 holds SDRAM various configuration registers value.
|
||||
* r11 holds return function address.
|
||||
*******************************************************************************/
|
||||
/* Setting the offsets of the I2C registers */
|
||||
#define DIMM_TYPE_OFFSET 2
|
||||
#define NUM_OF_ROWS_OFFSET 3
|
||||
#define NUM_OF_COLS_OFFSET 4
|
||||
#define NUM_OF_RANKS 5
|
||||
#define DIMM_CONFIG_TYPE 11
|
||||
#define SDRAM_WIDTH_OFFSET 13
|
||||
#define NUM_OF_BANKS_OFFSET 17
|
||||
#define SUPPORTED_CL_OFFSET 18
|
||||
#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */
|
||||
#define SDRAM_MODULES_ATTR_OFFSET 21
|
||||
#define RANK_SIZE_OFFSET 31
|
||||
|
||||
#define DRAM_DEV_DENSITY_128M 128
|
||||
#define DRAM_DEV_DENSITY_256M 256
|
||||
#define DRAM_DEV_DENSITY_512M 512
|
||||
#define DRAM_DEV_DENSITY_1G 1024
|
||||
#define DRAM_DEV_DENSITY_2G 2048
|
||||
|
||||
#define DRAM_RANK_DENSITY_128M 0x20
|
||||
#define DRAM_RANK_DENSITY_256M 0x40
|
||||
#define DRAM_RANK_DENSITY_512M 0x80
|
||||
#define DRAM_RANK_DENSITY_1G 0x1
|
||||
#define DRAM_RANK_DENSITY_2G 0x2
|
||||
|
||||
.globl _mvDramIfBasicInit
|
||||
.extern _i2cInit
|
||||
_mvDramIfBasicInit:
|
||||
|
||||
mov r11, LR /* Save link register */
|
||||
|
||||
/* Set Dunit high control register */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
|
||||
orr r6, r6, #BIT7 /* SDRAM__D2P_EN */
|
||||
orr r6, r6, #BIT8 /* SDRAM__P2D_EN */
|
||||
#ifdef MV78XX0
|
||||
orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */
|
||||
orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */
|
||||
orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */
|
||||
#endif
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
|
||||
|
||||
#ifdef MV78XX0
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
|
||||
orr r6, r6, #BIT4 /* Enable 2T mode */
|
||||
bic r6, r6, #BIT6 /* clear ctrlPos */
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
|
||||
#endif
|
||||
|
||||
/*DDR SDRAM Initialization Control */
|
||||
ldr r6, =DSICR_INIT_EN
|
||||
MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
|
||||
2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
|
||||
and r6, r6, #DSICR_INIT_EN
|
||||
cmp r6, #0
|
||||
bne 2b
|
||||
|
||||
mov r5, #1
|
||||
ldr r8, =dramBoot1
|
||||
str r5, [r8] /* We started executing from DRAM */
|
||||
|
||||
/* If we boot from NAND jump to DRAM address */
|
||||
ldr r8, dramBoot1
|
||||
cmp r8, #0
|
||||
movne pc, r11
|
||||
|
||||
bl _i2cInit /* Initialize TWSI master */
|
||||
|
||||
/* Check if we have more then 1 dimm */
|
||||
ldr r6, =0
|
||||
MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14)
|
||||
#ifdef MV78XX0
|
||||
bl _is_Second_Dimm_Exist
|
||||
beq single_dimm
|
||||
ldr r6, =1
|
||||
MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14)
|
||||
single_dimm:
|
||||
bl _i2cInit /* Initialize TWSI master */
|
||||
#endif
|
||||
|
||||
/* Get default SDRAM Config values */
|
||||
MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
|
||||
|
||||
/* Get registered/non registered info from DIMM */
|
||||
bl _is_Registered
|
||||
beq nonRegistered
|
||||
|
||||
setRegistered:
|
||||
orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */
|
||||
nonRegistered:
|
||||
#ifdef MV78XX0
|
||||
/* Get ECC/non ECC info from DIMM */
|
||||
bl _is_Ecc
|
||||
beq setConfigReg
|
||||
|
||||
setEcc:
|
||||
orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */
|
||||
#endif
|
||||
setConfigReg:
|
||||
MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1)
|
||||
|
||||
/* Set maximum CL supported by DIMM */
|
||||
bl _get_CAL
|
||||
|
||||
/* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */
|
||||
clz r6, r7
|
||||
rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */
|
||||
|
||||
casDdr2:
|
||||
ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */
|
||||
ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/
|
||||
ldr r8, =0x32 /* Assuming MAX CL = 3 */
|
||||
cmp r6, #3 /* If CL = 3 break */
|
||||
beq casDdr2Cont
|
||||
|
||||
ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */
|
||||
ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/
|
||||
ldr r8, =0x42 /* Assuming MAX CL = 4 */
|
||||
cmp r6, #4 /* If CL = 4 break */
|
||||
beq casDdr2Cont
|
||||
|
||||
ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */
|
||||
ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/
|
||||
ldr r8, =0x52 /* Assuming MAX CL = 5 */
|
||||
cmp r6, #5 /* If CL = 5 break */
|
||||
beq casDdr2Cont
|
||||
|
||||
ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */
|
||||
ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/
|
||||
ldr r8, =0x62 /* Assuming MAX CL = 6 */
|
||||
cmp r6, #6 /* If CL = 5 break */
|
||||
beq casDdr2Cont
|
||||
|
||||
/* This is an error. return */
|
||||
b exit_ddrAutoConfig /* This is an error !! */
|
||||
casDdr2Cont:
|
||||
|
||||
/* Get default SDRAM Mode values */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG)
|
||||
bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */
|
||||
orr r6, r6, r8
|
||||
MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2)
|
||||
|
||||
/* Set Dunit control register according to max CL detected */
|
||||
MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1)
|
||||
tst r6, #SDRAM_REGISTERED
|
||||
beq setDunitReg
|
||||
mov r7, r3
|
||||
|
||||
setDunitReg:
|
||||
#ifdef MV78XX0
|
||||
/* Set SDRAM Extended Mode register for double DIMM */
|
||||
/* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */
|
||||
|
||||
MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
|
||||
ldr r5, =MSAR_SYSCLCK_MASK
|
||||
and r4, r4, r5
|
||||
ldr r5, =MSAR_SYSCLCK_333
|
||||
cmp r4, r5
|
||||
ble Clock333
|
||||
add r7, r7, #0x10
|
||||
Clock333:
|
||||
#endif
|
||||
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
|
||||
bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */
|
||||
orr r6, r6, #BIT4 /* Enable 2T mode */
|
||||
bic r6, r6, #BIT6 /* clear ctrlPos */
|
||||
orr r6, r6, r7, LSL #20
|
||||
MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3)
|
||||
|
||||
/* Set Dunit high control register */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
|
||||
orr r6, r6, #BIT7 /* SDRAM__D2P_EN */
|
||||
orr r6, r6, #BIT8 /* SDRAM__P2D_EN */
|
||||
#ifdef MV78XX0
|
||||
orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */
|
||||
orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */
|
||||
orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */
|
||||
#endif
|
||||
MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13)
|
||||
|
||||
/* DIMM density configuration*/
|
||||
/* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */
|
||||
Density:
|
||||
/* Get bank 0 and 1 density */
|
||||
ldr r6, =0
|
||||
bl _getDensity
|
||||
|
||||
mov r8, r7
|
||||
mov r8, r8, LSR #20 /* Move density 20 bits to the right */
|
||||
/* For example 0x10000000 --> 0x1000 */
|
||||
|
||||
mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1))
|
||||
cmp r8, #DRAM_DEV_DENSITY_256M
|
||||
beq get_bank_2_density
|
||||
|
||||
mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1))
|
||||
cmp r8, #DRAM_DEV_DENSITY_512M
|
||||
beq get_bank_2_density
|
||||
|
||||
mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1))
|
||||
cmp r8, #DRAM_DEV_DENSITY_1G
|
||||
beq get_bank_2_density
|
||||
|
||||
mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1))
|
||||
cmp r8, #DRAM_DEV_DENSITY_2G
|
||||
beq get_bank_2_density
|
||||
|
||||
/* This is an error. return */
|
||||
b exit_ddrAutoConfig
|
||||
|
||||
get_bank_2_density:
|
||||
/* Check for second dimm */
|
||||
MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
|
||||
cmp r6, #1
|
||||
bne get_width
|
||||
|
||||
/* Get bank 2 and 3 density */
|
||||
ldr r6, =2
|
||||
bl _getDensity
|
||||
|
||||
mov r8, r7
|
||||
mov r8, r8, LSR #20 /* Move density 20 bits to the right */
|
||||
/* For example 0x10000000 --> 0x1000 */
|
||||
|
||||
orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3))
|
||||
cmp r8, #DRAM_DEV_DENSITY_256M
|
||||
beq get_width
|
||||
|
||||
and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
|
||||
orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3))
|
||||
cmp r8, #DRAM_DEV_DENSITY_512M
|
||||
beq get_width
|
||||
|
||||
and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
|
||||
orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3))
|
||||
cmp r8, #DRAM_DEV_DENSITY_1G
|
||||
beq get_width
|
||||
|
||||
and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
|
||||
orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3))
|
||||
cmp r8, #DRAM_DEV_DENSITY_2G
|
||||
beq get_width
|
||||
|
||||
/* This is an error. return */
|
||||
b exit_ddrAutoConfig
|
||||
|
||||
/* Get SDRAM width */
|
||||
get_width:
|
||||
/* Get bank 0 and 1 width */
|
||||
ldr r6, =0
|
||||
bl _get_width
|
||||
|
||||
cmp r7, #8 /* x8 devices */
|
||||
beq get_bank_2_width
|
||||
|
||||
orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */
|
||||
cmp r7, #16
|
||||
beq get_bank_2_width
|
||||
|
||||
/* This is an error. return */
|
||||
b exit_ddrAutoConfig
|
||||
|
||||
get_bank_2_width:
|
||||
/* Check for second dimm */
|
||||
MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
|
||||
cmp r6, #1
|
||||
bne densCont
|
||||
|
||||
/* Get bank 2 and 3 width */
|
||||
ldr r6, =2
|
||||
bl _get_width
|
||||
|
||||
cmp r7, #8 /* x8 devices */
|
||||
beq densCont
|
||||
|
||||
orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */
|
||||
cmp r7, #16
|
||||
beq densCont
|
||||
|
||||
/* This is an error. return */
|
||||
b exit_ddrAutoConfig
|
||||
|
||||
densCont:
|
||||
MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4)
|
||||
|
||||
/* Set SDRAM timing control low register */
|
||||
ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT
|
||||
/* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5)
|
||||
|
||||
/* Set SDRAM timing control high register */
|
||||
ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT
|
||||
|
||||
MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
|
||||
ldr r5, =MSAR_SYSCLCK_MASK
|
||||
and r4, r4, r5
|
||||
ldr r5, =MSAR_SYSCLCK_333
|
||||
cmp r4, r5
|
||||
blt timingHighClock333
|
||||
orr r6, r6, #BIT9
|
||||
|
||||
timingHighClock333:
|
||||
/* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */
|
||||
MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
|
||||
|
||||
/* Check for second dimm */
|
||||
MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
|
||||
cmp r6, #1
|
||||
bne single_dimm_odt
|
||||
|
||||
/* Set SDRAM ODT control low register for double DIMM*/
|
||||
ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7)
|
||||
|
||||
/* Set DUNIT ODT control register for double DIMM */
|
||||
ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9)
|
||||
|
||||
#ifdef MV78XX0
|
||||
/* Set SDRAM Extended Mode register for double DIMM */
|
||||
/* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */
|
||||
|
||||
MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
|
||||
ldr r5, =MSAR_SYSCLCK_MASK
|
||||
and r4, r4, r5
|
||||
ldr r5, =MSAR_SYSCLCK_267
|
||||
cmp r4, r5
|
||||
beq slow_dram_clock_rtt
|
||||
ldr r5, =MSAR_SYSCLCK_300
|
||||
cmp r4, r5
|
||||
beq slow_dram_clock_rtt
|
||||
ldr r5, =MSAR_SYSCLCK_333
|
||||
cmp r4, r5
|
||||
beq fast_dram_clock_rtt
|
||||
ldr r5, =MSAR_SYSCLCK_400
|
||||
cmp r4, r5
|
||||
beq fast_dram_clock_rtt
|
||||
|
||||
b slow_dram_clock_rtt
|
||||
|
||||
fast_dram_clock_rtt:
|
||||
ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
|
||||
b odt_config_end
|
||||
#endif
|
||||
slow_dram_clock_rtt:
|
||||
ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
|
||||
b odt_config_end
|
||||
|
||||
single_dimm_odt:
|
||||
/* Set SDRAM ODT control low register */
|
||||
ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7)
|
||||
|
||||
/* Set DUNIT ODT control register */
|
||||
ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9)
|
||||
|
||||
/* Set SDRAM Extended Mode register */
|
||||
ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
|
||||
|
||||
odt_config_end:
|
||||
/* SDRAM ODT control high register is left as default */
|
||||
MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8)
|
||||
|
||||
/*Read CL and set the DDR2 registers accordingly */
|
||||
MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2)
|
||||
and r6, r6, #SDRAM_CL_MASK
|
||||
mov r4, r6
|
||||
orr r4, r4, r6, LSL #4
|
||||
orr r4, r4, r6, LSL #8
|
||||
orr r4, r4, r6, LSL #12
|
||||
mov r5, #0x30000
|
||||
add r4, r4, r5
|
||||
sub r4, r4, #0x30
|
||||
/* Set SDRAM Ddr2 Timing Low register */
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11)
|
||||
|
||||
/* Set SDRAM Ddr2 Timing High register */
|
||||
mov r4, r4, LSR #4
|
||||
MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12)
|
||||
|
||||
timeParamDone:
|
||||
/* Close all windows */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
|
||||
and r6, r6,#~SCSR_SIZE_MASK
|
||||
and r6, r6,#~1
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
|
||||
and r6, r6,#~SCSR_SIZE_MASK
|
||||
and r6, r6,#~1
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
|
||||
and r6, r6,#~SCSR_SIZE_MASK
|
||||
and r6, r6,#~1
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
|
||||
and r6, r6,#~SCSR_SIZE_MASK
|
||||
and r6, r6,#~1
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
|
||||
|
||||
/* Set sdram bank 0 size and enable it */
|
||||
ldr r6, =0
|
||||
bl _mvDramIfGetDimmSizeFromSpd
|
||||
#ifdef MV78XX0
|
||||
/* Check DRAM width */
|
||||
MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG)
|
||||
ldr r5, =SDRAM_DWIDTH_MASK
|
||||
and r4, r4, r5
|
||||
ldr r5, =SDRAM_DWIDTH_64BIT
|
||||
cmp r4, r5
|
||||
beq dram_64bit_width
|
||||
/* Utilize only 32bit width */
|
||||
mov r8, r8, LSR #1
|
||||
#else
|
||||
/* Utilize only 16bit width */
|
||||
mov r8, r8, LSR #2
|
||||
#endif
|
||||
dram_64bit_width:
|
||||
/* Update first dimm size return value R8 */
|
||||
MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0))
|
||||
ldr r6, =~SCSR_SIZE_MASK
|
||||
and r5, r5, r6
|
||||
orr r5, r5, r8
|
||||
MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0))
|
||||
|
||||
/* Clear bank 2 size */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
|
||||
and r6, r6,#~SCSR_SIZE_MASK
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
|
||||
|
||||
/* Check for second dimm */
|
||||
MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
|
||||
cmp r6, #1
|
||||
bne defualt_order
|
||||
|
||||
/* Set sdram bank 2 size */
|
||||
ldr r6, =2
|
||||
bl _mvDramIfGetDimmSizeFromSpd
|
||||
#ifdef MV78XX0
|
||||
/* Check DRAM width */
|
||||
MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG)
|
||||
ldr r5, =SDRAM_DWIDTH_MASK
|
||||
and r4, r4, r5
|
||||
ldr r5, =SDRAM_DWIDTH_64BIT
|
||||
cmp r4, r5
|
||||
beq dram_64bit_width2
|
||||
/* Utilize only 32bit width */
|
||||
mov r8, r8, LSR #1
|
||||
#else
|
||||
/* Utilize only 16bit width */
|
||||
mov r8, r8, LSR #2
|
||||
#endif
|
||||
dram_64bit_width2:
|
||||
/* Update first dimm size return value R8 */
|
||||
MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2))
|
||||
ldr r6, =~SCSR_SIZE_MASK
|
||||
and r5, r5, r6
|
||||
orr r5, r5, r8
|
||||
MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2))
|
||||
|
||||
/* Close windows 1 and 3 */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
|
||||
and r6, r6,#~1
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
|
||||
and r6, r6,#~1
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
|
||||
|
||||
/* Check dimm size for setting dram bank order */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
|
||||
MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2))
|
||||
and r6, r6,#SCSR_SIZE_MASK
|
||||
and r4, r4,#SCSR_SIZE_MASK
|
||||
cmp r6, r4
|
||||
bge defualt_order
|
||||
|
||||
/* Bank 2 is biger then bank 0 */
|
||||
ldr r6,=0
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2))
|
||||
|
||||
/* Open win 2 */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
|
||||
orr r6, r6,#1
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
|
||||
|
||||
ldr sp,=0
|
||||
bl _mvDramIfConfig
|
||||
#ifdef MV78XX0
|
||||
/* Init ECC on CS 2 */
|
||||
ldr r0, =2
|
||||
bl _mvDramIfEccMemInit
|
||||
#endif
|
||||
mov PC, r11 /* r11 is saved link register */
|
||||
|
||||
defualt_order:
|
||||
|
||||
/* Open win 0 */
|
||||
MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
|
||||
orr r6, r6,#1
|
||||
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
|
||||
|
||||
ldr sp,=0
|
||||
bl _mvDramIfConfig
|
||||
#ifdef MV78XX0
|
||||
/* Init ECC on CS 0 */
|
||||
ldr r0, =0
|
||||
bl _mvDramIfEccMemInit
|
||||
#endif
|
||||
exit_ddrAutoConfig:
|
||||
mov PC, r11 /* r11 is saved link register */
|
||||
|
||||
|
||||
/***************************************************************************************/
|
||||
/* r4 holds I2C EEPROM address
|
||||
* r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value
|
||||
* r8 holds SDRAM various configuration registers value.
|
||||
* r13 holds Link register
|
||||
*/
|
||||
/**************************/
|
||||
_getDensity:
|
||||
mov r13, LR /* Save link register */
|
||||
|
||||
/* Read SPD rank size from DIMM0 */
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
|
||||
cmp r6, #0
|
||||
beq 1f
|
||||
|
||||
/* Read SPD rank size from DIMM1 */
|
||||
mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
|
||||
|
||||
1:
|
||||
mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */
|
||||
bl _i2cRead
|
||||
mov r8, r7 /* r8 save number of rows */
|
||||
|
||||
mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */
|
||||
bl _i2cRead
|
||||
add r8, r8, r7 /* r8 = number of rows + number of col */
|
||||
|
||||
mov r7, #0x1
|
||||
mov r8, r7, LSL r8 /* r8 = (1 << r8) */
|
||||
|
||||
mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */
|
||||
bl _i2cRead
|
||||
mul r8, r7, r8
|
||||
|
||||
mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */
|
||||
bl _i2cRead
|
||||
mul r7, r8, r7
|
||||
|
||||
mov PC, r13
|
||||
|
||||
/**************************/
|
||||
_get_width:
|
||||
mov r13, LR /* Save link register */
|
||||
|
||||
/* Read SPD rank size from DIMM0 */
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
|
||||
cmp r6, #0
|
||||
beq 1f
|
||||
|
||||
/* Read SPD rank size from DIMM1 */
|
||||
mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
|
||||
|
||||
1:
|
||||
/* Get SDRAM width (SPD offset 13) */
|
||||
mov r7, #SDRAM_WIDTH_OFFSET
|
||||
bl _i2cRead /* result in r7 */
|
||||
|
||||
mov PC, r13
|
||||
|
||||
/**************************/
|
||||
_get_CAL:
|
||||
mov r13, LR /* Save link register */
|
||||
|
||||
/* Set maximum CL supported by DIMM */
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */
|
||||
bl _i2cRead
|
||||
|
||||
mov PC, r13
|
||||
|
||||
/**************************/
|
||||
/* R8 - sdram configuration register.
|
||||
* Return value in flag if no-registered then Z-flag is set
|
||||
*/
|
||||
_is_Registered:
|
||||
mov r13, LR /* Save link register */
|
||||
#if defined(MV645xx)
|
||||
/* Get registered/non registered info from DIMM */
|
||||
tst r8, #SDRAM_DTYPE_DDR2
|
||||
bne regDdr2
|
||||
|
||||
regDdr1:
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #SDRAM_MODULES_ATTR_OFFSET
|
||||
bl _i2cRead /* result in r7 */
|
||||
|
||||
tst r7, #0x2
|
||||
b exit
|
||||
#endif
|
||||
regDdr2:
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #DIMM_TYPE_INFO_OFFSET
|
||||
bl _i2cRead /* result in r7 */
|
||||
|
||||
tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */
|
||||
/* or Mini-RDIMM (0x10) */
|
||||
exit:
|
||||
mov PC, r13
|
||||
|
||||
|
||||
/**************************/
|
||||
/* Return value in flag if no-Ecc then Z-flag is set */
|
||||
_is_Ecc:
|
||||
mov r13, LR /* Save link register */
|
||||
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #DIMM_CONFIG_TYPE
|
||||
bl _i2cRead /* result in r7 */
|
||||
|
||||
tst r7, #0x2 /* bit 1 -> Data ECC */
|
||||
mov PC, r13
|
||||
|
||||
/**************************/
|
||||
/* Return value in flag if no second DIMM then Z-flag is set */
|
||||
_is_Second_Dimm_Exist:
|
||||
mov r13, LR /* Save link register */
|
||||
|
||||
mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */
|
||||
mov r7, #DIMM_TYPE_OFFSET
|
||||
bl _i2cRead /* result in r7 */
|
||||
|
||||
tst r7, #0x8 /* bit3 is '1' -> DDR 2 */
|
||||
mov PC, r13
|
||||
|
||||
/*******************************************************************************
|
||||
* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* The function will read the bank 0 dram size(SPD version 1.0 and above )
|
||||
*
|
||||
* INPUT:
|
||||
* r6 - dram bank number.
|
||||
*
|
||||
* OUTPUT:
|
||||
* none
|
||||
*/
|
||||
_mvDramIfGetDimmSizeFromSpd:
|
||||
|
||||
mov r13, LR /* Save link register */
|
||||
|
||||
/* Read SPD rank size from DIMM0 */
|
||||
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
||||
|
||||
cmp r6, #0
|
||||
beq 1f
|
||||
|
||||
/* Read SPD rank size from DIMM1 */
|
||||
mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
|
||||
|
||||
1:
|
||||
mov r7, #RANK_SIZE_OFFSET /* offset 31 */
|
||||
bl _i2cRead
|
||||
|
||||
pass_read:
|
||||
ldr r8, =(0x7 << SCSR_SIZE_OFFS)
|
||||
cmp r7, #DRAM_RANK_DENSITY_128M
|
||||
beq endDimmSize
|
||||
|
||||
ldr r8, =(0xf << SCSR_SIZE_OFFS)
|
||||
cmp r7, #DRAM_RANK_DENSITY_256M
|
||||
beq endDimmSize
|
||||
|
||||
ldr r8, =(0x1f << SCSR_SIZE_OFFS)
|
||||
cmp r7, #DRAM_RANK_DENSITY_512M
|
||||
beq endDimmSize
|
||||
|
||||
ldr r8, =(0x3f << SCSR_SIZE_OFFS)
|
||||
cmp r7, #DRAM_RANK_DENSITY_1G
|
||||
beq endDimmSize
|
||||
|
||||
ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */
|
||||
endDimmSize:
|
||||
mov PC, r13
|
||||
#endif
|
||||
@ -0,0 +1,528 @@
|
||||
/*******************************************************************************
|
||||
Copyright (C) Marvell International Ltd. and its affiliates
|
||||
|
||||
This software file (the "File") is owned and distributed by Marvell
|
||||
International Ltd. and/or its affiliates ("Marvell") under the following
|
||||
alternative licensing terms. Once you have made an election to distribute the
|
||||
File under one of the following license alternatives, please (i) delete this
|
||||
introductory statement regarding license alternatives, (ii) delete the two
|
||||
license alternatives that you have not elected to use and (iii) preserve the
|
||||
Marvell copyright notice above.
|
||||
|
||||
********************************************************************************
|
||||
Marvell Commercial License Option
|
||||
|
||||
If you received this File from Marvell and you have entered into a commercial
|
||||
license agreement (a "Commercial License") with Marvell, the File is licensed
|
||||
to you under the terms of the applicable Commercial License.
|
||||
|
||||
********************************************************************************
|
||||
Marvell GPL License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File in accordance with the terms and conditions of the General
|
||||
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
|
||||
available along with the File in the license.txt file or by writing to the Free
|
||||
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
|
||||
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
|
||||
|
||||
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
|
||||
DISCLAIMED. The GPL License provides additional details about this warranty
|
||||
disclaimer.
|
||||
********************************************************************************
|
||||
Marvell BSD License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File under the following licensing terms.
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of Marvell nor the names of its contributors may be
|
||||
used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* mvDramIfBasicAsm.s
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* Memory full detection and best timing configuration is done in
|
||||
* C code. C runtime environment requires a stack. This module API
|
||||
* initialize DRAM interface chip select 0 for basic functionality for
|
||||
* the use of stack.
|
||||
* The module API assumes DRAM information is stored in I2C EEPROM reside
|
||||
* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM
|
||||
* internal data structure is assumed to be orgenzied in common DRAM
|
||||
* vendor SPD structure.
|
||||
* NOTE: DFCDL values are assumed to be already initialized prior to
|
||||
* this module API activity.
|
||||
*
|
||||
*
|
||||
* DEPENDENCIES:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/* includes */
|
||||
#define _ASMLANGUAGE
|
||||
#define MV_ASMLANGUAGE
|
||||
#include "mvOsAsm.h"
|
||||
#include "mvSysHwConfig.h"
|
||||
#include "mvDramIfRegs.h"
|
||||
#include "mvDramIfConfig.h"
|
||||
#include "ctrlEnv/sys/mvCpuIfRegs.h"
|
||||
#include "pex/mvPexRegs.h"
|
||||
#include "ctrlEnv/mvCtrlEnvSpec.h"
|
||||
#include "mvCommon.h"
|
||||
|
||||
/* defines */
|
||||
|
||||
/* locals */
|
||||
.data
|
||||
.globl _mvDramIfConfig
|
||||
.text
|
||||
.globl _mvDramIfMemInit
|
||||
|
||||
/*******************************************************************************
|
||||
* _mvDramIfConfig - Basic DRAM interface initialization.
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* The function will initialize the following DRAM parameters using the
|
||||
* values prepared by mvDramIfDetect routine. Values are located
|
||||
* in predefined registers.
|
||||
*
|
||||
* INPUT:
|
||||
* None.
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
_mvDramIfConfig:
|
||||
|
||||
/* Save register on stack */
|
||||
cmp sp, #0
|
||||
beq no_stack_s
|
||||
save_on_stack:
|
||||
stmdb sp!, {r1, r2, r3, r4}
|
||||
no_stack_s:
|
||||
|
||||
/* Dunit FTDLL Configuration Register */
|
||||
/* 0) Write to SDRAM FTDLL coniguration register */
|
||||
ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT;
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG)
|
||||
str r4, [r1]
|
||||
ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT;
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG)
|
||||
str r4, [r1]
|
||||
ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP;
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 1) Write to SDRAM coniguration register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 2) Write Dunit control low register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 2) Write Dunit control high register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 3) Write SDRAM address control register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG)
|
||||
str r4, [r1]
|
||||
#if defined(MV_STATIC_DRAM_ON_BOARD)
|
||||
/* 4) Write SDRAM bank 0 size register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0))
|
||||
str r4, [r1]
|
||||
#endif
|
||||
|
||||
/* 5) Write SDRAM open pages control register */
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG)
|
||||
ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV
|
||||
str r4, [r1]
|
||||
|
||||
/* 6) Write SDRAM timing Low register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 7) Write SDRAM timing High register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* Config DDR2 On Die Termination (ODT) registers */
|
||||
/* Write SDRAM DDR2 ODT control low register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* Write SDRAM DDR2 ODT control high register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* Write SDRAM DDR2 Dunit ODT control register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* Write DDR2 SDRAM timing Low register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* Write DDR2 SDRAM timing High register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 8) Write SDRAM mode register */
|
||||
/* The CPU must not attempt to change the SDRAM Mode register setting */
|
||||
/* prior to DRAM controller completion of the DRAM initialization */
|
||||
/* sequence. To guarantee this restriction, it is recommended that */
|
||||
/* the CPU sets the SDRAM Operation register to NOP command, performs */
|
||||
/* read polling until the register is back in Normal operation value, */
|
||||
/* and then sets SDRAM Mode register to its new value. */
|
||||
|
||||
/* 8.1 write 'nop' to SDRAM operation */
|
||||
mov r4, #0x5 /* 'NOP' command */
|
||||
MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG)
|
||||
|
||||
/* 8.2 poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll1:
|
||||
ldr r4, [r1]
|
||||
cmp r4, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll1
|
||||
|
||||
/* 8.3 Now its safe to write new value to SDRAM Mode register */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 8.4 Make the Dunit write the DRAM its new mode */
|
||||
mov r4, #0x3 /* Mode Register Set command */
|
||||
MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
|
||||
|
||||
/* 8.5 poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll2:
|
||||
ldr r4, [r1]
|
||||
cmp r4, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll2
|
||||
|
||||
/* Now its safe to write new value to SDRAM Extended Mode regist */
|
||||
ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10)
|
||||
ldr r4, [r1]
|
||||
ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG)
|
||||
str r4, [r1]
|
||||
|
||||
/* 9) Write SDRAM Extended mode register This operation should be */
|
||||
/* done for each memory bank */
|
||||
/* write 'nop' to SDRAM operation */
|
||||
mov r4, #0x5 /* 'NOP' command */
|
||||
MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
|
||||
|
||||
/* poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll3:
|
||||
ldr r4, [r1]
|
||||
cmp r4, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll3
|
||||
/* Go over each of the Banks */
|
||||
ldr r3, =0 /* r3 = DRAM bank Num */
|
||||
|
||||
extModeLoop:
|
||||
/* Set the SDRAM Operation Control to each of the DRAM banks */
|
||||
mov r4, r3 /* Do not swap the bank counter value */
|
||||
MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG)
|
||||
|
||||
/* Make the Dunit write the DRAM its new mode */
|
||||
mov r4, #0x4 /* Extended Mode Register Set command */
|
||||
MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
|
||||
|
||||
/* poll SDRAM operation. Make sure its back to normal operation */
|
||||
_sdramOpPoll4:
|
||||
ldr r4, [r1]
|
||||
cmp r4, #0 /* '0' = Normal SDRAM Mode */
|
||||
bne _sdramOpPoll4
|
||||
|
||||
add r3, r3, #1
|
||||
cmp r3, #4 /* 4 = Number of banks */
|
||||
bne extModeLoop
|
||||
|
||||
extModeEnd:
|
||||
cmp sp, #0
|
||||
beq no_stack_l
|
||||
mov r1, LR /* Save link register */
|
||||
#if defined(MV78XX0)
|
||||
bl _mvDramIfMemInit
|
||||
#endif
|
||||
mov LR,r1 /* restore link register */
|
||||
load_from_stack:
|
||||
/* Restore registers */
|
||||
ldmia sp!, {r1, r2, r3, r4}
|
||||
no_stack_l:
|
||||
|
||||
mov pc, lr
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* _mvDramIfEccMemInit - Basic DRAM ECC initialization.
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* INPUT:
|
||||
* None.
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */
|
||||
#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */
|
||||
#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */
|
||||
/* XOR engine register offsets macros */
|
||||
#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4))
|
||||
#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4))
|
||||
#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30)
|
||||
#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50)
|
||||
#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60)
|
||||
#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0)
|
||||
#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4)
|
||||
#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4))
|
||||
#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4))
|
||||
|
||||
/* XOR Engine Address Decoding Register Map */
|
||||
#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4)))
|
||||
#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4)))
|
||||
#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4)))
|
||||
|
||||
.globl _mvDramIfEccMemInit
|
||||
/*******************************************************************************
|
||||
* _mvDramIfEccMemInit - mem init for dram cs
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* This function will clean the cs by ussing the XOR mem init.
|
||||
*
|
||||
* INPUT:
|
||||
* r0 - dram bank number.
|
||||
*
|
||||
* OUTPUT:
|
||||
* none
|
||||
*/
|
||||
_mvDramIfEccMemInit:
|
||||
|
||||
/* Save register on stack */
|
||||
cmp sp, #0
|
||||
beq no_stack_s1
|
||||
save_on_stack1:
|
||||
stmdb sp!, {r0,r1, r2, r3, r4, r5, r6}
|
||||
no_stack_s1:
|
||||
|
||||
ldr r1, = 0
|
||||
|
||||
/* Disable all XOR address decode windows to avoid possible overlap */
|
||||
MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)))
|
||||
|
||||
/* Init r5 to first XOR_SIZE_MASK_REG */
|
||||
mov r5, r0, LSL #3
|
||||
add r5, r5,#0x1500
|
||||
add r5, r5,#0x04
|
||||
add r5, r5,#(INTER_REGS_BASE)
|
||||
ldr r6, [r5]
|
||||
HTOLL(r6,r5)
|
||||
MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0))
|
||||
|
||||
mov r5, r0, LSL #3
|
||||
add r5, r5,#0x1500
|
||||
add r5, r5,#(INTER_REGS_BASE)
|
||||
ldr r6, [r5]
|
||||
/* Update destination & size */
|
||||
MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0))
|
||||
HTOLL(r6,r5)
|
||||
/* Init r6 to first XOR_BASE_ADDR_REG */
|
||||
ldr r4, = 0xf
|
||||
ldr r5, = 0x1
|
||||
mov r5, r5, LSL r0
|
||||
bic r4, r4, r5
|
||||
mov r4, r4, LSL #8
|
||||
|
||||
orr r6, r6, r4
|
||||
MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0))
|
||||
|
||||
ldr r6, = 0xff0001
|
||||
MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))
|
||||
|
||||
/* Configure XOR engine for memory init function. */
|
||||
MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0))
|
||||
and r6, r6, #~0x7 /* Clear operation mode field */
|
||||
orr r6, r6, #0x4 /* Set operation to memory init */
|
||||
MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0))
|
||||
|
||||
/* Set initVal in the XOR Engine Initial Value Registers */
|
||||
ldr r6, = 0xfeedfeed
|
||||
MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG)
|
||||
ldr r6, = 0xfeedfeed
|
||||
MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG)
|
||||
|
||||
/* Set block size using DRAM bank size */
|
||||
|
||||
mov r5, r0, LSL #3
|
||||
add r5, r5,#0x1500
|
||||
add r5, r5,#0x04
|
||||
add r5, r5,#(INTER_REGS_BASE)
|
||||
|
||||
ldr r6, [r5]
|
||||
HTOLL(r6,r5)
|
||||
and r6, r6, #SCSR_SIZE_MASK
|
||||
mov r5, r6, LSR #SCSR_SIZE_OFFS
|
||||
add r5, r5, #1
|
||||
mov r6, r5, LSL #SCSR_SIZE_OFFS
|
||||
MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0))
|
||||
|
||||
/* Clean interrupt cause*/
|
||||
MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG)
|
||||
|
||||
/* Clean error interrupt cause*/
|
||||
MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG)
|
||||
MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG)
|
||||
|
||||
/* Start transfer */
|
||||
MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0))
|
||||
orr r6, r6, #0x1 /* Preform start command */
|
||||
MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0))
|
||||
|
||||
/* Wait for engine to finish */
|
||||
waitForComplete:
|
||||
MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG)
|
||||
and r6, r6, #2
|
||||
cmp r6, #0
|
||||
beq waitForComplete
|
||||
|
||||
/* Clear all error report registers */
|
||||
MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG)
|
||||
MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG)
|
||||
|
||||
MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG)
|
||||
|
||||
cmp sp, #0
|
||||
beq no_stack_l1
|
||||
load_from_stack1:
|
||||
ldmia sp!, {r0, r1, r2, r3, r4, r5, r6}
|
||||
no_stack_l1:
|
||||
mov pc, lr
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* mvDramIfMemInit - Use XOR to clear all memory.
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern.
|
||||
* INPUT:
|
||||
* None.
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
#if defined(MV78XX0)
|
||||
|
||||
_mvDramIfMemInit:
|
||||
stmdb sp!, {r0,r1, r2, r3, r4, r5, r6}
|
||||
mov r6, LR /* Save link register */
|
||||
/* Check if dram bank 0 has to be init for ECC */
|
||||
MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0))
|
||||
and r3, r0, #SCSR_WIN_EN
|
||||
cmp r3, #0
|
||||
beq no_bank_0
|
||||
MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0))
|
||||
cmp r0, #0
|
||||
beq no_bank_0
|
||||
mov r0,#0
|
||||
bl _mvDramIfEccMemInit
|
||||
|
||||
no_bank_0:
|
||||
/* Check if dram bank 1 has to be init for ECC */
|
||||
MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1))
|
||||
and r0, r0, #SCSR_WIN_EN
|
||||
cmp r0, #0
|
||||
beq no_bank_1
|
||||
mov r0,#1
|
||||
bl _mvDramIfEccMemInit
|
||||
no_bank_1:
|
||||
/* Check if dram bank 2 has to be init for ECC */
|
||||
MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2))
|
||||
and r0, r0, #SCSR_WIN_EN
|
||||
cmp r0, #0
|
||||
beq no_bank_2
|
||||
MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2))
|
||||
cmp r0, #0
|
||||
beq no_bank_2
|
||||
mov r0,#2
|
||||
bl _mvDramIfEccMemInit
|
||||
|
||||
no_bank_2:
|
||||
/* Check if dram bank 3 has to be init for ECC */
|
||||
MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3))
|
||||
and r0, r0, #SCSR_WIN_EN
|
||||
cmp r0, #0
|
||||
beq no_bank_3
|
||||
mov r0,#3
|
||||
bl _mvDramIfEccMemInit
|
||||
no_bank_3:
|
||||
mov LR ,r6 /* restore link register */
|
||||
ldmia sp!, {r0, r1, r2, r3, r4, r5, r6}
|
||||
mov pc, lr
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.4
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.4
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.3
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.2
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.4
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.3
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.3
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
Global HAL Version: FEROCEON_HAL_3_1_7
|
||||
Unit HAL Version: 3.1.5
|
||||
Description: This component includes an implementation of the unit HAL drivers
|
||||
|
||||
@ -0,0 +1,457 @@
|
||||
/*******************************************************************************
|
||||
Copyright (C) Marvell International Ltd. and its affiliates
|
||||
|
||||
This software file (the "File") is owned and distributed by Marvell
|
||||
International Ltd. and/or its affiliates ("Marvell") under the following
|
||||
alternative licensing terms. Once you have made an election to distribute the
|
||||
File under one of the following license alternatives, please (i) delete this
|
||||
introductory statement regarding license alternatives, (ii) delete the two
|
||||
license alternatives that you have not elected to use and (iii) preserve the
|
||||
Marvell copyright notice above.
|
||||
|
||||
********************************************************************************
|
||||
Marvell Commercial License Option
|
||||
|
||||
If you received this File from Marvell and you have entered into a commercial
|
||||
license agreement (a "Commercial License") with Marvell, the File is licensed
|
||||
to you under the terms of the applicable Commercial License.
|
||||
|
||||
********************************************************************************
|
||||
Marvell GPL License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File in accordance with the terms and conditions of the General
|
||||
Public License Version 2, June 1991 (the "GPL License"), a copy of which is
|
||||
available along with the File in the license.txt file or by writing to the Free
|
||||
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
|
||||
on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
|
||||
|
||||
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
|
||||
DISCLAIMED. The GPL License provides additional details about this warranty
|
||||
disclaimer.
|
||||
********************************************************************************
|
||||
Marvell BSD License Option
|
||||
|
||||
If you received this File from Marvell, you may opt to use, redistribute and/or
|
||||
modify this File under the following licensing terms.
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of Marvell nor the names of its contributors may be
|
||||
used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* includes */
|
||||
#define MV_ASMLANGUAGE
|
||||
#include "ctrlEnv/mvCtrlEnvSpec.h"
|
||||
#include "boardEnv/mvBoardEnvSpec.h"
|
||||
#include "mvOsAsm.h"
|
||||
#include "mvTwsiSpec.h"
|
||||
#include "mvSysHwConfig.h"
|
||||
#include "ctrlEnv/sys/mvCpuIfRegs.h"
|
||||
#include "mvCommon.h"
|
||||
|
||||
#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL
|
||||
|
||||
/* defines */
|
||||
/* defines */
|
||||
|
||||
|
||||
.data
|
||||
.global _i2cInit
|
||||
.global _i2cRead
|
||||
|
||||
.text
|
||||
|
||||
/*******************************************************************************
|
||||
* _i2cInit - Initialize TWSI interface
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* The function performs TWSI interface initialization. It resets the
|
||||
* TWSI state machine and initialize its clock to 100KHz assuming Tclock
|
||||
* of 133MHz.
|
||||
*
|
||||
* INPUT:
|
||||
* None.
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
_i2cInit:
|
||||
mov r9, LR /* Save link register */
|
||||
mov r0, #0 /* Make sure r0 is zero */
|
||||
|
||||
/* Reset the i2c Mechanism first */
|
||||
MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH))
|
||||
|
||||
bl _twsiDelay
|
||||
bl _twsiDelay
|
||||
|
||||
/* Initializing the I2C mechanism. Assuming Tclock frequency */
|
||||
/* of 166MHz. The I2C frequency in that case will be 100KHz. */
|
||||
/* For this settings, M = 9 and N = 3. Set the baud-rate with the */
|
||||
/* value of 0x2b (freq of ==> 100KHz */
|
||||
/* see spec for more details about the calculation of this value) */
|
||||
mov r6, #(9 << 3 | 3)
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||||
|
||||
/* Enable the I2C master */
|
||||
/* Enable TWSI interrupt in main mask reg */
|
||||
mov r6, #0xC4
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
|
||||
/* Let the slow TWSI machine get used to the idea that it is enabled */
|
||||
bl _twsiDelay
|
||||
|
||||
|
||||
mov PC, r9 /* r9 is saved link register */
|
||||
|
||||
/*******************************************************************************
|
||||
* _twsiDelay - Perform delay.
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* The function performs a delay to enable TWSI logic to stable.
|
||||
*
|
||||
* INPUT:
|
||||
* None.
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
_twsiDelay:
|
||||
mov r10, #0x100000 /*was 0x400*/
|
||||
|
||||
_twsiDelayLoop:
|
||||
subs r10, r10, #1
|
||||
bne _twsiDelayLoop
|
||||
|
||||
mov PC, LR
|
||||
|
||||
/*******************************************************************************
|
||||
* _i2cRead - Read byte from I2C EEPROM device.
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* The function returns a byte from I2C EEPROM device.
|
||||
* The EEPROM device is 7-bit address type.
|
||||
*
|
||||
* INPUT:
|
||||
* r4 has the DIMM0 base address with shift 1 bit to the left
|
||||
* r7 has the EEPROM offset
|
||||
*
|
||||
* OUTPUT:
|
||||
* None.
|
||||
*
|
||||
* RETURN:
|
||||
* r4 returns '0' if address can not be read.
|
||||
* r7 has byte value in case read is successful.
|
||||
*
|
||||
*******************************************************************************/
|
||||
_i2cRead:
|
||||
mov r9, LR /* Save link register */
|
||||
|
||||
/* Transmit the device address and desired offset within the EEPROM. */
|
||||
|
||||
/* Generate Start Bit */
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
orr r6, r6, #TWSI_CONTROL_START_BIT
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
|
||||
/* Wait for the interrupt flag (bit3) to be set */
|
||||
mov r10, #0x50000
|
||||
loop_1:
|
||||
subs r10, r10, #1
|
||||
beq loop_1_timeout
|
||||
#ifdef MV78XX0
|
||||
MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
|
||||
tst r6, #BIT2
|
||||
#else
|
||||
MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
|
||||
tst r6, #BIT5
|
||||
#endif
|
||||
beq loop_1
|
||||
|
||||
loop_1_timeout:
|
||||
|
||||
/* Wait for the start bit to be reset by HW */
|
||||
mov r10, #0x50000
|
||||
loop_2:
|
||||
subs r10, r10, #1
|
||||
beq loop_2_timeout
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
tst r6, #TWSI_CONTROL_START_BIT
|
||||
bne loop_2
|
||||
|
||||
loop_2_timeout:
|
||||
|
||||
/* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */
|
||||
mov r10, #0x50000
|
||||
loop_3:
|
||||
subs r10, r10, #1
|
||||
beq loop_3_timeout
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||||
cmp r6, #0x08
|
||||
bne loop_3
|
||||
|
||||
loop_3_timeout:
|
||||
|
||||
/* writing the address of (DIMM0/1 << 1) with write indication */
|
||||
mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH))
|
||||
|
||||
bl _twsiDelay
|
||||
/* Clear the interrupt flag */
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bl _twsiDelay
|
||||
|
||||
/* Waiting for the interrupt flag to be set which means that the
|
||||
address has been transmitted */
|
||||
loop_4:
|
||||
#ifdef MV78XX0
|
||||
MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
|
||||
tst r6, #BIT2
|
||||
#else
|
||||
MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
|
||||
tst r6, #BIT5
|
||||
#endif
|
||||
beq loop_4 /* if tst = 0, then the bit is not set yet */
|
||||
|
||||
/* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */
|
||||
mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */
|
||||
|
||||
loop_5:
|
||||
subs r10, r10, #1 /* timeout count down */
|
||||
bne testStatus
|
||||
mov r4, #0 /* r4 = 0 -> operation failed */
|
||||
b exit_i2cRead /* Exit if timeout (No DIMM) */
|
||||
|
||||
testStatus:
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||||
cmp r6, #0x18
|
||||
bne loop_5
|
||||
|
||||
|
||||
/* check if the offset is bigger than 256 byte*/
|
||||
tst r7, #0x80000000
|
||||
bne great_than_256
|
||||
|
||||
/* Write the offset to be read from the DIMM EEPROM */
|
||||
MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH))
|
||||
|
||||
b after_offset
|
||||
|
||||
great_than_256:
|
||||
mov r10, r7, LSR #8
|
||||
and r10, r10, #0xff
|
||||
/* Write the offset0 to be read from the EEPROM */
|
||||
MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH))
|
||||
|
||||
/* Clear the interrupt flag ==> signaling that the address can now
|
||||
be transmited */
|
||||
|
||||
bl _twsiDelay
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bl _twsiDelay
|
||||
|
||||
/* Wait for the interrupt to be set again ==> address has transmited */
|
||||
loop_6_1:
|
||||
#ifdef MV78XX0
|
||||
MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
|
||||
tst r6, #BIT2
|
||||
#else
|
||||
MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
|
||||
tst r6, #BIT5
|
||||
#endif
|
||||
beq loop_6_1
|
||||
|
||||
/* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */
|
||||
loop_7_1:
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||||
cmp r6, #0x28
|
||||
bne loop_7_1
|
||||
|
||||
|
||||
mov r10, r7
|
||||
and r10, r10, #0xff
|
||||
/* Write the offset1 to be read from the EEPROM */
|
||||
MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH))
|
||||
|
||||
|
||||
|
||||
after_offset:
|
||||
|
||||
/* Clear the interrupt flag ==> signaling that the address can now
|
||||
be transmited */
|
||||
|
||||
bl _twsiDelay
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bl _twsiDelay
|
||||
|
||||
/* Wait for the interrupt to be set again ==> address has transmited */
|
||||
loop_6:
|
||||
#ifdef MV78XX0
|
||||
MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
|
||||
tst r6, #BIT2
|
||||
#else
|
||||
MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
|
||||
tst r6, #BIT5
|
||||
#endif
|
||||
beq loop_6
|
||||
|
||||
/* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */
|
||||
loop_7:
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||||
cmp r6, #0x28
|
||||
bne loop_7
|
||||
|
||||
/* Retransmit the device address with read indication to get the data */
|
||||
|
||||
/* generate a repeated start bit */
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
orr r6, r6, #TWSI_CONTROL_START_BIT
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
|
||||
|
||||
/* Clear the interrupt flag ==> the start bit will be transmitted. */
|
||||
bl _twsiDelay
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bl _twsiDelay
|
||||
|
||||
/* Wait for the interrupt flag (bit3) to be set */
|
||||
loop_9:
|
||||
#ifdef MV78XX0
|
||||
MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
|
||||
tst r6, #BIT2
|
||||
#else
|
||||
MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
|
||||
tst r6, #BIT5
|
||||
#endif
|
||||
beq loop_9
|
||||
|
||||
/* Wait for the start bit to be reset by HW */
|
||||
loop_8:
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
tst r6, #TWSI_CONTROL_START_BIT
|
||||
bne loop_8
|
||||
|
||||
/* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */
|
||||
loop_10:
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||||
cmp r6, #0x10
|
||||
bne loop_10
|
||||
|
||||
/* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */
|
||||
mov r6, r4, LSL #1
|
||||
orr r6, r6, #1 /* Read operation address bit 0 must be 1 */
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH))
|
||||
|
||||
/* Clear the interrupt flag ==> the address will be transmitted */
|
||||
bl _twsiDelay
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bl _twsiDelay
|
||||
|
||||
/* Wait for the interrupt flag (bit3) to be set as a result of
|
||||
transmitting the address. */
|
||||
loop_11:
|
||||
#ifdef MV78XX0
|
||||
MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
|
||||
tst r6, #BIT2
|
||||
#else
|
||||
MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
|
||||
tst r6, #BIT5
|
||||
#endif
|
||||
beq loop_11
|
||||
|
||||
/* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */
|
||||
loop_12:
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||||
cmp r6, #0x40
|
||||
bne loop_12
|
||||
|
||||
/* Clear the interrupt flag and the Acknoledge bit */
|
||||
bl _twsiDelay
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK)
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bl _twsiDelay
|
||||
|
||||
/* Wait for the interrupt flag (bit3) to be set */
|
||||
loop_14:
|
||||
#ifdef MV78XX0
|
||||
MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
|
||||
tst r6, #BIT2
|
||||
#else
|
||||
MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
|
||||
tst r6, #BIT5
|
||||
#endif
|
||||
beq loop_14
|
||||
|
||||
/* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */
|
||||
loop_15:
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||||
cmp r6, #0x58
|
||||
bne loop_15
|
||||
|
||||
/* Store the data in r7. */
|
||||
MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH))
|
||||
|
||||
/* Generate stop bit */
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
orr r6, r6, #TWSI_CONTROL_STOP_BIT
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
|
||||
|
||||
/* Clear the interrupt flag */
|
||||
bl _twsiDelay
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
|
||||
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
bl _twsiDelay
|
||||
|
||||
/* Wait for the stop bit to be reset by HW */
|
||||
loop_16:
|
||||
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||||
tst r6, #TWSI_CONTROL_INT_FLAG_SET
|
||||
bne loop_16
|
||||
|
||||
exit_i2cRead:
|
||||
mov PC, r9 /* r9 is saved link register */
|
||||
@ -287,6 +287,8 @@ static inline void *sg_virt(struct scatterlist *sg)
|
||||
|
||||
#define sg_init_table(sg, n)
|
||||
|
||||
#define sg_mark_end(sg)
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef late_initcall
|
||||
@ -359,13 +361,9 @@ static inline int ocf_run_thread(void *arg)
|
||||
#include <linux/kthread.h>
|
||||
#endif
|
||||
|
||||
#include <linux/skbuff.h>
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)
|
||||
static inline struct page *skb_frag_page(const skb_frag_t *frag)
|
||||
{
|
||||
return frag->page;
|
||||
}
|
||||
#define skb_frag_page(x) ((x)->page)
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
@ -1944,12 +1944,10 @@ static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent)
|
||||
return(-ENODEV);
|
||||
}
|
||||
|
||||
#ifdef HAVE_PCI_SET_MWI
|
||||
if (pci_set_mwi(dev)) {
|
||||
printk("safe: pci_set_mwi failed!");
|
||||
return(-ENODEV);
|
||||
}
|
||||
#endif
|
||||
|
||||
sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL);
|
||||
if (!sc)
|
||||
|
||||
@ -1,13 +1,3 @@
|
||||
--- a/kernel/pid.c
|
||||
+++ b/kernel/pid.c
|
||||
@@ -430,6 +430,7 @@ struct task_struct *find_task_by_vpid(pi
|
||||
{
|
||||
return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns);
|
||||
}
|
||||
+EXPORT_SYMBOL(find_task_by_vpid);
|
||||
|
||||
struct pid *get_task_pid(struct task_struct *task, enum pid_type type)
|
||||
{
|
||||
--- a/drivers/char/random.c
|
||||
+++ b/drivers/char/random.c
|
||||
@@ -130,6 +130,9 @@
|
||||
@ -120,7 +110,38 @@
|
||||
#define RTC_MINOR 135
|
||||
--- a/include/linux/random.h
|
||||
+++ b/include/linux/random.h
|
||||
@@ -54,6 +54,10 @@ extern void add_input_randomness(unsigne
|
||||
@@ -34,6 +34,30 @@
|
||||
/* Clear the entropy pool and associated counters. (Superuser only.) */
|
||||
#define RNDCLEARPOOL _IO( 'R', 0x06 )
|
||||
|
||||
+#ifdef CONFIG_FIPS_RNG
|
||||
+
|
||||
+/* Size of seed value - equal to AES blocksize */
|
||||
+#define AES_BLOCK_SIZE_BYTES 16
|
||||
+#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES
|
||||
+/* Size of AES key */
|
||||
+#define KEY_SIZE_BYTES 16
|
||||
+
|
||||
+/* ioctl() structure used by FIPS 140-2 Tests */
|
||||
+struct rand_fips_test {
|
||||
+ unsigned char key[KEY_SIZE_BYTES]; /* Input */
|
||||
+ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */
|
||||
+ unsigned char seed[SEED_SIZE_BYTES]; /* Input */
|
||||
+ unsigned char result[SEED_SIZE_BYTES]; /* Output */
|
||||
+};
|
||||
+
|
||||
+/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */
|
||||
+#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test)
|
||||
+
|
||||
+/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */
|
||||
+#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test)
|
||||
+
|
||||
+#endif /* #ifdef CONFIG_FIPS_RNG */
|
||||
+
|
||||
struct rand_pool_info {
|
||||
int entropy_count;
|
||||
int buf_size;
|
||||
@@ -54,6 +78,10 @@ extern void add_input_randomness(unsigne
|
||||
unsigned int value);
|
||||
extern void add_interrupt_randomness(int irq);
|
||||
|
||||
@ -131,3 +152,13 @@
|
||||
extern void get_random_bytes(void *buf, int nbytes);
|
||||
void generate_random_uuid(unsigned char uuid_out[16]);
|
||||
|
||||
--- a/kernel/pid.c
|
||||
+++ b/kernel/pid.c
|
||||
@@ -430,6 +430,7 @@ struct task_struct *find_task_by_vpid(pi
|
||||
{
|
||||
return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns);
|
||||
}
|
||||
+EXPORT_SYMBOL(find_task_by_vpid);
|
||||
|
||||
struct pid *get_task_pid(struct task_struct *task, enum pid_type type)
|
||||
{
|
||||
Loading…
Reference in New Issue
Block a user