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mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-11-27 20:41:53 +02:00

[backfire] backport ssb updates from r21269, this is required for future mac80211 updates

git-svn-id: svn://svn.openwrt.org/openwrt/branches/backfire@21276 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd 2010-04-30 16:54:57 +00:00
parent 5970ed4ddb
commit 9631bdae21
9 changed files with 2295 additions and 192 deletions

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@ -345,7 +345,7 @@
}
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -739,6 +739,9 @@ static void __cpuinit build_r4000_tlb_re
@@ -733,6 +733,9 @@ static void __cpuinit build_r4000_tlb_re
/* No need for uasm_i_nop */
}
@ -355,7 +355,7 @@
#ifdef CONFIG_64BIT
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
#else
@@ -1193,6 +1196,9 @@ build_r4000_tlbchange_handler_head(u32 *
@@ -1185,6 +1188,9 @@ build_r4000_tlbchange_handler_head(u32 *
struct uasm_reloc **r, unsigned int pte,
unsigned int ptr)
{

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@ -1,36 +0,0 @@
From 83e34f03ee9b86b49bde4707a1fe03a1837e29be Mon Sep 17 00:00:00 2001
From: Jochen Friedrich <jochen@scram.de>
Date: Wed, 3 Feb 2010 21:28:11 +0100
Subject: [PATCH 1/1] ssb: fix interrupt assignment
Explicitely enable shared interrupt 2 for any core that didn't get a dedicated IRQ
anymore (fallthrough case) and for EXTIF cores to make gpio interrupts work.
Also remove a bogus comment.
Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
---
drivers/ssb/driver_mipscore.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
set_irq(dev, irq++);
}
break;
- /* fallthrough */
case SSB_DEV_PCI:
case SSB_DEV_ETHERNET:
case SSB_DEV_ETHERNET_GBIT:
@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
set_irq(dev, irq++);
break;
}
+ /* fallthrough */
+ case SSB_DEV_EXTIF:
+ set_irq(dev, 0);
+ break;
}
}
ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");

View File

@ -1,6 +1,6 @@
--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
u32 *plltype, u32 *n, u32 *m)
{
@ -9,7 +9,7 @@
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
switch (*plltype) {
@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
u32 *plltype, u32 *n, u32 *m)
{
@ -31,7 +31,7 @@
}
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -1066,6 +1066,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
@@ -1073,6 +1073,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
if (bus->chip_id == 0x5365) {
rate = 100000000;

View File

@ -102,7 +102,7 @@
tg3_readphy(tp, MII_BMSR, &tmp);
if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
(tmp & BMSR_LSTATUS))
@@ -6264,6 +6289,11 @@ static int tg3_poll_fw(struct tg3 *tp)
@@ -6273,6 +6298,11 @@ static int tg3_poll_fw(struct tg3 *tp)
int i;
u32 val;
@ -114,7 +114,7 @@
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
/* Wait up to 20ms for init done. */
for (i = 0; i < 200; i++) {
@@ -6541,6 +6571,14 @@ static int tg3_chip_reset(struct tg3 *tp
@@ -6550,6 +6580,14 @@ static int tg3_chip_reset(struct tg3 *tp
tw32(0x5000, 0x400);
}
@ -129,7 +129,7 @@
tw32(GRC_MODE, tp->grc_mode);
if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
@@ -6695,9 +6733,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
@@ -6704,9 +6742,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
return -ENODEV;
}
@ -145,7 +145,7 @@
return 0;
}
@@ -6760,6 +6801,11 @@ static int tg3_load_5701_a0_firmware_fix
@@ -6769,6 +6810,11 @@ static int tg3_load_5701_a0_firmware_fix
const __be32 *fw_data;
int err, i;
@ -157,7 +157,7 @@
fw_data = (void *)tp->fw->data;
/* Firmware blob starts with version numbers, followed by
@@ -6819,6 +6865,11 @@ static int tg3_load_tso_firmware(struct
@@ -6828,6 +6874,11 @@ static int tg3_load_tso_firmware(struct
unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
int err, i;
@ -169,7 +169,7 @@
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
return 0;
@@ -7906,6 +7957,11 @@ static void tg3_timer(unsigned long __op
@@ -7915,6 +7966,11 @@ static void tg3_timer(unsigned long __op
spin_lock(&tp->lock);
@ -181,7 +181,7 @@
if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
/* All of this garbage is because when using non-tagged
* IRQ status the mailbox/status_block protocol the chip
@@ -9791,6 +9847,11 @@ static int tg3_test_nvram(struct tg3 *tp
@@ -9800,6 +9856,11 @@ static int tg3_test_nvram(struct tg3 *tp
if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
return 0;
@ -193,7 +193,7 @@
if (tg3_nvram_read(tp, 0, &magic) != 0)
return -EIO;
@@ -10585,7 +10646,7 @@ static int tg3_ioctl(struct net_device *
@@ -10594,7 +10655,7 @@ static int tg3_ioctl(struct net_device *
return -EAGAIN;
spin_lock_bh(&tp->lock);
@ -202,7 +202,7 @@
spin_unlock_bh(&tp->lock);
data->val_out = mii_regval;
@@ -10601,7 +10662,7 @@ static int tg3_ioctl(struct net_device *
@@ -10610,7 +10671,7 @@ static int tg3_ioctl(struct net_device *
return -EAGAIN;
spin_lock_bh(&tp->lock);
@ -211,7 +211,7 @@
spin_unlock_bh(&tp->lock);
return err;
@@ -11246,6 +11307,12 @@ static void __devinit tg3_get_5717_nvram
@@ -11255,6 +11316,12 @@ static void __devinit tg3_get_5717_nvram
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
static void __devinit tg3_nvram_init(struct tg3 *tp)
{
@ -224,7 +224,7 @@
tw32_f(GRC_EEPROM_ADDR,
(EEPROM_ADDR_FSM_RESET |
(EEPROM_DEFAULT_CLOCK_PERIOD <<
@@ -11506,6 +11573,9 @@ static int tg3_nvram_write_block(struct
@@ -11515,6 +11582,9 @@ static int tg3_nvram_write_block(struct
{
int ret;
@ -234,7 +234,7 @@
if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
~GRC_LCLCTRL_GPIO_OUTPUT1);
@@ -12788,6 +12858,11 @@ static int __devinit tg3_get_invariants(
@@ -12800,6 +12870,11 @@ static int __devinit tg3_get_invariants(
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
@ -246,7 +246,7 @@
/* Get eeprom hw config before calling tg3_set_power_state().
* In particular, the TG3_FLG2_IS_NIC flag must be
* determined before calling tg3_set_power_state() so that
@@ -13177,6 +13252,10 @@ static int __devinit tg3_get_device_addr
@@ -13189,6 +13264,10 @@ static int __devinit tg3_get_device_addr
}
if (!is_valid_ether_addr(&dev->dev_addr[0])) {
@ -257,7 +257,7 @@
#ifdef CONFIG_SPARC
if (!tg3_get_default_macaddr_sparc(tp))
return 0;
@@ -13669,6 +13748,7 @@ static char * __devinit tg3_phy_string(s
@@ -13681,6 +13760,7 @@ static char * __devinit tg3_phy_string(s
case PHY_ID_BCM5704: return "5704";
case PHY_ID_BCM5705: return "5705";
case PHY_ID_BCM5750: return "5750";
@ -265,7 +265,7 @@
case PHY_ID_BCM5752: return "5752";
case PHY_ID_BCM5714: return "5714";
case PHY_ID_BCM5780: return "5780";
@@ -13880,6 +13960,13 @@ static int __devinit tg3_init_one(struct
@@ -13892,6 +13972,13 @@ static int __devinit tg3_init_one(struct
tp->msg_enable = tg3_debug;
else
tp->msg_enable = TG3_DEF_MSG_ENABLE;
@ -291,7 +291,7 @@
#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
@@ -2821,6 +2824,7 @@ struct tg3 {
@@ -2824,6 +2827,7 @@ struct tg3 {
#define PHY_ID_BCM5714 0x60008340
#define PHY_ID_BCM5780 0x60008350
#define PHY_ID_BCM5755 0xbc050cc0
@ -299,7 +299,7 @@
#define PHY_ID_BCM5787 0xbc050ce0
#define PHY_ID_BCM5756 0xbc050ed0
#define PHY_ID_BCM5784 0xbc050fa0
@@ -2865,7 +2869,7 @@ struct tg3 {
@@ -2868,7 +2872,7 @@ struct tg3 {
(X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
(X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
(X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \

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@ -1,6 +1,6 @@
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -815,7 +815,7 @@ static int b44_rx(struct b44 *bp, int bu
@@ -848,7 +848,7 @@ static int b44_rx(struct b44 *bp, int bu
struct sk_buff *copy_skb;
b44_recycle_rx(bp, cons, bp->rx_prod);

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@ -31,7 +31,7 @@
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -601,6 +601,9 @@ build_get_pgde32(u32 **p, unsigned int t
@@ -595,6 +595,9 @@ build_get_pgde32(u32 **p, unsigned int t
#endif
uasm_i_addu(p, ptr, tmp, ptr);
#else
@ -41,7 +41,7 @@
UASM_i_LA_mostly(p, ptr, pgdc);
#endif
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
@@ -739,12 +742,12 @@ static void __cpuinit build_r4000_tlb_re
@@ -733,12 +736,12 @@ static void __cpuinit build_r4000_tlb_re
/* No need for uasm_i_nop */
}
@ -57,7 +57,7 @@
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
#endif
@@ -756,6 +759,9 @@ static void __cpuinit build_r4000_tlb_re
@@ -750,6 +753,9 @@ static void __cpuinit build_r4000_tlb_re
build_update_entries(&p, K0, K1);
build_tlb_write_entry(&p, &l, &r, tlb_random);
uasm_l_leave(&l, p);
@ -67,7 +67,7 @@
uasm_i_eret(&p); /* return from trap */
#ifdef CONFIG_HUGETLB_PAGE
@@ -1196,12 +1202,12 @@ build_r4000_tlbchange_handler_head(u32 *
@@ -1188,12 +1194,12 @@ build_r4000_tlbchange_handler_head(u32 *
struct uasm_reloc **r, unsigned int pte,
unsigned int ptr)
{
@ -83,7 +83,7 @@
build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
#endif
@@ -1238,6 +1244,9 @@ build_r4000_tlbchange_handler_tail(u32 *
@@ -1230,6 +1236,9 @@ build_r4000_tlbchange_handler_tail(u32 *
build_update_entries(p, tmp, ptr);
build_tlb_write_entry(p, l, r, tlb_indexed);
uasm_l_leave(l, *p);

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@ -1,51 +0,0 @@
--- a/drivers/ssb/driver_pcicore.c
+++ b/drivers/ssb/driver_pcicore.c
@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
.pci_ops = &ssb_pcicore_pciops,
.io_resource = &ssb_pcicore_io_resource,
.mem_resource = &ssb_pcicore_mem_resource,
- .mem_offset = 0x24000000,
};
-static u32 ssb_pcicore_pcibus_iobase = 0x100;
-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
-
/* This function is called when doing a pci_enable_device().
* We must first check if the device is a device on the PCI-core bridge. */
int ssb_pcicore_plat_dev_init(struct pci_dev *d)
{
- struct resource *res;
- int pos, size;
- u32 *base;
-
if (d->bus->ops != &ssb_pcicore_pciops) {
/* This is not a device on the PCI-core bridge. */
return -ENODEV;
@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
pci_name(d));
- /* Fix up resource bases */
- for (pos = 0; pos < 6; pos++) {
- res = &d->resource[pos];
- if (res->flags & IORESOURCE_IO)
- base = &ssb_pcicore_pcibus_iobase;
- else
- base = &ssb_pcicore_pcibus_membase;
- res->flags |= IORESOURCE_PCI_FIXED;
- if (res->end) {
- size = res->end - res->start + 1;
- if (*base & (size - 1))
- *base = (*base + size) & ~(size - 1);
- res->start = *base;
- res->end = res->start + size - 1;
- *base += size;
- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
- }
- /* Fix up PCI bridge BAR0 only */
- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
- break;
- }
/* Fix up interrupt lines */
d->irq = ssb_mips_irq(extpci_core->dev) + 2;
pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);

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