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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-24 02:19:23 +02:00
[backfire] backport ssb updates from r21269, this is required for future mac80211 updates
git-svn-id: svn://svn.openwrt.org/openwrt/branches/backfire@21276 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
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5970ed4ddb
commit
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@ -345,7 +345,7 @@
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}
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -739,6 +739,9 @@ static void __cpuinit build_r4000_tlb_re
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@@ -733,6 +733,9 @@ static void __cpuinit build_r4000_tlb_re
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/* No need for uasm_i_nop */
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}
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@ -355,7 +355,7 @@
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#ifdef CONFIG_64BIT
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build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
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#else
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@@ -1193,6 +1196,9 @@ build_r4000_tlbchange_handler_head(u32 *
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@@ -1185,6 +1188,9 @@ build_r4000_tlbchange_handler_head(u32 *
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struct uasm_reloc **r, unsigned int pte,
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unsigned int ptr)
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{
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@ -1,36 +0,0 @@
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From 83e34f03ee9b86b49bde4707a1fe03a1837e29be Mon Sep 17 00:00:00 2001
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From: Jochen Friedrich <jochen@scram.de>
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Date: Wed, 3 Feb 2010 21:28:11 +0100
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Subject: [PATCH 1/1] ssb: fix interrupt assignment
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Explicitely enable shared interrupt 2 for any core that didn't get a dedicated IRQ
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anymore (fallthrough case) and for EXTIF cores to make gpio interrupts work.
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Also remove a bogus comment.
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Signed-off-by: Jochen Friedrich <jochen@scram.de>
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Signed-off-by: John W. Linville <linville@tuxdriver.com>
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---
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drivers/ssb/driver_mipscore.c | 5 ++++-
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1 files changed, 4 insertions(+), 1 deletions(-)
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
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set_irq(dev, irq++);
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}
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break;
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- /* fallthrough */
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case SSB_DEV_PCI:
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case SSB_DEV_ETHERNET:
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case SSB_DEV_ETHERNET_GBIT:
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@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
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set_irq(dev, irq++);
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break;
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}
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+ /* fallthrough */
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+ case SSB_DEV_EXTIF:
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+ set_irq(dev, 0);
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+ break;
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}
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}
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ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
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@ -1,6 +1,6 @@
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--- a/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
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@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco
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void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
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u32 *plltype, u32 *n, u32 *m)
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{
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@ -9,7 +9,7 @@
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*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
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*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
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switch (*plltype) {
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@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
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@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
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void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
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u32 *plltype, u32 *n, u32 *m)
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{
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@ -31,7 +31,7 @@
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}
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -1066,6 +1066,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
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@@ -1073,6 +1073,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
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if (bus->chip_id == 0x5365) {
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rate = 100000000;
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@ -102,7 +102,7 @@
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tg3_readphy(tp, MII_BMSR, &tmp);
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if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
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(tmp & BMSR_LSTATUS))
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@@ -6264,6 +6289,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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@@ -6273,6 +6298,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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int i;
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u32 val;
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@ -114,7 +114,7 @@
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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/* Wait up to 20ms for init done. */
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for (i = 0; i < 200; i++) {
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@@ -6541,6 +6571,14 @@ static int tg3_chip_reset(struct tg3 *tp
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@@ -6550,6 +6580,14 @@ static int tg3_chip_reset(struct tg3 *tp
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tw32(0x5000, 0x400);
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}
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@ -129,7 +129,7 @@
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tw32(GRC_MODE, tp->grc_mode);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
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@@ -6695,9 +6733,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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@@ -6704,9 +6742,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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return -ENODEV;
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}
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@ -145,7 +145,7 @@
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return 0;
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}
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@@ -6760,6 +6801,11 @@ static int tg3_load_5701_a0_firmware_fix
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@@ -6769,6 +6810,11 @@ static int tg3_load_5701_a0_firmware_fix
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const __be32 *fw_data;
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int err, i;
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@ -157,7 +157,7 @@
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fw_data = (void *)tp->fw->data;
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/* Firmware blob starts with version numbers, followed by
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@@ -6819,6 +6865,11 @@ static int tg3_load_tso_firmware(struct
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@@ -6828,6 +6874,11 @@ static int tg3_load_tso_firmware(struct
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unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
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int err, i;
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@ -169,7 +169,7 @@
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if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
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return 0;
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@@ -7906,6 +7957,11 @@ static void tg3_timer(unsigned long __op
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@@ -7915,6 +7966,11 @@ static void tg3_timer(unsigned long __op
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spin_lock(&tp->lock);
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@ -181,7 +181,7 @@
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if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
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/* All of this garbage is because when using non-tagged
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* IRQ status the mailbox/status_block protocol the chip
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@@ -9791,6 +9847,11 @@ static int tg3_test_nvram(struct tg3 *tp
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@@ -9800,6 +9856,11 @@ static int tg3_test_nvram(struct tg3 *tp
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if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
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return 0;
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@ -193,7 +193,7 @@
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if (tg3_nvram_read(tp, 0, &magic) != 0)
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return -EIO;
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@@ -10585,7 +10646,7 @@ static int tg3_ioctl(struct net_device *
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@@ -10594,7 +10655,7 @@ static int tg3_ioctl(struct net_device *
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return -EAGAIN;
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spin_lock_bh(&tp->lock);
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@ -202,7 +202,7 @@
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spin_unlock_bh(&tp->lock);
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data->val_out = mii_regval;
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@@ -10601,7 +10662,7 @@ static int tg3_ioctl(struct net_device *
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@@ -10610,7 +10671,7 @@ static int tg3_ioctl(struct net_device *
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return -EAGAIN;
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spin_lock_bh(&tp->lock);
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@ -211,7 +211,7 @@
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spin_unlock_bh(&tp->lock);
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return err;
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@@ -11246,6 +11307,12 @@ static void __devinit tg3_get_5717_nvram
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@@ -11255,6 +11316,12 @@ static void __devinit tg3_get_5717_nvram
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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static void __devinit tg3_nvram_init(struct tg3 *tp)
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{
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@ -224,7 +224,7 @@
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tw32_f(GRC_EEPROM_ADDR,
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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@@ -11506,6 +11573,9 @@ static int tg3_nvram_write_block(struct
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@@ -11515,6 +11582,9 @@ static int tg3_nvram_write_block(struct
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{
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int ret;
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@ -234,7 +234,7 @@
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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@@ -12788,6 +12858,11 @@ static int __devinit tg3_get_invariants(
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@@ -12800,6 +12870,11 @@ static int __devinit tg3_get_invariants(
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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@ -246,7 +246,7 @@
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/* Get eeprom hw config before calling tg3_set_power_state().
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* In particular, the TG3_FLG2_IS_NIC flag must be
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* determined before calling tg3_set_power_state() so that
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@@ -13177,6 +13252,10 @@ static int __devinit tg3_get_device_addr
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@@ -13189,6 +13264,10 @@ static int __devinit tg3_get_device_addr
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}
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if (!is_valid_ether_addr(&dev->dev_addr[0])) {
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@ -257,7 +257,7 @@
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#ifdef CONFIG_SPARC
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if (!tg3_get_default_macaddr_sparc(tp))
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return 0;
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@@ -13669,6 +13748,7 @@ static char * __devinit tg3_phy_string(s
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@@ -13681,6 +13760,7 @@ static char * __devinit tg3_phy_string(s
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case PHY_ID_BCM5704: return "5704";
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case PHY_ID_BCM5705: return "5705";
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case PHY_ID_BCM5750: return "5750";
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@ -265,7 +265,7 @@
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case PHY_ID_BCM5752: return "5752";
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case PHY_ID_BCM5714: return "5714";
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case PHY_ID_BCM5780: return "5780";
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@@ -13880,6 +13960,13 @@ static int __devinit tg3_init_one(struct
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@@ -13892,6 +13972,13 @@ static int __devinit tg3_init_one(struct
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tp->msg_enable = tg3_debug;
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else
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tp->msg_enable = TG3_DEF_MSG_ENABLE;
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@ -291,7 +291,7 @@
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#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
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@@ -2821,6 +2824,7 @@ struct tg3 {
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@@ -2824,6 +2827,7 @@ struct tg3 {
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#define PHY_ID_BCM5714 0x60008340
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#define PHY_ID_BCM5780 0x60008350
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#define PHY_ID_BCM5755 0xbc050cc0
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@ -299,7 +299,7 @@
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#define PHY_ID_BCM5787 0xbc050ce0
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#define PHY_ID_BCM5756 0xbc050ed0
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#define PHY_ID_BCM5784 0xbc050fa0
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@@ -2865,7 +2869,7 @@ struct tg3 {
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@@ -2868,7 +2872,7 @@ struct tg3 {
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(X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
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(X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
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(X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
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@ -1,6 +1,6 @@
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--- a/drivers/net/b44.c
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+++ b/drivers/net/b44.c
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@@ -815,7 +815,7 @@ static int b44_rx(struct b44 *bp, int bu
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@@ -848,7 +848,7 @@ static int b44_rx(struct b44 *bp, int bu
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struct sk_buff *copy_skb;
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b44_recycle_rx(bp, cons, bp->rx_prod);
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@ -31,7 +31,7 @@
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -601,6 +601,9 @@ build_get_pgde32(u32 **p, unsigned int t
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@@ -595,6 +595,9 @@ build_get_pgde32(u32 **p, unsigned int t
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#endif
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uasm_i_addu(p, ptr, tmp, ptr);
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#else
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@ -41,7 +41,7 @@
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UASM_i_LA_mostly(p, ptr, pgdc);
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#endif
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uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
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@@ -739,12 +742,12 @@ static void __cpuinit build_r4000_tlb_re
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@@ -733,12 +736,12 @@ static void __cpuinit build_r4000_tlb_re
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/* No need for uasm_i_nop */
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}
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@ -57,7 +57,7 @@
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build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
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#endif
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@@ -756,6 +759,9 @@ static void __cpuinit build_r4000_tlb_re
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@@ -750,6 +753,9 @@ static void __cpuinit build_r4000_tlb_re
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build_update_entries(&p, K0, K1);
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build_tlb_write_entry(&p, &l, &r, tlb_random);
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uasm_l_leave(&l, p);
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@ -67,7 +67,7 @@
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uasm_i_eret(&p); /* return from trap */
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#ifdef CONFIG_HUGETLB_PAGE
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@@ -1196,12 +1202,12 @@ build_r4000_tlbchange_handler_head(u32 *
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@@ -1188,12 +1194,12 @@ build_r4000_tlbchange_handler_head(u32 *
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struct uasm_reloc **r, unsigned int pte,
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unsigned int ptr)
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{
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@ -83,7 +83,7 @@
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build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
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#endif
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@@ -1238,6 +1244,9 @@ build_r4000_tlbchange_handler_tail(u32 *
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@@ -1230,6 +1236,9 @@ build_r4000_tlbchange_handler_tail(u32 *
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build_update_entries(p, tmp, ptr);
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build_tlb_write_entry(p, l, r, tlb_indexed);
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uasm_l_leave(l, *p);
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@ -1,51 +0,0 @@
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--- a/drivers/ssb/driver_pcicore.c
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+++ b/drivers/ssb/driver_pcicore.c
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@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
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.pci_ops = &ssb_pcicore_pciops,
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.io_resource = &ssb_pcicore_io_resource,
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.mem_resource = &ssb_pcicore_mem_resource,
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- .mem_offset = 0x24000000,
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};
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-static u32 ssb_pcicore_pcibus_iobase = 0x100;
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-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
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-
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/* This function is called when doing a pci_enable_device().
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* We must first check if the device is a device on the PCI-core bridge. */
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int ssb_pcicore_plat_dev_init(struct pci_dev *d)
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{
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- struct resource *res;
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- int pos, size;
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- u32 *base;
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-
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if (d->bus->ops != &ssb_pcicore_pciops) {
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/* This is not a device on the PCI-core bridge. */
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return -ENODEV;
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@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
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ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
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pci_name(d));
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- /* Fix up resource bases */
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- for (pos = 0; pos < 6; pos++) {
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- res = &d->resource[pos];
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- if (res->flags & IORESOURCE_IO)
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- base = &ssb_pcicore_pcibus_iobase;
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- else
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- base = &ssb_pcicore_pcibus_membase;
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- res->flags |= IORESOURCE_PCI_FIXED;
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- if (res->end) {
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- size = res->end - res->start + 1;
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- if (*base & (size - 1))
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- *base = (*base + size) & ~(size - 1);
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- res->start = *base;
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- res->end = res->start + size - 1;
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- *base += size;
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- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
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- }
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- /* Fix up PCI bridge BAR0 only */
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- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
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- break;
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- }
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/* Fix up interrupt lines */
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d->irq = ssb_mips_irq(extpci_core->dev) + 2;
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pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
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File diff suppressed because it is too large
Load Diff
1231
target/linux/generic-2.6/patches-2.6.32/975-ssb_update.patch
Normal file
1231
target/linux/generic-2.6/patches-2.6.32/975-ssb_update.patch
Normal file
File diff suppressed because it is too large
Load Diff
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