mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
add u-boot sources for danube
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11108 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
2033
target/linux/ifxmips/image/u-boot/files/include/asm-mips/danube.h
Normal file
2033
target/linux/ifxmips/image/u-boot/files/include/asm-mips/danube.h
Normal file
File diff suppressed because it is too large
Load Diff
138
target/linux/ifxmips/image/u-boot/files/include/asm-mips/errno.h
Normal file
138
target/linux/ifxmips/image/u-boot/files/include/asm-mips/errno.h
Normal file
@@ -0,0 +1,138 @@
|
||||
#ifndef _ARM_ERRNO_H
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||||
#define _ARM_ERRNO_H
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||||
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||||
#define EPERM 1 /* Operation not permitted */
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||||
#define ENOENT 2 /* No such file or directory */
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||||
#define ESRCH 3 /* No such process */
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#define EINTR 4 /* Interrupted system call */
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||||
#define EIO 5 /* I/O error */
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||||
#define ENXIO 6 /* No such device or address */
|
||||
#define E2BIG 7 /* Arg list too long */
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||||
#define ENOEXEC 8 /* Exec format error */
|
||||
#define EBADF 9 /* Bad file number */
|
||||
#define ECHILD 10 /* No child processes */
|
||||
#define EAGAIN 11 /* Try again */
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#define ENOMEM 12 /* Out of memory */
|
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#define EACCES 13 /* Permission denied */
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||||
#define EFAULT 14 /* Bad address */
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||||
#define ENOTBLK 15 /* Block device required */
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||||
#define EBUSY 16 /* Device or resource busy */
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||||
#define EEXIST 17 /* File exists */
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#define EXDEV 18 /* Cross-device link */
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#define ENODEV 19 /* No such device */
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#define ENOTDIR 20 /* Not a directory */
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#define EISDIR 21 /* Is a directory */
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||||
#define EINVAL 22 /* Invalid argument */
|
||||
#define ENFILE 23 /* File table overflow */
|
||||
#define EMFILE 24 /* Too many open files */
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||||
#define ENOTTY 25 /* Not a typewriter */
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||||
#define ETXTBSY 26 /* Text file busy */
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||||
#define EFBIG 27 /* File too large */
|
||||
#define ENOSPC 28 /* No space left on device */
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||||
#define ESPIPE 29 /* Illegal seek */
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||||
#define EROFS 30 /* Read-only file system */
|
||||
#define EMLINK 31 /* Too many links */
|
||||
#define EPIPE 32 /* Broken pipe */
|
||||
#define EDOM 33 /* Math argument out of domain of func */
|
||||
#define ERANGE 34 /* Math result not representable */
|
||||
#define EDEADLK 35 /* Resource deadlock would occur */
|
||||
#define ENAMETOOLONG 36 /* File name too long */
|
||||
#define ENOLCK 37 /* No record locks available */
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||||
#define ENOSYS 38 /* Function not implemented */
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||||
#define ENOTEMPTY 39 /* Directory not empty */
|
||||
#define ELOOP 40 /* Too many symbolic links encountered */
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#define EWOULDBLOCK EAGAIN /* Operation would block */
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#define ENOMSG 42 /* No message of desired type */
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#define EIDRM 43 /* Identifier removed */
|
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#define ECHRNG 44 /* Channel number out of range */
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#define EL2NSYNC 45 /* Level 2 not synchronized */
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#define EL3HLT 46 /* Level 3 halted */
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#define EL3RST 47 /* Level 3 reset */
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||||
#define ELNRNG 48 /* Link number out of range */
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#define EUNATCH 49 /* Protocol driver not attached */
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#define ENOCSI 50 /* No CSI structure available */
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#define EL2HLT 51 /* Level 2 halted */
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#define EBADE 52 /* Invalid exchange */
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#define EBADR 53 /* Invalid request descriptor */
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#define EXFULL 54 /* Exchange full */
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#define ENOANO 55 /* No anode */
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#define EBADRQC 56 /* Invalid request code */
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#define EBADSLT 57 /* Invalid slot */
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#define EDEADLOCK 58 /* File locking deadlock error */
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#define EBFONT 59 /* Bad font file format */
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#define ENOSTR 60 /* Device not a stream */
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#define ENODATA 61 /* No data available */
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#define ETIME 62 /* Timer expired */
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#define ENOSR 63 /* Out of streams resources */
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#define ENONET 64 /* Machine is not on the network */
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||||
#define ENOPKG 65 /* Package not installed */
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#define EREMOTE 66 /* Object is remote */
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#define ENOLINK 67 /* Link has been severed */
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||||
#define EADV 68 /* Advertise error */
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||||
#define ESRMNT 69 /* Srmount error */
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#define ECOMM 70 /* Communication error on send */
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#define EPROTO 71 /* Protocol error */
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#define EMULTIHOP 72 /* Multihop attempted */
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#define EDOTDOT 73 /* RFS specific error */
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||||
#define EBADMSG 74 /* Not a data message */
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#define EOVERFLOW 75 /* Value too large for defined data type */
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||||
#define ENOTUNIQ 76 /* Name not unique on network */
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||||
#define EBADFD 77 /* File descriptor in bad state */
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#define EREMCHG 78 /* Remote address changed */
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#define ELIBACC 79 /* Can not access a needed shared library */
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#define ELIBBAD 80 /* Accessing a corrupted shared library */
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||||
#define ELIBSCN 81 /* .lib section in a.out corrupted */
|
||||
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
|
||||
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
|
||||
#define EILSEQ 84 /* Illegal byte sequence */
|
||||
#define ERESTART 85 /* Interrupted system call should be restarted */
|
||||
#define ESTRPIPE 86 /* Streams pipe error */
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||||
#define EUSERS 87 /* Too many users */
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||||
#define ENOTSOCK 88 /* Socket operation on non-socket */
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||||
#define EDESTADDRREQ 89 /* Destination address required */
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#define EMSGSIZE 90 /* Message too long */
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||||
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
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||||
#define ENOPROTOOPT 92 /* Protocol not available */
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||||
#define EPROTONOSUPPORT 93 /* Protocol not supported */
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#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
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||||
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
|
||||
#define EPFNOSUPPORT 96 /* Protocol family not supported */
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||||
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
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||||
#define EADDRINUSE 98 /* Address already in use */
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||||
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
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#define ENETDOWN 100 /* Network is down */
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#define ENETUNREACH 101 /* Network is unreachable */
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||||
#define ENETRESET 102 /* Network dropped connection because of reset */
|
||||
#define ECONNABORTED 103 /* Software caused connection abort */
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||||
#define ECONNRESET 104 /* Connection reset by peer */
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||||
#define ENOBUFS 105 /* No buffer space available */
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#define EISCONN 106 /* Transport endpoint is already connected */
|
||||
#define ENOTCONN 107 /* Transport endpoint is not connected */
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||||
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
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||||
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
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#define ETIMEDOUT 110 /* Connection timed out */
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#define ECONNREFUSED 111 /* Connection refused */
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#define EHOSTDOWN 112 /* Host is down */
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#define EHOSTUNREACH 113 /* No route to host */
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#define EALREADY 114 /* Operation already in progress */
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#define EINPROGRESS 115 /* Operation now in progress */
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#define ESTALE 116 /* Stale NFS file handle */
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#define EUCLEAN 117 /* Structure needs cleaning */
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#define ENOTNAM 118 /* Not a XENIX named type file */
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||||
#define ENAVAIL 119 /* No XENIX semaphores available */
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||||
#define EISNAM 120 /* Is a named type file */
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||||
#define EREMOTEIO 121 /* Remote I/O error */
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#define EDQUOT 122 /* Quota exceeded */
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#define ENOMEDIUM 123 /* No medium found */
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#define EMEDIUMTYPE 124 /* Wrong medium type */
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||||
/* Should never be seen by user programs */
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||||
#define ERESTARTSYS 512
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#define ERESTARTNOINTR 513
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#define ERESTARTNOHAND 514 /* restart if no handler.. */
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#define ENOIOCTLCMD 515 /* No ioctl command */
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#define _LAST_ERRNO 515
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#endif
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@@ -0,0 +1,220 @@
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/*****************************************************************************
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* DANUBE BootROM
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* Copyright (c) 2005, Infineon Technologies AG, All rights reserved
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* IFAP DC COM SD
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*****************************************************************************/
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#ifndef __ASC_H
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#define __ASC_H
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#define DANUBEASC_TXFIFO_FL 1
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#define DANUBEASC_RXFIFO_FL 1
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#define DANUBEASC_TXFIFO_FULL 16
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/* channel operating modes */
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#define ASCOPT_CSIZE 0x00000003
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#define ASCOPT_CS7 0x00000001
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#define ASCOPT_CS8 0x00000002
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#define ASCOPT_PARENB 0x00000004
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#define ASCOPT_STOPB 0x00000008
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#define ASCOPT_PARODD 0x00000010
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#define ASCOPT_CREAD 0x00000020
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#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
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/* ASC input select (0 or 1) */
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#define CONSOLE_TTY 0
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#define DANUBEASC_TXFIFO_FL 1
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#define DANUBEASC_RXFIFO_FL 1
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#define DANUBEASC_TXFIFO_FULL 16
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/* interrupt lines masks for the ASC device interrupts*/
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/* change these macroses if it's necessary */
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#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
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#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
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#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
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#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
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#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
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#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
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#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
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#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
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/* interrupt controller access macros */
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#define ASC_INTERRUPTS_ENABLE(X) \
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*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X;
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#define ASC_INTERRUPTS_DISABLE(X) \
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*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X;
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#define ASC_INTERRUPTS_CLEAR(X) \
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*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X;
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/* CLC register's bits and bitfields */
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#define ASCCLC_DISR 0x00000001
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#define ASCCLC_DISS 0x00000002
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#define ASCCLC_RMCMASK 0x0000FF00
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#define ASCCLC_RMCOFFSET 8
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/* CON register's bits and bitfields */
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#define ASCCON_MODEMASK 0x0000000f
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#define ASCCON_M_8ASYNC 0x0
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#define ASCCON_M_8IRDA 0x1
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#define ASCCON_M_7ASYNC 0x2
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#define ASCCON_M_7IRDA 0x3
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#define ASCCON_WLSMASK 0x0000000c
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#define ASCCON_WLSOFFSET 2
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#define ASCCON_WLS_8BIT 0x0
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#define ASCCON_WLS_7BIT 0x1
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#define ASCCON_PEN 0x00000010
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#define ASCCON_ODD 0x00000020
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#define ASCCON_SP 0x00000040
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#define ASCCON_STP 0x00000080
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#define ASCCON_BRS 0x00000100
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#define ASCCON_FDE 0x00000200
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#define ASCCON_ERRCLK 0x00000400
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#define ASCCON_EMMASK 0x00001800
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#define ASCCON_EMOFFSET 11
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#define ASCCON_EM_ECHO_OFF 0x0
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#define ASCCON_EM_ECHO_AB 0x1
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#define ASCCON_EM_ECHO_ON 0x2
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#define ASCCON_LB 0x00002000
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#define ASCCON_ACO 0x00004000
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#define ASCCON_R 0x00008000
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#define ASCCON_PAL 0x00010000
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#define ASCCON_FEN 0x00020000
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#define ASCCON_RUEN 0x00040000
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#define ASCCON_ROEN 0x00080000
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#define ASCCON_TOEN 0x00100000
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#define ASCCON_BEN 0x00200000
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#define ASCCON_TXINV 0x01000000
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#define ASCCON_RXINV 0x02000000
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#define ASCCON_TXMSB 0x04000000
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#define ASCCON_RXMSB 0x08000000
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/* STATE register's bits and bitfields */
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#define ASCSTATE_REN 0x00000001
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#define ASCSTATE_PE 0x00010000
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#define ASCSTATE_FE 0x00020000
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#define ASCSTATE_RUE 0x00040000
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#define ASCSTATE_ROE 0x00080000
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#define ASCSTATE_TOE 0x00100000
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#define ASCSTATE_BE 0x00200000
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#define ASCSTATE_TXBVMASK 0x07000000
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#define ASCSTATE_TXBVOFFSET 24
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#define ASCSTATE_TXEOM 0x08000000
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||||
#define ASCSTATE_RXBVMASK 0x70000000
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#define ASCSTATE_RXBVOFFSET 28
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#define ASCSTATE_RXEOM 0x80000000
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/* WHBSTATE register's bits and bitfields */
|
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#define ASCWHBSTATE_CLRREN 0x00000001
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#define ASCWHBSTATE_SETREN 0x00000002
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#define ASCWHBSTATE_CLRPE 0x00000004
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#define ASCWHBSTATE_CLRFE 0x00000008
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#define ASCWHBSTATE_CLRRUE 0x00000010
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#define ASCWHBSTATE_CLRROE 0x00000020
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#define ASCWHBSTATE_CLRTOE 0x00000040
|
||||
#define ASCWHBSTATE_CLRBE 0x00000080
|
||||
#define ASCWHBSTATE_SETPE 0x00000100
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#define ASCWHBSTATE_SETFE 0x00000200
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#define ASCWHBSTATE_SETRUE 0x00000400
|
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#define ASCWHBSTATE_SETROE 0x00000800
|
||||
#define ASCWHBSTATE_SETTOE 0x00001000
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||||
#define ASCWHBSTATE_SETBE 0x00002000
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||||
|
||||
/* ABCON register's bits and bitfields */
|
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#define ASCABCON_ABEN 0x0001
|
||||
#define ASCABCON_AUREN 0x0002
|
||||
#define ASCABCON_ABSTEN 0x0004
|
||||
#define ASCABCON_ABDETEN 0x0008
|
||||
#define ASCABCON_FCDETEN 0x0010
|
||||
|
||||
/* FDV register mask, offset and bitfields*/
|
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#define ASCFDV_VALUE_MASK 0x000001FF
|
||||
|
||||
/* WHBABCON register's bits and bitfields */
|
||||
#define ASCWHBABCON_CLRABEN 0x0001
|
||||
#define ASCWHBABCON_SETABEN 0x0002
|
||||
|
||||
/* ABSTAT register's bits and bitfields */
|
||||
#define ASCABSTAT_FCSDET 0x0001
|
||||
#define ASCABSTAT_FCCDET 0x0002
|
||||
#define ASCABSTAT_SCSDET 0x0004
|
||||
#define ASCABSTAT_SCCDET 0x0008
|
||||
#define ASCABSTAT_DETWAIT 0x0010
|
||||
|
||||
/* WHBABSTAT register's bits and bitfields */
|
||||
#define ASCWHBABSTAT_CLRFCSDET 0x0001
|
||||
#define ASCWHBABSTAT_SETFCSDET 0x0002
|
||||
#define ASCWHBABSTAT_CLRFCCDET 0x0004
|
||||
#define ASCWHBABSTAT_SETFCCDET 0x0008
|
||||
#define ASCWHBABSTAT_CLRSCSDET 0x0010
|
||||
#define ASCWHBABSTAT_SETSCSDET 0x0020
|
||||
#define ASCWHBABSTAT_CLRSCCDET 0x0040
|
||||
#define ASCWHBABSTAT_SETSCCDET 0x0080
|
||||
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
|
||||
#define ASCWHBABSTAT_SETDETWAIT 0x0200
|
||||
|
||||
/* TXFCON register's bits and bitfields */
|
||||
#define ASCTXFCON_TXFIFO1 0x00000400
|
||||
#define ASCTXFCON_TXFEN 0x0001
|
||||
#define ASCTXFCON_TXFFLU 0x0002
|
||||
#define ASCTXFCON_TXFITLMASK 0x3F00
|
||||
#define ASCTXFCON_TXFITLOFF 8
|
||||
|
||||
/* RXFCON register's bits and bitfields */
|
||||
#define ASCRXFCON_RXFIFO1 0x00000400
|
||||
#define ASCRXFCON_RXFEN 0x0001
|
||||
#define ASCRXFCON_RXFFLU 0x0002
|
||||
#define ASCRXFCON_RXFITLMASK 0x3F00
|
||||
#define ASCRXFCON_RXFITLOFF 8
|
||||
|
||||
/* FSTAT register's bits and bitfields */
|
||||
#define ASCFSTAT_RXFFLMASK 0x003F
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
|
||||
typedef struct /* DanubeAsc_t */
|
||||
{
|
||||
volatile unsigned long asc_clc; /*0x0000*/
|
||||
volatile unsigned long asc_pisel; /*0x0004*/
|
||||
volatile unsigned long asc_id; /*0x0008*/
|
||||
volatile unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/
|
||||
volatile unsigned long asc_con; /*0x0010*/
|
||||
volatile unsigned long asc_state; /*0x0014*/
|
||||
volatile unsigned long asc_whbstate; /*0x0018*/
|
||||
volatile unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/
|
||||
volatile unsigned long asc_tbuf; /*0x0020*/
|
||||
volatile unsigned long asc_rbuf; /*0x0024*/
|
||||
volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/
|
||||
volatile unsigned long asc_abcon; /*0x0030*/
|
||||
volatile unsigned long asc_abstat; /* not used */ /*0x0034*/
|
||||
volatile unsigned long asc_whbabcon; /*0x0038*/
|
||||
volatile unsigned long asc_whbabstat; /* not used */ /*0x003C*/
|
||||
volatile unsigned long asc_rxfcon; /*0x0040*/
|
||||
volatile unsigned long asc_txfcon; /*0x0044*/
|
||||
volatile unsigned long asc_fstat; /*0x0048*/
|
||||
volatile unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/
|
||||
volatile unsigned long asc_bg; /*0x0050*/
|
||||
volatile unsigned long asc_bg_timer; /*0x0054*/
|
||||
volatile unsigned long asc_fdv; /*0x0058*/
|
||||
volatile unsigned long asc_pmw; /*0x005C*/
|
||||
volatile unsigned long asc_modcon; /*0x0060*/
|
||||
volatile unsigned long asc_modstat; /*0x0064*/
|
||||
volatile unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/
|
||||
volatile unsigned long asc_sfcc; /*0x0070*/
|
||||
volatile unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/
|
||||
volatile unsigned long asc_eomcon; /*0x0080*/
|
||||
volatile unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/
|
||||
volatile unsigned long asc_dmacon; /*0x00EC*/
|
||||
volatile unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/
|
||||
volatile unsigned long asc_irnen; /*0x00F4*/
|
||||
volatile unsigned long asc_irnicr; /*0x00F8*/
|
||||
volatile unsigned long asc_irncr; /*0x00FC*/
|
||||
} DanubeAsc_t;
|
||||
|
||||
int asc_init (void);
|
||||
void asc_puts (const char *s);
|
||||
void asc_putc (const char c);
|
||||
int asc_getc (void);
|
||||
|
||||
#endif /* __ASC_H */
|
||||
@@ -0,0 +1,634 @@
|
||||
/************************************************************************
|
||||
*
|
||||
* Copyright (c) 2005
|
||||
* Infineon Technologies AG
|
||||
* St. Martin Strasse 53; 81669 Muenchen; Germany
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
************************************************************************/
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : DMA register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_DMA (KSEG1+0x14101000)
|
||||
/***********************************************************************/
|
||||
#define CONFIGURATION_REGISTERS_CLC (INCA_IP2_DMA + 0x00)
|
||||
#define CONFIGURATION_REGISTERS_ID (INCA_IP2_DMA + 0x08)
|
||||
#define GENERAL_REGISTERS_DMA_CTRL (INCA_IP2_DMA + 0x10)
|
||||
#define CHANNEL_RELATED_REGISTERS_DMA_CS (INCA_IP2_DMA + 0x18)
|
||||
#define CHANNEL_RELATED_REGISTERS_DMA_CCTRL (INCA_IP2_DMA + 0x1C)
|
||||
#define CHANNEL_RELATED_REGISTERS_DMA_CDBA (INCA_IP2_DMA + 0x20)
|
||||
#define CHANNEL_RELATED_REGISTERS_DMA_CDLEN (INCA_IP2_DMA + 0x24)
|
||||
#define CHANNEL_RELATED_REGISTERS_DMA_CIE (INCA_IP2_DMA + 0x2C)
|
||||
#define CHANNEL_RELATED_REGISTERS_DMA_CIS (INCA_IP2_DMA + 0x28)
|
||||
#define CHANNEL_RELATED_REGISTERS_DMA_CPOLL (INCA_IP2_DMA + 0x14)
|
||||
|
||||
#define PORT_RELATED_REGISTERS_DMA_PS (INCA_IP2_DMA + 0x40)
|
||||
#define PORT_RELATED_REGISTERS_DMA_PCTRL (INCA_IP2_DMA + 0x44)
|
||||
|
||||
#define INTERRUPT_NODE_REGISTERS_DMA_IRNEN (INCA_IP2_DMA + 0xF4)
|
||||
#define INTERRUPT_NODE_REGISTERS_DMA_IRNCR (INCA_IP2_DMA + 0xF8)
|
||||
#define INTERRUPT_NODE_REGISTERS_DMA_IRNICR (INCA_IP2_DMA + 0xFC)
|
||||
|
||||
#if 0
|
||||
/* ISR */
|
||||
#define DMA_ISR_RDERR 0x20
|
||||
#define DMA_ISR_CMDCPT 0x10
|
||||
#define DMA_ISR_CPT 0x8
|
||||
#define DMA_ISR_DURR 0x4
|
||||
#define DMA_ISR_EOP 0x2
|
||||
#endif
|
||||
#define DMA_RESET_CHANNEL 0x00000002
|
||||
#define DMA_ENABLE_CHANNEL 0x00000001
|
||||
#define DMA_DESC_BYTEOFF_SHIFT 22
|
||||
|
||||
#define DMA_POLLING_ENABLE 0x80000000
|
||||
#define DMA_POLLING_CNT 0x50 /*minimum 0x10, max 0xfff0*/
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : ICU register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_ICU (KSEG1+0x1F880200)
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_ICU_IM0_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0000))
|
||||
#define INCA_IP2_ICU_IM0_IER ((volatile u32*)(INCA_IP2_ICU + 0x0008))
|
||||
#define INCA_IP2_ICU_IM0_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0010))
|
||||
#define INCA_IP2_ICU_IM0_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0018))
|
||||
#define INCA_IP2_ICU_IM0_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0020))
|
||||
#define INCA_IP2_ICU_IM0_IMR_IID (1 << 31)
|
||||
#define INCA_IP2_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
|
||||
#define INCA_IP2_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
|
||||
#define INCA_IP2_ICU_IM0_IR(value) (1 << (value))
|
||||
|
||||
#define INCA_IP2_ICU_IM1_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0028))
|
||||
#define INCA_IP2_ICU_IM1_IER ((volatile u32*)(INCA_IP2_ICU + 0x0030))
|
||||
#define INCA_IP2_ICU_IM1_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0038))
|
||||
#define INCA_IP2_ICU_IM1_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0040))
|
||||
#define INCA_IP2_ICU_IM1_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0048))
|
||||
#define INCA_IP2_ICU_IM1_IMR_IID (1 << 31)
|
||||
#define INCA_IP2_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
|
||||
#define INCA_IP2_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
|
||||
#define INCA_IP2_ICU_IM1_IR(value) (1 << (value))
|
||||
|
||||
#define INCA_IP2_ICU_IM2_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0050))
|
||||
#define INCA_IP2_ICU_IM2_IER ((volatile u32*)(INCA_IP2_ICU + 0x0058))
|
||||
#define INCA_IP2_ICU_IM2_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0060))
|
||||
#define INCA_IP2_ICU_IM2_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0068))
|
||||
#define INCA_IP2_ICU_IM2_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0070))
|
||||
#define INCA_IP2_ICU_IM2_IMR_IID (1 << 31)
|
||||
#define INCA_IP2_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
|
||||
#define INCA_IP2_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
|
||||
#define INCA_IP2_ICU_IM2_IR(value) (1 << (value))
|
||||
|
||||
#define INCA_IP2_ICU_IM3_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0078))
|
||||
#define INCA_IP2_ICU_IM3_IER ((volatile u32*)(INCA_IP2_ICU + 0x0080))
|
||||
#define INCA_IP2_ICU_IM3_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0088))
|
||||
#define INCA_IP2_ICU_IM3_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0090))
|
||||
#define INCA_IP2_ICU_IM3_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0098))
|
||||
#define INCA_IP2_ICU_IM3_IMR_IID (1 << 31)
|
||||
#define INCA_IP2_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
|
||||
#define INCA_IP2_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
|
||||
#define INCA_IP2_ICU_IM3_IR(value) (1 << (value))
|
||||
|
||||
#define INCA_IP2_ICU_IM4_ISR ((volatile u32*)(INCA_IP2_ICU + 0x00A0))
|
||||
#define INCA_IP2_ICU_IM4_IER ((volatile u32*)(INCA_IP2_ICU + 0x00A8))
|
||||
#define INCA_IP2_ICU_IM4_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x00B0))
|
||||
#define INCA_IP2_ICU_IM4_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x00B8))
|
||||
#define INCA_IP2_ICU_IM4_IMR ((volatile u32*)(INCA_IP2_ICU + 0x00C0))
|
||||
#define INCA_IP2_ICU_IM4_IMR_IID (1 << 31)
|
||||
#define INCA_IP2_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
|
||||
#define INCA_IP2_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
|
||||
#define INCA_IP2_ICU_IM4_IR(value) (1 << (value))
|
||||
|
||||
#define INCA_IP2_ICU_IM5_ISR ((volatile u32*)(INCA_IP2_ICU + 0x00C8))
|
||||
#define INCA_IP2_ICU_IM5_IER ((volatile u32*)(INCA_IP2_ICU + 0x00D0))
|
||||
#define INCA_IP2_ICU_IM5_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x00D8))
|
||||
#define INCA_IP2_ICU_IM5_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x00E0))
|
||||
#define INCA_IP2_ICU_IM5_IMR ((volatile u32*)(INCA_IP2_ICU + 0x00E8))
|
||||
#define INCA_IP2_ICU_IM5_IMR_IID (1 << 31)
|
||||
#define INCA_IP2_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
|
||||
#define INCA_IP2_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
|
||||
#define INCA_IP2_ICU_IM5_IR(value) (1 << (value))
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : CGU register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_CGU (KSEG1+0x1F100800)
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_CGU_PLL2CR ((volatile u32*)(INCA_IP2_CGU + 0x0008))
|
||||
#define INCA_IP2_CGU_FBSCR ((volatile u32*)(INCA_IP2_CGU + 0x0018))
|
||||
#define INCA_IP2_CGU_FBSCR_LPBSDIV_GET(value) (((value) >> 6) & ((1 << 2) - 1))
|
||||
#define INCA_IP2_CGU_FBSCR_DIV0_GET(value) (((value) >> 0) & ((1 << 3) - 1))
|
||||
#define INCA_IP2_CGU_FBSCR_DIV1_GET(value) (((value) >> 4) & ((1 << 2) - 1))
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : MPS register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_MPS (KSEG1+0x1F101400)
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_MPS_CHIPID ((volatile u32*)(INCA_IP2_MPS + 0x0344))
|
||||
#define INCA_IP2_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
|
||||
#define INCA_IP2_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
|
||||
#define INCA_IP2_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
|
||||
#define INCA_IP2_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
|
||||
#define INCA_IP2_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
|
||||
#define INCA_IP2_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
|
||||
|
||||
|
||||
/* voice channel 0 ... 3 interrupt enable register */
|
||||
#define INCA_IP2_MPS_VC0ENR ((volatile u32*)(INCA_IP2_MPS + 0x0000))
|
||||
#define INCA_IP2_MPS_VC1ENR ((volatile u32*)(INCA_IP2_MPS + 0x0004))
|
||||
#define INCA_IP2_MPS_VC2ENR ((volatile u32*)(INCA_IP2_MPS + 0x0008))
|
||||
#define INCA_IP2_MPS_VC3ENR ((volatile u32*)(INCA_IP2_MPS + 0x000C))
|
||||
/* voice channel 0 ... 3 interrupt status read register */
|
||||
#define INCA_IP2_MPS_RVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0010))
|
||||
#define INCA_IP2_MPS_RVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0014))
|
||||
#define INCA_IP2_MPS_RVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0018))
|
||||
#define INCA_IP2_MPS_RVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x001C))
|
||||
/* voice channel 0 ... 3 interrupt status set register */
|
||||
#define INCA_IP2_MPS_SVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0020))
|
||||
#define INCA_IP2_MPS_SVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0024))
|
||||
#define INCA_IP2_MPS_SVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0028))
|
||||
#define INCA_IP2_MPS_SVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x002C))
|
||||
/* voice channel 0 ... 3 interrupt status clear register */
|
||||
#define INCA_IP2_MPS_CVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0030))
|
||||
#define INCA_IP2_MPS_CVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0034))
|
||||
#define INCA_IP2_MPS_CVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0038))
|
||||
#define INCA_IP2_MPS_CVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x003C))
|
||||
/* common status 0 and 1 read register */
|
||||
#define INCA_IP2_MPS_RAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0040))
|
||||
#define INCA_IP2_MPS_RAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x0044))
|
||||
/* common status 0 and 1 set register */
|
||||
#define INCA_IP2_MPS_SAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0048))
|
||||
#define INCA_IP2_MPS_SAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x004C))
|
||||
/* common status 0 and 1 clear register */
|
||||
#define INCA_IP2_MPS_CAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0050))
|
||||
#define INCA_IP2_MPS_CAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x0054))
|
||||
/* notification enable register */
|
||||
#define INCA_IP2_MPS_CPU0_NFER ((volatile u32*)(INCA_IP2_MPS + 0x0060))
|
||||
#define INCA_IP2_MPS_CPU1_NFER ((volatile u32*)(INCA_IP2_MPS + 0x0064))
|
||||
/* CPU to CPU interrup request register */
|
||||
#define INCA_IP2_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(INCA_IP2_MPS + 0x0070))
|
||||
#define INCA_IP2_MPS_CPU0_2_CPU1_IER ((volatile u32*)(INCA_IP2_MPS + 0x0074))
|
||||
/* Global interrupt request and request enable register */
|
||||
#define INCA_IP2_MPS_GIRR ((volatile u32*)(INCA_IP2_MPS + 0x0078))
|
||||
#define INCA_IP2_MPS_GIER ((volatile u32*)(INCA_IP2_MPS + 0x007C))
|
||||
|
||||
/* Addresses of enable registers not yet defined
|
||||
#define INCA_IP2_MPS_AD0ENR ((volatile u32*)(INCA_IP2_MPS + 0x????))
|
||||
#define INCA_IP2_MPS_AD1ENR ((volatile u32*)(INCA_IP2_MPS + 0x????))
|
||||
*/
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : ASC0 register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_ASC0 (KSEG1+0x1E000400)
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_ASC0_TBUF ((volatile u32*)(INCA_IP2_ASC0 + 0x0020))
|
||||
#define INCA_IP2_ASC0_RBUF ((volatile u32*)(INCA_IP2_ASC0 + 0x0024))
|
||||
#define INCA_IP2_ASC0_FSTAT ((volatile u32*)(INCA_IP2_ASC0 + 0x0048))
|
||||
#define INCA_IP2_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
|
||||
#define INCA_IP2_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
|
||||
#define INCA_IP2_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
|
||||
#define INCA_IP2_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
|
||||
#define INCA_IP2_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
|
||||
#define INCA_IP2_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
|
||||
#define INCA_IP2_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
|
||||
#define INCA_IP2_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : ASC1 register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_ASC1 (KSEG1+0x1E000800)
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_ASC1_TBUF ((volatile u32*)(INCA_IP2_ASC1 + 0x0020))
|
||||
#define INCA_IP2_ASC1_RBUF ((volatile u32*)(INCA_IP2_ASC1 + 0x0024))
|
||||
#define INCA_IP2_ASC1_FSTAT ((volatile u32*)(INCA_IP2_ASC1 + 0x0048))
|
||||
#define INCA_IP2_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
|
||||
#define INCA_IP2_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
|
||||
#define INCA_IP2_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
|
||||
#define INCA_IP2_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
|
||||
#define INCA_IP2_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
|
||||
#define INCA_IP2_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
|
||||
#define INCA_IP2_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
|
||||
#define INCA_IP2_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : RCU register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_RCU (KSEG1+0x1E001C00)
|
||||
/***********************************************************************/
|
||||
|
||||
/***Reset Request Register***/
|
||||
#define INCA_IP2_RCU_RST_REQ ((volatile u32*)(INCA_IP2_RCU + 0x0000))
|
||||
#define INCA_IP2_RCU_RST_REQ_CPU0 (1 << 31)
|
||||
#define INCA_IP2_RCU_RST_REQ_CPU1 (1 << 30)
|
||||
#define INCA_IP2_RCU_RST_REQ_CPUSUB (1 << 29)
|
||||
#define INCA_IP2_RCU_RST_REQ_HRST (1 << 28)
|
||||
#define INCA_IP2_RCU_RST_REQ_WDT0 (1 << 27)
|
||||
#define INCA_IP2_RCU_RST_REQ_WDT1 (1 << 26)
|
||||
#define INCA_IP2_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1))
|
||||
#define INCA_IP2_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23)
|
||||
#define INCA_IP2_RCU_RST_REQ_SWTBOOT (1 << 22)
|
||||
#define INCA_IP2_RCU_RST_REQ_DMA (1 << 21)
|
||||
#define INCA_IP2_RCU_RST_REQ_ETHPHY1 (1 << 20)
|
||||
#define INCA_IP2_RCU_RST_REQ_ETHPHY0 (1 << 19)
|
||||
#define INCA_IP2_RCU_RST_REQ_CPU0_BR (1 << 18)
|
||||
|
||||
/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */
|
||||
#define INCA_IP2_RCU_RST_REQ_ALL 0xFC380000
|
||||
|
||||
/***NMI Status Register***/
|
||||
#define INCA_IP2_RCU_NMISR ((volatile u32*)(INCA_IP2_RCU + 0x00F4))
|
||||
#define INCA_IP2_RCU_NMISR_NMIEXT (1 << 2)
|
||||
#define INCA_IP2_RCU_NMISR_NMIPLL2 (1 << 1)
|
||||
#define INCA_IP2_RCU_NMISR_NMIPLL1 (1 << 0)
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : WDT register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_WDT (KSEG1+0x1F880000)
|
||||
/***********************************************************************/
|
||||
|
||||
/***Watchdog Timer Control Register ***/
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR ((volatile u32*)(INCA_IP2_WDT + 0x03F0))
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_GEN (1 << 31)
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_DSEN (1 << 30)
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_LPEN (1 << 29)
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26)
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1))
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1))
|
||||
#define INCA_IP2_WDT_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
|
||||
|
||||
/***Watchdog Timer Status Register***/
|
||||
#define INCA_IP2_WDT_BIU_WDT_SR ((volatile u32*)(INCA_IP2_WDT + 0x03F8))
|
||||
#define INCA_IP2_WDT_BIU_WDT_SR_EN (1 << 31)
|
||||
#define INCA_IP2_WDT_BIU_WDT_SR_AE (1 << 30)
|
||||
#define INCA_IP2_WDT_BIU_WDT_SR_PRW (1 << 29)
|
||||
#define INCA_IP2_WDT_BIU_WDT_SR_EXP (1 << 28)
|
||||
#define INCA_IP2_WDT_BIU_WDT_SR_PWD (1 << 27)
|
||||
#define INCA_IP2_WDT_BIU_WDT_SR_DS (1 << 26)
|
||||
#define INCA_IP2_WDT_BIU_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1))
|
||||
#define INCA_IP2_WDT_BIU_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : BCU0 register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_BCU0 (KSEG1+0x14100000)
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_BCU0_CON ((volatile u32*)(INCA_IP2_BCU0 + 0x0010))
|
||||
#define INCA_IP2_BCU0_ECON ((volatile u32*)(INCA_IP2_BCU0 + 0x0020))
|
||||
#define INCA_IP2_BCU0_EADD ((volatile u32*)(INCA_IP2_BCU0 + 0x0024))
|
||||
#define INCA_IP2_BCU0_EDAT ((volatile u32*)(INCA_IP2_BCU0 + 0x0028))
|
||||
#define INCA_IP2_BCU0_IRNCR1 ((volatile u32*)(INCA_IP2_BCU0 + 0x00F8))
|
||||
#define INCA_IP2_BCU0_IRNCR0 ((volatile u32*)(INCA_IP2_BCU0 + 0x00FC))
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : BCU1 register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_BCU1 (KSEG1+0x1E000000)
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_BCU1_CON ((volatile u32*)(INCA_IP2_BCU1 + 0x0010))
|
||||
#define INCA_IP2_BCU1_ECON ((volatile u32*)(INCA_IP2_BCU1 + 0x0020))
|
||||
#define INCA_IP2_BCU1_EADD ((volatile u32*)(INCA_IP2_BCU1 + 0x0024))
|
||||
#define INCA_IP2_BCU1_EDAT ((volatile u32*)(INCA_IP2_BCU1 + 0x0028))
|
||||
#define INCA_IP2_BCU1_IRNCR1 ((volatile u32*)(INCA_IP2_BCU1 + 0x00F8))
|
||||
#define INCA_IP2_BCU1_IRNCR0 ((volatile u32*)(INCA_IP2_BCU1 + 0x00FC))
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : MC register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_MC (KSEG1+0x1F800000)
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_MC_ERRCAUSE ((volatile u32*)(INCA_IP2_MC + 0x0010))
|
||||
#define INCA_IP2_MC_ERRADDR ((volatile u32*)(INCA_IP2_MC + 0x0020))
|
||||
#define INCA_IP2_MC_CON ((volatile u32*)(INCA_IP2_MC + 0x0060))
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : MC SDRAM register address and bits */
|
||||
/***********************************************************************/
|
||||
#define INCA_IP2_SDRAM (KSEG1+0x1F800200)
|
||||
/***********************************************************************/
|
||||
#define INCA_IP2_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP2_SDRAM + 0x0040))
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : MC DDR register address and bits */
|
||||
/***********************************************************************/
|
||||
#define INCA_IP2_DDR (KSEG1+0x1F801000)
|
||||
/***********************************************************************/
|
||||
#define INCA_IP2_DDR_MC_DC19 ((volatile u32*)(INCA_IP2_DDR + 0x0130))
|
||||
#define INCA_IP2_DDR_MC_DC20 ((volatile u32*)(INCA_IP2_DDR + 0x0140))
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : PMS register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_PMS (KSEG1 + 0x1F100C00)
|
||||
|
||||
#define INCA_IP2_PMS_PMS_SR ((volatile u32*) (INCA_IP2_PMS + 0x0000))
|
||||
#define INCA_IP2_PMS_PMS_SR_ASC1 (1 << 14)
|
||||
#define INCA_IP2_PMS_PMS_SR_ASC0 (1 << 13)
|
||||
#define INCA_IP2_PMS_PMS_GEN ((volatile u32*) (INCA_IP2_PMS + 0x0004))
|
||||
#define INCA_IP2_PMS_PMS_GEN_DMA (1 << 16)
|
||||
#define INCA_IP2_PMS_PMS_GEN_ASC1 (1 << 14)
|
||||
#define INCA_IP2_PMS_PMS_GEN_ASC0 (1 << 13)
|
||||
#define INCA_IP2_PMS_PMS_GEN_SPI0 (1 << 11)
|
||||
#define INCA_IP2_PMS_PMS_GEN_SPI1 (1 << 12)
|
||||
#define INCA_IP2_PMS_PMS_CFG ((volatile u32*) (INCA_IP2_PMS + 0x0008))
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : GPIO register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_GPIO (KSEG1 + 0x1F102600)
|
||||
|
||||
#define INCA_IP2_GPIO_OUT ((volatile u32*) (INCA_IP2_GPIO + 0x0000))
|
||||
#define INCA_IP2_GPIO_IN ((volatile u32*) (INCA_IP2_GPIO + 0x0004))
|
||||
#define INCA_IP2_GPIO_DIR ((volatile u32*) (INCA_IP2_GPIO + 0x0008))
|
||||
#define INCA_IP2_GPIO_ALTSEL1 ((volatile u32*) (INCA_IP2_GPIO + 0x000C))
|
||||
#define INCA_IP2_GPIO_ALTSEL2 ((volatile u32*) (INCA_IP2_GPIO + 0x0010))
|
||||
#define INCA_IP2_GPIO_STOFF ((volatile u32*) (INCA_IP2_GPIO + 0x0014))
|
||||
#define INCA_IP2_GPIO_OD ((volatile u32*) (INCA_IP2_GPIO + 0x0018))
|
||||
#define INCA_IP2_GPIO_PUDEB ((volatile u32*) (INCA_IP2_GPIO + 0x001C))
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : RCU register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_RCU (KSEG1+0x1E001C00)
|
||||
/***********************************************************************/
|
||||
|
||||
/***Reset Request Register***/
|
||||
#define INCA_IP2_RCU_RST_REQ ((volatile u32*)(INCA_IP2_RCU + 0x0000))
|
||||
#define INCA_IP2_RCU_RST_REQ_CPU0 (1 << 31)
|
||||
#define INCA_IP2_RCU_RST_REQ_CPU1 (1 << 30)
|
||||
#define INCA_IP2_RCU_RST_REQ_CPUSUB (1 << 29)
|
||||
#define INCA_IP2_RCU_RST_REQ_HRST (1 << 28)
|
||||
#define INCA_IP2_RCU_RST_REQ_WDT0 (1 << 27)
|
||||
#define INCA_IP2_RCU_RST_REQ_WDT1 (1 << 26)
|
||||
#define INCA_IP2_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1))
|
||||
#define INCA_IP2_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23)
|
||||
#define INCA_IP2_RCU_RST_REQ_SWTBOOT (1 << 22)
|
||||
#define INCA_IP2_RCU_RST_REQ_DMA (1 << 21)
|
||||
#define INCA_IP2_RCU_RST_REQ_ETHPHY1 (1 << 20)
|
||||
#define INCA_IP2_RCU_RST_REQ_ETHPHY0 (1 << 19)
|
||||
#define INCA_IP2_RCU_RST_REQ_CPU0_BR (1 << 18)
|
||||
|
||||
/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */
|
||||
#define INCA_IP2_RCU_RST_REQ_ALL 0xFC380000
|
||||
|
||||
/***Reset Status Register***/
|
||||
#define INCA_IP2_RCU_SR ((volatile u32*)(INCA_IP2_RCU + 0x0008))
|
||||
|
||||
/***NMI Status Register***/
|
||||
#define INCA_IP2_RCU_NMISR ((volatile u32*)(INCA_IP2_RCU + 0x00F4))
|
||||
#define INCA_IP2_RCU_NMISR_NMIEXT (1 << 2)
|
||||
#define INCA_IP2_RCU_NMISR_NMIPLL2 (1 << 1)
|
||||
#define INCA_IP2_RCU_NMISR_NMIPLL1 (1 << 0)
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : EBU register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_EBU (KSEG1+0x14102000)
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_EBU_ADDSEL0 ((volatile u32*)(INCA_IP2_EBU + 0x0020))
|
||||
#define INCA_IP2_EBU_ADDSEL1 ((volatile u32*)(INCA_IP2_EBU + 0x0024))
|
||||
#define INCA_IP2_EBU_ADDSEL2 ((volatile u32*)(INCA_IP2_EBU + 0x0028))
|
||||
#define INCA_IP2_EBU_ADDSEL3 ((volatile u32*)(INCA_IP2_EBU + 0x002C))
|
||||
#define INCA_IP2_EBU_CON0 ((volatile u32*)(INCA_IP2_EBU + 0x0060))
|
||||
#define INCA_IP2_EBU_CON1 ((volatile u32*)(INCA_IP2_EBU + 0x0064))
|
||||
#define INCA_IP2_EBU_CON2 ((volatile u32*)(INCA_IP2_EBU + 0x0068))
|
||||
#define INCA_IP2_EBU_CON3 ((volatile u32*)(INCA_IP2_EBU + 0x006C))
|
||||
#define INCA_IP2_EBU_CON_WRDIS (1 << 31)
|
||||
|
||||
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : SWITCH register address and bits */
|
||||
/***********************************************************************/
|
||||
|
||||
#define INCA_IP2_SWITCH (KSEG1+0x18000000)
|
||||
/***********************************************************************/
|
||||
|
||||
/* PR Base address */
|
||||
#define PR_BASE (INCA_IP2_SWITCH + 0x00008000)
|
||||
|
||||
/* SE Base Address */
|
||||
#define SE_BASE (INCA_IP2_SWITCH + 0x00009000)
|
||||
|
||||
#define PR_CTRL_REG (PR_BASE + 0x0000)
|
||||
#define MA_LEARN_REG (PR_BASE + 0x0004)
|
||||
#define DST_LOOKUP_REG (PR_BASE + 0x0008)
|
||||
|
||||
#define COS_SEL_REG (PR_BASE + 0x000c)
|
||||
#define PRI2_COS_REG (PR_BASE + 0x0010)
|
||||
#define UNKNOWN_DEST_REG (PR_BASE + 0x0014)
|
||||
|
||||
#define CPU_ACS_CTRL_REG (PR_BASE + 0x0018)
|
||||
#define CPU_ACS_DATA_REG (PR_BASE + 0x001c)
|
||||
|
||||
#define MA_READ_REG (PR_BASE + 0x0020)
|
||||
#define TB_CTRL_REG (PR_BASE + 0x0024)
|
||||
#define RATE_REG (PR_BASE + 0x0028)
|
||||
#define BURST_REG (PR_BASE + 0x0048)
|
||||
#define EBURST_REG (PR_BASE + 0x0068)
|
||||
|
||||
#define RULE_SEL_REG (PR_BASE + 0x0088)
|
||||
|
||||
#define GEN_SFT_AGE_STB (PR_BASE + 0x008C)
|
||||
#define PR_ISR_REG (PR_BASE + 0x0090)
|
||||
#define PR_IMR_REG (PR_BASE + 0x0094)
|
||||
#define PR_IPR_REG (PR_BASE + 0x0098)
|
||||
#define BPDU_REG (PR_BASE + 0x00A4)
|
||||
|
||||
/* Switching Engine Register Description */
|
||||
#define QLL_CMD_REG (SE_BASE)
|
||||
#define QLL_DATA_REG0 (SE_BASE + 0x0004)
|
||||
#define QLL_DATA_REG1 (SE_BASE + 0x0008)
|
||||
|
||||
#define VLAN_MIBS_CMD_REG (SE_BASE + 0x000c)
|
||||
#define VLAN_MIBS_DATA_REG (SE_BASE + 0x0010)
|
||||
|
||||
#define SD_CMD_REG (SE_BASE + 0x0014)
|
||||
#define SD_DATA_REGS0 (SE_BASE + 0x0018)
|
||||
#define SD_DATA_REGS1 (SE_BASE + 0x001C)
|
||||
#define SD_DATA_REGS2 (SE_BASE + 0x0020)
|
||||
|
||||
#define VLAN_TBL_CMD_REG (SE_BASE + 0x0024)
|
||||
#define VLAN_TBL_DATA_REG (SE_BASE + 0x0028)
|
||||
|
||||
#define FD_TBL_CMD_REG (SE_BASE + 0x002c)
|
||||
#define FD_TBL_DATA_REG (SE_BASE + 0x0030)
|
||||
|
||||
#define SYMM_VLAN_REG (SE_BASE + 0x0038)
|
||||
#define PORT_AUTH (SE_BASE + 0x0048)
|
||||
#define CPU_LINK_OK_REG (SE_BASE + 0x0050)
|
||||
/* #define TRUNK_CTRL_REGS (SE_BASE + 0x0054) */
|
||||
#define MIRROR_PORT_REG (SE_BASE + 0x0064)
|
||||
|
||||
#define ST_PT_REG (SE_BASE + 0x0068)
|
||||
#define JUMBO_ENABLE_REG (SE_BASE + 0x006C)
|
||||
#define STACK_PORT_REG (SE_BASE + 0x0074)
|
||||
#define EG_MON_REG (SE_BASE + 0x007C)
|
||||
#define VR_MIB_REG (SE_BASE + 0x0080)
|
||||
#define QUEUE_CMD_REGS (SE_BASE + 0x0090)
|
||||
|
||||
#define GLOBAL_RX_WM_REG (SE_BASE + 0x0200)
|
||||
#define PORT0_RX_WM_REG0 (SE_BASE + 0x0204)
|
||||
#define PORT1_RX_WM_REG0 (SE_BASE + 0x0208)
|
||||
#define PORT2_RX_WM_REG0 (SE_BASE + 0x020C)
|
||||
|
||||
#define PORT_RX_WM_REGS (SE_BASE + 0x0200)
|
||||
#define PORT_TX_WM_REGS (SE_BASE + 0x0300)
|
||||
#define PORT0_TX_WM_REG0 (SE_BASE + 0x0330)
|
||||
#define PORT1_TX_WM_REG0 (SE_BASE + 0x0338)
|
||||
#define PORT2_TX_WM_REG0 (SE_BASE + 0x0340)
|
||||
#define PORT0_TX_WM_REG1 (SE_BASE + 0x0334)
|
||||
#define PORT1_TX_WM_REG1 (SE_BASE + 0x033C)
|
||||
#define PORT2_TX_WM_REG1 (SE_BASE + 0x0344)
|
||||
|
||||
|
||||
#define QUEUE_STATUS_REGS (SE_BASE + 0x0400)
|
||||
|
||||
#define SE_INT_STS_REG (SE_BASE + 0x08e0)
|
||||
#define SE_INT_MSK_REG_RD (SE_BASE + 0x08e4)
|
||||
#define SE_INT_MSK_REG_WR (SE_BASE + 0x08e8)
|
||||
#define SE_INT_PRI_REG_RD (SE_BASE + 0x08ec)
|
||||
#define SE_INT_PRI_REG_WR (SE_BASE + 0x08f0) /* address too be defined*/
|
||||
|
||||
/***********************************************************************/
|
||||
/* Module : Ethernet Switch port related addresses and bits */
|
||||
/***********************************************************************/
|
||||
#define GPORT0_BASE (KSEG1+0x18006000)
|
||||
#define GPORT1_BASE (KSEG1+0x18007000)
|
||||
#define GPORT2_BASE (KSEG1+0x1800C000)
|
||||
|
||||
#define PORTREG_BASE GPORT0_BASE
|
||||
|
||||
#define SWITCH_P0_GMAC_REG (GPORT0_BASE + 0x0004)
|
||||
#define SWITCH_P0_GMAC_CTRL (GPORT0_BASE + 0x000C)
|
||||
#define SWITCH_P0_RTX_INT_STATUS (GPORT0_BASE + 0x0010)
|
||||
#define SWITCH_P0_RTX_INT_MASK (GPORT0_BASE + 0x0014)
|
||||
#define SWITCH_P0_INT_PRIORITY (GPORT0_BASE + 0x0018)
|
||||
#define SWITCH_P0_RX_CONF (GPORT0_BASE + 0x0400)
|
||||
#define SWITCH_P0_OFFSET0_REG (GPORT0_BASE + 0x0404)
|
||||
#define SWITCH_P0_OFFSET1_REG (GPORT0_BASE + 0x0408)
|
||||
#define SWITCH_P0_PORT_MASK0_REG (GPORT0_BASE + 0x0420)
|
||||
#define SWITCH_P0_PORT_MASK1_REG (GPORT0_BASE + 0x0424)
|
||||
#define SWITCH_P0_PORT_MASK2_REG (GPORT0_BASE + 0x0428)
|
||||
#define SWITCH_P0_PORT_MASK3_REG (GPORT0_BASE + 0x042C)
|
||||
#define SWITCH_P0_PORT_RULE0_REG (GPORT0_BASE + 0x0430)
|
||||
#define SWITCH_P0_PORT_RULE1_REG (GPORT0_BASE + 0x0434)
|
||||
#define SWITCH_P0_PORT_RULE2_REG (GPORT0_BASE + 0x0438)
|
||||
#define SWITCH_P0_PORT_RULE3_REG (GPORT0_BASE + 0x043C)
|
||||
#define SWITCH_P0_PORT_IKEY_SEL (GPORT0_BASE + 0x0440)
|
||||
#define SWITCH_P0_PORT_RX_VLAN_ID (GPORT0_BASE + 0x0450)
|
||||
#define SWITCH_P0_TX_CONF (GPORT0_BASE + 0x0800)
|
||||
#define SWITCH_P0_PORT_TX_VLAN_ID (GPORT0_BASE + 0x0804)
|
||||
#define SWITCH_P0_PORT_MIB_REG_0 (GPORT0_BASE + 0x0C00)
|
||||
#define SWITCH_P0_GMAC_MIB_REG_0 (GPORT0_BASE + 0x0C54)
|
||||
|
||||
#define SWITCH_P1_GMAC_REG (GPORT1_BASE + 0x0004)
|
||||
#define SWITCH_P1_GMAC_CTRL (GPORT1_BASE + 0x000C)
|
||||
#define SWITCH_P1_RTX_INT_STATUS (GPORT1_BASE + 0x0010)
|
||||
#define SWITCH_P1_RTX_INT_MASK (GPORT1_BASE + 0x0014)
|
||||
#define SWITCH_P1_INT_PRIORITY (GPORT1_BASE + 0x0018)
|
||||
#define SWITCH_P1_RX_CONF (GPORT1_BASE + 0x0400)
|
||||
#define SWITCH_P1_OFFSET0_REG (GPORT1_BASE + 0x0404)
|
||||
#define SWITCH_P1_OFFSET1_REG (GPORT1_BASE + 0x0408)
|
||||
#define SWITCH_P1_PORT_MASK0_REG (GPORT1_BASE + 0x0420)
|
||||
#define SWITCH_P1_PORT_MASK1_REG (GPORT1_BASE + 0x0424)
|
||||
#define SWITCH_P1_PORT_MASK2_REG (GPORT1_BASE + 0x0428)
|
||||
#define SWITCH_P1_PORT_MASK3_REG (GPORT1_BASE + 0x042C)
|
||||
#define SWITCH_P1_PORT_RULE0_REG (GPORT1_BASE + 0x0430)
|
||||
#define SWITCH_P1_PORT_RULE1_REG (GPORT1_BASE + 0x0434)
|
||||
#define SWITCH_P1_PORT_RULE2_REG (GPORT1_BASE + 0x0438)
|
||||
#define SWITCH_P1_PORT_RULE3_REG (GPORT1_BASE + 0x043C)
|
||||
#define SWITCH_P1_PORT_IKEY_SEL (GPORT1_BASE + 0x0440)
|
||||
#define SWITCH_P1_PORT_RX_VLAN_ID (GPORT1_BASE + 0x0450)
|
||||
#define SWITCH_P1_TX_CONF (GPORT1_BASE + 0x0800)
|
||||
#define SWITCH_P1_PORT_TX_VLAN_ID (GPORT1_BASE + 0x0804)
|
||||
#define SWITCH_P1_PORT_MIB_REG_0 (GPORT1_BASE + 0x0C00)
|
||||
#define SWITCH_P1_GMAC_MIB_REG_0 (GPORT1_BASE + 0x0C54)
|
||||
|
||||
#define SWITCH_P2_GMAC_REG (GPORT2_BASE + 0x0004)
|
||||
#define SWITCH_P2_GMAC_CTRL (GPORT2_BASE + 0x000C)
|
||||
#define SWITCH_P2_RTX_INT_STATUS (GPORT2_BASE + 0x0010)
|
||||
#define SWITCH_P2_RTX_INT_MASK (GPORT2_BASE + 0x0014)
|
||||
#define SWITCH_P2_INT_PRIORITY (GPORT2_BASE + 0x0018)
|
||||
#define SWITCH_P2_MDIO_ID_1 (GPORT2_BASE + 0x00A8)
|
||||
#define SWITCH_P2_PAUSE_CTL_1 (GPORT2_BASE + 0x00B0)
|
||||
#define SWITCH_P2_MDIO_MOD_SEL (GPORT2_BASE + 0x00B4)
|
||||
#define SWITCH_P2_MDIO_ACC_0 (GPORT2_BASE + 0x00B8)
|
||||
#define SWITCH_P2_RX_CONF (GPORT2_BASE + 0x0400)
|
||||
#define SWITCH_P2_OFFSET0_REG (GPORT2_BASE + 0x0404)
|
||||
#define SWITCH_P2_OFFSET1_REG (GPORT2_BASE + 0x0408)
|
||||
#define SWITCH_P2_PORT_MASK0_REG (GPORT2_BASE + 0x0420)
|
||||
#define SWITCH_P2_PORT_MASK1_REG (GPORT2_BASE + 0x0424)
|
||||
#define SWITCH_P2_PORT_MASK2_REG (GPORT2_BASE + 0x0428)
|
||||
#define SWITCH_P2_PORT_MASK3_REG (GPORT2_BASE + 0x042C)
|
||||
#define SWITCH_P2_PORT_RULE0_REG (GPORT2_BASE + 0x0430)
|
||||
#define SWITCH_P2_PORT_RULE1_REG (GPORT2_BASE + 0x0434)
|
||||
#define SWITCH_P2_PORT_RULE2_REG (GPORT2_BASE + 0x0438)
|
||||
#define SWITCH_P2_PORT_RULE3_REG (GPORT2_BASE + 0x043C)
|
||||
#define SWITCH_P2_PORT_IKEY_SEL (GPORT2_BASE + 0x0440)
|
||||
#define SWITCH_P2_PORT_RX_VLAN_ID (GPORT2_BASE + 0x0450)
|
||||
#define SWITCH_P2_TX_CONF (GPORT2_BASE + 0x0800)
|
||||
#define SWITCH_P2_PORT_TX_VLAN_ID (GPORT2_BASE + 0x0804)
|
||||
#define SWITCH_P2_PORT_MIB_REG_0 (GPORT2_BASE + 0x0C00)
|
||||
#define SWITCH_P2_GMAC_MIB_REG_0 (GPORT2_BASE + 0x0C54)
|
||||
|
||||
#define MDIO_MOD_SEL SWITCH_P2_MDIO_MOD_SEL
|
||||
#define SWITCH_MDIO_ACC SWITCH_P2_MDIO_ACC_0
|
||||
#define SWITCH_MDIO_ID SWITCH_P2_MDIO_ID_1
|
||||
/* #define TX_CONFIG_REG SWITCH_P0_TX_CONF */
|
||||
|
||||
#define SWITCH_PMAC_HD_CTL (GPORT2_BASE + 0x0070)
|
||||
#define SWITCH_PMAC_SA1 (GPORT2_BASE + 0x0074)
|
||||
#define SWITCH_PMAC_SA2 (GPORT2_BASE + 0x0078)
|
||||
#define SWITCH_PMAC_DA1 (GPORT2_BASE + 0x007C)
|
||||
#define SWITCH_PMAC_DA2 (GPORT2_BASE + 0x0080)
|
||||
#define SWITCH_PMAC_VLAN (GPORT2_BASE + 0x0084)
|
||||
#define SWITCH_PMAC_TX_IPG (GPORT2_BASE + 0x0088)
|
||||
#define SWITCH_PMAC_RX_IPG (GPORT2_BASE + 0x008C)
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
#define FLASH_STRAP 0x1
|
||||
#define MII_0_STRAP 0x2
|
||||
#define MII_1_STRAP 0x3
|
||||
#define ASC_STRAP 0x4
|
||||
#define SFLASH_STRAP 0x5
|
||||
#define RESERVE_STRAP 0x6
|
||||
#define PRODUCT_TEST_STRAP 0x7
|
||||
#define PIN_STRAP_MASK 0x001C0000
|
||||
#define PIN_STRAP_SHIFT 18
|
||||
#define PIN_STRAP 0xB0100914
|
||||
#define SDRAM_WIDTH_MASK 0x400000
|
||||
#define SDRAM_WIDTH_SHIFT 22
|
||||
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains the configuration parameters for the DANUBE board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
|
||||
#define EXCEPTION_BASE 0x200
|
||||
|
||||
/*****************************************************************************
|
||||
* DANUBE
|
||||
*****************************************************************************/
|
||||
/* lock cache for C program stack */
|
||||
/* points to ROM */
|
||||
/* stack size is 16K */
|
||||
#define LOCK_DCACHE_ADDR 0x9FC00000
|
||||
#define LOCK_DCACHE_SIZE 0x1000
|
||||
#define CFG_EBU_BOOTWORD 0x688c688c
|
||||
|
||||
#define CFG_HZ (danube_get_cpuclk() / 2)
|
||||
|
||||
|
||||
/*
|
||||
* Memory layout
|
||||
*/
|
||||
//#define CFG_SDRAM_BASE 0x80080000
|
||||
#define CFG_CACHE_LOCK_SIZE LOCK_DCACHE_SIZE
|
||||
#define CFG_INIT_SP_OFFSET CFG_CACHE_LOCK_SIZE
|
||||
|
||||
/*
|
||||
* Cache settings
|
||||
*/
|
||||
#define CFG_CACHE_SIZE 16384
|
||||
#define CFG_CACHE_LINES 32
|
||||
#define CFG_CACHE_WAYS 4
|
||||
#define CFG_CACHE_SETS 128
|
||||
|
||||
#define CFG_ICACHE_SIZE CFG_CACHE_SIZE
|
||||
#define CFG_DCACHE_SIZE CFG_CACHE_SIZE
|
||||
#define CFG_CACHELINE_SIZE CFG_CACHE_LINES
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Reference in New Issue
Block a user