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made the danube pmu f00 generic
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9759 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -22,6 +22,7 @@
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#include <asm/danube/danube.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube_irq.h>
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#include <asm/danube/danube_irq.h>
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#include <asm/danube/danube_dma.h>
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#include <asm/danube/danube_dma.h>
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#include <asm/danube/danube_pmu.h>
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/*25 descriptors for each dma channel,4096/8/20=25.xx*/
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/*25 descriptors for each dma channel,4096/8/20=25.xx*/
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#define DANUBE_DMA_DESCRIPTOR_OFFSET 25
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#define DANUBE_DMA_DESCRIPTOR_OFFSET 25
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@ -684,7 +685,7 @@ dma_chip_init(void)
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int i;
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int i;
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// enable DMA from PMU
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// enable DMA from PMU
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writel(readl(DANUBE_PMU_PWDCR) & ~DANUBE_PMU_PWDCR_DMA, DANUBE_PMU_PWDCR);
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danube_pmu_enable(DANUBE_PMU_PWDCR_DMA);
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// reset DMA
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// reset DMA
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writel(readl(DANUBE_DMA_CTRL) | 1, DANUBE_DMA_CTRL);
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writel(readl(DANUBE_DMA_CTRL) | 1, DANUBE_DMA_CTRL);
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45
target/linux/danube/files/arch/mips/danube/pmu.c
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45
target/linux/danube/files/arch/mips/danube/pmu.c
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@ -0,0 +1,45 @@
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/*
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* arch/mips/danube/pmu.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/version.h>
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#include <asm/danube/danube.h>
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void
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danube_pmu_enable (unsigned int module)
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{
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int err = 1000000;
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writel(readl(DANUBE_PMU_PWDCR) & ~module, DANUBE_PMU_PWDCR);
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while (--err && (readl(DANUBE_PMU_PWDSR) & module)) {}
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if (!err)
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panic("activating PMU module failed!");
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}
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EXPORT_SYMBOL(danube_pmu_enable);
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void
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danube_pmu_disable (unsigned int module)
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{
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writel(readl(DANUBE_PMU_PWDCR) | module, DANUBE_PMU_PWDCR);
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}
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EXPORT_SYMBOL(danube_pmu_disable);
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@ -32,6 +32,7 @@
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#include <asm/irq.h>
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#include <asm/irq.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube_irq.h>
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#include <asm/danube/danube_irq.h>
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#include <asm/danube/danube_pmu.h>
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static unsigned int r4k_offset; /* Amount to increment compare reg each time */
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static unsigned int r4k_offset; /* Amount to increment compare reg each time */
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static unsigned int r4k_cur; /* What counter should be at next timer irq */
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static unsigned int r4k_cur; /* What counter should be at next timer irq */
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@ -138,7 +139,7 @@ plat_timer_setup (struct irqaction *irq)
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r4k_cur = (read_c0_count() + r4k_offset);
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r4k_cur = (read_c0_count() + r4k_offset);
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write_c0_compare(r4k_cur);
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write_c0_compare(r4k_cur);
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writel(readl(DANUBE_PMU_PWDCR) & ~(DANUBE_PMU_PWDCR_GPT|DANUBE_PMU_PWDCR_FPI), DANUBE_PMU_PWDCR);
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danube_pmu_enable(DANUBE_PMU_PWDCR_GPT | DANUBE_PMU_PWDCR_FPI);
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writel(0x100, DANUBE_GPTU_GPT_CLC);
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writel(0x100, DANUBE_GPTU_GPT_CLC);
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@ -29,7 +29,7 @@
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#include <linux/errno.h>
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#include <linux/errno.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube_gpio.h>
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#include <asm/danube/danube_gpio.h>
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#include <asm/delay.h>
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#include <asm/danube/danube_pmu.h>
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#define DANUBE_LED_CLK_EDGE DANUBE_LED_FALLING
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#define DANUBE_LED_CLK_EDGE DANUBE_LED_FALLING
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//#define DANUBE_LED_CLK_EDGE DANUBE_LED_RISING
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//#define DANUBE_LED_CLK_EDGE DANUBE_LED_RISING
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@ -87,24 +87,6 @@ danube_led_setup_gpio (void)
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}
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}
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}
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}
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static void
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danube_led_enable (void)
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{
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int err = 1000000;
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writel(readl(DANUBE_PMU_PWDCR) & ~DANUBE_PMU_PWDCR_LED, DANUBE_PMU_PWDCR);
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while (--err && (readl(DANUBE_PMU_PWDSR) & DANUBE_PMU_PWDCR_LED)) {}
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if (!err)
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panic("Activating LED in PMU failed!");
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}
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static inline void
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danube_led_disable (void)
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{
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writel(readl(DANUBE_PMU_PWDCR) | DANUBE_PMU_PWDCR_LED, DANUBE_PMU_PWDCR);
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}
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static int
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static int
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led_ioctl (struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
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led_ioctl (struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
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{
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{
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@ -187,7 +169,7 @@ danube_led_init (void)
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writel(readl(DANUBE_LED_CON0) | DANUBE_LED_ADSL_SRC, DANUBE_LED_CON0);
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writel(readl(DANUBE_LED_CON0) | DANUBE_LED_ADSL_SRC, DANUBE_LED_CON0);
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/* per default, the leds are turned on */
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/* per default, the leds are turned on */
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danube_led_enable();
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danube_pmu_enable(DANUBE_PMU_PWDCR_LED);
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danube_led_major = register_chrdev(0, "danube_led", &danube_led_fops);
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danube_led_major = register_chrdev(0, "danube_led", &danube_led_fops);
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@ -44,6 +44,7 @@
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#include <asm/danube/danube.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube_mii0.h>
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#include <asm/danube/danube_mii0.h>
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#include <asm/danube/danube_dma.h>
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#include <asm/danube/danube_dma.h>
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#include <asm/danube/danube_pmu.h>
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static struct net_device danube_mii0_dev;
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static struct net_device danube_mii0_dev;
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static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
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static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
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@ -372,9 +373,8 @@ switch_init (struct net_device *dev)
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static void
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static void
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danube_sw_chip_init (int mode)
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danube_sw_chip_init (int mode)
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{
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{
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writel(readl(DANUBE_PMU_PWDCR) & ~DANUBE_PMU_PWDCR_DMA, DANUBE_PMU_PWDCR);
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danube_pmu_enable(DANUBE_PMU_PWDCR_DMA);
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writel(readl(DANUBE_PMU_PWDCR) & ~DANUBE_PMU_PWDCR_PPE, DANUBE_PMU_PWDCR);
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danube_pmu_enable(DANUBE_PMU_PWDCR_PPE);
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wmb();
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if(mode == REV_MII_MODE)
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if(mode == REV_MII_MODE)
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writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, DANUBE_PPE32_CFG);
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writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, DANUBE_PPE32_CFG);
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@ -163,12 +163,6 @@
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#define DANUBE_PMU_PWDCR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
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#define DANUBE_PMU_PWDCR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
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#define DANUBE_PMU_PWDSR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x0020))
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#define DANUBE_PMU_PWDSR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x0020))
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#define DANUBE_PMU_PWDCR_DMA 0x20
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#define DANUBE_PMU_PWDCR_LED 0x800
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#define DANUBE_PMU_PWDCR_GPT 0x1000
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#define DANUBE_PMU_PWDCR_PPE 0x2000
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#define DANUBE_PMU_PWDCR_FPI 0x4000
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/*------------ ICU */
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/*------------ ICU */
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@ -0,0 +1,31 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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*/
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#ifndef _DANUBE_PMU_H__
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#define _DANUBE_PMU_H__
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#define DANUBE_PMU_PWDCR_DMA 0x20
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#define DANUBE_PMU_PWDCR_LED 0x800
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#define DANUBE_PMU_PWDCR_GPT 0x1000
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#define DANUBE_PMU_PWDCR_PPE 0x2000
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#define DANUBE_PMU_PWDCR_FPI 0x4000
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void danube_pmu_enable (unsigned int module);
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void danube_pmu_disable (unsigned int module);
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#endif
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