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[ar71xx] rename DDR registers
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13363 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -198,7 +198,7 @@ static struct resource ar71xx_eth0_resources[] = {
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struct ag71xx_platform_data ar71xx_eth0_data = {
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.reset_bit = RESET_MODULE_GE0_MAC,
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.flush_reg = DDR_REG_FLUSH_GE0,
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.flush_reg = AR71XX_DDR_REG_FLUSH_GE0,
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};
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static struct platform_device ar71xx_eth0_device = {
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@ -237,7 +237,7 @@ static struct resource ar71xx_eth1_resources[] = {
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struct ag71xx_platform_data ar71xx_eth1_data = {
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.reset_bit = RESET_MODULE_GE1_MAC,
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.flush_reg = DDR_REG_FLUSH_GE1,
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.flush_reg = AR71XX_DDR_REG_FLUSH_GE1,
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};
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static struct platform_device ar71xx_eth1_device = {
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@ -316,14 +316,14 @@ static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
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ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
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AR71XX_PCI_CFG_SIZE);
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ar71xx_ddr_wr(DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
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ar71xx_ddr_wr(DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
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ar71xx_ddr_wr(DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
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ar71xx_ddr_wr(DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
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ar71xx_ddr_wr(DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
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ar71xx_ddr_wr(DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
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ar71xx_ddr_wr(DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
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ar71xx_ddr_wr(DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
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ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
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ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
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ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
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ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
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ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
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ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
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ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
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ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
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ar71xx_pci_delay();
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@ -207,18 +207,18 @@ extern void ar71xx_gpio_function_disable(u32 mask);
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/*
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* DDR_CTRL block
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*/
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#define DDR_REG_PCI_WIN0 0x7c
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#define DDR_REG_PCI_WIN1 0x80
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#define DDR_REG_PCI_WIN2 0x84
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#define DDR_REG_PCI_WIN3 0x88
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#define DDR_REG_PCI_WIN4 0x8c
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#define DDR_REG_PCI_WIN5 0x90
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#define DDR_REG_PCI_WIN6 0x94
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#define DDR_REG_PCI_WIN7 0x98
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#define DDR_REG_FLUSH_GE0 0x9c
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#define DDR_REG_FLUSH_GE1 0xa0
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#define DDR_REG_FLUSH_USB 0xa4
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#define DDR_REG_FLUSH_PCI 0xa8
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#define AR71XX_DDR_REG_PCI_WIN0 0x7c
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#define AR71XX_DDR_REG_PCI_WIN1 0x80
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#define AR71XX_DDR_REG_PCI_WIN2 0x84
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#define AR71XX_DDR_REG_PCI_WIN3 0x88
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#define AR71XX_DDR_REG_PCI_WIN4 0x8c
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#define AR71XX_DDR_REG_PCI_WIN5 0x90
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#define AR71XX_DDR_REG_PCI_WIN6 0x94
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#define AR71XX_DDR_REG_PCI_WIN7 0x98
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#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
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#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
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#define AR71XX_DDR_REG_FLUSH_USB 0xa4
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#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
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#define PCI_WIN0_OFFS 0x10000000
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#define PCI_WIN1_OFFS 0x11000000
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