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[atheros]: move files for kernel 2.6.26 to a special directory.

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In kernel 2.6.28 the directory structure has chanced, so for kernel 2.6.26 a own files directory is needed.


git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14583 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
hauke
2009-02-20 16:19:46 +00:00
parent 58b41997f2
commit a348226cd2
28 changed files with 0 additions and 0 deletions
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533
target/linux/atheros/files-2.6.26/drivers/mtd/devices/spiflash.c Normal file
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/*
* MTD driver for the SPI Flash Memory support.
*
* Copyright (c) 2005-2006 Atheros Communications Inc.
* Copyright (C) 2006-2007 FON Technology, SL.
* Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
* Copyright (C) 2006-2007 Felix Fietkau <nbd@openwrt.org>
*
* This code is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*===========================================================================
** !!!! VERY IMPORTANT NOTICE !!!! FLASH DATA STORED IN LITTLE ENDIAN FORMAT
**
** This module contains the Serial Flash access routines for the Atheros SOC.
** The Atheros SOC integrates a SPI flash controller that is used to access
** serial flash parts. The SPI flash controller executes in "Little Endian"
** mode. THEREFORE, all WRITES and READS from the MIPS CPU must be
** BYTESWAPPED! The SPI Flash controller hardware by default performs READ
** ONLY byteswapping when accessed via the SPI Flash Alias memory region
** (Physical Address 0x0800_0000 - 0x0fff_ffff). The data stored in the
** flash sectors is stored in "Little Endian" format.
**
** The spiflash_write() routine performs byteswapping on all write
** operations.
**===========================================================================*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/version.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/squashfs_fs.h>
#include <linux/root_dev.h>
#include <linux/delay.h>
#include <asm/delay.h>
#include <asm/io.h>
#include "spiflash.h"
#ifndef __BIG_ENDIAN
#error This driver currently only works with big endian CPU.
#endif
#define MAX_PARTS 32
#define SPIFLASH "spiflash: "
#define MIN(a,b) ((a) < (b) ? (a) : (b))
#define busy_wait(condition, wait) \
do { \
while (condition) { \
spin_unlock_bh(&spidata->mutex); \
if (wait > 1) \
msleep(wait); \
else if ((wait == 1) && need_resched()) \
schedule(); \
else \
udelay(1); \
spin_lock_bh(&spidata->mutex); \
} \
} while (0)
static __u32 spiflash_regread32(int reg);
static void spiflash_regwrite32(int reg, __u32 data);
static __u32 spiflash_sendcmd (int op, u32 addr);
int __init spiflash_init (void);
void __exit spiflash_exit (void);
static int spiflash_probe_chip (void);
static int spiflash_erase (struct mtd_info *mtd,struct erase_info *instr);
static int spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf);
static int spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf);
/* Flash configuration table */
struct flashconfig {
__u32 byte_cnt;
__u32 sector_cnt;
__u32 sector_size;
__u32 cs_addrmask;
} flashconfig_tbl[MAX_FLASH] =
{
{ 0, 0, 0, 0},
{ STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE, 0x0},
{ STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE, 0x0},
{ STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE, 0x0},
{ STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE, 0x0},
{ STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE, 0x0}
};
/* Mapping of generic opcodes to STM serial flash opcodes */
#define SPI_WRITE_ENABLE 0
#define SPI_WRITE_DISABLE 1
#define SPI_RD_STATUS 2
#define SPI_WR_STATUS 3
#define SPI_RD_DATA 4
#define SPI_FAST_RD_DATA 5
#define SPI_PAGE_PROGRAM 6
#define SPI_SECTOR_ERASE 7
#define SPI_BULK_ERASE 8
#define SPI_DEEP_PWRDOWN 9
#define SPI_RD_SIG 10
#define SPI_MAX_OPCODES 11
struct opcodes {
__u16 code;
__s8 tx_cnt;
__s8 rx_cnt;
} stm_opcodes[] = {
{STM_OP_WR_ENABLE, 1, 0},
{STM_OP_WR_DISABLE, 1, 0},
{STM_OP_RD_STATUS, 1, 1},
{STM_OP_WR_STATUS, 1, 0},
{STM_OP_RD_DATA, 4, 4},
{STM_OP_FAST_RD_DATA, 5, 0},
{STM_OP_PAGE_PGRM, 8, 0},
{STM_OP_SECTOR_ERASE, 4, 0},
{STM_OP_BULK_ERASE, 1, 0},
{STM_OP_DEEP_PWRDOWN, 1, 0},
{STM_OP_RD_SIG, 4, 1},
};
/* Driver private data structure */
struct spiflash_data {
struct mtd_info *mtd;
struct mtd_partition *parsed_parts; /* parsed partitions */
void *readaddr; /* memory mapped data for read */
void *mmraddr; /* memory mapped register space */
wait_queue_head_t wq;
spinlock_t mutex;
int state;
};
enum {
FL_READY,
FL_READING,
FL_ERASING,
FL_WRITING
};
static struct spiflash_data *spidata;
extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
/***************************************************************************************************/
static __u32
spiflash_regread32(int reg)
{
volatile __u32 *data = (__u32 *)(spidata->mmraddr + reg);
return (*data);
}
static void
spiflash_regwrite32(int reg, __u32 data)
{
volatile __u32 *addr = (__u32 *)(spidata->mmraddr + reg);
*addr = data;
return;
}
static __u32
spiflash_sendcmd (int op, u32 addr)
{
u32 reg;
u32 mask;
struct opcodes *ptr_opcode;
ptr_opcode = &stm_opcodes[op];
busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
spiflash_regwrite32(SPI_FLASH_OPCODE, ((u32) ptr_opcode->code) | (addr << 8));
reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt |
(ptr_opcode->rx_cnt << 4) | SPI_CTL_START;
spiflash_regwrite32(SPI_FLASH_CTL, reg);
busy_wait(spiflash_regread32(SPI_FLASH_CTL) & SPI_CTL_BUSY, 0);
if (!ptr_opcode->rx_cnt)
return 0;
reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
switch (ptr_opcode->rx_cnt) {
case 1:
mask = 0x000000ff;
break;
case 2:
mask = 0x0000ffff;
break;
case 3:
mask = 0x00ffffff;
break;
default:
mask = 0xffffffff;
break;
}
reg &= mask;
return reg;
}
/* Probe SPI flash device
* Function returns 0 for failure.
* and flashconfig_tbl array index for success.
*/
static int
spiflash_probe_chip (void)
{
__u32 sig;
int flash_size;
/* Read the signature on the flash device */
spin_lock_bh(&spidata->mutex);
sig = spiflash_sendcmd(SPI_RD_SIG, 0);
spin_unlock_bh(&spidata->mutex);
switch (sig) {
case STM_8MBIT_SIGNATURE:
flash_size = FLASH_1MB;
break;
case STM_16MBIT_SIGNATURE:
flash_size = FLASH_2MB;
break;
case STM_32MBIT_SIGNATURE:
flash_size = FLASH_4MB;
break;
case STM_64MBIT_SIGNATURE:
flash_size = FLASH_8MB;
break;
case STM_128MBIT_SIGNATURE:
flash_size = FLASH_16MB;
break;
default:
printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n");
return (0);
}
return (flash_size);
}
/* wait until the flash chip is ready and grab a lock */
static int spiflash_wait_ready(int state)
{
DECLARE_WAITQUEUE(wait, current);
retry:
spin_lock_bh(&spidata->mutex);
if (spidata->state != FL_READY) {
set_current_state(TASK_UNINTERRUPTIBLE);
add_wait_queue(&spidata->wq, &wait);
spin_unlock_bh(&spidata->mutex);
schedule();
remove_wait_queue(&spidata->wq, &wait);
if(signal_pending(current))
return 0;
goto retry;
}
spidata->state = state;
return 1;
}
static inline void spiflash_done(void)
{
spidata->state = FL_READY;
spin_unlock_bh(&spidata->mutex);
wake_up(&spidata->wq);
}
static int
spiflash_erase (struct mtd_info *mtd,struct erase_info *instr)
{
struct opcodes *ptr_opcode;
u32 temp, reg;
/* sanity checks */
if (instr->addr + instr->len > mtd->size) return (-EINVAL);
if (!spiflash_wait_ready(FL_ERASING))
return -EINTR;
spiflash_sendcmd(SPI_WRITE_ENABLE, 0);
busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
reg = spiflash_regread32(SPI_FLASH_CTL);
ptr_opcode = &stm_opcodes[SPI_SECTOR_ERASE];
temp = ((__u32)instr->addr << 8) | (__u32)(ptr_opcode->code);
spiflash_regwrite32(SPI_FLASH_OPCODE, temp);
reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt | SPI_CTL_START;
spiflash_regwrite32(SPI_FLASH_CTL, reg);
/* this will take some time */
spin_unlock_bh(&spidata->mutex);
msleep(800);
spin_lock_bh(&spidata->mutex);
busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 20);
spiflash_done();
instr->state = MTD_ERASE_DONE;
if (instr->callback) instr->callback (instr);
return 0;
}
static int
spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf)
{
u8 *read_addr;
/* sanity checks */
if (!len) return (0);
if (from + len > mtd->size) return (-EINVAL);
/* we always read len bytes */
*retlen = len;
if (!spiflash_wait_ready(FL_READING))
return -EINTR;
read_addr = (u8 *)(spidata->readaddr + from);
memcpy(buf, read_addr, len);
spiflash_done();
return 0;
}
static int
spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf)
{
u32 opcode, bytes_left;
*retlen = 0;
/* sanity checks */
if (!len) return (0);
if (to + len > mtd->size) return (-EINVAL);
opcode = stm_opcodes[SPI_PAGE_PROGRAM].code;
bytes_left = len;
do {
u32 xact_len, reg, page_offset, spi_data = 0;
xact_len = MIN(bytes_left, sizeof(__u32));
/* 32-bit writes cannot span across a page boundary
* (256 bytes). This types of writes require two page
* program operations to handle it correctly. The STM part
* will write the overflow data to the beginning of the
* current page as opposed to the subsequent page.
*/
page_offset = (to & (STM_PAGE_SIZE - 1)) + xact_len;
if (page_offset > STM_PAGE_SIZE) {
xact_len -= (page_offset - STM_PAGE_SIZE);
}
if (!spiflash_wait_ready(FL_WRITING))
return -EINTR;
spiflash_sendcmd(SPI_WRITE_ENABLE, 0);
switch (xact_len) {
case 1:
spi_data = (u32) ((u8) *buf);
break;
case 2:
spi_data = (buf[1] << 8) | buf[0];
break;
case 3:
spi_data = (buf[2] << 16) | (buf[1] << 8) | buf[0];
break;
case 4:
spi_data = (buf[3] << 24) | (buf[2] << 16) |
(buf[1] << 8) | buf[0];
break;
default:
spi_data = 0;
break;
}
spiflash_regwrite32(SPI_FLASH_DATA, spi_data);
opcode = (opcode & SPI_OPCODE_MASK) | ((__u32)to << 8);
spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
reg = spiflash_regread32(SPI_FLASH_CTL);
reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | (xact_len + 4) | SPI_CTL_START;
spiflash_regwrite32(SPI_FLASH_CTL, reg);
/* give the chip some time before we start busy waiting */
spin_unlock_bh(&spidata->mutex);
schedule();
spin_lock_bh(&spidata->mutex);
busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 0);
spiflash_done();
bytes_left -= xact_len;
to += xact_len;
buf += xact_len;
*retlen += xact_len;
} while (bytes_left != 0);
return 0;
}
#ifdef CONFIG_MTD_PARTITIONS
static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL };
#endif
static int spiflash_probe(struct platform_device *pdev)
{
int result = -1;
int index, num_parts;
struct mtd_info *mtd;
spidata->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
spin_lock_init(&spidata->mutex);
init_waitqueue_head(&spidata->wq);
spidata->state = FL_READY;
if (!spidata->mmraddr) {
printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
kfree(spidata);
spidata = NULL;
}
mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
if (!mtd) {
kfree(spidata);
return -ENXIO;
}
if (!(index = spiflash_probe_chip())) {
printk (KERN_WARNING SPIFLASH "Found no serial flash device\n");
goto error;
}
spidata->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
if (!spidata->readaddr) {
printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
goto error;
}
mtd->name = "spiflash";
mtd->type = MTD_NORFLASH;
mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
mtd->size = flashconfig_tbl[index].byte_cnt;
mtd->erasesize = flashconfig_tbl[index].sector_size;
mtd->writesize = 1;
mtd->numeraseregions = 0;
mtd->eraseregions = NULL;
mtd->erase = spiflash_erase;
mtd->read = spiflash_read;
mtd->write = spiflash_write;
mtd->owner = THIS_MODULE;
/* parse redboot partitions */
num_parts = parse_mtd_partitions(mtd, part_probe_types, &spidata->parsed_parts, 0);
if (!num_parts)
goto error;
result = add_mtd_partitions(mtd, spidata->parsed_parts, num_parts);
spidata->mtd = mtd;
return (result);
error:
kfree(mtd);
kfree(spidata);
return -ENXIO;
}
static int spiflash_remove (struct platform_device *pdev)
{
del_mtd_partitions (spidata->mtd);
kfree(spidata->mtd);
return 0;
}
struct platform_driver spiflash_driver = {
.driver.name = "spiflash",
.probe = spiflash_probe,
.remove = spiflash_remove,
};
int __init
spiflash_init (void)
{
spidata = kmalloc(sizeof(struct spiflash_data), GFP_KERNEL);
if (!spidata)
return (-ENXIO);
spin_lock_init(&spidata->mutex);
platform_driver_register(&spiflash_driver);
return 0;
}
void __exit
spiflash_exit (void)
{
kfree(spidata);
}
module_init (spiflash_init);
module_exit (spiflash_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");

120
target/linux/atheros/files-2.6.26/drivers/mtd/devices/spiflash.h Normal file
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/*
* SPI Flash Memory support header file.
*
* $Id: //depot/sw/releases/linuxsrc/src/kernels/mips-linux-2.4.25/drivers/mtd/devices/spiflash.h#3 $
*
*
* Copyright (c) 2005, Atheros Communications Inc.
* Copyright (C) 2006 FON Technology, SL.
* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
*
* This code is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#define FLASH_1MB 1
#define FLASH_2MB 2
#define FLASH_4MB 3
#define FLASH_8MB 4
#define FLASH_16MB 5
#define MAX_FLASH 6
#define STM_PAGE_SIZE 256
#define SFI_WRITE_BUFFER_SIZE 4
#define SFI_FLASH_ADDR_MASK 0x00ffffff
#define STM_8MBIT_SIGNATURE 0x13
#define STM_M25P80_BYTE_COUNT 1048576
#define STM_M25P80_SECTOR_COUNT 16
#define STM_M25P80_SECTOR_SIZE 0x10000
#define STM_16MBIT_SIGNATURE 0x14
#define STM_M25P16_BYTE_COUNT 2097152
#define STM_M25P16_SECTOR_COUNT 32
#define STM_M25P16_SECTOR_SIZE 0x10000
#define STM_32MBIT_SIGNATURE 0x15
#define STM_M25P32_BYTE_COUNT 4194304
#define STM_M25P32_SECTOR_COUNT 64
#define STM_M25P32_SECTOR_SIZE 0x10000
#define STM_64MBIT_SIGNATURE 0x16
#define STM_M25P64_BYTE_COUNT 8388608
#define STM_M25P64_SECTOR_COUNT 128
#define STM_M25P64_SECTOR_SIZE 0x10000
#define STM_128MBIT_SIGNATURE 0x17
#define STM_M25P128_BYTE_COUNT 16777216
#define STM_M25P128_SECTOR_COUNT 256
#define STM_M25P128_SECTOR_SIZE 0x10000
#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
/*
* ST Microelectronics Opcodes for Serial Flash
*/
#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
#define STM_OP_RD_STATUS 0x05 /* Read Status */
#define STM_OP_WR_STATUS 0x01 /* Write Status */
#define STM_OP_RD_DATA 0x03 /* Read Data */
#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
/*
* SPI Flash Interface Registers
*/
#define AR531XPLUS_SPI_READ 0x08000000
#define AR531XPLUS_SPI_MMR 0x11300000
#define AR531XPLUS_SPI_MMR_SIZE 12
#define AR531XPLUS_SPI_CTL 0x00
#define AR531XPLUS_SPI_OPCODE 0x04
#define AR531XPLUS_SPI_DATA 0x08
#define SPI_FLASH_READ AR531XPLUS_SPI_READ
#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR
#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE
#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL
#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE
#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA
#define SPI_CTL_START 0x00000100
#define SPI_CTL_BUSY 0x00010000
#define SPI_CTL_TXCNT_MASK 0x0000000f
#define SPI_CTL_RXCNT_MASK 0x000000f0
#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
#define SPI_CTL_SIZE_MASK 0x00060000
#define SPI_CTL_CLK_SEL_MASK 0x03000000
#define SPI_OPCODE_MASK 0x000000ff
#define SPI_STATUS_WIP STM_STATUS_WIP

5
target/linux/atheros/files-2.6.26/drivers/net/ar2313/Makefile Normal file
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#
# Makefile for the AR2313 ethernet driver
#
obj-$(CONFIG_AR2313) += ar2313.o

1409
target/linux/atheros/files-2.6.26/drivers/net/ar2313/ar2313.c Normal file
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195
target/linux/atheros/files-2.6.26/drivers/net/ar2313/ar2313.h Normal file
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#ifndef _AR2313_H_
#define _AR2313_H_
#include <linux/autoconf.h>
#include <asm/bootinfo.h>
#include <ar531x_platform.h>
/*
* probe link timer - 5 secs
*/
#define LINK_TIMER (5*HZ)
#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
#define AR2313_TX_TIMEOUT (HZ/4)
/*
* Rings
*/
#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
static inline int tx_space(u32 csm, u32 prd)
{
return (csm - prd - 1) & (AR2313_DESCR_ENTRIES - 1);
}
#if MAX_SKB_FRAGS
#define TX_RESERVED (MAX_SKB_FRAGS+1) /* +1 for message header */
#define tx_ring_full(csm, prd) (tx_space(csm, prd) <= TX_RESERVED)
#else
#define tx_ring_full 0
#endif
#define AR2313_MBGET 2
#define AR2313_MBSET 3
#define AR2313_PCI_RECONFIG 4
#define AR2313_PCI_DUMP 5
#define AR2313_TEST_PANIC 6
#define AR2313_TEST_NULLPTR 7
#define AR2313_READ_DATA 8
#define AR2313_WRITE_DATA 9
#define AR2313_GET_VERSION 10
#define AR2313_TEST_HANG 11
#define AR2313_SYNC 12
//
// New Combo structure for Both Eth0 AND eth1
//
typedef struct {
volatile unsigned int mac_control; /* 0x00 */
volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
volatile unsigned int mii_addr; /* 0x14 */
volatile unsigned int mii_data; /* 0x18 */
volatile unsigned int flow_control; /* 0x1c */
volatile unsigned int vlan_tag; /* 0x20 */
volatile unsigned int pad[7]; /* 0x24 - 0x3c */
volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
} ETHERNET_STRUCT;
/********************************************************************
* Interrupt controller
********************************************************************/
typedef struct {
volatile unsigned int wdog_control; /* 0x08 */
volatile unsigned int wdog_timer; /* 0x0c */
volatile unsigned int misc_status; /* 0x10 */
volatile unsigned int misc_mask; /* 0x14 */
volatile unsigned int global_status; /* 0x18 */
volatile unsigned int reserved; /* 0x1c */
volatile unsigned int reset_control; /* 0x20 */
} INTERRUPT;
/********************************************************************
* DMA controller
********************************************************************/
typedef struct {
volatile unsigned int bus_mode; /* 0x00 (CSR0) */
volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
volatile unsigned int rcv_base; /* 0x0c (CSR3) */
volatile unsigned int xmt_base; /* 0x10 (CSR4) */
volatile unsigned int status; /* 0x14 (CSR5) */
volatile unsigned int control; /* 0x18 (CSR6) */
volatile unsigned int intr_ena; /* 0x1c (CSR7) */
volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
} DMA;
/*
* Struct private for the Sibyte.
*
* Elements are grouped so variables used by the tx handling goes
* together, and will go into the same cache lines etc. in order to
* avoid cache line contention between the rx and tx handling on SMP.
*
* Frequently accessed variables are put at the beginning of the
* struct to help the compiler generate better/shorter code.
*/
struct ar2313_private {
struct net_device *dev;
int version;
u32 mb[2];
volatile ETHERNET_STRUCT *phy_regs;
volatile ETHERNET_STRUCT *eth_regs;
volatile DMA *dma_regs;
volatile u32 *int_regs;
struct ar531x_eth *cfg;
spinlock_t lock; /* Serialise access to device */
/*
* RX and TX descriptors, must be adjacent
*/
ar2313_descr_t *rx_ring;
ar2313_descr_t *tx_ring;
struct sk_buff **rx_skb;
struct sk_buff **tx_skb;
/*
* RX elements
*/
u32 rx_skbprd;
u32 cur_rx;
/*
* TX elements
*/
u32 tx_prd;
u32 tx_csm;
/*
* Misc elements
*/
int board_idx;
char name[48];
struct {
u32 address;
u32 length;
char *mapping;
} desc;
struct timer_list link_timer;
unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
unsigned short mac;
unsigned short link; /* 0 - link down, 1 - link up */
u16 phyData;
struct tasklet_struct rx_tasklet;
int unloading;
struct phy_device *phy_dev;
struct mii_bus mii_bus;
int oldduplex;
};
/*
* Prototypes
*/
static int ar2313_init(struct net_device *dev);
#ifdef TX_TIMEOUT
static void ar2313_tx_timeout(struct net_device *dev);
#endif
#if 0
static void ar2313_multicast_list(struct net_device *dev);
#endif
static int ar2313_restart(struct net_device *dev);
#if DEBUG
static void ar2313_dump_regs(struct net_device *dev);
#endif
static void ar2313_load_rx_ring(struct net_device *dev, int bufs);
static irqreturn_t ar2313_interrupt(int irq, void *dev_id);
static int ar2313_open(struct net_device *dev);
static int ar2313_start_xmit(struct sk_buff *skb, struct net_device *dev);
static int ar2313_close(struct net_device *dev);
static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr,
int cmd);
static void ar2313_init_cleanup(struct net_device *dev);
static int ar2313_setup_timer(struct net_device *dev);
static void ar2313_link_timer_fn(unsigned long data);
static void ar2313_check_link(struct net_device *dev);
#endif /* _AR2313_H_ */

142
target/linux/atheros/files-2.6.26/drivers/net/ar2313/dma.h Normal file
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#ifndef __ARUBA_DMA_H__
#define __ARUBA_DMA_H__
/*******************************************************************************
*
* Copyright 2002 Integrated Device Technology, Inc.
* All rights reserved.
*
* DMA register definition.
*
* File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
*
* Author : ryan.holmQVist@idt.com
* Date : 20011005
* Update :
* $Log: dma.h,v $
* Revision 1.3 2002/06/06 18:34:03 astichte
* Added XXX_PhysicalAddress and XXX_VirtualAddress
*
* Revision 1.2 2002/06/05 18:30:46 astichte
* Removed IDTField
*
* Revision 1.1 2002/05/29 17:33:21 sysarch
* jba File moved from vcode/include/idt/acacia
*
*
******************************************************************************/
#define AR_BIT(x) (1 << (x))
#define DMA_RX_ERR_CRC AR_BIT(1)
#define DMA_RX_ERR_DRIB AR_BIT(2)
#define DMA_RX_ERR_MII AR_BIT(3)
#define DMA_RX_EV2 AR_BIT(5)
#define DMA_RX_ERR_COL AR_BIT(6)
#define DMA_RX_LONG AR_BIT(7)
#define DMA_RX_LS AR_BIT(8) /* last descriptor */
#define DMA_RX_FS AR_BIT(9) /* first descriptor */
#define DMA_RX_MF AR_BIT(10) /* multicast frame */
#define DMA_RX_ERR_RUNT AR_BIT(11) /* runt frame */
#define DMA_RX_ERR_LENGTH AR_BIT(12) /* length error */
#define DMA_RX_ERR_DESC AR_BIT(14) /* descriptor error */
#define DMA_RX_ERROR AR_BIT(15) /* error summary */
#define DMA_RX_LEN_MASK 0x3fff0000
#define DMA_RX_LEN_SHIFT 16
#define DMA_RX_FILT AR_BIT(30)
#define DMA_RX_OWN AR_BIT(31) /* desc owned by DMA controller */
#define DMA_RX1_BSIZE_MASK 0x000007ff
#define DMA_RX1_BSIZE_SHIFT 0
#define DMA_RX1_CHAINED AR_BIT(24)
#define DMA_RX1_RER AR_BIT(25)
#define DMA_TX_ERR_UNDER AR_BIT(1) /* underflow error */
#define DMA_TX_ERR_DEFER AR_BIT(2) /* excessive deferral */
#define DMA_TX_COL_MASK 0x78
#define DMA_TX_COL_SHIFT 3
#define DMA_TX_ERR_HB AR_BIT(7) /* hearbeat failure */
#define DMA_TX_ERR_COL AR_BIT(8) /* excessive collisions */
#define DMA_TX_ERR_LATE AR_BIT(9) /* late collision */
#define DMA_TX_ERR_LINK AR_BIT(10) /* no carrier */
#define DMA_TX_ERR_LOSS AR_BIT(11) /* loss of carrier */
#define DMA_TX_ERR_JABBER AR_BIT(14) /* transmit jabber timeout */
#define DMA_TX_ERROR AR_BIT(15) /* frame aborted */
#define DMA_TX_OWN AR_BIT(31) /* descr owned by DMA controller */
#define DMA_TX1_BSIZE_MASK 0x000007ff
#define DMA_TX1_BSIZE_SHIFT 0
#define DMA_TX1_CHAINED AR_BIT(24) /* chained descriptors */
#define DMA_TX1_TER AR_BIT(25) /* transmit end of ring */
#define DMA_TX1_FS AR_BIT(29) /* first segment */
#define DMA_TX1_LS AR_BIT(30) /* last segment */
#define DMA_TX1_IC AR_BIT(31) /* interrupt on completion */
#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
#define MAC_CONTROL_RE AR_BIT(2) /* receive enable */
#define MAC_CONTROL_TE AR_BIT(3) /* transmit enable */
#define MAC_CONTROL_DC AR_BIT(5) /* Deferral check */
#define MAC_CONTROL_ASTP AR_BIT(8) /* Auto pad strip */
#define MAC_CONTROL_DRTY AR_BIT(10) /* Disable retry */
#define MAC_CONTROL_DBF AR_BIT(11) /* Disable bcast frames */
#define MAC_CONTROL_LCC AR_BIT(12) /* late collision ctrl */
#define MAC_CONTROL_HP AR_BIT(13) /* Hash Perfect filtering */
#define MAC_CONTROL_HASH AR_BIT(14) /* Unicast hash filtering */
#define MAC_CONTROL_HO AR_BIT(15) /* Hash only filtering */
#define MAC_CONTROL_PB AR_BIT(16) /* Pass Bad frames */
#define MAC_CONTROL_IF AR_BIT(17) /* Inverse filtering */
#define MAC_CONTROL_PR AR_BIT(18) /* promiscuous mode (valid frames
only) */
#define MAC_CONTROL_PM AR_BIT(19) /* pass multicast */
#define MAC_CONTROL_F AR_BIT(20) /* full-duplex */
#define MAC_CONTROL_DRO AR_BIT(23) /* Disable Receive Own */
#define MAC_CONTROL_HBD AR_BIT(28) /* heart-beat disabled (MUST BE
SET) */
#define MAC_CONTROL_BLE AR_BIT(30) /* big endian mode */
#define MAC_CONTROL_RA AR_BIT(31) /* receive all (valid and invalid
frames) */
#define MII_ADDR_BUSY AR_BIT(0)
#define MII_ADDR_WRITE AR_BIT(1)
#define MII_ADDR_REG_SHIFT 6
#define MII_ADDR_PHY_SHIFT 11
#define MII_DATA_SHIFT 0
#define FLOW_CONTROL_FCE AR_BIT(1)
#define DMA_BUS_MODE_SWR AR_BIT(0) /* software reset */
#define DMA_BUS_MODE_BLE AR_BIT(7) /* big endian mode */
#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
#define DMA_BUS_MODE_DBO AR_BIT(20) /* big-endian descriptors */
#define DMA_STATUS_TI AR_BIT(0) /* transmit interrupt */
#define DMA_STATUS_TPS AR_BIT(1) /* transmit process stopped */
#define DMA_STATUS_TU AR_BIT(2) /* transmit buffer unavailable */
#define DMA_STATUS_TJT AR_BIT(3) /* transmit buffer timeout */
#define DMA_STATUS_UNF AR_BIT(5) /* transmit underflow */
#define DMA_STATUS_RI AR_BIT(6) /* receive interrupt */
#define DMA_STATUS_RU AR_BIT(7) /* receive buffer unavailable */
#define DMA_STATUS_RPS AR_BIT(8) /* receive process stopped */
#define DMA_STATUS_ETI AR_BIT(10) /* early transmit interrupt */
#define DMA_STATUS_FBE AR_BIT(13) /* fatal bus interrupt */
#define DMA_STATUS_ERI AR_BIT(14) /* early receive interrupt */
#define DMA_STATUS_AIS AR_BIT(15) /* abnormal interrupt summary */
#define DMA_STATUS_NIS AR_BIT(16) /* normal interrupt summary */
#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
#define DMA_STATUS_EB_SHIFT 23 /* error bits */
#define DMA_CONTROL_SR AR_BIT(1) /* start receive */
#define DMA_CONTROL_ST AR_BIT(13) /* start transmit */
#define DMA_CONTROL_SF AR_BIT(21) /* store and forward */
typedef struct {
volatile unsigned int status; // OWN, Device control and status.
volatile unsigned int devcs; // pkt Control bits + Length
volatile unsigned int addr; // Current Address.
volatile unsigned int descr; // Next descriptor in chain.
} ar2313_descr_t;
#endif // __ARUBA_DMA_H__

198
target/linux/atheros/files-2.6.26/drivers/watchdog/ar2315-wtd.c Normal file
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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2008 John Crispin <blogic@openwrt.org>
* Based on EP93xx and ifxmips wdt driver
*/
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/addrspace.h>
#include <ar531x.h>
#define CLOCK_RATE 40000000
#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x)
static int wdt_timeout = 20;
static int started = 0;
static int in_use = 0;
static void
ar2315_wdt_enable(void)
{
sysRegWrite(AR5315_WD, wdt_timeout * CLOCK_RATE);
sysRegWrite(AR5315_ISR, 0x80);
}
static ssize_t
ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos)
{
if(len)
ar2315_wdt_enable();
return len;
}
static int
ar2315_wdt_open(struct inode *inode, struct file *file)
{
if(in_use)
return -EBUSY;
ar2315_wdt_enable();
in_use = started = 1;
return nonseekable_open(inode, file);
}
static int
ar2315_wdt_release(struct inode *inode, struct file *file)
{
in_use = 0;
return 0;
}
static irqreturn_t
ar2315_wdt_interrupt(int irq, void *dev_id)
{
if(started)
{
printk(KERN_CRIT "watchdog expired, rebooting system\n");
emergency_restart();
} else {
sysRegWrite(AR5315_WDC, 0);
sysRegWrite(AR5315_WD, 0);
sysRegWrite(AR5315_ISR, 0x80);
}
return IRQ_HANDLED;
}
static struct watchdog_info ident = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
.identity = "ar2315 Watchdog",
};
static int
ar2315_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
{
int new_wdt_timeout;
int ret = -ENOIOCTLCMD;
switch(cmd)
{
case WDIOC_GETSUPPORT:
ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0;
break;
case WDIOC_KEEPALIVE:
ar2315_wdt_enable();
ret = 0;
break;
case WDIOC_SETTIMEOUT:
if((ret = get_user(new_wdt_timeout, (int __user *)arg)))
break;
wdt_timeout = HEARTBEAT(new_wdt_timeout);
ar2315_wdt_enable();
break;
case WDIOC_GETTIMEOUT:
ret = put_user(wdt_timeout, (int __user *)arg);
break;
}
return ret;
}
static struct file_operations ar2315_wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = ar2315_wdt_write,
.ioctl = ar2315_wdt_ioctl,
.open = ar2315_wdt_open,
.release = ar2315_wdt_release,
};
static struct miscdevice ar2315_wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &ar2315_wdt_fops,
};
static int
ar2315_wdt_probe(struct platform_device *dev)
{
int ret = 0;
ar2315_wdt_enable();
ret = request_irq(AR531X_MISC_IRQ_WATCHDOG, ar2315_wdt_interrupt, IRQF_DISABLED, "ar2315_wdt", NULL);
if(ret)
{
printk(KERN_ERR "ar2315wdt: failed to register inetrrupt\n");
goto out;
}
ret = misc_register(&ar2315_wdt_miscdev);
if(ret)
printk(KERN_ERR "ar2315wdt: failed to register miscdev\n");
out:
return ret;
}
static int
ar2315_wdt_remove(struct platform_device *dev)
{
misc_deregister(&ar2315_wdt_miscdev);
free_irq(AR531X_MISC_IRQ_WATCHDOG, NULL);
return 0;
}
static struct platform_driver ar2315_wdt_driver = {
.probe = ar2315_wdt_probe,
.remove = ar2315_wdt_remove,
.driver = {
.name = "ar2315_wdt",
.owner = THIS_MODULE,
},
};
static int __init
init_ar2315_wdt(void)
{
int ret = platform_driver_register(&ar2315_wdt_driver);
if(ret)
printk(KERN_INFO "ar2315_wdt: error registering platfom driver!");
return ret;
}
static void __exit
exit_ar2315_wdt(void)
{
platform_driver_unregister(&ar2315_wdt_driver);
}
module_init(init_ar2315_wdt);
module_exit(exit_ar2315_wdt);