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git://projects.qi-hardware.com/openwrt-xburst.git
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[boot] move boot related packages to their own folder
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33781 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
199
package/boot/uboot-xburst/files/cpu/mips/jz4740_nand.c
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199
package/boot/uboot-xburst/files/cpu/mips/jz4740_nand.c
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/*
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* Platform independend driver for JZ4740.
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*
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* Copyright (c) 2007 Ingenic Semiconductor Inc.
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* Author: <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#if defined(CONFIG_CMD_NAND) && defined(CONFIG_JZ4740)
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#include <nand.h>
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#include <asm/jz4740.h>
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#include <asm/io.h>
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#define PAR_SIZE 9
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#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST )
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#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
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#define __nand_select_rs_ecc() (REG_EMC_NFECR |= EMC_NFECR_RS)
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#define __nand_rs_ecc_encoding() (REG_EMC_NFECR |= EMC_NFECR_RS_ENCODING)
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#define __nand_rs_ecc_decoding() (REG_EMC_NFECR |= EMC_NFECR_RS_DECODING)
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#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
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#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
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static void jz_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
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if (ctrl & NAND_CTRL_CHANGE) {
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/* Change this to use I/O accessors. */
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if (ctrl & NAND_NCE)
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REG_EMC_NFCSR |= EMC_NFCSR_NFCE1;
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else
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REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
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}
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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nandaddr |= 0x00008000;
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else /* must be ALE */
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nandaddr |= 0x00010000;
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writeb(cmd, (uint8_t *)nandaddr);
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}
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static int jz_device_ready(struct mtd_info *mtd)
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{
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int ready;
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udelay(20); /* FIXME: add 20us delay */
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ready = (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0;
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return ready;
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}
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/*
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* EMC setup
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*/
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static void jz_device_setup(void)
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{
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/* Set NFE bit */
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REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
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REG_EMC_SMCR1 = 0x094c4400;
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/* REG_EMC_SMCR3 = 0x04444400; */
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}
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void board_nand_select_device(struct nand_chip *nand, int chip)
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{
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/*
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* Don't use "chip" to address the NAND device,
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* generate the cs from the address where it is encoded.
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*/
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}
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static int jzsoc_nand_calculate_rs_ecc(struct mtd_info* mtd, const u_char* dat,
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u_char* ecc_code)
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{
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volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
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short i;
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__nand_ecc_encode_sync()
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__nand_ecc_disable();
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for(i = 0; i < PAR_SIZE; i++)
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ecc_code[i] = *paraddr++;
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return 0;
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}
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static void jzsoc_nand_enable_rs_hwecc(struct mtd_info* mtd, int mode)
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{
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__nand_ecc_enable();
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__nand_select_rs_ecc();
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REG_EMC_NFINTS = 0x0;
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if (NAND_ECC_READ == mode){
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__nand_rs_ecc_decoding();
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}
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if (NAND_ECC_WRITE == mode){
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__nand_rs_ecc_encoding();
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}
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}
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/* Correct 1~9-bit errors in 512-bytes data */
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static void jzsoc_rs_correct(unsigned char *dat, int idx, int mask)
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{
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int i;
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idx--;
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i = idx + (idx >> 3);
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if (i >= 512)
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return;
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mask <<= (idx & 0x7);
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dat[i] ^= mask & 0xff;
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if (i < 511)
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dat[i+1] ^= (mask >> 8) & 0xff;
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}
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static int jzsoc_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
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short k;
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u32 stat;
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/* Set PAR values */
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for (k = 0; k < PAR_SIZE; k++) {
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*paraddr++ = read_ecc[k];
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}
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/* Set PRDY */
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REG_EMC_NFECR |= EMC_NFECR_PRDY;
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/* Wait for completion */
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__nand_ecc_decode_sync();
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__nand_ecc_disable();
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/* Check decoding */
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stat = REG_EMC_NFINTS;
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if (stat & EMC_NFINTS_ERR) {
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if (stat & EMC_NFINTS_UNCOR) {
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printk("Uncorrectable error occurred\n");
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return -1;
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}
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else {
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u32 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
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switch (errcnt) {
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case 4:
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jzsoc_rs_correct(dat, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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case 3:
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jzsoc_rs_correct(dat, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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case 2:
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jzsoc_rs_correct(dat, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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case 1:
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jzsoc_rs_correct(dat, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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return 0;
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default:
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break;
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}
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}
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}
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/* no error need to be correct */
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return 0;
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}
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/*
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* Main initialization routine
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*/
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int board_nand_init(struct nand_chip *nand)
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{
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jz_device_setup();
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nand->cmd_ctrl = jz_hwcontrol;
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nand->dev_ready = jz_device_ready;
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/* FIXME: should use NAND_ECC_SOFT */
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nand->ecc.hwctl = jzsoc_nand_enable_rs_hwecc;
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nand->ecc.correct = jzsoc_nand_rs_correct_data;
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nand->ecc.calculate = jzsoc_nand_calculate_rs_ecc;
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.size = 512;
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nand->ecc.bytes = 9;
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/* 20 us command delay time */
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nand->chip_delay = 20;
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return 0;
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}
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#endif /* (CONFIG_SYS_CMD_NAND) */
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