mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
[boot] move boot related packages to their own folder
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33781 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
429
package/boot/uboot-xburst/files/nand_spl/nand_boot_jz4740.c
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429
package/boot/uboot-xburst/files/nand_spl/nand_boot_jz4740.c
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@@ -0,0 +1,429 @@
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/*
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* Copyright (C) 2007 Ingenic Semiconductor Inc.
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* Author: Peter <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <asm/jz4740.h>
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#define KEY_U_OUT (32 * 2 + 16)
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#define KEY_U_IN (32 * 3 + 19)
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/*
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* NAND flash definitions
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*/
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#define NAND_DATAPORT 0xb8000000
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#define NAND_ADDRPORT 0xb8010000
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#define NAND_COMMPORT 0xb8008000
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#define ECC_BLOCK 512
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#define ECC_POS 6
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#define PAR_SIZE 9
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#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1)
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#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
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#define __nand_ecc_rs_encoding() \
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(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
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#define __nand_ecc_rs_decoding() \
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(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING)
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#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
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#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
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#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
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static inline void __nand_dev_ready(void)
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{
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unsigned int timeout = 10000;
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while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
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while (!(REG_GPIO_PXPIN(2) & 0x40000000));
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}
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#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n))
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#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n))
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#define __nand_data8() REG8(NAND_DATAPORT)
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#define __nand_data16() REG16(NAND_DATAPORT)
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#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3)
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#define NAND_BUS_WIDTH 8
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#define NAND_ROW_CYCLE 3
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#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
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#define NAND_BUS_WIDTH 8
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#define NAND_ROW_CYCLE 2
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#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3)
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#define NAND_BUS_WIDTH 16
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#define NAND_ROW_CYCLE 3
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#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
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#define NAND_BUS_WIDTH 16
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#define NAND_ROW_CYCLE 2
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#endif
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/*
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* NAND flash parameters
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*/
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static int page_size = 2048;
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static int oob_size = 64;
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static int ecc_count = 4;
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static int page_per_block = 64;
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static int bad_block_pos = 0;
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static int block_size = 131072;
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static unsigned char oob_buf[128] = {0};
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/*
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* External routines
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*/
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extern void flush_cache_all(void);
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extern int serial_init(void);
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extern void serial_puts(const char *s);
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extern void sdram_init(void);
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extern void pll_init(void);
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extern void usb_boot();
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/*
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* NAND flash routines
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*/
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#if NAND_BUS_WIDTH == 16
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static inline void nand_read_buf16(void *buf, int count)
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{
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int i;
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u16 *p = (u16 *)buf;
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for (i = 0; i < count; i += 2)
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*p++ = __nand_data16();
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}
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#define nand_read_buf nand_read_buf16
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#elif NAND_BUS_WIDTH == 8
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static inline void nand_read_buf8(void *buf, int count)
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{
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int i;
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u8 *p = (u8 *)buf;
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for (i = 0; i < count; i++)
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*p++ = __nand_data8();
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}
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#define nand_read_buf nand_read_buf8
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#endif
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/* Correct 1~9-bit errors in 512-bytes data */
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static void rs_correct(unsigned char *dat, int idx, int mask)
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{
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int i;
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idx--;
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i = idx + (idx >> 3);
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if (i >= 512)
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return;
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mask <<= (idx & 0x7);
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dat[i] ^= mask & 0xff;
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if (i < 511)
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dat[i+1] ^= (mask >> 8) & 0xff;
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}
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static int nand_read_oob(int page_addr, uchar *buf, int size)
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{
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int col_addr;
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if (page_size != 512)
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col_addr = page_size;
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else {
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col_addr = 0;
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__nand_dev_ready();
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}
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if (page_size != 512)
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/* Send READ0 command */
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__nand_cmd(NAND_CMD_READ0);
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else
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/* Send READOOB command */
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__nand_cmd(NAND_CMD_READOOB);
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/* Send column address */
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__nand_addr(col_addr & 0xff);
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if (page_size != 512)
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__nand_addr((col_addr >> 8) & 0xff);
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/* Send page address */
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__nand_addr(page_addr & 0xff);
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__nand_addr((page_addr >> 8) & 0xff);
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#ifdef NAND_ROW_CYCLE == 3
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__nand_addr((page_addr >> 16) & 0xff);
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#endif
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/* Send READSTART command for 2048 or 4096 ps NAND */
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if (page_size != 512)
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__nand_cmd(NAND_CMD_READSTART);
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/* Wait for device ready */
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__nand_dev_ready();
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/* Read oob data */
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nand_read_buf(buf, size);
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if (page_size == 512)
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__nand_dev_ready();
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return 0;
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}
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static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
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{
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uchar *databuf = dst, *tmpbuf;
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int i, j;
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/*
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* Read oob data
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*/
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nand_read_oob(page_addr, oobbuf, oob_size);
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/*
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* Read page data
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*/
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/* Send READ0 command */
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__nand_cmd(NAND_CMD_READ0);
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/* Send column address */
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__nand_addr(0);
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if (page_size != 512)
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__nand_addr(0);
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/* Send page address */
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__nand_addr(page_addr & 0xff);
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__nand_addr((page_addr >> 8) & 0xff);
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#if NAND_ROW_CYCLE == 3
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__nand_addr((page_addr >> 16) & 0xff);
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#endif
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/* Send READSTART command for 2048 or 4096 ps NAND */
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if (page_size != 512)
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__nand_cmd(NAND_CMD_READSTART);
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/* Wait for device ready */
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__nand_dev_ready();
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/* Read page data */
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tmpbuf = databuf;
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for (i = 0; i < ecc_count; i++) {
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volatile unsigned char *paraddr = (volatile unsigned char *)EMC_NFPAR0;
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unsigned int stat;
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/* Enable RS decoding */
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REG_EMC_NFINTS = 0x0;
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__nand_ecc_rs_decoding();
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/* Read data */
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nand_read_buf((void *)tmpbuf, ECC_BLOCK);
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/* Set PAR values */
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for (j = 0; j < PAR_SIZE; j++) {
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#if defined(CONFIG_SYS_NAND_ECC_POS)
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*paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*PAR_SIZE + j];
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#else
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*paraddr++ = oobbuf[ECC_POS + i*PAR_SIZE + j];
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#endif
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}
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/* Set PRDY */
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REG_EMC_NFECR |= EMC_NFECR_PRDY;
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/* Wait for completion */
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__nand_ecc_decode_sync();
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/* Disable decoding */
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__nand_ecc_disable();
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/* Check result of decoding */
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stat = REG_EMC_NFINTS;
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if (stat & EMC_NFINTS_ERR) {
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/* Error occurred */
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/* serial_puts("\n Error occurred\n"); */
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if (stat & EMC_NFINTS_UNCOR) {
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/* Uncorrectable error occurred */
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/* serial_puts("\nUncorrectable error occurred\n"); */
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}
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else {
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unsigned int errcnt, index, mask;
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errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
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switch (errcnt) {
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case 4:
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index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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rs_correct(tmpbuf, index, mask);
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/* FALL-THROUGH */
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case 3:
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index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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rs_correct(tmpbuf, index, mask);
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/* FALL-THROUGH */
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case 2:
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index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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rs_correct(tmpbuf, index, mask);
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/* FALL-THROUGH */
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case 1:
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index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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rs_correct(tmpbuf, index, mask);
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break;
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default:
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break;
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}
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}
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}
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tmpbuf += ECC_BLOCK;
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}
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return 0;
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}
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#ifndef CONFIG_SYS_NAND_BADBLOCK_PAGE
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#define CONFIG_SYS_NAND_BADBLOCK_PAGE 0 /* NAND bad block was marked at this page in a block, starting from 0 */
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#endif
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static void nand_load(int offs, int uboot_size, uchar *dst)
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{
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int page;
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int pagecopy_count;
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__nand_enable();
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page = offs / page_size;
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pagecopy_count = 0;
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while (pagecopy_count < (uboot_size / page_size)) {
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if (page % page_per_block == 0) {
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nand_read_oob(page + CONFIG_SYS_NAND_BADBLOCK_PAGE, oob_buf, oob_size);
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if (oob_buf[bad_block_pos] != 0xff) {
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page += page_per_block;
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/* Skip bad block */
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continue;
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}
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}
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/* Load this page to dst, do the ECC */
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nand_read_page(page, dst, oob_buf);
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dst += page_size;
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page++;
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pagecopy_count++;
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}
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__nand_disable();
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}
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static void jz_nand_init(void) {
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/* Optimize the timing of nand */
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REG_EMC_SMCR1 = 0x094c4400;
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}
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static void gpio_init(void)
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{
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/*
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* Initialize SDRAM pins
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*/
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#if defined(CONFIG_JZ4720)
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__gpio_as_sdram_16bit_4720();
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#elif defined(CONFIG_JZ4725)
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__gpio_as_sdram_16bit_4725();
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#else
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__gpio_as_sdram_32bit();
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#endif
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/*
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* Initialize UART0 pins
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*/
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__gpio_as_uart0();
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}
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static int is_usb_boot()
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{
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int keyU = 0;
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__gpio_as_input(KEY_U_IN);
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__gpio_enable_pull(KEY_U_IN);
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__gpio_as_output(KEY_U_OUT);
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__gpio_clear_pin(KEY_U_OUT);
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keyU = __gpio_get_pin(KEY_U_IN);
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if (keyU)
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serial_puts("[U] not pressed\n");
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else
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serial_puts("[U] pressed\n");
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return !keyU;
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}
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void nand_boot(void)
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{
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void (*uboot)(void);
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/*
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* Init hardware
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*/
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jz_nand_init();
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gpio_init();
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serial_init();
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serial_puts("\n\nNAND Secondary Program Loader\n\n");
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pll_init();
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sdram_init();
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#if defined(CONFIG_NANONOTE)
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if(is_usb_boot()) {
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serial_puts("enter USB BOOT mode\n");
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usb_boot();
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}
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#endif
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page_size = CONFIG_SYS_NAND_PAGE_SIZE;
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block_size = CONFIG_SYS_NAND_BLOCK_SIZE;
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page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
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bad_block_pos = (page_size == 512) ? 5 : 0;
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oob_size = page_size / 32;
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ecc_count = page_size / ECC_BLOCK;
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/*
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* Load U-Boot image from NAND into RAM
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*/
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nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
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(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
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uboot = (void (*)(void))CONFIG_SYS_NAND_U_BOOT_START;
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serial_puts("Starting U-Boot ...\n");
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/*
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* Flush caches
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*/
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flush_cache_all();
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/*
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* Jump to U-Boot image
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*/
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(*uboot)();
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}
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