mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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spiflash cleanup
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7084 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
66f85d3b83
commit
a44177ee58
@ -3,9 +3,9 @@
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* MTD driver for the SPI Flash Memory support.
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* MTD driver for the SPI Flash Memory support.
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*
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*
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* Copyright (c) 2005-2006 Atheros Communications Inc.
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* Copyright (c) 2005-2006 Atheros Communications Inc.
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* Copyright (C) 2006 FON Technology, SL.
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* Copyright (C) 2006-2007 FON Technology, SL.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2006-2007 Felix Fietkau <nbd@openwrt.org>
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*
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*
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* This code is free software; you can redistribute it and/or modify
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* it under the terms of the GNU General Public License version 2 as
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@ -40,30 +40,39 @@
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/squashfs_fs.h>
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#include <linux/squashfs_fs.h>
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#include <linux/root_dev.h>
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#include <linux/root_dev.h>
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#include <linux/delay.h>
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#include <asm/delay.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include "spiflash.h"
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#include "spiflash.h"
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/* debugging */
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/* #define SPIFLASH_DEBUG */
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#ifndef __BIG_ENDIAN
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#ifndef __BIG_ENDIAN
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#error This driver currently only works with big endian CPU.
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#error This driver currently only works with big endian CPU.
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#endif
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#endif
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#define MAX_PARTS 32
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#define MAX_PARTS 32
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static char module_name[] = "spiflash";
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#define SPIFLASH "spiflash: "
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#define MIN(a,b) ((a) < (b) ? (a) : (b))
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#define MIN(a,b) ((a) < (b) ? (a) : (b))
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#define FALSE 0
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#define TRUE 1
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#define ROOTFS_NAME "rootfs"
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#define busy_wait(condition, wait) \
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do { \
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while (condition) { \
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spin_unlock_bh(&spidata->mutex); \
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if (wait > 1) \
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msleep(wait); \
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else if ((wait == 1) && need_resched()) \
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schedule(); \
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else \
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udelay(1); \
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spin_lock_bh(&spidata->mutex); \
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} \
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} while (0)
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static __u32 spiflash_regread32(int reg);
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static __u32 spiflash_regread32(int reg);
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static void spiflash_regwrite32(int reg, __u32 data);
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static void spiflash_regwrite32(int reg, __u32 data);
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static __u32 spiflash_sendcmd (int op);
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static __u32 spiflash_sendcmd (int op, u32 addr);
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int __init spiflash_init (void);
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int __init spiflash_init (void);
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void __exit spiflash_exit (void);
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void __exit spiflash_exit (void);
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@ -89,6 +98,19 @@ struct flashconfig {
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};
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};
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/* Mapping of generic opcodes to STM serial flash opcodes */
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/* Mapping of generic opcodes to STM serial flash opcodes */
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#define SPI_WRITE_ENABLE 0
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#define SPI_WRITE_DISABLE 1
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#define SPI_RD_STATUS 2
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#define SPI_WR_STATUS 3
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#define SPI_RD_DATA 4
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#define SPI_FAST_RD_DATA 5
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#define SPI_PAGE_PROGRAM 6
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#define SPI_SECTOR_ERASE 7
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#define SPI_BULK_ERASE 8
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#define SPI_DEEP_PWRDOWN 9
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#define SPI_RD_SIG 10
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#define SPI_MAX_OPCODES 11
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struct opcodes {
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struct opcodes {
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__u16 code;
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__u16 code;
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__s8 tx_cnt;
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__s8 tx_cnt;
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@ -99,21 +121,29 @@ struct opcodes {
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{STM_OP_RD_STATUS, 1, 1},
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{STM_OP_RD_STATUS, 1, 1},
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{STM_OP_WR_STATUS, 1, 0},
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{STM_OP_WR_STATUS, 1, 0},
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{STM_OP_RD_DATA, 4, 4},
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{STM_OP_RD_DATA, 4, 4},
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{STM_OP_FAST_RD_DATA, 1, 0},
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{STM_OP_FAST_RD_DATA, 5, 0},
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{STM_OP_PAGE_PGRM, 8, 0},
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{STM_OP_PAGE_PGRM, 8, 0},
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{STM_OP_SECTOR_ERASE, 4, 0},
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{STM_OP_SECTOR_ERASE, 4, 0},
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{STM_OP_BULK_ERASE, 1, 0},
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{STM_OP_BULK_ERASE, 1, 0},
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{STM_OP_DEEP_PWRDOWN, 1, 0},
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{STM_OP_DEEP_PWRDOWN, 1, 0},
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{STM_OP_RD_SIG, 4, 1}
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{STM_OP_RD_SIG, 4, 1},
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};
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};
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/* Driver private data structure */
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/* Driver private data structure */
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struct spiflash_data {
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struct spiflash_data {
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struct mtd_info *mtd;
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struct mtd_info *mtd;
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struct mtd_partition *parsed_parts; /* parsed partitions */
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struct mtd_partition *parsed_parts; /* parsed partitions */
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void *spiflash_readaddr; /* memory mapped data for read */
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void *readaddr; /* memory mapped data for read */
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void *spiflash_mmraddr; /* memory mapped register space */
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void *mmraddr; /* memory mapped register space */
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wait_queue_head_t wq;
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spinlock_t mutex;
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spinlock_t mutex;
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int state;
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};
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enum {
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FL_READY,
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FL_READING,
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FL_ERASING,
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FL_WRITING
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};
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};
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static struct spiflash_data *spidata;
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static struct spiflash_data *spidata;
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@ -125,7 +155,7 @@ extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partitio
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static __u32
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static __u32
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spiflash_regread32(int reg)
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spiflash_regread32(int reg)
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{
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{
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volatile __u32 *data = (__u32 *)(spidata->spiflash_mmraddr + reg);
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volatile __u32 *data = (__u32 *)(spidata->mmraddr + reg);
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return (*data);
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return (*data);
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}
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}
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@ -133,63 +163,56 @@ spiflash_regread32(int reg)
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static void
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static void
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spiflash_regwrite32(int reg, __u32 data)
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spiflash_regwrite32(int reg, __u32 data)
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{
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{
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volatile __u32 *addr = (__u32 *)(spidata->spiflash_mmraddr + reg);
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volatile __u32 *addr = (__u32 *)(spidata->mmraddr + reg);
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*addr = data;
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*addr = data;
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return;
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return;
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}
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}
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static __u32
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static __u32
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spiflash_sendcmd (int op)
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spiflash_sendcmd (int op, u32 addr)
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{
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{
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__u32 reg;
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u32 reg;
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__u32 mask;
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u32 mask;
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struct opcodes *ptr_opcode;
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struct opcodes *ptr_opcode;
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ptr_opcode = &stm_opcodes[op];
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ptr_opcode = &stm_opcodes[op];
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busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
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do {
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spiflash_regwrite32(SPI_FLASH_OPCODE, ((u32) ptr_opcode->code) | (addr << 8));
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reg = spiflash_regread32(SPI_FLASH_CTL);
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} while (reg & SPI_CTL_BUSY);
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spiflash_regwrite32(SPI_FLASH_OPCODE, ptr_opcode->code);
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reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt |
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reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt |
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(ptr_opcode->rx_cnt << 4) | SPI_CTL_START;
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(ptr_opcode->rx_cnt << 4) | SPI_CTL_START;
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spiflash_regwrite32(SPI_FLASH_CTL, reg);
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spiflash_regwrite32(SPI_FLASH_CTL, reg);
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busy_wait(spiflash_regread32(SPI_FLASH_CTL) & SPI_CTL_BUSY, 0);
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if (ptr_opcode->rx_cnt > 0) {
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if (!ptr_opcode->rx_cnt)
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do {
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return 0;
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reg = spiflash_regread32(SPI_FLASH_CTL);
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} while (reg & SPI_CTL_BUSY);
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reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
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reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
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switch (ptr_opcode->rx_cnt) {
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switch (ptr_opcode->rx_cnt) {
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case 1:
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case 1:
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mask = 0x000000ff;
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mask = 0x000000ff;
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break;
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break;
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case 2:
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case 2:
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mask = 0x0000ffff;
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mask = 0x0000ffff;
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break;
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break;
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case 3:
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case 3:
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mask = 0x00ffffff;
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mask = 0x00ffffff;
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break;
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break;
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default:
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default:
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mask = 0xffffffff;
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mask = 0xffffffff;
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break;
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break;
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}
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}
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reg &= mask;
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reg &= mask;
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}
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else {
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reg = 0;
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}
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return reg;
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return reg;
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}
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}
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/* Probe SPI flash device
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/* Probe SPI flash device
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* Function returns 0 for failure.
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* Function returns 0 for failure.
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* and flashconfig_tbl array index for success.
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* and flashconfig_tbl array index for success.
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@ -201,7 +224,9 @@ spiflash_probe_chip (void)
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int flash_size;
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int flash_size;
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/* Read the signature on the flash device */
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/* Read the signature on the flash device */
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sig = spiflash_sendcmd(SPI_RD_SIG);
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spin_lock_bh(&spidata->mutex);
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sig = spiflash_sendcmd(SPI_RD_SIG, 0);
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spin_unlock_bh(&spidata->mutex);
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switch (sig) {
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switch (sig) {
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case STM_8MBIT_SIGNATURE:
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case STM_8MBIT_SIGNATURE:
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@ -220,7 +245,7 @@ spiflash_probe_chip (void)
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flash_size = FLASH_16MB;
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flash_size = FLASH_16MB;
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break;
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break;
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default:
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default:
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printk (KERN_WARNING "%s: Read of flash device signature failed!\n", module_name);
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printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n");
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return (0);
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return (0);
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}
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}
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@ -228,90 +253,102 @@ spiflash_probe_chip (void)
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}
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}
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/* wait until the flash chip is ready and grab a lock */
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static int spiflash_wait_ready(int state)
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{
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DECLARE_WAITQUEUE(wait, current);
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retry:
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spin_lock_bh(&spidata->mutex);
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if (spidata->state != FL_READY) {
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set_current_state(TASK_UNINTERRUPTIBLE);
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add_wait_queue(&spidata->wq, &wait);
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spin_unlock_bh(&spidata->mutex);
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schedule();
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remove_wait_queue(&spidata->wq, &wait);
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if(signal_pending(current))
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return 0;
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goto retry;
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}
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spidata->state = state;
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return 1;
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}
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static inline void spiflash_done(void)
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{
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spidata->state = FL_READY;
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spin_unlock_bh(&spidata->mutex);
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wake_up(&spidata->wq);
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}
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static int
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static int
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spiflash_erase (struct mtd_info *mtd,struct erase_info *instr)
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spiflash_erase (struct mtd_info *mtd,struct erase_info *instr)
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{
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{
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struct opcodes *ptr_opcode;
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struct opcodes *ptr_opcode;
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__u32 temp, reg;
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u32 temp, reg;
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int finished = FALSE;
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#ifdef SPIFLASH_DEBUG
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printk (KERN_DEBUG "%s(addr = 0x%.8x, len = %d)\n",__FUNCTION__,instr->addr,instr->len);
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#endif
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/* sanity checks */
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/* sanity checks */
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if (instr->addr + instr->len > mtd->size) return (-EINVAL);
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if (instr->addr + instr->len > mtd->size) return (-EINVAL);
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if (!spiflash_wait_ready(FL_ERASING))
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return -EINTR;
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spiflash_sendcmd(SPI_WRITE_ENABLE, 0);
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busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
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reg = spiflash_regread32(SPI_FLASH_CTL);
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ptr_opcode = &stm_opcodes[SPI_SECTOR_ERASE];
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ptr_opcode = &stm_opcodes[SPI_SECTOR_ERASE];
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temp = ((__u32)instr->addr << 8) | (__u32)(ptr_opcode->code);
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temp = ((__u32)instr->addr << 8) | (__u32)(ptr_opcode->code);
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spin_lock(&spidata->mutex);
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spiflash_sendcmd(SPI_WRITE_ENABLE);
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do {
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schedule();
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reg = spiflash_regread32(SPI_FLASH_CTL);
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} while (reg & SPI_CTL_BUSY);
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spiflash_regwrite32(SPI_FLASH_OPCODE, temp);
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spiflash_regwrite32(SPI_FLASH_OPCODE, temp);
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reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt | SPI_CTL_START;
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reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt | SPI_CTL_START;
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spiflash_regwrite32(SPI_FLASH_CTL, reg);
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spiflash_regwrite32(SPI_FLASH_CTL, reg);
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do {
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/* this will take some time */
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schedule();
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spin_unlock_bh(&spidata->mutex);
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reg = spiflash_sendcmd(SPI_RD_STATUS);
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msleep(800);
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if (!(reg & SPI_STATUS_WIP)) {
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spin_lock_bh(&spidata->mutex);
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finished = TRUE;
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}
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busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 20);
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} while (!finished);
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spiflash_done();
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spin_unlock(&spidata->mutex);
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instr->state = MTD_ERASE_DONE;
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instr->state = MTD_ERASE_DONE;
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if (instr->callback) instr->callback (instr);
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if (instr->callback) instr->callback (instr);
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#ifdef SPIFLASH_DEBUG
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return 0;
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printk (KERN_DEBUG "%s return\n",__FUNCTION__);
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#endif
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return (0);
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}
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}
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static int
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static int
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spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf)
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spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf)
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{
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{
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u_char *read_addr;
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u8 *read_addr;
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#ifdef SPIFLASH_DEBUG
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printk (KERN_DEBUG "%s(from = 0x%.8x, len = %d)\n",__FUNCTION__,(__u32) from,(int)len);
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#endif
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/* sanity checks */
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/* sanity checks */
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if (!len) return (0);
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if (!len) return (0);
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if (from + len > mtd->size) return (-EINVAL);
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if (from + len > mtd->size) return (-EINVAL);
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/* we always read len bytes */
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/* we always read len bytes */
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*retlen = len;
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*retlen = len;
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read_addr = (u_char *)(spidata->spiflash_readaddr + from);
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if (!spiflash_wait_ready(FL_READING))
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spin_lock(&spidata->mutex);
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return -EINTR;
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read_addr = (u8 *)(spidata->readaddr + from);
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memcpy(buf, read_addr, len);
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memcpy(buf, read_addr, len);
|
||||||
spin_unlock(&spidata->mutex);
|
spiflash_done();
|
||||||
|
|
||||||
return (0);
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int
|
static int
|
||||||
spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf)
|
spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf)
|
||||||
{
|
{
|
||||||
int done = FALSE, page_offset, bytes_left, finished;
|
u32 opcode, bytes_left;
|
||||||
__u32 xact_len, spi_data = 0, opcode, reg;
|
|
||||||
|
|
||||||
#ifdef SPIFLASH_DEBUG
|
|
||||||
printk (KERN_DEBUG "%s(to = 0x%.8x, len = %d)\n",__FUNCTION__,(__u32) to,len);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
*retlen = 0;
|
*retlen = 0;
|
||||||
|
|
||||||
/* sanity checks */
|
/* sanity checks */
|
||||||
if (!len) return (0);
|
if (!len) return (0);
|
||||||
if (to + len > mtd->size) return (-EINVAL);
|
if (to + len > mtd->size) return (-EINVAL);
|
||||||
@ -319,7 +356,9 @@ spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u
|
|||||||
opcode = stm_opcodes[SPI_PAGE_PROGRAM].code;
|
opcode = stm_opcodes[SPI_PAGE_PROGRAM].code;
|
||||||
bytes_left = len;
|
bytes_left = len;
|
||||||
|
|
||||||
while (done == FALSE) {
|
do {
|
||||||
|
u32 xact_len, reg, page_offset, spi_data = 0;
|
||||||
|
|
||||||
xact_len = MIN(bytes_left, sizeof(__u32));
|
xact_len = MIN(bytes_left, sizeof(__u32));
|
||||||
|
|
||||||
/* 32-bit writes cannot span across a page boundary
|
/* 32-bit writes cannot span across a page boundary
|
||||||
@ -334,14 +373,10 @@ spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u
|
|||||||
xact_len -= (page_offset - STM_PAGE_SIZE);
|
xact_len -= (page_offset - STM_PAGE_SIZE);
|
||||||
}
|
}
|
||||||
|
|
||||||
spin_lock(&spidata->mutex);
|
if (!spiflash_wait_ready(FL_WRITING))
|
||||||
spiflash_sendcmd(SPI_WRITE_ENABLE);
|
return -EINTR;
|
||||||
|
|
||||||
do {
|
spiflash_sendcmd(SPI_WRITE_ENABLE, 0);
|
||||||
schedule();
|
|
||||||
reg = spiflash_regread32(SPI_FLASH_CTL);
|
|
||||||
} while (reg & SPI_CTL_BUSY);
|
|
||||||
|
|
||||||
switch (xact_len) {
|
switch (xact_len) {
|
||||||
case 1:
|
case 1:
|
||||||
spi_data = (u32) ((u8) *buf);
|
spi_data = (u32) ((u8) *buf);
|
||||||
@ -357,7 +392,7 @@ spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u
|
|||||||
(buf[1] << 8) | buf[0];
|
(buf[1] << 8) | buf[0];
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printk("spiflash_write: default case\n");
|
spi_data = 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -365,31 +400,26 @@ spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u
|
|||||||
opcode = (opcode & SPI_OPCODE_MASK) | ((__u32)to << 8);
|
opcode = (opcode & SPI_OPCODE_MASK) | ((__u32)to << 8);
|
||||||
spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
|
spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
|
||||||
|
|
||||||
|
reg = spiflash_regread32(SPI_FLASH_CTL);
|
||||||
reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | (xact_len + 4) | SPI_CTL_START;
|
reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | (xact_len + 4) | SPI_CTL_START;
|
||||||
spiflash_regwrite32(SPI_FLASH_CTL, reg);
|
spiflash_regwrite32(SPI_FLASH_CTL, reg);
|
||||||
finished = FALSE;
|
|
||||||
|
/* give the chip some time before we start busy waiting */
|
||||||
do {
|
spin_unlock_bh(&spidata->mutex);
|
||||||
schedule();
|
schedule();
|
||||||
reg = spiflash_sendcmd(SPI_RD_STATUS);
|
spin_lock_bh(&spidata->mutex);
|
||||||
if (!(reg & SPI_STATUS_WIP)) {
|
|
||||||
finished = TRUE;
|
busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 0);
|
||||||
}
|
spiflash_done();
|
||||||
} while (!finished);
|
|
||||||
spin_unlock(&spidata->mutex);
|
|
||||||
|
|
||||||
bytes_left -= xact_len;
|
bytes_left -= xact_len;
|
||||||
to += xact_len;
|
to += xact_len;
|
||||||
buf += xact_len;
|
buf += xact_len;
|
||||||
|
|
||||||
*retlen += xact_len;
|
*retlen += xact_len;
|
||||||
|
} while (bytes_left != 0);
|
||||||
|
|
||||||
if (bytes_left == 0) {
|
return 0;
|
||||||
done = TRUE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return (0);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -400,14 +430,17 @@ static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL };
|
|||||||
|
|
||||||
static int spiflash_probe(struct platform_device *pdev)
|
static int spiflash_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
int i, result = -1;
|
int result = -1;
|
||||||
int index, num_parts;
|
int index, num_parts;
|
||||||
struct mtd_info *mtd;
|
struct mtd_info *mtd;
|
||||||
|
|
||||||
spidata->spiflash_mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
|
spidata->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
|
||||||
|
spin_lock_init(&spidata->mutex);
|
||||||
|
init_waitqueue_head(&spidata->wq);
|
||||||
|
spidata->state = FL_READY;
|
||||||
|
|
||||||
if (!spidata->spiflash_mmraddr) {
|
if (!spidata->mmraddr) {
|
||||||
printk (KERN_WARNING "%s: Failed to map flash device\n", module_name);
|
printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
|
||||||
kfree(spidata);
|
kfree(spidata);
|
||||||
spidata = NULL;
|
spidata = NULL;
|
||||||
}
|
}
|
||||||
@ -415,29 +448,21 @@ static int spiflash_probe(struct platform_device *pdev)
|
|||||||
mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
|
mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
|
||||||
if (!mtd) {
|
if (!mtd) {
|
||||||
kfree(spidata);
|
kfree(spidata);
|
||||||
return (-ENXIO);
|
return -ENXIO;
|
||||||
}
|
}
|
||||||
|
|
||||||
printk ("MTD driver for SPI flash.\n");
|
|
||||||
printk ("%s: Probing for Serial flash ...\n", module_name);
|
|
||||||
if (!(index = spiflash_probe_chip())) {
|
if (!(index = spiflash_probe_chip())) {
|
||||||
printk (KERN_WARNING "%s: Found no serial flash device\n", module_name);
|
printk (KERN_WARNING SPIFLASH "Found no serial flash device\n");
|
||||||
kfree(mtd);
|
goto error;
|
||||||
kfree(spidata);
|
|
||||||
return (-ENXIO);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
printk ("%s: Found SPI serial Flash.\n", module_name);
|
spidata->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
|
||||||
|
if (!spidata->readaddr) {
|
||||||
spidata->spiflash_readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
|
printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
|
||||||
if (!spidata->spiflash_readaddr) {
|
goto error;
|
||||||
printk (KERN_WARNING "%s: Failed to map flash device\n", module_name);
|
|
||||||
kfree(mtd);
|
|
||||||
kfree(spidata);
|
|
||||||
return (-ENXIO);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
mtd->name = module_name;
|
mtd->name = "spiflash";
|
||||||
mtd->type = MTD_NORFLASH;
|
mtd->type = MTD_NORFLASH;
|
||||||
mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
|
mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
|
||||||
mtd->size = flashconfig_tbl[index].byte_cnt;
|
mtd->size = flashconfig_tbl[index].byte_cnt;
|
||||||
@ -450,57 +475,26 @@ static int spiflash_probe(struct platform_device *pdev)
|
|||||||
mtd->write = spiflash_write;
|
mtd->write = spiflash_write;
|
||||||
mtd->owner = THIS_MODULE;
|
mtd->owner = THIS_MODULE;
|
||||||
|
|
||||||
#ifdef SPIFLASH_DEBUG
|
|
||||||
printk (KERN_DEBUG
|
|
||||||
"mtd->name = %s\n"
|
|
||||||
"mtd->size = 0x%.8x (%uM)\n"
|
|
||||||
"mtd->erasesize = 0x%.8x (%uK)\n"
|
|
||||||
"mtd->numeraseregions = %d\n",
|
|
||||||
mtd->name,
|
|
||||||
mtd->size, mtd->size / (1024*1024),
|
|
||||||
mtd->erasesize, mtd->erasesize / 1024,
|
|
||||||
mtd->numeraseregions);
|
|
||||||
|
|
||||||
if (mtd->numeraseregions) {
|
|
||||||
for (result = 0; result < mtd->numeraseregions; result++) {
|
|
||||||
printk (KERN_DEBUG
|
|
||||||
"\n\n"
|
|
||||||
"mtd->eraseregions[%d].offset = 0x%.8x\n"
|
|
||||||
"mtd->eraseregions[%d].erasesize = 0x%.8x (%uK)\n"
|
|
||||||
"mtd->eraseregions[%d].numblocks = %d\n",
|
|
||||||
result,mtd->eraseregions[result].offset,
|
|
||||||
result,mtd->eraseregions[result].erasesize,mtd->eraseregions[result].erasesize / 1024,
|
|
||||||
result,mtd->eraseregions[result].numblocks);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
/* parse redboot partitions */
|
/* parse redboot partitions */
|
||||||
num_parts = parse_mtd_partitions(mtd, part_probe_types, &spidata->parsed_parts, 0);
|
num_parts = parse_mtd_partitions(mtd, part_probe_types, &spidata->parsed_parts, 0);
|
||||||
|
if (!num_parts)
|
||||||
|
goto error;
|
||||||
|
|
||||||
#ifdef SPIFLASH_DEBUG
|
result = add_mtd_partitions(mtd, spidata->parsed_parts, num_parts);
|
||||||
printk (KERN_DEBUG "Found %d partitions\n", num_parts);
|
|
||||||
#endif
|
|
||||||
if (num_parts) {
|
|
||||||
result = add_mtd_partitions(mtd, spidata->parsed_parts, num_parts);
|
|
||||||
} else {
|
|
||||||
#ifdef SPIFLASH_DEBUG
|
|
||||||
printk (KERN_DEBUG "Did not find any partitions\n");
|
|
||||||
#endif
|
|
||||||
kfree(mtd);
|
|
||||||
kfree(spidata);
|
|
||||||
return (-ENXIO);
|
|
||||||
}
|
|
||||||
|
|
||||||
spidata->mtd = mtd;
|
spidata->mtd = mtd;
|
||||||
|
|
||||||
return (result);
|
return (result);
|
||||||
|
|
||||||
|
error:
|
||||||
|
kfree(mtd);
|
||||||
|
kfree(spidata);
|
||||||
|
return -ENXIO;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int spiflash_remove (struct platform_device *pdev)
|
static int spiflash_remove (struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
del_mtd_partitions (spidata->mtd);
|
del_mtd_partitions (spidata->mtd);
|
||||||
kfree(spidata->mtd);
|
kfree(spidata->mtd);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -533,6 +527,6 @@ module_init (spiflash_init);
|
|||||||
module_exit (spiflash_exit);
|
module_exit (spiflash_exit);
|
||||||
|
|
||||||
MODULE_LICENSE("GPL");
|
MODULE_LICENSE("GPL");
|
||||||
MODULE_AUTHOR("Atheros Communications Inc");
|
MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
|
||||||
MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
|
MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
|
||||||
|
|
||||||
|
@ -22,19 +22,6 @@
|
|||||||
|
|
||||||
#define STM_PAGE_SIZE 256
|
#define STM_PAGE_SIZE 256
|
||||||
|
|
||||||
#define SPI_WRITE_ENABLE 0
|
|
||||||
#define SPI_WRITE_DISABLE 1
|
|
||||||
#define SPI_RD_STATUS 2
|
|
||||||
#define SPI_WR_STATUS 3
|
|
||||||
#define SPI_RD_DATA 4
|
|
||||||
#define SPI_FAST_RD_DATA 5
|
|
||||||
#define SPI_PAGE_PROGRAM 6
|
|
||||||
#define SPI_SECTOR_ERASE 7
|
|
||||||
#define SPI_BULK_ERASE 8
|
|
||||||
#define SPI_DEEP_PWRDOWN 9
|
|
||||||
#define SPI_RD_SIG 10
|
|
||||||
#define SPI_MAX_OPCODES 11
|
|
||||||
|
|
||||||
#define SFI_WRITE_BUFFER_SIZE 4
|
#define SFI_WRITE_BUFFER_SIZE 4
|
||||||
#define SFI_FLASH_ADDR_MASK 0x00ffffff
|
#define SFI_FLASH_ADDR_MASK 0x00ffffff
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user